15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 2609903c5eSJC Kuo misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91f89b58ceSMikko Perttunen ethernet@2490000 { 9219dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9319dc772aSThierry Reding "nvidia,tegra186-eqos", 94f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 95f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 96f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 101f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 104f89b58ceSMikko Perttunen reset-names = "eqos"; 105d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 108c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 109f89b58ceSMikko Perttunen status = "disabled"; 110f89b58ceSMikko Perttunen 111f89b58ceSMikko Perttunen snps,write-requests = <1>; 112f89b58ceSMikko Perttunen snps,read-requests = <3>; 113f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 114f89b58ceSMikko Perttunen snps,txpbl = <16>; 115f89b58ceSMikko Perttunen snps,rxpbl = <8>; 116f89b58ceSMikko Perttunen }; 117f89b58ceSMikko Perttunen 1181aaa7698SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1325d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1335d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1345d2249ddSSameer Pujar interrupt-parent = <&agic>; 1355d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1665d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1675d2249ddSSameer Pujar #dma-cells = <1>; 1685d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1695d2249ddSSameer Pujar clock-names = "d_audio"; 1705d2249ddSSameer Pujar status = "disabled"; 1715d2249ddSSameer Pujar }; 1725d2249ddSSameer Pujar 1735d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1745d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1755d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1765d2249ddSSameer Pujar #interrupt-cells = <3>; 1775d2249ddSSameer Pujar interrupt-controller; 1785d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1795d2249ddSSameer Pujar <0x02a42000 0x2000>; 1805d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1815d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1825d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1835d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1845d2249ddSSameer Pujar clock-names = "clk"; 1855d2249ddSSameer Pujar status = "disabled"; 1865d2249ddSSameer Pujar }; 187177208f7SSameer Pujar 188177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 189177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 190177208f7SSameer Pujar "nvidia,tegra186-ahub"; 191177208f7SSameer Pujar reg = <0x02900800 0x800>; 192177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 193177208f7SSameer Pujar clock-names = "ahub"; 194177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 195177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 196177208f7SSameer Pujar #address-cells = <1>; 197177208f7SSameer Pujar #size-cells = <1>; 198177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar 201177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 202177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 203177208f7SSameer Pujar "nvidia,tegra186-admaif"; 204177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 205177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 206177208f7SSameer Pujar <&adma 2>, <&adma 2>, 207177208f7SSameer Pujar <&adma 3>, <&adma 3>, 208177208f7SSameer Pujar <&adma 4>, <&adma 4>, 209177208f7SSameer Pujar <&adma 5>, <&adma 5>, 210177208f7SSameer Pujar <&adma 6>, <&adma 6>, 211177208f7SSameer Pujar <&adma 7>, <&adma 7>, 212177208f7SSameer Pujar <&adma 8>, <&adma 8>, 213177208f7SSameer Pujar <&adma 9>, <&adma 9>, 214177208f7SSameer Pujar <&adma 10>, <&adma 10>, 215177208f7SSameer Pujar <&adma 11>, <&adma 11>, 216177208f7SSameer Pujar <&adma 12>, <&adma 12>, 217177208f7SSameer Pujar <&adma 13>, <&adma 13>, 218177208f7SSameer Pujar <&adma 14>, <&adma 14>, 219177208f7SSameer Pujar <&adma 15>, <&adma 15>, 220177208f7SSameer Pujar <&adma 16>, <&adma 16>, 221177208f7SSameer Pujar <&adma 17>, <&adma 17>, 222177208f7SSameer Pujar <&adma 18>, <&adma 18>, 223177208f7SSameer Pujar <&adma 19>, <&adma 19>, 224177208f7SSameer Pujar <&adma 20>, <&adma 20>; 225177208f7SSameer Pujar dma-names = "rx1", "tx1", 226177208f7SSameer Pujar "rx2", "tx2", 227177208f7SSameer Pujar "rx3", "tx3", 228177208f7SSameer Pujar "rx4", "tx4", 229177208f7SSameer Pujar "rx5", "tx5", 230177208f7SSameer Pujar "rx6", "tx6", 231177208f7SSameer Pujar "rx7", "tx7", 232177208f7SSameer Pujar "rx8", "tx8", 233177208f7SSameer Pujar "rx9", "tx9", 234177208f7SSameer Pujar "rx10", "tx10", 235177208f7SSameer Pujar "rx11", "tx11", 236177208f7SSameer Pujar "rx12", "tx12", 237177208f7SSameer Pujar "rx13", "tx13", 238177208f7SSameer Pujar "rx14", "tx14", 239177208f7SSameer Pujar "rx15", "tx15", 240177208f7SSameer Pujar "rx16", "tx16", 241177208f7SSameer Pujar "rx17", "tx17", 242177208f7SSameer Pujar "rx18", "tx18", 243177208f7SSameer Pujar "rx19", "tx19", 244177208f7SSameer Pujar "rx20", "tx20"; 245177208f7SSameer Pujar status = "disabled"; 246177208f7SSameer Pujar }; 247177208f7SSameer Pujar 248177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 249177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 250177208f7SSameer Pujar "nvidia,tegra210-i2s"; 251177208f7SSameer Pujar reg = <0x2901000 0x100>; 252177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 253177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 254177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 255177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 256177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 257177208f7SSameer Pujar assigned-clock-rates = <1536000>; 258177208f7SSameer Pujar sound-name-prefix = "I2S1"; 259177208f7SSameer Pujar status = "disabled"; 260177208f7SSameer Pujar }; 261177208f7SSameer Pujar 262177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 263177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 264177208f7SSameer Pujar "nvidia,tegra210-i2s"; 265177208f7SSameer Pujar reg = <0x2901100 0x100>; 266177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 267177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 268177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 269177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 270177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 271177208f7SSameer Pujar assigned-clock-rates = <1536000>; 272177208f7SSameer Pujar sound-name-prefix = "I2S2"; 273177208f7SSameer Pujar status = "disabled"; 274177208f7SSameer Pujar }; 275177208f7SSameer Pujar 276177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 277177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 278177208f7SSameer Pujar "nvidia,tegra210-i2s"; 279177208f7SSameer Pujar reg = <0x2901200 0x100>; 280177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 281177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 282177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 283177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 284177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 285177208f7SSameer Pujar assigned-clock-rates = <1536000>; 286177208f7SSameer Pujar sound-name-prefix = "I2S3"; 287177208f7SSameer Pujar status = "disabled"; 288177208f7SSameer Pujar }; 289177208f7SSameer Pujar 290177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 291177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 292177208f7SSameer Pujar "nvidia,tegra210-i2s"; 293177208f7SSameer Pujar reg = <0x2901300 0x100>; 294177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 295177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 296177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 297177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 298177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 299177208f7SSameer Pujar assigned-clock-rates = <1536000>; 300177208f7SSameer Pujar sound-name-prefix = "I2S4"; 301177208f7SSameer Pujar status = "disabled"; 302177208f7SSameer Pujar }; 303177208f7SSameer Pujar 304177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 305177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 306177208f7SSameer Pujar "nvidia,tegra210-i2s"; 307177208f7SSameer Pujar reg = <0x2901400 0x100>; 308177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 309177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 310177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 311177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 312177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 313177208f7SSameer Pujar assigned-clock-rates = <1536000>; 314177208f7SSameer Pujar sound-name-prefix = "I2S5"; 315177208f7SSameer Pujar status = "disabled"; 316177208f7SSameer Pujar }; 317177208f7SSameer Pujar 318177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 319177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 320177208f7SSameer Pujar "nvidia,tegra210-i2s"; 321177208f7SSameer Pujar reg = <0x2901500 0x100>; 322177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 323177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 324177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 325177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 326177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 327177208f7SSameer Pujar assigned-clock-rates = <1536000>; 328177208f7SSameer Pujar sound-name-prefix = "I2S6"; 329177208f7SSameer Pujar status = "disabled"; 330177208f7SSameer Pujar }; 331177208f7SSameer Pujar 332177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 333177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 334177208f7SSameer Pujar "nvidia,tegra210-dmic"; 335177208f7SSameer Pujar reg = <0x2904000 0x100>; 336177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 337177208f7SSameer Pujar clock-names = "dmic"; 338177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 339177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340177208f7SSameer Pujar assigned-clock-rates = <3072000>; 341177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 342177208f7SSameer Pujar status = "disabled"; 343177208f7SSameer Pujar }; 344177208f7SSameer Pujar 345177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 346177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 347177208f7SSameer Pujar "nvidia,tegra210-dmic"; 348177208f7SSameer Pujar reg = <0x2904100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 350177208f7SSameer Pujar clock-names = "dmic"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <3072000>; 354177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar 358177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 359177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 360177208f7SSameer Pujar "nvidia,tegra210-dmic"; 361177208f7SSameer Pujar reg = <0x2904200 0x100>; 362177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 363177208f7SSameer Pujar clock-names = "dmic"; 364177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 365177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 366177208f7SSameer Pujar assigned-clock-rates = <3072000>; 367177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 368177208f7SSameer Pujar status = "disabled"; 369177208f7SSameer Pujar }; 370177208f7SSameer Pujar 371177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 372177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 373177208f7SSameer Pujar "nvidia,tegra210-dmic"; 374177208f7SSameer Pujar reg = <0x2904300 0x100>; 375177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 376177208f7SSameer Pujar clock-names = "dmic"; 377177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 378177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 379177208f7SSameer Pujar assigned-clock-rates = <3072000>; 380177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 381177208f7SSameer Pujar status = "disabled"; 382177208f7SSameer Pujar }; 383177208f7SSameer Pujar 384177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 385177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 386177208f7SSameer Pujar "nvidia,tegra186-dspk"; 387177208f7SSameer Pujar reg = <0x2905000 0x100>; 388177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 389177208f7SSameer Pujar clock-names = "dspk"; 390177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 391177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 392177208f7SSameer Pujar assigned-clock-rates = <12288000>; 393177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 394177208f7SSameer Pujar status = "disabled"; 395177208f7SSameer Pujar }; 396177208f7SSameer Pujar 397177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 398177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 399177208f7SSameer Pujar "nvidia,tegra186-dspk"; 400177208f7SSameer Pujar reg = <0x2905100 0x100>; 401177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 402177208f7SSameer Pujar clock-names = "dspk"; 403177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 404177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 405177208f7SSameer Pujar assigned-clock-rates = <12288000>; 406177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 407177208f7SSameer Pujar status = "disabled"; 408177208f7SSameer Pujar }; 409848f3290SSameer Pujar 410848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 411848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 412848f3290SSameer Pujar "nvidia,tegra210-sfc"; 413848f3290SSameer Pujar reg = <0x2902000 0x200>; 414848f3290SSameer Pujar sound-name-prefix = "SFC1"; 415848f3290SSameer Pujar status = "disabled"; 416848f3290SSameer Pujar }; 417848f3290SSameer Pujar 418848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 419848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 420848f3290SSameer Pujar "nvidia,tegra210-sfc"; 421848f3290SSameer Pujar reg = <0x2902200 0x200>; 422848f3290SSameer Pujar sound-name-prefix = "SFC2"; 423848f3290SSameer Pujar status = "disabled"; 424848f3290SSameer Pujar }; 425848f3290SSameer Pujar 426848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 427848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 428848f3290SSameer Pujar "nvidia,tegra210-sfc"; 429848f3290SSameer Pujar reg = <0x2902400 0x200>; 430848f3290SSameer Pujar sound-name-prefix = "SFC3"; 431848f3290SSameer Pujar status = "disabled"; 432848f3290SSameer Pujar }; 433848f3290SSameer Pujar 434848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 435848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 436848f3290SSameer Pujar "nvidia,tegra210-sfc"; 437848f3290SSameer Pujar reg = <0x2902600 0x200>; 438848f3290SSameer Pujar sound-name-prefix = "SFC4"; 439848f3290SSameer Pujar status = "disabled"; 440848f3290SSameer Pujar }; 441848f3290SSameer Pujar 442848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 443848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 444848f3290SSameer Pujar "nvidia,tegra210-mvc"; 445848f3290SSameer Pujar reg = <0x290a000 0x200>; 446848f3290SSameer Pujar sound-name-prefix = "MVC1"; 447848f3290SSameer Pujar status = "disabled"; 448848f3290SSameer Pujar }; 449848f3290SSameer Pujar 450848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 451848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 452848f3290SSameer Pujar "nvidia,tegra210-mvc"; 453848f3290SSameer Pujar reg = <0x290a200 0x200>; 454848f3290SSameer Pujar sound-name-prefix = "MVC2"; 455848f3290SSameer Pujar status = "disabled"; 456848f3290SSameer Pujar }; 457848f3290SSameer Pujar 458848f3290SSameer Pujar tegra_amx1: amx@2903000 { 459848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 460848f3290SSameer Pujar reg = <0x2903000 0x100>; 461848f3290SSameer Pujar sound-name-prefix = "AMX1"; 462848f3290SSameer Pujar status = "disabled"; 463848f3290SSameer Pujar }; 464848f3290SSameer Pujar 465848f3290SSameer Pujar tegra_amx2: amx@2903100 { 466848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 467848f3290SSameer Pujar reg = <0x2903100 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX2"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx3: amx@2903200 { 473848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 474848f3290SSameer Pujar reg = <0x2903200 0x100>; 475848f3290SSameer Pujar sound-name-prefix = "AMX3"; 476848f3290SSameer Pujar status = "disabled"; 477848f3290SSameer Pujar }; 478848f3290SSameer Pujar 479848f3290SSameer Pujar tegra_amx4: amx@2903300 { 480848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 481848f3290SSameer Pujar reg = <0x2903300 0x100>; 482848f3290SSameer Pujar sound-name-prefix = "AMX4"; 483848f3290SSameer Pujar status = "disabled"; 484848f3290SSameer Pujar }; 485848f3290SSameer Pujar 486848f3290SSameer Pujar tegra_adx1: adx@2903800 { 487848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 488848f3290SSameer Pujar "nvidia,tegra210-adx"; 489848f3290SSameer Pujar reg = <0x2903800 0x100>; 490848f3290SSameer Pujar sound-name-prefix = "ADX1"; 491848f3290SSameer Pujar status = "disabled"; 492848f3290SSameer Pujar }; 493848f3290SSameer Pujar 494848f3290SSameer Pujar tegra_adx2: adx@2903900 { 495848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 496848f3290SSameer Pujar "nvidia,tegra210-adx"; 497848f3290SSameer Pujar reg = <0x2903900 0x100>; 498848f3290SSameer Pujar sound-name-prefix = "ADX2"; 499848f3290SSameer Pujar status = "disabled"; 500848f3290SSameer Pujar }; 501848f3290SSameer Pujar 502848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 503848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 504848f3290SSameer Pujar "nvidia,tegra210-adx"; 505848f3290SSameer Pujar reg = <0x2903a00 0x100>; 506848f3290SSameer Pujar sound-name-prefix = "ADX3"; 507848f3290SSameer Pujar status = "disabled"; 508848f3290SSameer Pujar }; 509848f3290SSameer Pujar 510848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 511848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 512848f3290SSameer Pujar "nvidia,tegra210-adx"; 513848f3290SSameer Pujar reg = <0x2903b00 0x100>; 514848f3290SSameer Pujar sound-name-prefix = "ADX4"; 515848f3290SSameer Pujar status = "disabled"; 516848f3290SSameer Pujar }; 517848f3290SSameer Pujar 518848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 519848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 520848f3290SSameer Pujar "nvidia,tegra210-amixer"; 521848f3290SSameer Pujar reg = <0x290bb00 0x800>; 522848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 523848f3290SSameer Pujar status = "disabled"; 524848f3290SSameer Pujar }; 525177208f7SSameer Pujar }; 5265d2249ddSSameer Pujar }; 5275d2249ddSSameer Pujar 528dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 529dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 530644c569dSThierry Reding reg = <0x2430000 0x17000>, 531644c569dSThierry Reding <0xc300000 0x4000>; 532dbb72e2cSVidya Sagar 533dbb72e2cSVidya Sagar status = "okay"; 534dbb72e2cSVidya Sagar 535dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 536dbb72e2cSVidya Sagar pex_rst { 537dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 538dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 539dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5406b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 541dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 542dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543dbb72e2cSVidya Sagar }; 544dbb72e2cSVidya Sagar }; 545dbb72e2cSVidya Sagar 546dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 547dbb72e2cSVidya Sagar clkreq { 548dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 549dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 550dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5516b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 552dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 553dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 554dbb72e2cSVidya Sagar }; 555dbb72e2cSVidya Sagar }; 556dbb72e2cSVidya Sagar }; 557dbb72e2cSVidya Sagar 558be9b887fSThierry Reding mc: memory-controller@2c00000 { 559be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 560be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 561be9b887fSThierry Reding <0x02b80000 0x040000>, 562be9b887fSThierry Reding <0x01700000 0x100000>; 5638613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564d5237c7cSThierry Reding #interconnect-cells = <1>; 565be9b887fSThierry Reding status = "disabled"; 566be9b887fSThierry Reding 567be9b887fSThierry Reding #address-cells = <2>; 568be9b887fSThierry Reding #size-cells = <2>; 569be9b887fSThierry Reding 570be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 571be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 572be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 573be9b887fSThierry Reding 574be9b887fSThierry Reding /* 575be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 576be9b887fSThierry Reding * controller selects the XBAR format used when memory 577be9b887fSThierry Reding * is accessed. This is used to transparently access 578be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 579be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 580be9b887fSThierry Reding * 581be9b887fSThierry Reding * As a consequence, the operating system must ensure 582be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 583be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 584be9b887fSThierry Reding * devices require access to the XBAR switch, their 585be9b887fSThierry Reding * drivers must set this bit explicitly. 586be9b887fSThierry Reding * 587be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 588be9b887fSThierry Reding */ 589be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 590be9b887fSThierry Reding 591be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 592be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 593be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 594be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 595be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 596be9b887fSThierry Reding clock-names = "emc"; 597be9b887fSThierry Reding 598d5237c7cSThierry Reding #interconnect-cells = <0>; 599d5237c7cSThierry Reding 600be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 601be9b887fSThierry Reding }; 602be9b887fSThierry Reding }; 603be9b887fSThierry Reding 6045425fb15SMikko Perttunen uarta: serial@3100000 { 6055425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6065425fb15SMikko Perttunen reg = <0x03100000 0x40>; 6075425fb15SMikko Perttunen reg-shift = <2>; 6085425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 6095425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 6105425fb15SMikko Perttunen clock-names = "serial"; 6115425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 6125425fb15SMikko Perttunen reset-names = "serial"; 6135425fb15SMikko Perttunen status = "disabled"; 6145425fb15SMikko Perttunen }; 6155425fb15SMikko Perttunen 6165425fb15SMikko Perttunen uartb: serial@3110000 { 6175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6185425fb15SMikko Perttunen reg = <0x03110000 0x40>; 6195425fb15SMikko Perttunen reg-shift = <2>; 6205425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 6215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 6225425fb15SMikko Perttunen clock-names = "serial"; 6235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 6245425fb15SMikko Perttunen reset-names = "serial"; 6255425fb15SMikko Perttunen status = "disabled"; 6265425fb15SMikko Perttunen }; 6275425fb15SMikko Perttunen 6285425fb15SMikko Perttunen uartd: serial@3130000 { 6295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6305425fb15SMikko Perttunen reg = <0x03130000 0x40>; 6315425fb15SMikko Perttunen reg-shift = <2>; 6325425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 6335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 6345425fb15SMikko Perttunen clock-names = "serial"; 6355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 6365425fb15SMikko Perttunen reset-names = "serial"; 6375425fb15SMikko Perttunen status = "disabled"; 6385425fb15SMikko Perttunen }; 6395425fb15SMikko Perttunen 6405425fb15SMikko Perttunen uarte: serial@3140000 { 6415425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6425425fb15SMikko Perttunen reg = <0x03140000 0x40>; 6435425fb15SMikko Perttunen reg-shift = <2>; 6445425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 6455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 6465425fb15SMikko Perttunen clock-names = "serial"; 6475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 6485425fb15SMikko Perttunen reset-names = "serial"; 6495425fb15SMikko Perttunen status = "disabled"; 6505425fb15SMikko Perttunen }; 6515425fb15SMikko Perttunen 6525425fb15SMikko Perttunen uartf: serial@3150000 { 6535425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6545425fb15SMikko Perttunen reg = <0x03150000 0x40>; 6555425fb15SMikko Perttunen reg-shift = <2>; 6565425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 6575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 6585425fb15SMikko Perttunen clock-names = "serial"; 6595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 6605425fb15SMikko Perttunen reset-names = "serial"; 6615425fb15SMikko Perttunen status = "disabled"; 6625425fb15SMikko Perttunen }; 6635425fb15SMikko Perttunen 6645425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 665d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6665425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 6675425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 6685425fb15SMikko Perttunen #address-cells = <1>; 6695425fb15SMikko Perttunen #size-cells = <0>; 6705425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 6715425fb15SMikko Perttunen clock-names = "div-clk"; 6725425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 6735425fb15SMikko Perttunen reset-names = "i2c"; 6745425fb15SMikko Perttunen status = "disabled"; 6755425fb15SMikko Perttunen }; 6765425fb15SMikko Perttunen 6775425fb15SMikko Perttunen uarth: serial@3170000 { 6785425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6795425fb15SMikko Perttunen reg = <0x03170000 0x40>; 6805425fb15SMikko Perttunen reg-shift = <2>; 6815425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 6825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 6835425fb15SMikko Perttunen clock-names = "serial"; 6845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 6855425fb15SMikko Perttunen reset-names = "serial"; 6865425fb15SMikko Perttunen status = "disabled"; 6875425fb15SMikko Perttunen }; 6885425fb15SMikko Perttunen 6895425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 690d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6915425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 6925425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 6935425fb15SMikko Perttunen #address-cells = <1>; 6945425fb15SMikko Perttunen #size-cells = <0>; 6955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 6965425fb15SMikko Perttunen clock-names = "div-clk"; 6975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 6985425fb15SMikko Perttunen reset-names = "i2c"; 6995425fb15SMikko Perttunen status = "disabled"; 7005425fb15SMikko Perttunen }; 7015425fb15SMikko Perttunen 7025425fb15SMikko Perttunen /* shares pads with dpaux1 */ 7035425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 704d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7055425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 7065425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 7075425fb15SMikko Perttunen #address-cells = <1>; 7085425fb15SMikko Perttunen #size-cells = <0>; 7095425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 7105425fb15SMikko Perttunen clock-names = "div-clk"; 7115425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 7125425fb15SMikko Perttunen reset-names = "i2c"; 713a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 714a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 715a4131561SThierry Reding pinctrl-names = "default", "idle"; 7165425fb15SMikko Perttunen status = "disabled"; 7175425fb15SMikko Perttunen }; 7185425fb15SMikko Perttunen 7195425fb15SMikko Perttunen /* shares pads with dpaux0 */ 7205425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 721d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7225425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 7235425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7245425fb15SMikko Perttunen #address-cells = <1>; 7255425fb15SMikko Perttunen #size-cells = <0>; 7265425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 7275425fb15SMikko Perttunen clock-names = "div-clk"; 7285425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 7295425fb15SMikko Perttunen reset-names = "i2c"; 730a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 731a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 732a4131561SThierry Reding pinctrl-names = "default", "idle"; 7335425fb15SMikko Perttunen status = "disabled"; 7345425fb15SMikko Perttunen }; 7355425fb15SMikko Perttunen 736a4131561SThierry Reding /* shares pads with dpaux2 */ 737a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 738d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7395425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 7405425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 7415425fb15SMikko Perttunen #address-cells = <1>; 7425425fb15SMikko Perttunen #size-cells = <0>; 7435425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 7445425fb15SMikko Perttunen clock-names = "div-clk"; 7455425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 7465425fb15SMikko Perttunen reset-names = "i2c"; 747a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 748a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 749a4131561SThierry Reding pinctrl-names = "default", "idle"; 7505425fb15SMikko Perttunen status = "disabled"; 7515425fb15SMikko Perttunen }; 7525425fb15SMikko Perttunen 753a4131561SThierry Reding /* shares pads with dpaux3 */ 754a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 755d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7565425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 7575425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 7585425fb15SMikko Perttunen #address-cells = <1>; 7595425fb15SMikko Perttunen #size-cells = <0>; 7605425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 7615425fb15SMikko Perttunen clock-names = "div-clk"; 7625425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 7635425fb15SMikko Perttunen reset-names = "i2c"; 764a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 765a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 766a4131561SThierry Reding pinctrl-names = "default", "idle"; 7675425fb15SMikko Perttunen status = "disabled"; 7685425fb15SMikko Perttunen }; 7695425fb15SMikko Perttunen 77096ded827SSowjanya Komatineni spi@3270000 { 77196ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 77296ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 77396ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 77496ded827SSowjanya Komatineni #address-cells = <1>; 77596ded827SSowjanya Komatineni #size-cells = <0>; 77696ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 77796ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 77896ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 77996ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 78096ded827SSowjanya Komatineni reset-names = "qspi"; 78196ded827SSowjanya Komatineni status = "disabled"; 78296ded827SSowjanya Komatineni }; 78396ded827SSowjanya Komatineni 78496ded827SSowjanya Komatineni spi@3300000 { 78596ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 78696ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 78796ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 78896ded827SSowjanya Komatineni #address-cells = <1>; 78996ded827SSowjanya Komatineni #size-cells = <0>; 79096ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 79196ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 79296ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 79396ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 79496ded827SSowjanya Komatineni reset-names = "qspi"; 79596ded827SSowjanya Komatineni status = "disabled"; 79696ded827SSowjanya Komatineni }; 79796ded827SSowjanya Komatineni 7986a574ec7SThierry Reding pwm1: pwm@3280000 { 7996a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8006a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8016a574ec7SThierry Reding reg = <0x3280000 0x10000>; 8026a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 8036a574ec7SThierry Reding clock-names = "pwm"; 8046a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 8056a574ec7SThierry Reding reset-names = "pwm"; 8066a574ec7SThierry Reding status = "disabled"; 8076a574ec7SThierry Reding #pwm-cells = <2>; 8086a574ec7SThierry Reding }; 8096a574ec7SThierry Reding 8106a574ec7SThierry Reding pwm2: pwm@3290000 { 8116a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8126a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8136a574ec7SThierry Reding reg = <0x3290000 0x10000>; 8146a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 8156a574ec7SThierry Reding clock-names = "pwm"; 8166a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 8176a574ec7SThierry Reding reset-names = "pwm"; 8186a574ec7SThierry Reding status = "disabled"; 8196a574ec7SThierry Reding #pwm-cells = <2>; 8206a574ec7SThierry Reding }; 8216a574ec7SThierry Reding 8226a574ec7SThierry Reding pwm3: pwm@32a0000 { 8236a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8246a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8256a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 8266a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 8276a574ec7SThierry Reding clock-names = "pwm"; 8286a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 8296a574ec7SThierry Reding reset-names = "pwm"; 8306a574ec7SThierry Reding status = "disabled"; 8316a574ec7SThierry Reding #pwm-cells = <2>; 8326a574ec7SThierry Reding }; 8336a574ec7SThierry Reding 8346a574ec7SThierry Reding pwm5: pwm@32c0000 { 8356a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8366a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8376a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 8386a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 8396a574ec7SThierry Reding clock-names = "pwm"; 8406a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 8416a574ec7SThierry Reding reset-names = "pwm"; 8426a574ec7SThierry Reding status = "disabled"; 8436a574ec7SThierry Reding #pwm-cells = <2>; 8446a574ec7SThierry Reding }; 8456a574ec7SThierry Reding 8466a574ec7SThierry Reding pwm6: pwm@32d0000 { 8476a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8486a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8496a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 8506a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 8516a574ec7SThierry Reding clock-names = "pwm"; 8526a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 8536a574ec7SThierry Reding reset-names = "pwm"; 8546a574ec7SThierry Reding status = "disabled"; 8556a574ec7SThierry Reding #pwm-cells = <2>; 8566a574ec7SThierry Reding }; 8576a574ec7SThierry Reding 8586a574ec7SThierry Reding pwm7: pwm@32e0000 { 8596a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8606a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8616a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 8626a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 8636a574ec7SThierry Reding clock-names = "pwm"; 8646a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 8656a574ec7SThierry Reding reset-names = "pwm"; 8666a574ec7SThierry Reding status = "disabled"; 8676a574ec7SThierry Reding #pwm-cells = <2>; 8686a574ec7SThierry Reding }; 8696a574ec7SThierry Reding 8706a574ec7SThierry Reding pwm8: pwm@32f0000 { 8716a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8726a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8736a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 8746a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 8756a574ec7SThierry Reding clock-names = "pwm"; 8766a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 8776a574ec7SThierry Reding reset-names = "pwm"; 8786a574ec7SThierry Reding status = "disabled"; 8796a574ec7SThierry Reding #pwm-cells = <2>; 8806a574ec7SThierry Reding }; 8816a574ec7SThierry Reding 88267bb17f6SThierry Reding sdmmc1: mmc@3400000 { 8832c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 8845425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 8855425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 886c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 887c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 888c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8895425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 8905425fb15SMikko Perttunen reset-names = "sdhci"; 891d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 892d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 893d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 894c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 895ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 896ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 897ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 8984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 8994e0f1229SSowjanya Komatineni <0x07>; 9004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9014e0f1229SSowjanya Komatineni <0x07>; 9024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9044e0f1229SSowjanya Komatineni <0x07>; 9054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9064e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9074e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9084e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 909ff21087eSPrathamesh Shete sd-uhs-sdr25; 910ff21087eSPrathamesh Shete sd-uhs-sdr50; 911ff21087eSPrathamesh Shete sd-uhs-ddr50; 912ff21087eSPrathamesh Shete sd-uhs-sdr104; 9135425fb15SMikko Perttunen status = "disabled"; 9145425fb15SMikko Perttunen }; 9155425fb15SMikko Perttunen 91667bb17f6SThierry Reding sdmmc3: mmc@3440000 { 9172c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9185425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 9195425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 920c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 921c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 922c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 9245425fb15SMikko Perttunen reset-names = "sdhci"; 925d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 926d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 927d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 928c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 929ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 930ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 931ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 9324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 9334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 9344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 9354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9364e0f1229SSowjanya Komatineni <0x07>; 9374e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9384e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9394e0f1229SSowjanya Komatineni <0x07>; 9404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9424e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9434e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 944ff21087eSPrathamesh Shete sd-uhs-sdr25; 945ff21087eSPrathamesh Shete sd-uhs-sdr50; 946ff21087eSPrathamesh Shete sd-uhs-ddr50; 947ff21087eSPrathamesh Shete sd-uhs-sdr104; 9485425fb15SMikko Perttunen status = "disabled"; 9495425fb15SMikko Perttunen }; 9505425fb15SMikko Perttunen 95167bb17f6SThierry Reding sdmmc4: mmc@3460000 { 9522c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9535425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 9545425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 955c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 956c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 957c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 958351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 959351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 960351648d0SSowjanya Komatineni assigned-clock-parents = 961351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 9625425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 9635425fb15SMikko Perttunen reset-names = "sdhci"; 964d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 965d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 966d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 967c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 9684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 9694e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 9704e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 9714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9724e0f1229SSowjanya Komatineni <0x0a>; 9734e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9744e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9754e0f1229SSowjanya Komatineni <0x0a>; 9764e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 9774e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 9784e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 979*c2fee443SPrathamesh Shete cap-mmc-highspeed; 980*c2fee443SPrathamesh Shete mmc-ddr-1_8v; 981*c2fee443SPrathamesh Shete mmc-hs200-1_8v; 982*c2fee443SPrathamesh Shete mmc-hs400-1_8v; 983*c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 984dfd3cb6fSSowjanya Komatineni supports-cqe; 9855425fb15SMikko Perttunen status = "disabled"; 9865425fb15SMikko Perttunen }; 9875425fb15SMikko Perttunen 9884878cc0cSSameer Pujar hda@3510000 { 9894878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 9904878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 9914878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 9924878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 99348f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 99448f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 99548f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 9964878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 99748f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 99848f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 99948f6e195SSameer Pujar reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 10004878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1001d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1002d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1003d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1004c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 10054878cc0cSSameer Pujar status = "disabled"; 10064878cc0cSSameer Pujar }; 10074878cc0cSSameer Pujar 1008fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1009fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1010fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1011fab7a039SJC Kuo <0x03540000 0x1000>; 1012fab7a039SJC Kuo reg-names = "padctl", "ao"; 10136450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1014fab7a039SJC Kuo 1015fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1016fab7a039SJC Kuo reset-names = "padctl"; 1017fab7a039SJC Kuo 1018fab7a039SJC Kuo status = "disabled"; 1019fab7a039SJC Kuo 1020fab7a039SJC Kuo pads { 1021fab7a039SJC Kuo usb2 { 1022fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1023fab7a039SJC Kuo clock-names = "trk"; 1024fab7a039SJC Kuo 1025fab7a039SJC Kuo lanes { 1026fab7a039SJC Kuo usb2-0 { 1027fab7a039SJC Kuo nvidia,function = "xusb"; 1028fab7a039SJC Kuo status = "disabled"; 1029fab7a039SJC Kuo #phy-cells = <0>; 1030fab7a039SJC Kuo }; 1031fab7a039SJC Kuo 1032fab7a039SJC Kuo usb2-1 { 1033fab7a039SJC Kuo nvidia,function = "xusb"; 1034fab7a039SJC Kuo status = "disabled"; 1035fab7a039SJC Kuo #phy-cells = <0>; 1036fab7a039SJC Kuo }; 1037fab7a039SJC Kuo 1038fab7a039SJC Kuo usb2-2 { 1039fab7a039SJC Kuo nvidia,function = "xusb"; 1040fab7a039SJC Kuo status = "disabled"; 1041fab7a039SJC Kuo #phy-cells = <0>; 1042fab7a039SJC Kuo }; 1043fab7a039SJC Kuo 1044fab7a039SJC Kuo usb2-3 { 1045fab7a039SJC Kuo nvidia,function = "xusb"; 1046fab7a039SJC Kuo status = "disabled"; 1047fab7a039SJC Kuo #phy-cells = <0>; 1048fab7a039SJC Kuo }; 1049fab7a039SJC Kuo }; 1050fab7a039SJC Kuo }; 1051fab7a039SJC Kuo 1052fab7a039SJC Kuo usb3 { 1053fab7a039SJC Kuo lanes { 1054fab7a039SJC Kuo usb3-0 { 1055fab7a039SJC Kuo nvidia,function = "xusb"; 1056fab7a039SJC Kuo status = "disabled"; 1057fab7a039SJC Kuo #phy-cells = <0>; 1058fab7a039SJC Kuo }; 1059fab7a039SJC Kuo 1060fab7a039SJC Kuo usb3-1 { 1061fab7a039SJC Kuo nvidia,function = "xusb"; 1062fab7a039SJC Kuo status = "disabled"; 1063fab7a039SJC Kuo #phy-cells = <0>; 1064fab7a039SJC Kuo }; 1065fab7a039SJC Kuo 1066fab7a039SJC Kuo usb3-2 { 1067fab7a039SJC Kuo nvidia,function = "xusb"; 1068fab7a039SJC Kuo status = "disabled"; 1069fab7a039SJC Kuo #phy-cells = <0>; 1070fab7a039SJC Kuo }; 1071fab7a039SJC Kuo 1072fab7a039SJC Kuo usb3-3 { 1073fab7a039SJC Kuo nvidia,function = "xusb"; 1074fab7a039SJC Kuo status = "disabled"; 1075fab7a039SJC Kuo #phy-cells = <0>; 1076fab7a039SJC Kuo }; 1077fab7a039SJC Kuo }; 1078fab7a039SJC Kuo }; 1079fab7a039SJC Kuo }; 1080fab7a039SJC Kuo 1081fab7a039SJC Kuo ports { 1082fab7a039SJC Kuo usb2-0 { 1083fab7a039SJC Kuo status = "disabled"; 1084fab7a039SJC Kuo }; 1085fab7a039SJC Kuo 1086fab7a039SJC Kuo usb2-1 { 1087fab7a039SJC Kuo status = "disabled"; 1088fab7a039SJC Kuo }; 1089fab7a039SJC Kuo 1090fab7a039SJC Kuo usb2-2 { 1091fab7a039SJC Kuo status = "disabled"; 1092fab7a039SJC Kuo }; 1093fab7a039SJC Kuo 1094fab7a039SJC Kuo usb2-3 { 1095fab7a039SJC Kuo status = "disabled"; 1096fab7a039SJC Kuo }; 1097fab7a039SJC Kuo 1098fab7a039SJC Kuo usb3-0 { 1099fab7a039SJC Kuo status = "disabled"; 1100fab7a039SJC Kuo }; 1101fab7a039SJC Kuo 1102fab7a039SJC Kuo usb3-1 { 1103fab7a039SJC Kuo status = "disabled"; 1104fab7a039SJC Kuo }; 1105fab7a039SJC Kuo 1106fab7a039SJC Kuo usb3-2 { 1107fab7a039SJC Kuo status = "disabled"; 1108fab7a039SJC Kuo }; 1109fab7a039SJC Kuo 1110fab7a039SJC Kuo usb3-3 { 1111fab7a039SJC Kuo status = "disabled"; 1112fab7a039SJC Kuo }; 1113fab7a039SJC Kuo }; 1114fab7a039SJC Kuo }; 1115fab7a039SJC Kuo 1116bc8788b2SNagarjuna Kristam usb@3550000 { 1117bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1118bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1119bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1120bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1121bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1122bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1123bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1124bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1125bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1126bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1127c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1128c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1129c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1130c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1131bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1132bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1133bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1134bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1135bc8788b2SNagarjuna Kristam status = "disabled"; 1136bc8788b2SNagarjuna Kristam }; 1137bc8788b2SNagarjuna Kristam 1138fab7a039SJC Kuo usb@3610000 { 1139fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1140fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1141fab7a039SJC Kuo <0x03600000 0x10000>; 1142fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1143fab7a039SJC Kuo 1144fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1145a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1146fab7a039SJC Kuo 1147fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1148fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1149fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1150fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1151fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1152fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1153fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1154fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1155fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1156fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1157fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1158fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1159fab7a039SJC Kuo "pll_e"; 1160c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1161c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1162c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1163c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1164fab7a039SJC Kuo 1165fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1166fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1167fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1168fab7a039SJC Kuo 1169fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1170fab7a039SJC Kuo status = "disabled"; 1171fab7a039SJC Kuo }; 1172fab7a039SJC Kuo 117309903c5eSJC Kuo fuse@3820000 { 117409903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 117509903c5eSJC Kuo reg = <0x03820000 0x10000>; 117609903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 117709903c5eSJC Kuo clock-names = "fuse"; 117809903c5eSJC Kuo }; 117909903c5eSJC Kuo 11805425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 11815425fb15SMikko Perttunen compatible = "arm,gic-400"; 11825425fb15SMikko Perttunen #interrupt-cells = <3>; 11835425fb15SMikko Perttunen interrupt-controller; 11845425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 11855425fb15SMikko Perttunen <0x03882000 0x2000>, 11865425fb15SMikko Perttunen <0x03884000 0x2000>, 11875425fb15SMikko Perttunen <0x03886000 0x2000>; 11885425fb15SMikko Perttunen interrupts = <GIC_PPI 9 11895425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 11905425fb15SMikko Perttunen interrupt-parent = <&gic>; 11915425fb15SMikko Perttunen }; 11925425fb15SMikko Perttunen 1193badb80beSThierry Reding cec@3960000 { 1194badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1195badb80beSThierry Reding reg = <0x03960000 0x10000>; 1196badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1197badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1198badb80beSThierry Reding clock-names = "cec"; 1199badb80beSThierry Reding status = "disabled"; 1200badb80beSThierry Reding }; 1201badb80beSThierry Reding 12025425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1203cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 12045425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1205a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1206a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1207a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1208a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1209a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1210a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1211a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1212a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1213a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1214a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1215a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1216a38570c2SMikko Perttunen "shared7"; 1217a38570c2SMikko Perttunen #mbox-cells = <2>; 1218a38570c2SMikko Perttunen }; 1219a38570c2SMikko Perttunen 12202602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 12212602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12222602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 12232602c32fSVidya Sagar reg-names = "ctl"; 12242602c32fSVidya Sagar 12252602c32fSVidya Sagar #phy-cells = <0>; 12262602c32fSVidya Sagar }; 12272602c32fSVidya Sagar 12282602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 12292602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12302602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 12312602c32fSVidya Sagar reg-names = "ctl"; 12322602c32fSVidya Sagar 12332602c32fSVidya Sagar #phy-cells = <0>; 12342602c32fSVidya Sagar }; 12352602c32fSVidya Sagar 12362602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 12372602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12382602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 12392602c32fSVidya Sagar reg-names = "ctl"; 12402602c32fSVidya Sagar 12412602c32fSVidya Sagar #phy-cells = <0>; 12422602c32fSVidya Sagar }; 12432602c32fSVidya Sagar 12442602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 12452602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12462602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 12472602c32fSVidya Sagar reg-names = "ctl"; 12482602c32fSVidya Sagar 12492602c32fSVidya Sagar #phy-cells = <0>; 12502602c32fSVidya Sagar }; 12512602c32fSVidya Sagar 12522602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 12532602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12542602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 12552602c32fSVidya Sagar reg-names = "ctl"; 12562602c32fSVidya Sagar 12572602c32fSVidya Sagar #phy-cells = <0>; 12582602c32fSVidya Sagar }; 12592602c32fSVidya Sagar 12602602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 12612602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12622602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 12632602c32fSVidya Sagar reg-names = "ctl"; 12642602c32fSVidya Sagar 12652602c32fSVidya Sagar #phy-cells = <0>; 12662602c32fSVidya Sagar }; 12672602c32fSVidya Sagar 12682602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 12692602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12702602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 12712602c32fSVidya Sagar reg-names = "ctl"; 12722602c32fSVidya Sagar 12732602c32fSVidya Sagar #phy-cells = <0>; 12742602c32fSVidya Sagar }; 12752602c32fSVidya Sagar 12762602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 12772602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12782602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 12792602c32fSVidya Sagar reg-names = "ctl"; 12802602c32fSVidya Sagar 12812602c32fSVidya Sagar #phy-cells = <0>; 12822602c32fSVidya Sagar }; 12832602c32fSVidya Sagar 12842602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 12852602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12862602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 12872602c32fSVidya Sagar reg-names = "ctl"; 12882602c32fSVidya Sagar 12892602c32fSVidya Sagar #phy-cells = <0>; 12902602c32fSVidya Sagar }; 12912602c32fSVidya Sagar 12922602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 12932602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12942602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 12952602c32fSVidya Sagar reg-names = "ctl"; 12962602c32fSVidya Sagar 12972602c32fSVidya Sagar #phy-cells = <0>; 12982602c32fSVidya Sagar }; 12992602c32fSVidya Sagar 13002602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 13012602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13022602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 13032602c32fSVidya Sagar reg-names = "ctl"; 13042602c32fSVidya Sagar 13052602c32fSVidya Sagar #phy-cells = <0>; 13062602c32fSVidya Sagar }; 13072602c32fSVidya Sagar 13082602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 13092602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13102602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 13112602c32fSVidya Sagar reg-names = "ctl"; 13122602c32fSVidya Sagar 13132602c32fSVidya Sagar #phy-cells = <0>; 13142602c32fSVidya Sagar }; 13152602c32fSVidya Sagar 13162602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 13172602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13182602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 13192602c32fSVidya Sagar reg-names = "ctl"; 13202602c32fSVidya Sagar 13212602c32fSVidya Sagar #phy-cells = <0>; 13222602c32fSVidya Sagar }; 13232602c32fSVidya Sagar 13242602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 13252602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13262602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 13272602c32fSVidya Sagar reg-names = "ctl"; 13282602c32fSVidya Sagar 13292602c32fSVidya Sagar #phy-cells = <0>; 13302602c32fSVidya Sagar }; 13312602c32fSVidya Sagar 13322602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 13332602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13342602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 13352602c32fSVidya Sagar reg-names = "ctl"; 13362602c32fSVidya Sagar 13372602c32fSVidya Sagar #phy-cells = <0>; 13382602c32fSVidya Sagar }; 13392602c32fSVidya Sagar 13402602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 13412602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13422602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 13432602c32fSVidya Sagar reg-names = "ctl"; 13442602c32fSVidya Sagar 13452602c32fSVidya Sagar #phy-cells = <0>; 13462602c32fSVidya Sagar }; 13472602c32fSVidya Sagar 13482602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 13492602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13502602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 13512602c32fSVidya Sagar reg-names = "ctl"; 13522602c32fSVidya Sagar 13532602c32fSVidya Sagar #phy-cells = <0>; 13542602c32fSVidya Sagar }; 13552602c32fSVidya Sagar 13562602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 13572602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13582602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 13592602c32fSVidya Sagar reg-names = "ctl"; 13602602c32fSVidya Sagar 13612602c32fSVidya Sagar #phy-cells = <0>; 13622602c32fSVidya Sagar }; 13632602c32fSVidya Sagar 13642602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 13652602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13662602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 13672602c32fSVidya Sagar reg-names = "ctl"; 13682602c32fSVidya Sagar 13692602c32fSVidya Sagar #phy-cells = <0>; 13702602c32fSVidya Sagar }; 13712602c32fSVidya Sagar 13722602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 13732602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13742602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 13752602c32fSVidya Sagar reg-names = "ctl"; 13762602c32fSVidya Sagar 13772602c32fSVidya Sagar #phy-cells = <0>; 13782602c32fSVidya Sagar }; 13792602c32fSVidya Sagar 1380a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1381cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13821741e187SDipen Patel reg = <0x0c150000 0x90000>; 1383a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1384a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1385a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1386a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1387a38570c2SMikko Perttunen /* 1388a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1389a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1390a38570c2SMikko Perttunen */ 1391a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 13925425fb15SMikko Perttunen #mbox-cells = <2>; 13935425fb15SMikko Perttunen }; 13945425fb15SMikko Perttunen 13955425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1396d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 13975425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 13985425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 13995425fb15SMikko Perttunen #address-cells = <1>; 14005425fb15SMikko Perttunen #size-cells = <0>; 14015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 14025425fb15SMikko Perttunen clock-names = "div-clk"; 14035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 14045425fb15SMikko Perttunen reset-names = "i2c"; 14055425fb15SMikko Perttunen status = "disabled"; 14065425fb15SMikko Perttunen }; 14075425fb15SMikko Perttunen 14085425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1409d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14105425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 14115425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 14125425fb15SMikko Perttunen #address-cells = <1>; 14135425fb15SMikko Perttunen #size-cells = <0>; 14145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 14155425fb15SMikko Perttunen clock-names = "div-clk"; 14165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 14175425fb15SMikko Perttunen reset-names = "i2c"; 14185425fb15SMikko Perttunen status = "disabled"; 14195425fb15SMikko Perttunen }; 14205425fb15SMikko Perttunen 14215425fb15SMikko Perttunen uartc: serial@c280000 { 14225425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14235425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 14245425fb15SMikko Perttunen reg-shift = <2>; 14255425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 14265425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 14275425fb15SMikko Perttunen clock-names = "serial"; 14285425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 14295425fb15SMikko Perttunen reset-names = "serial"; 14305425fb15SMikko Perttunen status = "disabled"; 14315425fb15SMikko Perttunen }; 14325425fb15SMikko Perttunen 14335425fb15SMikko Perttunen uartg: serial@c290000 { 14345425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14355425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 14365425fb15SMikko Perttunen reg-shift = <2>; 14375425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 14385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 14395425fb15SMikko Perttunen clock-names = "serial"; 14405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 14415425fb15SMikko Perttunen reset-names = "serial"; 14425425fb15SMikko Perttunen status = "disabled"; 14435425fb15SMikko Perttunen }; 14445425fb15SMikko Perttunen 144537e5a31dSThierry Reding rtc: rtc@c2a0000 { 144637e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 144737e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 144837e5a31dSThierry Reding interrupt-parent = <&pmc>; 144937e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 145037e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 145137e5a31dSThierry Reding clock-names = "rtc"; 145237e5a31dSThierry Reding status = "disabled"; 145337e5a31dSThierry Reding }; 145437e5a31dSThierry Reding 14554d286331SThierry Reding gpio_aon: gpio@c2f0000 { 14564d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 14574d286331SThierry Reding reg-names = "security", "gpio"; 14584d286331SThierry Reding reg = <0xc2f0000 0x1000>, 14594d286331SThierry Reding <0xc2f1000 0x1000>; 14600a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 14610a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 14620a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 14630a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 14644d286331SThierry Reding gpio-controller; 14654d286331SThierry Reding #gpio-cells = <2>; 14664d286331SThierry Reding interrupt-controller; 14674d286331SThierry Reding #interrupt-cells = <2>; 14684d286331SThierry Reding }; 14694d286331SThierry Reding 14706a574ec7SThierry Reding pwm4: pwm@c340000 { 14716a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 14726a574ec7SThierry Reding "nvidia,tegra186-pwm"; 14736a574ec7SThierry Reding reg = <0xc340000 0x10000>; 14746a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 14756a574ec7SThierry Reding clock-names = "pwm"; 14766a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 14776a574ec7SThierry Reding reset-names = "pwm"; 14786a574ec7SThierry Reding status = "disabled"; 14796a574ec7SThierry Reding #pwm-cells = <2>; 14806a574ec7SThierry Reding }; 14816a574ec7SThierry Reding 148238ecf1e5SThierry Reding pmc: pmc@c360000 { 14835425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 14845425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 14855425fb15SMikko Perttunen <0x0c370000 0x10000>, 14865425fb15SMikko Perttunen <0x0c380000 0x10000>, 14875425fb15SMikko Perttunen <0x0c390000 0x10000>, 14885425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 14895425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 149038ecf1e5SThierry Reding 149138ecf1e5SThierry Reding #interrupt-cells = <2>; 149238ecf1e5SThierry Reding interrupt-controller; 1493ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1494ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1495ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1496ff21087eSPrathamesh Shete }; 1497ff21087eSPrathamesh Shete 1498ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1499ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1500ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1501ff21087eSPrathamesh Shete }; 1502ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1503ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1504ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1505ff21087eSPrathamesh Shete }; 1506ff21087eSPrathamesh Shete 1507ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1508ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1509ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1510ff21087eSPrathamesh Shete }; 1511ff21087eSPrathamesh Shete 15125425fb15SMikko Perttunen }; 15133db6d3baSThierry Reding 1514e762232fSJon Hunter iommu@10000000 { 1515e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1516e762232fSJon Hunter reg = <0x10000000 0x800000>; 1517e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1518e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1519e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1520e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1521e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1522e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1523e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1524e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1525e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1526e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1527e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1528e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1529e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1530e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1531e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1532e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1533e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1534e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1535e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1536e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1537e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1538e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1539e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1540e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1541e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1542e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1543e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1544e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1545e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1546e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1547e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1548e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1549e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1550e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1551e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1552e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1553e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1554e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1555e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1556e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1557e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1558e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1559e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1560e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1582e762232fSJon Hunter stream-match-mask = <0x7f80>; 1583e762232fSJon Hunter #global-interrupts = <1>; 1584e762232fSJon Hunter #iommu-cells = <1>; 1585e762232fSJon Hunter 1586e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1587e762232fSJon Hunter status = "okay"; 1588e762232fSJon Hunter }; 1589e762232fSJon Hunter 1590c7289b1cSThierry Reding smmu: iommu@12000000 { 1591c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1592c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1593c7289b1cSThierry Reding <0x11000000 0x800000>; 1594c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1595c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1596c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1597c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1598c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1599c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1600c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1601c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1602c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1603c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1604c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1605c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1606c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1607c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1608c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1609c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1610c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1611c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1612c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1613c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1614c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1615c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1616c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1617c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1618c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1619c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1620c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1621c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1622c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1623c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1624c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1625c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1626c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1627c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1628c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1629c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1630c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1631c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1632c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1633c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1634c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1635c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1636c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1637c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1639c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1660c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1661c7289b1cSThierry Reding #global-interrupts = <2>; 1662c7289b1cSThierry Reding #iommu-cells = <1>; 1663c7289b1cSThierry Reding 1664c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1665c7289b1cSThierry Reding status = "okay"; 1666c7289b1cSThierry Reding }; 1667c7289b1cSThierry Reding 16683db6d3baSThierry Reding host1x@13e00000 { 1669ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 16703db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 16713db6d3baSThierry Reding <0x13e10000 0x10000>; 16723db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 16733db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 16743db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1675052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 16763db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 16773db6d3baSThierry Reding clock-names = "host1x"; 16783db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 16793db6d3baSThierry Reding reset-names = "host1x"; 16803db6d3baSThierry Reding 16813db6d3baSThierry Reding #address-cells = <1>; 16823db6d3baSThierry Reding #size-cells = <1>; 16833db6d3baSThierry Reding 16843db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1685d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1686d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1687c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 16883db6d3baSThierry Reding 168978a05873SMikko Perttunen nvdec@15140000 { 169078a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 169178a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 169278a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 169378a05873SMikko Perttunen clock-names = "nvdec"; 169478a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 169578a05873SMikko Perttunen reset-names = "nvdec"; 169678a05873SMikko Perttunen 169778a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 169878a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 169978a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 170078a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 170178a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 170278a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 170378a05873SMikko Perttunen dma-coherent; 170478a05873SMikko Perttunen 170578a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 170678a05873SMikko Perttunen }; 170778a05873SMikko Perttunen 17083db6d3baSThierry Reding display-hub@15200000 { 1709aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1710611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 17113db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 17123db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 17133db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 17143db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 17153db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 17163db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 17173db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 17183db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 17193db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 17203db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 17213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 17223db6d3baSThierry Reding clock-names = "disp", "hub"; 17233db6d3baSThierry Reding status = "disabled"; 17243db6d3baSThierry Reding 17253db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17263db6d3baSThierry Reding 17273db6d3baSThierry Reding #address-cells = <1>; 17283db6d3baSThierry Reding #size-cells = <1>; 17293db6d3baSThierry Reding 17303db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 17313db6d3baSThierry Reding 17323db6d3baSThierry Reding display@15200000 { 17333db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17343db6d3baSThierry Reding reg = <0x15200000 0x10000>; 17353db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 17363db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 17373db6d3baSThierry Reding clock-names = "dc"; 17383db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 17393db6d3baSThierry Reding reset-names = "dc"; 17403db6d3baSThierry Reding 17413db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1742d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1743d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1744d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17453db6d3baSThierry Reding 17463db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17473db6d3baSThierry Reding nvidia,head = <0>; 17483db6d3baSThierry Reding }; 17493db6d3baSThierry Reding 17503db6d3baSThierry Reding display@15210000 { 17513db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17523db6d3baSThierry Reding reg = <0x15210000 0x10000>; 17533db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 17543db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 17553db6d3baSThierry Reding clock-names = "dc"; 17563db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 17573db6d3baSThierry Reding reset-names = "dc"; 17583db6d3baSThierry Reding 17593db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1760d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1761d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1762d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17633db6d3baSThierry Reding 17643db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17653db6d3baSThierry Reding nvidia,head = <1>; 17663db6d3baSThierry Reding }; 17673db6d3baSThierry Reding 17683db6d3baSThierry Reding display@15220000 { 17693db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17703db6d3baSThierry Reding reg = <0x15220000 0x10000>; 17713db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 17723db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 17733db6d3baSThierry Reding clock-names = "dc"; 17743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 17753db6d3baSThierry Reding reset-names = "dc"; 17763db6d3baSThierry Reding 17773db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1778d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1779d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1780d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17813db6d3baSThierry Reding 17823db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17833db6d3baSThierry Reding nvidia,head = <2>; 17843db6d3baSThierry Reding }; 17853db6d3baSThierry Reding 17863db6d3baSThierry Reding display@15230000 { 17873db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17883db6d3baSThierry Reding reg = <0x15230000 0x10000>; 17893db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 17903db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 17913db6d3baSThierry Reding clock-names = "dc"; 17923db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 17933db6d3baSThierry Reding reset-names = "dc"; 17943db6d3baSThierry Reding 17953db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1796d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1797d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1798d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17993db6d3baSThierry Reding 18003db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18013db6d3baSThierry Reding nvidia,head = <3>; 18023db6d3baSThierry Reding }; 18033db6d3baSThierry Reding }; 18043db6d3baSThierry Reding 18058d424ec2SThierry Reding vic@15340000 { 18068d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 18078d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 18088d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 18098d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 18108d424ec2SThierry Reding clock-names = "vic"; 18118d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 18128d424ec2SThierry Reding reset-names = "vic"; 18138d424ec2SThierry Reding 18148d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1815d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1816d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1817d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1818c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 1819a52280c8SJon Hunter dma-coherent; 18208d424ec2SThierry Reding }; 18218d424ec2SThierry Reding 1822f7eb2785SJon Hunter nvjpg@15380000 { 1823f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 1824f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1825f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1826f7eb2785SJon Hunter clock-names = "nvjpg"; 1827f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 1828f7eb2785SJon Hunter reset-names = "nvjpg"; 1829f7eb2785SJon Hunter 1830f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1831f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1832f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1833f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1834f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 1835f7eb2785SJon Hunter dma-coherent; 1836f7eb2785SJon Hunter }; 1837f7eb2785SJon Hunter 183878a05873SMikko Perttunen nvdec@15480000 { 183978a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 184078a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 184178a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 184278a05873SMikko Perttunen clock-names = "nvdec"; 184378a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 184478a05873SMikko Perttunen reset-names = "nvdec"; 184578a05873SMikko Perttunen 184678a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 184778a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 184878a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 184978a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 185078a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 185178a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 185278a05873SMikko Perttunen dma-coherent; 185378a05873SMikko Perttunen 185478a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 185578a05873SMikko Perttunen }; 185678a05873SMikko Perttunen 1857f7eb2785SJon Hunter nvenc@154c0000 { 1858f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 1859f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1860f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 1861f7eb2785SJon Hunter clock-names = "nvenc"; 1862f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 1863f7eb2785SJon Hunter reset-names = "nvenc"; 1864f7eb2785SJon Hunter 1865f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1866f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1867f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1868f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1869f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 1870f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 1871f7eb2785SJon Hunter dma-coherent; 1872f7eb2785SJon Hunter 1873f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 1874f7eb2785SJon Hunter }; 1875f7eb2785SJon Hunter 18763db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 18773db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 18783db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 18793db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 18803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 18813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 18823db6d3baSThierry Reding clock-names = "dpaux", "parent"; 18833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 18843db6d3baSThierry Reding reset-names = "dpaux"; 18853db6d3baSThierry Reding status = "disabled"; 18863db6d3baSThierry Reding 18873db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18883db6d3baSThierry Reding 18893db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 18903db6d3baSThierry Reding groups = "dpaux-io"; 18913db6d3baSThierry Reding function = "aux"; 18923db6d3baSThierry Reding }; 18933db6d3baSThierry Reding 18943db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 18953db6d3baSThierry Reding groups = "dpaux-io"; 18963db6d3baSThierry Reding function = "i2c"; 18973db6d3baSThierry Reding }; 18983db6d3baSThierry Reding 18993db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 19003db6d3baSThierry Reding groups = "dpaux-io"; 19013db6d3baSThierry Reding function = "off"; 19023db6d3baSThierry Reding }; 19033db6d3baSThierry Reding 19043db6d3baSThierry Reding i2c-bus { 19053db6d3baSThierry Reding #address-cells = <1>; 19063db6d3baSThierry Reding #size-cells = <0>; 19073db6d3baSThierry Reding }; 19083db6d3baSThierry Reding }; 19093db6d3baSThierry Reding 19103db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 19113db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19123db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 19133db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 19143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 19153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19163db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 19183db6d3baSThierry Reding reset-names = "dpaux"; 19193db6d3baSThierry Reding status = "disabled"; 19203db6d3baSThierry Reding 19213db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19223db6d3baSThierry Reding 19233db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 19243db6d3baSThierry Reding groups = "dpaux-io"; 19253db6d3baSThierry Reding function = "aux"; 19263db6d3baSThierry Reding }; 19273db6d3baSThierry Reding 19283db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 19293db6d3baSThierry Reding groups = "dpaux-io"; 19303db6d3baSThierry Reding function = "i2c"; 19313db6d3baSThierry Reding }; 19323db6d3baSThierry Reding 19333db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 19343db6d3baSThierry Reding groups = "dpaux-io"; 19353db6d3baSThierry Reding function = "off"; 19363db6d3baSThierry Reding }; 19373db6d3baSThierry Reding 19383db6d3baSThierry Reding i2c-bus { 19393db6d3baSThierry Reding #address-cells = <1>; 19403db6d3baSThierry Reding #size-cells = <0>; 19413db6d3baSThierry Reding }; 19423db6d3baSThierry Reding }; 19433db6d3baSThierry Reding 19443db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 19453db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19463db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 19473db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 19483db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 19493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19503db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19513db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 19523db6d3baSThierry Reding reset-names = "dpaux"; 19533db6d3baSThierry Reding status = "disabled"; 19543db6d3baSThierry Reding 19553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19563db6d3baSThierry Reding 19573db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 19583db6d3baSThierry Reding groups = "dpaux-io"; 19593db6d3baSThierry Reding function = "aux"; 19603db6d3baSThierry Reding }; 19613db6d3baSThierry Reding 19623db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 19633db6d3baSThierry Reding groups = "dpaux-io"; 19643db6d3baSThierry Reding function = "i2c"; 19653db6d3baSThierry Reding }; 19663db6d3baSThierry Reding 19673db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 19683db6d3baSThierry Reding groups = "dpaux-io"; 19693db6d3baSThierry Reding function = "off"; 19703db6d3baSThierry Reding }; 19713db6d3baSThierry Reding 19723db6d3baSThierry Reding i2c-bus { 19733db6d3baSThierry Reding #address-cells = <1>; 19743db6d3baSThierry Reding #size-cells = <0>; 19753db6d3baSThierry Reding }; 19763db6d3baSThierry Reding }; 19773db6d3baSThierry Reding 19783db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 19793db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19803db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 19813db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 19823db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 19833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19843db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19853db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 19863db6d3baSThierry Reding reset-names = "dpaux"; 19873db6d3baSThierry Reding status = "disabled"; 19883db6d3baSThierry Reding 19893db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19903db6d3baSThierry Reding 19913db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 19923db6d3baSThierry Reding groups = "dpaux-io"; 19933db6d3baSThierry Reding function = "aux"; 19943db6d3baSThierry Reding }; 19953db6d3baSThierry Reding 19963db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 19973db6d3baSThierry Reding groups = "dpaux-io"; 19983db6d3baSThierry Reding function = "i2c"; 19993db6d3baSThierry Reding }; 20003db6d3baSThierry Reding 20013db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 20023db6d3baSThierry Reding groups = "dpaux-io"; 20033db6d3baSThierry Reding function = "off"; 20043db6d3baSThierry Reding }; 20053db6d3baSThierry Reding 20063db6d3baSThierry Reding i2c-bus { 20073db6d3baSThierry Reding #address-cells = <1>; 20083db6d3baSThierry Reding #size-cells = <0>; 20093db6d3baSThierry Reding }; 20103db6d3baSThierry Reding }; 20113db6d3baSThierry Reding 2012f7eb2785SJon Hunter nvenc@15a80000 { 2013f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2014f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2015f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2016f7eb2785SJon Hunter clock-names = "nvenc"; 2017f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2018f7eb2785SJon Hunter reset-names = "nvenc"; 2019f7eb2785SJon Hunter 2020f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2021f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2022f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2023f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2024f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2025f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2026f7eb2785SJon Hunter dma-coherent; 2027f7eb2785SJon Hunter 2028f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2029f7eb2785SJon Hunter }; 2030f7eb2785SJon Hunter 20313db6d3baSThierry Reding sor0: sor@15b00000 { 20323db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20333db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 20343db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 20353db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 20363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 20373db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 20383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 20413db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20423db6d3baSThierry Reding "pad"; 20433db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 20443db6d3baSThierry Reding reset-names = "sor"; 20453db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 20463db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 20473db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 20483db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20493db6d3baSThierry Reding status = "disabled"; 20503db6d3baSThierry Reding 20513db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20523db6d3baSThierry Reding nvidia,interface = <0>; 20533db6d3baSThierry Reding }; 20543db6d3baSThierry Reding 20553db6d3baSThierry Reding sor1: sor@15b40000 { 20563db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2057939e7430SThierry Reding reg = <0x15b40000 0x40000>; 20583db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 20593db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 20603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 20613db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 20623db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20633db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 20653db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20663db6d3baSThierry Reding "pad"; 20673db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 20683db6d3baSThierry Reding reset-names = "sor"; 20693db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 20703db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 20713db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 20723db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20733db6d3baSThierry Reding status = "disabled"; 20743db6d3baSThierry Reding 20753db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20763db6d3baSThierry Reding nvidia,interface = <1>; 20773db6d3baSThierry Reding }; 20783db6d3baSThierry Reding 20793db6d3baSThierry Reding sor2: sor@15b80000 { 20803db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20813db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 20823db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 20833db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 20843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 20853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 20863db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20883db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 20893db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20903db6d3baSThierry Reding "pad"; 20913db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 20923db6d3baSThierry Reding reset-names = "sor"; 20933db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 20943db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 20953db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 20963db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20973db6d3baSThierry Reding status = "disabled"; 20983db6d3baSThierry Reding 20993db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21003db6d3baSThierry Reding nvidia,interface = <2>; 21013db6d3baSThierry Reding }; 21023db6d3baSThierry Reding 21033db6d3baSThierry Reding sor3: sor@15bc0000 { 21043db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21053db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 21063db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 21073db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 21083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 21093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 21103db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 21133db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21143db6d3baSThierry Reding "pad"; 21153db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 21163db6d3baSThierry Reding reset-names = "sor"; 21173db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 21183db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 21193db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 21203db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21213db6d3baSThierry Reding status = "disabled"; 21223db6d3baSThierry Reding 21233db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21243db6d3baSThierry Reding nvidia,interface = <3>; 21253db6d3baSThierry Reding }; 21263db6d3baSThierry Reding }; 21270f134e39SThierry Reding 21280f134e39SThierry Reding gpu@17000000 { 21290f134e39SThierry Reding compatible = "nvidia,gv11b"; 2130818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2131818ae79aSThierry Reding <0x18000000 0x1000000>; 21320f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 21330f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 21340f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 21350f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 21360f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 21370f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 21380f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 21390f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 21400f134e39SThierry Reding reset-names = "gpu"; 21410f134e39SThierry Reding dma-coherent; 21420f134e39SThierry Reding 21430f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 21440f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 21450f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 21460f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 21470f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 21480f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 21490f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 21500f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 21510f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 21520f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 21530f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 21540f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 21550f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 21560f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 21570f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 21580f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 21590f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 21600f134e39SThierry Reding }; 21615425fb15SMikko Perttunen }; 21625425fb15SMikko Perttunen 21632602c32fSVidya Sagar pcie@14100000 { 2164f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 21652602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2166644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2167644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2168644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2169644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 21702602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 21712602c32fSVidya Sagar 21722602c32fSVidya Sagar status = "disabled"; 21732602c32fSVidya Sagar 21742602c32fSVidya Sagar #address-cells = <3>; 21752602c32fSVidya Sagar #size-cells = <2>; 21762602c32fSVidya Sagar device_type = "pci"; 21772602c32fSVidya Sagar num-lanes = <1>; 21782602c32fSVidya Sagar linux,pci-domain = <1>; 21792602c32fSVidya Sagar 21802602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 21812602c32fSVidya Sagar clock-names = "core"; 21822602c32fSVidya Sagar 21832602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 21842602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 21852602c32fSVidya Sagar reset-names = "apb", "core"; 21862602c32fSVidya Sagar 21872602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21882602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 21892602c32fSVidya Sagar interrupt-names = "intr", "msi"; 21902602c32fSVidya Sagar 21912602c32fSVidya Sagar #interrupt-cells = <1>; 21922602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21932602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 21942602c32fSVidya Sagar 21952602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 21962602c32fSVidya Sagar 21972602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21982602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21992602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22002602c32fSVidya Sagar 22012602c32fSVidya Sagar bus-range = <0x0 0xff>; 2202d5237c7cSThierry Reding 22038a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22048a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22058a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2206d5237c7cSThierry Reding 2207d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2208d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2209ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2210ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2211ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2212ba02920cSVidya Sagar dma-coherent; 22132602c32fSVidya Sagar }; 22142602c32fSVidya Sagar 22152602c32fSVidya Sagar pcie@14120000 { 2216f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22172602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2218644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2219644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2220644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2221644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22222602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22232602c32fSVidya Sagar 22242602c32fSVidya Sagar status = "disabled"; 22252602c32fSVidya Sagar 22262602c32fSVidya Sagar #address-cells = <3>; 22272602c32fSVidya Sagar #size-cells = <2>; 22282602c32fSVidya Sagar device_type = "pci"; 22292602c32fSVidya Sagar num-lanes = <1>; 22302602c32fSVidya Sagar linux,pci-domain = <2>; 22312602c32fSVidya Sagar 22322602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 22332602c32fSVidya Sagar clock-names = "core"; 22342602c32fSVidya Sagar 22352602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 22362602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 22372602c32fSVidya Sagar reset-names = "apb", "core"; 22382602c32fSVidya Sagar 22392602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22402602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22412602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22422602c32fSVidya Sagar 22432602c32fSVidya Sagar #interrupt-cells = <1>; 22442602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22452602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 22462602c32fSVidya Sagar 22472602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 22482602c32fSVidya Sagar 22492602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22502602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22512602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22522602c32fSVidya Sagar 22532602c32fSVidya Sagar bus-range = <0x0 0xff>; 2254d5237c7cSThierry Reding 22558a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22568a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22578a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2258d5237c7cSThierry Reding 2259d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2260d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2261ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2262ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2263ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2264ba02920cSVidya Sagar dma-coherent; 22652602c32fSVidya Sagar }; 22662602c32fSVidya Sagar 22672602c32fSVidya Sagar pcie@14140000 { 2268f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22692602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2270644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2271644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2272644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2273644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22742602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22752602c32fSVidya Sagar 22762602c32fSVidya Sagar status = "disabled"; 22772602c32fSVidya Sagar 22782602c32fSVidya Sagar #address-cells = <3>; 22792602c32fSVidya Sagar #size-cells = <2>; 22802602c32fSVidya Sagar device_type = "pci"; 22812602c32fSVidya Sagar num-lanes = <1>; 22822602c32fSVidya Sagar linux,pci-domain = <3>; 22832602c32fSVidya Sagar 22842602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 22852602c32fSVidya Sagar clock-names = "core"; 22862602c32fSVidya Sagar 22872602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 22882602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 22892602c32fSVidya Sagar reset-names = "apb", "core"; 22902602c32fSVidya Sagar 22912602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22922602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22932602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22942602c32fSVidya Sagar 22952602c32fSVidya Sagar #interrupt-cells = <1>; 22962602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22972602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 22982602c32fSVidya Sagar 22992602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 23002602c32fSVidya Sagar 23012602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23022602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23032602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23042602c32fSVidya Sagar 23052602c32fSVidya Sagar bus-range = <0x0 0xff>; 2306d5237c7cSThierry Reding 23078a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23088a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 23098a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2310d5237c7cSThierry Reding 2311d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2312d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2313ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2314ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2315ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2316ba02920cSVidya Sagar dma-coherent; 23172602c32fSVidya Sagar }; 23182602c32fSVidya Sagar 23192602c32fSVidya Sagar pcie@14160000 { 2320f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23212602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2322644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2323644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2324644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2325644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23262602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23272602c32fSVidya Sagar 23282602c32fSVidya Sagar status = "disabled"; 23292602c32fSVidya Sagar 23302602c32fSVidya Sagar #address-cells = <3>; 23312602c32fSVidya Sagar #size-cells = <2>; 23322602c32fSVidya Sagar device_type = "pci"; 23332602c32fSVidya Sagar num-lanes = <4>; 23342602c32fSVidya Sagar linux,pci-domain = <4>; 23352602c32fSVidya Sagar 23362602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 23372602c32fSVidya Sagar clock-names = "core"; 23382602c32fSVidya Sagar 23392602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 23402602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 23412602c32fSVidya Sagar reset-names = "apb", "core"; 23422602c32fSVidya Sagar 23432602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23442602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23452602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23462602c32fSVidya Sagar 23472602c32fSVidya Sagar #interrupt-cells = <1>; 23482602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23492602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 23502602c32fSVidya Sagar 23512602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 23522602c32fSVidya Sagar 23532602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23542602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23552602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23562602c32fSVidya Sagar 23572602c32fSVidya Sagar bus-range = <0x0 0xff>; 2358d5237c7cSThierry Reding 23598a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 23608a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 23618a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2362d5237c7cSThierry Reding 2363d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2364d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2365ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2366ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2367ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2368ba02920cSVidya Sagar dma-coherent; 23692602c32fSVidya Sagar }; 23702602c32fSVidya Sagar 23712602c32fSVidya Sagar pcie@14180000 { 2372f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23732602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2374644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2375644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2376644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2377644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23782602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23792602c32fSVidya Sagar 23802602c32fSVidya Sagar status = "disabled"; 23812602c32fSVidya Sagar 23822602c32fSVidya Sagar #address-cells = <3>; 23832602c32fSVidya Sagar #size-cells = <2>; 23842602c32fSVidya Sagar device_type = "pci"; 23852602c32fSVidya Sagar num-lanes = <8>; 23862602c32fSVidya Sagar linux,pci-domain = <0>; 23872602c32fSVidya Sagar 23882602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 23892602c32fSVidya Sagar clock-names = "core"; 23902602c32fSVidya Sagar 23912602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 23922602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 23932602c32fSVidya Sagar reset-names = "apb", "core"; 23942602c32fSVidya Sagar 23952602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23962602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23972602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23982602c32fSVidya Sagar 23992602c32fSVidya Sagar #interrupt-cells = <1>; 24002602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24012602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 24022602c32fSVidya Sagar 24032602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 24042602c32fSVidya Sagar 24052602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24062602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24072602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24082602c32fSVidya Sagar 24092602c32fSVidya Sagar bus-range = <0x0 0xff>; 2410d5237c7cSThierry Reding 24118a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24128a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24138a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2414d5237c7cSThierry Reding 2415d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2416d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2417ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2418ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2419ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2420ba02920cSVidya Sagar dma-coherent; 24212602c32fSVidya Sagar }; 24222602c32fSVidya Sagar 24232602c32fSVidya Sagar pcie@141a0000 { 2424f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24252602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2426644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2427644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2428644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2429644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24302602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24312602c32fSVidya Sagar 24322602c32fSVidya Sagar status = "disabled"; 24332602c32fSVidya Sagar 24342602c32fSVidya Sagar #address-cells = <3>; 24352602c32fSVidya Sagar #size-cells = <2>; 24362602c32fSVidya Sagar device_type = "pci"; 24372602c32fSVidya Sagar num-lanes = <8>; 24382602c32fSVidya Sagar linux,pci-domain = <5>; 24392602c32fSVidya Sagar 2440dbb72e2cSVidya Sagar pinctrl-names = "default"; 2441dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2442dbb72e2cSVidya Sagar 2443c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2444c453cc9eSThierry Reding clock-names = "core"; 24452602c32fSVidya Sagar 24462602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 24472602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 24482602c32fSVidya Sagar reset-names = "apb", "core"; 24492602c32fSVidya Sagar 24502602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24512602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24522602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24532602c32fSVidya Sagar 24542602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 24552602c32fSVidya Sagar 24562602c32fSVidya Sagar #interrupt-cells = <1>; 24572602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24582602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 24592602c32fSVidya Sagar 24602602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24612602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24622602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24632602c32fSVidya Sagar 24642602c32fSVidya Sagar bus-range = <0x0 0xff>; 2465d5237c7cSThierry Reding 24668a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24678a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24688a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2469d5237c7cSThierry Reding 2470d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2471d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2472ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2473ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2474ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2475ba02920cSVidya Sagar dma-coherent; 24762602c32fSVidya Sagar }; 24772602c32fSVidya Sagar 2478b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2479bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 24800c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2481644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2482644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2483644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2484644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 24850c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 24860c988b73SVidya Sagar 24870c988b73SVidya Sagar status = "disabled"; 24880c988b73SVidya Sagar 24890c988b73SVidya Sagar num-lanes = <4>; 24900c988b73SVidya Sagar num-ib-windows = <2>; 24910c988b73SVidya Sagar num-ob-windows = <8>; 24920c988b73SVidya Sagar 24930c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 24940c988b73SVidya Sagar clock-names = "core"; 24950c988b73SVidya Sagar 24960c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 24970c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 24980c988b73SVidya Sagar reset-names = "apb", "core"; 24990c988b73SVidya Sagar 25000c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25010c988b73SVidya Sagar interrupt-names = "intr"; 25020c988b73SVidya Sagar 25030c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 25040c988b73SVidya Sagar 25050c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25060c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25070c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2508ba02920cSVidya Sagar 2509ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2510ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2511ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2512ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2513ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2514ba02920cSVidya Sagar dma-coherent; 25150c988b73SVidya Sagar }; 25160c988b73SVidya Sagar 2517b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2518bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25190c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2520644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2521644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2522644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2523644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25240c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25250c988b73SVidya Sagar 25260c988b73SVidya Sagar status = "disabled"; 25270c988b73SVidya Sagar 25280c988b73SVidya Sagar num-lanes = <8>; 25290c988b73SVidya Sagar num-ib-windows = <2>; 25300c988b73SVidya Sagar num-ob-windows = <8>; 25310c988b73SVidya Sagar 25320c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 25330c988b73SVidya Sagar clock-names = "core"; 25340c988b73SVidya Sagar 25350c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 25360c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 25370c988b73SVidya Sagar reset-names = "apb", "core"; 25380c988b73SVidya Sagar 25390c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25400c988b73SVidya Sagar interrupt-names = "intr"; 25410c988b73SVidya Sagar 25420c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 25430c988b73SVidya Sagar 25440c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25450c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25460c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2547ba02920cSVidya Sagar 2548ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2549ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2550ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2551ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2552ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2553ba02920cSVidya Sagar dma-coherent; 25540c988b73SVidya Sagar }; 25550c988b73SVidya Sagar 2556b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2557bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25580c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2559644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2560644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2561644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2562644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25630c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25640c988b73SVidya Sagar 25650c988b73SVidya Sagar status = "disabled"; 25660c988b73SVidya Sagar 25670c988b73SVidya Sagar num-lanes = <8>; 25680c988b73SVidya Sagar num-ib-windows = <2>; 25690c988b73SVidya Sagar num-ob-windows = <8>; 25700c988b73SVidya Sagar 25710c988b73SVidya Sagar pinctrl-names = "default"; 25720c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 25730c988b73SVidya Sagar 25740c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 25750c988b73SVidya Sagar clock-names = "core"; 25760c988b73SVidya Sagar 25770c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 25780c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 25790c988b73SVidya Sagar reset-names = "apb", "core"; 25800c988b73SVidya Sagar 25810c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25820c988b73SVidya Sagar interrupt-names = "intr"; 25830c988b73SVidya Sagar 25840c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 25850c988b73SVidya Sagar 25860c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25870c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25880c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2589ba02920cSVidya Sagar 2590ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2591ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2592ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2593ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2594ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2595ba02920cSVidya Sagar dma-coherent; 25960c988b73SVidya Sagar }; 25970c988b73SVidya Sagar 2598e867fe41SThierry Reding sram@40000000 { 25995425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 26005425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 26015425fb15SMikko Perttunen #address-cells = <1>; 26025425fb15SMikko Perttunen #size-cells = <1>; 26035425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 26045425fb15SMikko Perttunen 2605e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 26065425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 26075425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 26085425fb15SMikko Perttunen pool; 26095425fb15SMikko Perttunen }; 26105425fb15SMikko Perttunen 2611e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 26125425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 26135425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 26145425fb15SMikko Perttunen pool; 26155425fb15SMikko Perttunen }; 26165425fb15SMikko Perttunen }; 26175425fb15SMikko Perttunen 26185425fb15SMikko Perttunen bpmp: bpmp { 26195425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 26205425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 26215425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 26227fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 26235425fb15SMikko Perttunen #clock-cells = <1>; 26245425fb15SMikko Perttunen #reset-cells = <1>; 26255425fb15SMikko Perttunen #power-domain-cells = <1>; 2626d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2627d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2628d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2629d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2630d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2631c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 26325425fb15SMikko Perttunen 26335425fb15SMikko Perttunen bpmp_i2c: i2c { 26345425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 26355425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 26365425fb15SMikko Perttunen #address-cells = <1>; 26375425fb15SMikko Perttunen #size-cells = <0>; 26385425fb15SMikko Perttunen }; 26395425fb15SMikko Perttunen 26405425fb15SMikko Perttunen bpmp_thermal: thermal { 26415425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 26425425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 26435425fb15SMikko Perttunen }; 26445425fb15SMikko Perttunen }; 26455425fb15SMikko Perttunen 26467780a034SMikko Perttunen cpus { 2647d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2648d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 26497780a034SMikko Perttunen #address-cells = <1>; 26507780a034SMikko Perttunen #size-cells = <0>; 26517780a034SMikko Perttunen 2652b45d322cSThierry Reding cpu0_0: cpu@0 { 265331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26547780a034SMikko Perttunen device_type = "cpu"; 2655b45d322cSThierry Reding reg = <0x000>; 26567780a034SMikko Perttunen enable-method = "psci"; 2657b45d322cSThierry Reding i-cache-size = <131072>; 2658b45d322cSThierry Reding i-cache-line-size = <64>; 2659b45d322cSThierry Reding i-cache-sets = <512>; 2660b45d322cSThierry Reding d-cache-size = <65536>; 2661b45d322cSThierry Reding d-cache-line-size = <64>; 2662b45d322cSThierry Reding d-cache-sets = <256>; 2663b45d322cSThierry Reding next-level-cache = <&l2c_0>; 26647780a034SMikko Perttunen }; 26657780a034SMikko Perttunen 2666b45d322cSThierry Reding cpu0_1: cpu@1 { 266731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26687780a034SMikko Perttunen device_type = "cpu"; 2669b45d322cSThierry Reding reg = <0x001>; 26707780a034SMikko Perttunen enable-method = "psci"; 2671b45d322cSThierry Reding i-cache-size = <131072>; 2672b45d322cSThierry Reding i-cache-line-size = <64>; 2673b45d322cSThierry Reding i-cache-sets = <512>; 2674b45d322cSThierry Reding d-cache-size = <65536>; 2675b45d322cSThierry Reding d-cache-line-size = <64>; 2676b45d322cSThierry Reding d-cache-sets = <256>; 2677b45d322cSThierry Reding next-level-cache = <&l2c_0>; 26787780a034SMikko Perttunen }; 26797780a034SMikko Perttunen 2680b45d322cSThierry Reding cpu1_0: cpu@100 { 268131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26827780a034SMikko Perttunen device_type = "cpu"; 26837780a034SMikko Perttunen reg = <0x100>; 26847780a034SMikko Perttunen enable-method = "psci"; 2685b45d322cSThierry Reding i-cache-size = <131072>; 2686b45d322cSThierry Reding i-cache-line-size = <64>; 2687b45d322cSThierry Reding i-cache-sets = <512>; 2688b45d322cSThierry Reding d-cache-size = <65536>; 2689b45d322cSThierry Reding d-cache-line-size = <64>; 2690b45d322cSThierry Reding d-cache-sets = <256>; 2691b45d322cSThierry Reding next-level-cache = <&l2c_1>; 26927780a034SMikko Perttunen }; 26937780a034SMikko Perttunen 2694b45d322cSThierry Reding cpu1_1: cpu@101 { 269531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26967780a034SMikko Perttunen device_type = "cpu"; 26977780a034SMikko Perttunen reg = <0x101>; 26987780a034SMikko Perttunen enable-method = "psci"; 2699b45d322cSThierry Reding i-cache-size = <131072>; 2700b45d322cSThierry Reding i-cache-line-size = <64>; 2701b45d322cSThierry Reding i-cache-sets = <512>; 2702b45d322cSThierry Reding d-cache-size = <65536>; 2703b45d322cSThierry Reding d-cache-line-size = <64>; 2704b45d322cSThierry Reding d-cache-sets = <256>; 2705b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27067780a034SMikko Perttunen }; 27077780a034SMikko Perttunen 2708b45d322cSThierry Reding cpu2_0: cpu@200 { 270931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27107780a034SMikko Perttunen device_type = "cpu"; 27117780a034SMikko Perttunen reg = <0x200>; 27127780a034SMikko Perttunen enable-method = "psci"; 2713b45d322cSThierry Reding i-cache-size = <131072>; 2714b45d322cSThierry Reding i-cache-line-size = <64>; 2715b45d322cSThierry Reding i-cache-sets = <512>; 2716b45d322cSThierry Reding d-cache-size = <65536>; 2717b45d322cSThierry Reding d-cache-line-size = <64>; 2718b45d322cSThierry Reding d-cache-sets = <256>; 2719b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27207780a034SMikko Perttunen }; 27217780a034SMikko Perttunen 2722b45d322cSThierry Reding cpu2_1: cpu@201 { 272331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27247780a034SMikko Perttunen device_type = "cpu"; 27257780a034SMikko Perttunen reg = <0x201>; 27267780a034SMikko Perttunen enable-method = "psci"; 2727b45d322cSThierry Reding i-cache-size = <131072>; 2728b45d322cSThierry Reding i-cache-line-size = <64>; 2729b45d322cSThierry Reding i-cache-sets = <512>; 2730b45d322cSThierry Reding d-cache-size = <65536>; 2731b45d322cSThierry Reding d-cache-line-size = <64>; 2732b45d322cSThierry Reding d-cache-sets = <256>; 2733b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27347780a034SMikko Perttunen }; 27357780a034SMikko Perttunen 2736b45d322cSThierry Reding cpu3_0: cpu@300 { 273731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27387780a034SMikko Perttunen device_type = "cpu"; 2739b45d322cSThierry Reding reg = <0x300>; 27407780a034SMikko Perttunen enable-method = "psci"; 2741b45d322cSThierry Reding i-cache-size = <131072>; 2742b45d322cSThierry Reding i-cache-line-size = <64>; 2743b45d322cSThierry Reding i-cache-sets = <512>; 2744b45d322cSThierry Reding d-cache-size = <65536>; 2745b45d322cSThierry Reding d-cache-line-size = <64>; 2746b45d322cSThierry Reding d-cache-sets = <256>; 2747b45d322cSThierry Reding next-level-cache = <&l2c_3>; 27487780a034SMikko Perttunen }; 27497780a034SMikko Perttunen 2750b45d322cSThierry Reding cpu3_1: cpu@301 { 275131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27527780a034SMikko Perttunen device_type = "cpu"; 2753b45d322cSThierry Reding reg = <0x301>; 27547780a034SMikko Perttunen enable-method = "psci"; 2755b45d322cSThierry Reding i-cache-size = <131072>; 2756b45d322cSThierry Reding i-cache-line-size = <64>; 2757b45d322cSThierry Reding i-cache-sets = <512>; 2758b45d322cSThierry Reding d-cache-size = <65536>; 2759b45d322cSThierry Reding d-cache-line-size = <64>; 2760b45d322cSThierry Reding d-cache-sets = <256>; 2761b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2762b45d322cSThierry Reding }; 2763b45d322cSThierry Reding 2764b45d322cSThierry Reding cpu-map { 2765b45d322cSThierry Reding cluster0 { 2766b45d322cSThierry Reding core0 { 2767b45d322cSThierry Reding cpu = <&cpu0_0>; 2768b45d322cSThierry Reding }; 2769b45d322cSThierry Reding 2770b45d322cSThierry Reding core1 { 2771b45d322cSThierry Reding cpu = <&cpu0_1>; 2772b45d322cSThierry Reding }; 2773b45d322cSThierry Reding }; 2774b45d322cSThierry Reding 2775b45d322cSThierry Reding cluster1 { 2776b45d322cSThierry Reding core0 { 2777b45d322cSThierry Reding cpu = <&cpu1_0>; 2778b45d322cSThierry Reding }; 2779b45d322cSThierry Reding 2780b45d322cSThierry Reding core1 { 2781b45d322cSThierry Reding cpu = <&cpu1_1>; 2782b45d322cSThierry Reding }; 2783b45d322cSThierry Reding }; 2784b45d322cSThierry Reding 2785b45d322cSThierry Reding cluster2 { 2786b45d322cSThierry Reding core0 { 2787b45d322cSThierry Reding cpu = <&cpu2_0>; 2788b45d322cSThierry Reding }; 2789b45d322cSThierry Reding 2790b45d322cSThierry Reding core1 { 2791b45d322cSThierry Reding cpu = <&cpu2_1>; 2792b45d322cSThierry Reding }; 2793b45d322cSThierry Reding }; 2794b45d322cSThierry Reding 2795b45d322cSThierry Reding cluster3 { 2796b45d322cSThierry Reding core0 { 2797b45d322cSThierry Reding cpu = <&cpu3_0>; 2798b45d322cSThierry Reding }; 2799b45d322cSThierry Reding 2800b45d322cSThierry Reding core1 { 2801b45d322cSThierry Reding cpu = <&cpu3_1>; 2802b45d322cSThierry Reding }; 2803b45d322cSThierry Reding }; 2804b45d322cSThierry Reding }; 2805b45d322cSThierry Reding 2806b45d322cSThierry Reding l2c_0: l2-cache0 { 2807b45d322cSThierry Reding cache-size = <2097152>; 2808b45d322cSThierry Reding cache-line-size = <64>; 2809b45d322cSThierry Reding cache-sets = <2048>; 2810b45d322cSThierry Reding next-level-cache = <&l3c>; 2811b45d322cSThierry Reding }; 2812b45d322cSThierry Reding 2813b45d322cSThierry Reding l2c_1: l2-cache1 { 2814b45d322cSThierry Reding cache-size = <2097152>; 2815b45d322cSThierry Reding cache-line-size = <64>; 2816b45d322cSThierry Reding cache-sets = <2048>; 2817b45d322cSThierry Reding next-level-cache = <&l3c>; 2818b45d322cSThierry Reding }; 2819b45d322cSThierry Reding 2820b45d322cSThierry Reding l2c_2: l2-cache2 { 2821b45d322cSThierry Reding cache-size = <2097152>; 2822b45d322cSThierry Reding cache-line-size = <64>; 2823b45d322cSThierry Reding cache-sets = <2048>; 2824b45d322cSThierry Reding next-level-cache = <&l3c>; 2825b45d322cSThierry Reding }; 2826b45d322cSThierry Reding 2827b45d322cSThierry Reding l2c_3: l2-cache3 { 2828b45d322cSThierry Reding cache-size = <2097152>; 2829b45d322cSThierry Reding cache-line-size = <64>; 2830b45d322cSThierry Reding cache-sets = <2048>; 2831b45d322cSThierry Reding next-level-cache = <&l3c>; 2832b45d322cSThierry Reding }; 2833b45d322cSThierry Reding 2834b45d322cSThierry Reding l3c: l3-cache { 2835b45d322cSThierry Reding cache-size = <4194304>; 2836b45d322cSThierry Reding cache-line-size = <64>; 2837b45d322cSThierry Reding cache-sets = <4096>; 28387780a034SMikko Perttunen }; 28397780a034SMikko Perttunen }; 28407780a034SMikko Perttunen 28419e79e58fSJon Hunter pmu { 28429e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 28439e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 28449e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 28459e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 28469e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 28479e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 28489e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 28499e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 28509e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 28519e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 28529e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 28539e79e58fSJon Hunter }; 28549e79e58fSJon Hunter 28557780a034SMikko Perttunen psci { 28567780a034SMikko Perttunen compatible = "arm,psci-1.0"; 28577780a034SMikko Perttunen status = "okay"; 28587780a034SMikko Perttunen method = "smc"; 28597780a034SMikko Perttunen }; 28607780a034SMikko Perttunen 28615b4f6323SSameer Pujar sound { 28625b4f6323SSameer Pujar status = "disabled"; 28635b4f6323SSameer Pujar 28645b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 28655b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 28665b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 28675b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 28685b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 28695b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 28705b4f6323SSameer Pujar assigned-clock-parents = <0>, 28715b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 28725b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 28735b4f6323SSameer Pujar /* 28745b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 28755b4f6323SSameer Pujar * for this to work and oscillate between base rates required 28765b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 28775b4f6323SSameer Pujar */ 28785b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 287934e0fc34SThierry Reding 288034e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 288134e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 288234e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 288334e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 28845b4f6323SSameer Pujar }; 28855b4f6323SSameer Pujar 288699d9bde5SThierry Reding tcu: serial { 2887a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2888a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2889a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2890a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2891a38570c2SMikko Perttunen }; 2892a38570c2SMikko Perttunen 2893686ba009SThierry Reding thermal-zones { 2894fe57ff53SThierry Reding cpu-thermal { 2895fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2896686ba009SThierry Reding status = "disabled"; 2897686ba009SThierry Reding }; 2898686ba009SThierry Reding 2899fe57ff53SThierry Reding gpu-thermal { 2900fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2901686ba009SThierry Reding status = "disabled"; 2902686ba009SThierry Reding }; 2903686ba009SThierry Reding 2904fe57ff53SThierry Reding aux-thermal { 2905fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2906686ba009SThierry Reding status = "disabled"; 2907686ba009SThierry Reding }; 2908686ba009SThierry Reding 2909fe57ff53SThierry Reding pllx-thermal { 2910fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2911686ba009SThierry Reding status = "disabled"; 2912686ba009SThierry Reding }; 2913686ba009SThierry Reding 2914fe57ff53SThierry Reding ao-thermal { 2915fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2916686ba009SThierry Reding status = "disabled"; 2917686ba009SThierry Reding }; 2918686ba009SThierry Reding 2919fe57ff53SThierry Reding tj-thermal { 2920fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2921686ba009SThierry Reding status = "disabled"; 2922686ba009SThierry Reding }; 2923686ba009SThierry Reding }; 2924686ba009SThierry Reding 29255425fb15SMikko Perttunen timer { 29265425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 29275425fb15SMikko Perttunen interrupts = <GIC_PPI 13 29285425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29295425fb15SMikko Perttunen <GIC_PPI 14 29305425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29315425fb15SMikko Perttunen <GIC_PPI 11 29325425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29335425fb15SMikko Perttunen <GIC_PPI 10 29345425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 29355425fb15SMikko Perttunen interrupt-parent = <&gic>; 2936b30be673SThierry Reding always-on; 29375425fb15SMikko Perttunen }; 29385425fb15SMikko Perttunen}; 2939