15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 65c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 66f89b58ceSMikko Perttunen status = "disabled"; 67f89b58ceSMikko Perttunen 68f89b58ceSMikko Perttunen snps,write-requests = <1>; 69f89b58ceSMikko Perttunen snps,read-requests = <3>; 70f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 71f89b58ceSMikko Perttunen snps,txpbl = <16>; 72f89b58ceSMikko Perttunen snps,rxpbl = <8>; 73f89b58ceSMikko Perttunen }; 74f89b58ceSMikko Perttunen 751aaa7698SThierry Reding aconnect@2900000 { 765d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 775d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 785d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 795d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 805d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 815d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 825d2249ddSSameer Pujar #address-cells = <1>; 835d2249ddSSameer Pujar #size-cells = <1>; 845d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 855d2249ddSSameer Pujar status = "disabled"; 865d2249ddSSameer Pujar 87177208f7SSameer Pujar adma: dma-controller@2930000 { 885d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 895d2249ddSSameer Pujar "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1395d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1405d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1415d2249ddSSameer Pujar clock-names = "clk"; 1425d2249ddSSameer Pujar status = "disabled"; 1435d2249ddSSameer Pujar }; 144177208f7SSameer Pujar 145177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 146177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 147177208f7SSameer Pujar "nvidia,tegra186-ahub"; 148177208f7SSameer Pujar reg = <0x02900800 0x800>; 149177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 150177208f7SSameer Pujar clock-names = "ahub"; 151177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 152177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 153177208f7SSameer Pujar #address-cells = <1>; 154177208f7SSameer Pujar #size-cells = <1>; 155177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 156177208f7SSameer Pujar status = "disabled"; 157177208f7SSameer Pujar 158177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 159177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 160177208f7SSameer Pujar "nvidia,tegra186-admaif"; 161177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 162177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 163177208f7SSameer Pujar <&adma 2>, <&adma 2>, 164177208f7SSameer Pujar <&adma 3>, <&adma 3>, 165177208f7SSameer Pujar <&adma 4>, <&adma 4>, 166177208f7SSameer Pujar <&adma 5>, <&adma 5>, 167177208f7SSameer Pujar <&adma 6>, <&adma 6>, 168177208f7SSameer Pujar <&adma 7>, <&adma 7>, 169177208f7SSameer Pujar <&adma 8>, <&adma 8>, 170177208f7SSameer Pujar <&adma 9>, <&adma 9>, 171177208f7SSameer Pujar <&adma 10>, <&adma 10>, 172177208f7SSameer Pujar <&adma 11>, <&adma 11>, 173177208f7SSameer Pujar <&adma 12>, <&adma 12>, 174177208f7SSameer Pujar <&adma 13>, <&adma 13>, 175177208f7SSameer Pujar <&adma 14>, <&adma 14>, 176177208f7SSameer Pujar <&adma 15>, <&adma 15>, 177177208f7SSameer Pujar <&adma 16>, <&adma 16>, 178177208f7SSameer Pujar <&adma 17>, <&adma 17>, 179177208f7SSameer Pujar <&adma 18>, <&adma 18>, 180177208f7SSameer Pujar <&adma 19>, <&adma 19>, 181177208f7SSameer Pujar <&adma 20>, <&adma 20>; 182177208f7SSameer Pujar dma-names = "rx1", "tx1", 183177208f7SSameer Pujar "rx2", "tx2", 184177208f7SSameer Pujar "rx3", "tx3", 185177208f7SSameer Pujar "rx4", "tx4", 186177208f7SSameer Pujar "rx5", "tx5", 187177208f7SSameer Pujar "rx6", "tx6", 188177208f7SSameer Pujar "rx7", "tx7", 189177208f7SSameer Pujar "rx8", "tx8", 190177208f7SSameer Pujar "rx9", "tx9", 191177208f7SSameer Pujar "rx10", "tx10", 192177208f7SSameer Pujar "rx11", "tx11", 193177208f7SSameer Pujar "rx12", "tx12", 194177208f7SSameer Pujar "rx13", "tx13", 195177208f7SSameer Pujar "rx14", "tx14", 196177208f7SSameer Pujar "rx15", "tx15", 197177208f7SSameer Pujar "rx16", "tx16", 198177208f7SSameer Pujar "rx17", "tx17", 199177208f7SSameer Pujar "rx18", "tx18", 200177208f7SSameer Pujar "rx19", "tx19", 201177208f7SSameer Pujar "rx20", "tx20"; 202177208f7SSameer Pujar status = "disabled"; 203177208f7SSameer Pujar }; 204177208f7SSameer Pujar 205177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 206177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 207177208f7SSameer Pujar "nvidia,tegra210-i2s"; 208177208f7SSameer Pujar reg = <0x2901000 0x100>; 209177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 210177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 211177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 212177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 213177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 214177208f7SSameer Pujar assigned-clock-rates = <1536000>; 215177208f7SSameer Pujar sound-name-prefix = "I2S1"; 216177208f7SSameer Pujar status = "disabled"; 217177208f7SSameer Pujar }; 218177208f7SSameer Pujar 219177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 220177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 221177208f7SSameer Pujar "nvidia,tegra210-i2s"; 222177208f7SSameer Pujar reg = <0x2901100 0x100>; 223177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 224177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 225177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 226177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 227177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 228177208f7SSameer Pujar assigned-clock-rates = <1536000>; 229177208f7SSameer Pujar sound-name-prefix = "I2S2"; 230177208f7SSameer Pujar status = "disabled"; 231177208f7SSameer Pujar }; 232177208f7SSameer Pujar 233177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 234177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 235177208f7SSameer Pujar "nvidia,tegra210-i2s"; 236177208f7SSameer Pujar reg = <0x2901200 0x100>; 237177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 238177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 239177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 240177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 241177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 242177208f7SSameer Pujar assigned-clock-rates = <1536000>; 243177208f7SSameer Pujar sound-name-prefix = "I2S3"; 244177208f7SSameer Pujar status = "disabled"; 245177208f7SSameer Pujar }; 246177208f7SSameer Pujar 247177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 248177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 249177208f7SSameer Pujar "nvidia,tegra210-i2s"; 250177208f7SSameer Pujar reg = <0x2901300 0x100>; 251177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 252177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 253177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 254177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 255177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256177208f7SSameer Pujar assigned-clock-rates = <1536000>; 257177208f7SSameer Pujar sound-name-prefix = "I2S4"; 258177208f7SSameer Pujar status = "disabled"; 259177208f7SSameer Pujar }; 260177208f7SSameer Pujar 261177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 262177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 263177208f7SSameer Pujar "nvidia,tegra210-i2s"; 264177208f7SSameer Pujar reg = <0x2901400 0x100>; 265177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 266177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 267177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 268177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 269177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270177208f7SSameer Pujar assigned-clock-rates = <1536000>; 271177208f7SSameer Pujar sound-name-prefix = "I2S5"; 272177208f7SSameer Pujar status = "disabled"; 273177208f7SSameer Pujar }; 274177208f7SSameer Pujar 275177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 276177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 277177208f7SSameer Pujar "nvidia,tegra210-i2s"; 278177208f7SSameer Pujar reg = <0x2901500 0x100>; 279177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 280177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 281177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 282177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 283177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284177208f7SSameer Pujar assigned-clock-rates = <1536000>; 285177208f7SSameer Pujar sound-name-prefix = "I2S6"; 286177208f7SSameer Pujar status = "disabled"; 287177208f7SSameer Pujar }; 288177208f7SSameer Pujar 289177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 290177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 291177208f7SSameer Pujar "nvidia,tegra210-dmic"; 292177208f7SSameer Pujar reg = <0x2904000 0x100>; 293177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 294177208f7SSameer Pujar clock-names = "dmic"; 295177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 296177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 297177208f7SSameer Pujar assigned-clock-rates = <3072000>; 298177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 299177208f7SSameer Pujar status = "disabled"; 300177208f7SSameer Pujar }; 301177208f7SSameer Pujar 302177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 303177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 304177208f7SSameer Pujar "nvidia,tegra210-dmic"; 305177208f7SSameer Pujar reg = <0x2904100 0x100>; 306177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 307177208f7SSameer Pujar clock-names = "dmic"; 308177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 309177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 310177208f7SSameer Pujar assigned-clock-rates = <3072000>; 311177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 312177208f7SSameer Pujar status = "disabled"; 313177208f7SSameer Pujar }; 314177208f7SSameer Pujar 315177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 316177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 317177208f7SSameer Pujar "nvidia,tegra210-dmic"; 318177208f7SSameer Pujar reg = <0x2904200 0x100>; 319177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 320177208f7SSameer Pujar clock-names = "dmic"; 321177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 322177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 323177208f7SSameer Pujar assigned-clock-rates = <3072000>; 324177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 325177208f7SSameer Pujar status = "disabled"; 326177208f7SSameer Pujar }; 327177208f7SSameer Pujar 328177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 329177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 330177208f7SSameer Pujar "nvidia,tegra210-dmic"; 331177208f7SSameer Pujar reg = <0x2904300 0x100>; 332177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 333177208f7SSameer Pujar clock-names = "dmic"; 334177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 335177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 336177208f7SSameer Pujar assigned-clock-rates = <3072000>; 337177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 338177208f7SSameer Pujar status = "disabled"; 339177208f7SSameer Pujar }; 340177208f7SSameer Pujar 341177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 342177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 343177208f7SSameer Pujar "nvidia,tegra186-dspk"; 344177208f7SSameer Pujar reg = <0x2905000 0x100>; 345177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 346177208f7SSameer Pujar clock-names = "dspk"; 347177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 348177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 349177208f7SSameer Pujar assigned-clock-rates = <12288000>; 350177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 351177208f7SSameer Pujar status = "disabled"; 352177208f7SSameer Pujar }; 353177208f7SSameer Pujar 354177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 355177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 356177208f7SSameer Pujar "nvidia,tegra186-dspk"; 357177208f7SSameer Pujar reg = <0x2905100 0x100>; 358177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 359177208f7SSameer Pujar clock-names = "dspk"; 360177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 361177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 362177208f7SSameer Pujar assigned-clock-rates = <12288000>; 363177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 364177208f7SSameer Pujar status = "disabled"; 365177208f7SSameer Pujar }; 366177208f7SSameer Pujar }; 3675d2249ddSSameer Pujar }; 3685d2249ddSSameer Pujar 369dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 370dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 371644c569dSThierry Reding reg = <0x2430000 0x17000>, 372644c569dSThierry Reding <0xc300000 0x4000>; 373dbb72e2cSVidya Sagar 374dbb72e2cSVidya Sagar status = "okay"; 375dbb72e2cSVidya Sagar 376dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 377dbb72e2cSVidya Sagar pex_rst { 378dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 379dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 380dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 381dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3826b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 383dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 384dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 385dbb72e2cSVidya Sagar }; 386dbb72e2cSVidya Sagar }; 387dbb72e2cSVidya Sagar 388dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 389dbb72e2cSVidya Sagar clkreq { 390dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 391dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 392dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 393dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3946b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 395dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 396dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 397dbb72e2cSVidya Sagar }; 398dbb72e2cSVidya Sagar }; 399dbb72e2cSVidya Sagar }; 400dbb72e2cSVidya Sagar 401be9b887fSThierry Reding mc: memory-controller@2c00000 { 402be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 403be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 404be9b887fSThierry Reding <0x02b80000 0x040000>, 405be9b887fSThierry Reding <0x01700000 0x100000>; 4068613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 407d5237c7cSThierry Reding #interconnect-cells = <1>; 408be9b887fSThierry Reding status = "disabled"; 409be9b887fSThierry Reding 410be9b887fSThierry Reding #address-cells = <2>; 411be9b887fSThierry Reding #size-cells = <2>; 412be9b887fSThierry Reding 413be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 414be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 415be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 416be9b887fSThierry Reding 417be9b887fSThierry Reding /* 418be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 419be9b887fSThierry Reding * controller selects the XBAR format used when memory 420be9b887fSThierry Reding * is accessed. This is used to transparently access 421be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 422be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 423be9b887fSThierry Reding * 424be9b887fSThierry Reding * As a consequence, the operating system must ensure 425be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 426be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 427be9b887fSThierry Reding * devices require access to the XBAR switch, their 428be9b887fSThierry Reding * drivers must set this bit explicitly. 429be9b887fSThierry Reding * 430be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 431be9b887fSThierry Reding */ 432be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 433be9b887fSThierry Reding 434be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 435be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 436be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 437be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 438be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 439be9b887fSThierry Reding clock-names = "emc"; 440be9b887fSThierry Reding 441d5237c7cSThierry Reding #interconnect-cells = <0>; 442d5237c7cSThierry Reding 443be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 444be9b887fSThierry Reding }; 445be9b887fSThierry Reding }; 446be9b887fSThierry Reding 4475425fb15SMikko Perttunen uarta: serial@3100000 { 4485425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4495425fb15SMikko Perttunen reg = <0x03100000 0x40>; 4505425fb15SMikko Perttunen reg-shift = <2>; 4515425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 4535425fb15SMikko Perttunen clock-names = "serial"; 4545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 4555425fb15SMikko Perttunen reset-names = "serial"; 4565425fb15SMikko Perttunen status = "disabled"; 4575425fb15SMikko Perttunen }; 4585425fb15SMikko Perttunen 4595425fb15SMikko Perttunen uartb: serial@3110000 { 4605425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4615425fb15SMikko Perttunen reg = <0x03110000 0x40>; 4625425fb15SMikko Perttunen reg-shift = <2>; 4635425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4645425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 4655425fb15SMikko Perttunen clock-names = "serial"; 4665425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 4675425fb15SMikko Perttunen reset-names = "serial"; 4685425fb15SMikko Perttunen status = "disabled"; 4695425fb15SMikko Perttunen }; 4705425fb15SMikko Perttunen 4715425fb15SMikko Perttunen uartd: serial@3130000 { 4725425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4735425fb15SMikko Perttunen reg = <0x03130000 0x40>; 4745425fb15SMikko Perttunen reg-shift = <2>; 4755425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 4765425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 4775425fb15SMikko Perttunen clock-names = "serial"; 4785425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 4795425fb15SMikko Perttunen reset-names = "serial"; 4805425fb15SMikko Perttunen status = "disabled"; 4815425fb15SMikko Perttunen }; 4825425fb15SMikko Perttunen 4835425fb15SMikko Perttunen uarte: serial@3140000 { 4845425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4855425fb15SMikko Perttunen reg = <0x03140000 0x40>; 4865425fb15SMikko Perttunen reg-shift = <2>; 4875425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 4885425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 4895425fb15SMikko Perttunen clock-names = "serial"; 4905425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 4915425fb15SMikko Perttunen reset-names = "serial"; 4925425fb15SMikko Perttunen status = "disabled"; 4935425fb15SMikko Perttunen }; 4945425fb15SMikko Perttunen 4955425fb15SMikko Perttunen uartf: serial@3150000 { 4965425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4975425fb15SMikko Perttunen reg = <0x03150000 0x40>; 4985425fb15SMikko Perttunen reg-shift = <2>; 4995425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 5005425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 5015425fb15SMikko Perttunen clock-names = "serial"; 5025425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 5035425fb15SMikko Perttunen reset-names = "serial"; 5045425fb15SMikko Perttunen status = "disabled"; 5055425fb15SMikko Perttunen }; 5065425fb15SMikko Perttunen 5075425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 508d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5095425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 5105425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 5115425fb15SMikko Perttunen #address-cells = <1>; 5125425fb15SMikko Perttunen #size-cells = <0>; 5135425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 5145425fb15SMikko Perttunen clock-names = "div-clk"; 5155425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 5165425fb15SMikko Perttunen reset-names = "i2c"; 5175425fb15SMikko Perttunen status = "disabled"; 5185425fb15SMikko Perttunen }; 5195425fb15SMikko Perttunen 5205425fb15SMikko Perttunen uarth: serial@3170000 { 5215425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5225425fb15SMikko Perttunen reg = <0x03170000 0x40>; 5235425fb15SMikko Perttunen reg-shift = <2>; 5245425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 5255425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 5265425fb15SMikko Perttunen clock-names = "serial"; 5275425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 5285425fb15SMikko Perttunen reset-names = "serial"; 5295425fb15SMikko Perttunen status = "disabled"; 5305425fb15SMikko Perttunen }; 5315425fb15SMikko Perttunen 5325425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 533d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5345425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 5355425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5365425fb15SMikko Perttunen #address-cells = <1>; 5375425fb15SMikko Perttunen #size-cells = <0>; 5385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 5395425fb15SMikko Perttunen clock-names = "div-clk"; 5405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 5415425fb15SMikko Perttunen reset-names = "i2c"; 5425425fb15SMikko Perttunen status = "disabled"; 5435425fb15SMikko Perttunen }; 5445425fb15SMikko Perttunen 5455425fb15SMikko Perttunen /* shares pads with dpaux1 */ 5465425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 547d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5485425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 5495425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 5505425fb15SMikko Perttunen #address-cells = <1>; 5515425fb15SMikko Perttunen #size-cells = <0>; 5525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 5535425fb15SMikko Perttunen clock-names = "div-clk"; 5545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 5555425fb15SMikko Perttunen reset-names = "i2c"; 556a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 557a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 558a4131561SThierry Reding pinctrl-names = "default", "idle"; 5595425fb15SMikko Perttunen status = "disabled"; 5605425fb15SMikko Perttunen }; 5615425fb15SMikko Perttunen 5625425fb15SMikko Perttunen /* shares pads with dpaux0 */ 5635425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 564d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5655425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 5665425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 5675425fb15SMikko Perttunen #address-cells = <1>; 5685425fb15SMikko Perttunen #size-cells = <0>; 5695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 5705425fb15SMikko Perttunen clock-names = "div-clk"; 5715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 5725425fb15SMikko Perttunen reset-names = "i2c"; 573a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 574a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 575a4131561SThierry Reding pinctrl-names = "default", "idle"; 5765425fb15SMikko Perttunen status = "disabled"; 5775425fb15SMikko Perttunen }; 5785425fb15SMikko Perttunen 579a4131561SThierry Reding /* shares pads with dpaux2 */ 580a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 581d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5825425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 5835425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 5845425fb15SMikko Perttunen #address-cells = <1>; 5855425fb15SMikko Perttunen #size-cells = <0>; 5865425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 5875425fb15SMikko Perttunen clock-names = "div-clk"; 5885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 5895425fb15SMikko Perttunen reset-names = "i2c"; 590a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 591a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 592a4131561SThierry Reding pinctrl-names = "default", "idle"; 5935425fb15SMikko Perttunen status = "disabled"; 5945425fb15SMikko Perttunen }; 5955425fb15SMikko Perttunen 596a4131561SThierry Reding /* shares pads with dpaux3 */ 597a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 598d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5995425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 6005425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 6015425fb15SMikko Perttunen #address-cells = <1>; 6025425fb15SMikko Perttunen #size-cells = <0>; 6035425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 6045425fb15SMikko Perttunen clock-names = "div-clk"; 6055425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 6065425fb15SMikko Perttunen reset-names = "i2c"; 607a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 608a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 609a4131561SThierry Reding pinctrl-names = "default", "idle"; 6105425fb15SMikko Perttunen status = "disabled"; 6115425fb15SMikko Perttunen }; 6125425fb15SMikko Perttunen 61396ded827SSowjanya Komatineni spi@3270000 { 61496ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 61596ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 61696ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 61796ded827SSowjanya Komatineni #address-cells = <1>; 61896ded827SSowjanya Komatineni #size-cells = <0>; 61996ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 62096ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 62196ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 62296ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 62396ded827SSowjanya Komatineni reset-names = "qspi"; 62496ded827SSowjanya Komatineni status = "disabled"; 62596ded827SSowjanya Komatineni }; 62696ded827SSowjanya Komatineni 62796ded827SSowjanya Komatineni spi@3300000 { 62896ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 62996ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 63096ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 63196ded827SSowjanya Komatineni #address-cells = <1>; 63296ded827SSowjanya Komatineni #size-cells = <0>; 63396ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 63496ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 63596ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 63696ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 63796ded827SSowjanya Komatineni reset-names = "qspi"; 63896ded827SSowjanya Komatineni status = "disabled"; 63996ded827SSowjanya Komatineni }; 64096ded827SSowjanya Komatineni 6416a574ec7SThierry Reding pwm1: pwm@3280000 { 6426a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6436a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6446a574ec7SThierry Reding reg = <0x3280000 0x10000>; 6456a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 6466a574ec7SThierry Reding clock-names = "pwm"; 6476a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 6486a574ec7SThierry Reding reset-names = "pwm"; 6496a574ec7SThierry Reding status = "disabled"; 6506a574ec7SThierry Reding #pwm-cells = <2>; 6516a574ec7SThierry Reding }; 6526a574ec7SThierry Reding 6536a574ec7SThierry Reding pwm2: pwm@3290000 { 6546a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6556a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6566a574ec7SThierry Reding reg = <0x3290000 0x10000>; 6576a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 6586a574ec7SThierry Reding clock-names = "pwm"; 6596a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 6606a574ec7SThierry Reding reset-names = "pwm"; 6616a574ec7SThierry Reding status = "disabled"; 6626a574ec7SThierry Reding #pwm-cells = <2>; 6636a574ec7SThierry Reding }; 6646a574ec7SThierry Reding 6656a574ec7SThierry Reding pwm3: pwm@32a0000 { 6666a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6676a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6686a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 6696a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 6706a574ec7SThierry Reding clock-names = "pwm"; 6716a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 6726a574ec7SThierry Reding reset-names = "pwm"; 6736a574ec7SThierry Reding status = "disabled"; 6746a574ec7SThierry Reding #pwm-cells = <2>; 6756a574ec7SThierry Reding }; 6766a574ec7SThierry Reding 6776a574ec7SThierry Reding pwm5: pwm@32c0000 { 6786a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6796a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6806a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 6816a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 6826a574ec7SThierry Reding clock-names = "pwm"; 6836a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 6846a574ec7SThierry Reding reset-names = "pwm"; 6856a574ec7SThierry Reding status = "disabled"; 6866a574ec7SThierry Reding #pwm-cells = <2>; 6876a574ec7SThierry Reding }; 6886a574ec7SThierry Reding 6896a574ec7SThierry Reding pwm6: pwm@32d0000 { 6906a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6916a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6926a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 6936a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 6946a574ec7SThierry Reding clock-names = "pwm"; 6956a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 6966a574ec7SThierry Reding reset-names = "pwm"; 6976a574ec7SThierry Reding status = "disabled"; 6986a574ec7SThierry Reding #pwm-cells = <2>; 6996a574ec7SThierry Reding }; 7006a574ec7SThierry Reding 7016a574ec7SThierry Reding pwm7: pwm@32e0000 { 7026a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7036a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7046a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 7056a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 7066a574ec7SThierry Reding clock-names = "pwm"; 7076a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 7086a574ec7SThierry Reding reset-names = "pwm"; 7096a574ec7SThierry Reding status = "disabled"; 7106a574ec7SThierry Reding #pwm-cells = <2>; 7116a574ec7SThierry Reding }; 7126a574ec7SThierry Reding 7136a574ec7SThierry Reding pwm8: pwm@32f0000 { 7146a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7156a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7166a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 7176a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 7186a574ec7SThierry Reding clock-names = "pwm"; 7196a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 7206a574ec7SThierry Reding reset-names = "pwm"; 7216a574ec7SThierry Reding status = "disabled"; 7226a574ec7SThierry Reding #pwm-cells = <2>; 7236a574ec7SThierry Reding }; 7246a574ec7SThierry Reding 72567bb17f6SThierry Reding sdmmc1: mmc@3400000 { 7262c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7275425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 7285425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 729c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 730c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 731c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7325425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 7335425fb15SMikko Perttunen reset-names = "sdhci"; 734d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 735d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 736d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 737c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 7384e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 7394e0f1229SSowjanya Komatineni <0x07>; 7404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7414e0f1229SSowjanya Komatineni <0x07>; 7424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7434e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7444e0f1229SSowjanya Komatineni <0x07>; 7454e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7464e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7474e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7484e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7495425fb15SMikko Perttunen status = "disabled"; 7505425fb15SMikko Perttunen }; 7515425fb15SMikko Perttunen 75267bb17f6SThierry Reding sdmmc3: mmc@3440000 { 7532c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7545425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 7555425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 756c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 757c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 758c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 7605425fb15SMikko Perttunen reset-names = "sdhci"; 761d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 762d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 763d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 764c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 7654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 7664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 7674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 7684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7694e0f1229SSowjanya Komatineni <0x07>; 7704e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7724e0f1229SSowjanya Komatineni <0x07>; 7734e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7744e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7754e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7764e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7775425fb15SMikko Perttunen status = "disabled"; 7785425fb15SMikko Perttunen }; 7795425fb15SMikko Perttunen 78067bb17f6SThierry Reding sdmmc4: mmc@3460000 { 7812c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7825425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 7835425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 784c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 785c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 786c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 787351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 788351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 789351648d0SSowjanya Komatineni assigned-clock-parents = 790351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 7915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 7925425fb15SMikko Perttunen reset-names = "sdhci"; 793d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 794d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 795d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 796c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 7974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 7984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 7994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 8004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 8014e0f1229SSowjanya Komatineni <0x0a>; 8024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 8034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 8044e0f1229SSowjanya Komatineni <0x0a>; 8054e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 8064e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 8074e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 808dfd3cb6fSSowjanya Komatineni supports-cqe; 8095425fb15SMikko Perttunen status = "disabled"; 8105425fb15SMikko Perttunen }; 8115425fb15SMikko Perttunen 8124878cc0cSSameer Pujar hda@3510000 { 8134878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 8144878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 8154878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 8164878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 81748f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 81848f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 81948f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 8204878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 82148f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 82248f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 82348f6e195SSameer Pujar reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 8244878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 825d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 826d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 827d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 828c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 8294878cc0cSSameer Pujar status = "disabled"; 8304878cc0cSSameer Pujar }; 8314878cc0cSSameer Pujar 832fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 833fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 834fab7a039SJC Kuo reg = <0x03520000 0x1000>, 835fab7a039SJC Kuo <0x03540000 0x1000>; 836fab7a039SJC Kuo reg-names = "padctl", "ao"; 8376450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 838fab7a039SJC Kuo 839fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 840fab7a039SJC Kuo reset-names = "padctl"; 841fab7a039SJC Kuo 842fab7a039SJC Kuo status = "disabled"; 843fab7a039SJC Kuo 844fab7a039SJC Kuo pads { 845fab7a039SJC Kuo usb2 { 846fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 847fab7a039SJC Kuo clock-names = "trk"; 848fab7a039SJC Kuo 849fab7a039SJC Kuo lanes { 850fab7a039SJC Kuo usb2-0 { 851fab7a039SJC Kuo nvidia,function = "xusb"; 852fab7a039SJC Kuo status = "disabled"; 853fab7a039SJC Kuo #phy-cells = <0>; 854fab7a039SJC Kuo }; 855fab7a039SJC Kuo 856fab7a039SJC Kuo usb2-1 { 857fab7a039SJC Kuo nvidia,function = "xusb"; 858fab7a039SJC Kuo status = "disabled"; 859fab7a039SJC Kuo #phy-cells = <0>; 860fab7a039SJC Kuo }; 861fab7a039SJC Kuo 862fab7a039SJC Kuo usb2-2 { 863fab7a039SJC Kuo nvidia,function = "xusb"; 864fab7a039SJC Kuo status = "disabled"; 865fab7a039SJC Kuo #phy-cells = <0>; 866fab7a039SJC Kuo }; 867fab7a039SJC Kuo 868fab7a039SJC Kuo usb2-3 { 869fab7a039SJC Kuo nvidia,function = "xusb"; 870fab7a039SJC Kuo status = "disabled"; 871fab7a039SJC Kuo #phy-cells = <0>; 872fab7a039SJC Kuo }; 873fab7a039SJC Kuo }; 874fab7a039SJC Kuo }; 875fab7a039SJC Kuo 876fab7a039SJC Kuo usb3 { 877fab7a039SJC Kuo lanes { 878fab7a039SJC Kuo usb3-0 { 879fab7a039SJC Kuo nvidia,function = "xusb"; 880fab7a039SJC Kuo status = "disabled"; 881fab7a039SJC Kuo #phy-cells = <0>; 882fab7a039SJC Kuo }; 883fab7a039SJC Kuo 884fab7a039SJC Kuo usb3-1 { 885fab7a039SJC Kuo nvidia,function = "xusb"; 886fab7a039SJC Kuo status = "disabled"; 887fab7a039SJC Kuo #phy-cells = <0>; 888fab7a039SJC Kuo }; 889fab7a039SJC Kuo 890fab7a039SJC Kuo usb3-2 { 891fab7a039SJC Kuo nvidia,function = "xusb"; 892fab7a039SJC Kuo status = "disabled"; 893fab7a039SJC Kuo #phy-cells = <0>; 894fab7a039SJC Kuo }; 895fab7a039SJC Kuo 896fab7a039SJC Kuo usb3-3 { 897fab7a039SJC Kuo nvidia,function = "xusb"; 898fab7a039SJC Kuo status = "disabled"; 899fab7a039SJC Kuo #phy-cells = <0>; 900fab7a039SJC Kuo }; 901fab7a039SJC Kuo }; 902fab7a039SJC Kuo }; 903fab7a039SJC Kuo }; 904fab7a039SJC Kuo 905fab7a039SJC Kuo ports { 906fab7a039SJC Kuo usb2-0 { 907fab7a039SJC Kuo status = "disabled"; 908fab7a039SJC Kuo }; 909fab7a039SJC Kuo 910fab7a039SJC Kuo usb2-1 { 911fab7a039SJC Kuo status = "disabled"; 912fab7a039SJC Kuo }; 913fab7a039SJC Kuo 914fab7a039SJC Kuo usb2-2 { 915fab7a039SJC Kuo status = "disabled"; 916fab7a039SJC Kuo }; 917fab7a039SJC Kuo 918fab7a039SJC Kuo usb2-3 { 919fab7a039SJC Kuo status = "disabled"; 920fab7a039SJC Kuo }; 921fab7a039SJC Kuo 922fab7a039SJC Kuo usb3-0 { 923fab7a039SJC Kuo status = "disabled"; 924fab7a039SJC Kuo }; 925fab7a039SJC Kuo 926fab7a039SJC Kuo usb3-1 { 927fab7a039SJC Kuo status = "disabled"; 928fab7a039SJC Kuo }; 929fab7a039SJC Kuo 930fab7a039SJC Kuo usb3-2 { 931fab7a039SJC Kuo status = "disabled"; 932fab7a039SJC Kuo }; 933fab7a039SJC Kuo 934fab7a039SJC Kuo usb3-3 { 935fab7a039SJC Kuo status = "disabled"; 936fab7a039SJC Kuo }; 937fab7a039SJC Kuo }; 938fab7a039SJC Kuo }; 939fab7a039SJC Kuo 940bc8788b2SNagarjuna Kristam usb@3550000 { 941bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 942bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 943bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 944bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 945bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 946bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 947bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 948bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 949bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 950bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 951c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 952c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 953c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 954c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 955bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 956bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 957bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 958bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 959bc8788b2SNagarjuna Kristam status = "disabled"; 960bc8788b2SNagarjuna Kristam }; 961bc8788b2SNagarjuna Kristam 962fab7a039SJC Kuo usb@3610000 { 963fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 964fab7a039SJC Kuo reg = <0x03610000 0x40000>, 965fab7a039SJC Kuo <0x03600000 0x10000>; 966fab7a039SJC Kuo reg-names = "hcd", "fpci"; 967fab7a039SJC Kuo 968fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 969a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 970fab7a039SJC Kuo 971fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 972fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 973fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 974fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 975fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 976fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 977fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 978fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 979fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 980fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 981fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 982fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 983fab7a039SJC Kuo "pll_e"; 984c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 985c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 986c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 987c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 988fab7a039SJC Kuo 989fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 990fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 991fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 992fab7a039SJC Kuo 993fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 994fab7a039SJC Kuo status = "disabled"; 995fab7a039SJC Kuo }; 996fab7a039SJC Kuo 99709903c5eSJC Kuo fuse@3820000 { 99809903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 99909903c5eSJC Kuo reg = <0x03820000 0x10000>; 100009903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 100109903c5eSJC Kuo clock-names = "fuse"; 100209903c5eSJC Kuo }; 100309903c5eSJC Kuo 10045425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 10055425fb15SMikko Perttunen compatible = "arm,gic-400"; 10065425fb15SMikko Perttunen #interrupt-cells = <3>; 10075425fb15SMikko Perttunen interrupt-controller; 10085425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 10095425fb15SMikko Perttunen <0x03882000 0x2000>, 10105425fb15SMikko Perttunen <0x03884000 0x2000>, 10115425fb15SMikko Perttunen <0x03886000 0x2000>; 10125425fb15SMikko Perttunen interrupts = <GIC_PPI 9 10135425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10145425fb15SMikko Perttunen interrupt-parent = <&gic>; 10155425fb15SMikko Perttunen }; 10165425fb15SMikko Perttunen 1017badb80beSThierry Reding cec@3960000 { 1018badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1019badb80beSThierry Reding reg = <0x03960000 0x10000>; 1020badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1021badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1022badb80beSThierry Reding clock-names = "cec"; 1023badb80beSThierry Reding status = "disabled"; 1024badb80beSThierry Reding }; 1025badb80beSThierry Reding 10265425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1027a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 10285425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1029a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1030a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1031a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1032a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1033a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1034a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1035a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1036a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1037a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1038a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1039a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1040a38570c2SMikko Perttunen "shared7"; 1041a38570c2SMikko Perttunen #mbox-cells = <2>; 1042a38570c2SMikko Perttunen }; 1043a38570c2SMikko Perttunen 10442602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 10452602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10462602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 10472602c32fSVidya Sagar reg-names = "ctl"; 10482602c32fSVidya Sagar 10492602c32fSVidya Sagar #phy-cells = <0>; 10502602c32fSVidya Sagar }; 10512602c32fSVidya Sagar 10522602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 10532602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10542602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 10552602c32fSVidya Sagar reg-names = "ctl"; 10562602c32fSVidya Sagar 10572602c32fSVidya Sagar #phy-cells = <0>; 10582602c32fSVidya Sagar }; 10592602c32fSVidya Sagar 10602602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 10612602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10622602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 10632602c32fSVidya Sagar reg-names = "ctl"; 10642602c32fSVidya Sagar 10652602c32fSVidya Sagar #phy-cells = <0>; 10662602c32fSVidya Sagar }; 10672602c32fSVidya Sagar 10682602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 10692602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10702602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 10712602c32fSVidya Sagar reg-names = "ctl"; 10722602c32fSVidya Sagar 10732602c32fSVidya Sagar #phy-cells = <0>; 10742602c32fSVidya Sagar }; 10752602c32fSVidya Sagar 10762602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 10772602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10782602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 10792602c32fSVidya Sagar reg-names = "ctl"; 10802602c32fSVidya Sagar 10812602c32fSVidya Sagar #phy-cells = <0>; 10822602c32fSVidya Sagar }; 10832602c32fSVidya Sagar 10842602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 10852602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10862602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 10872602c32fSVidya Sagar reg-names = "ctl"; 10882602c32fSVidya Sagar 10892602c32fSVidya Sagar #phy-cells = <0>; 10902602c32fSVidya Sagar }; 10912602c32fSVidya Sagar 10922602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 10932602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10942602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 10952602c32fSVidya Sagar reg-names = "ctl"; 10962602c32fSVidya Sagar 10972602c32fSVidya Sagar #phy-cells = <0>; 10982602c32fSVidya Sagar }; 10992602c32fSVidya Sagar 11002602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 11012602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11022602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 11032602c32fSVidya Sagar reg-names = "ctl"; 11042602c32fSVidya Sagar 11052602c32fSVidya Sagar #phy-cells = <0>; 11062602c32fSVidya Sagar }; 11072602c32fSVidya Sagar 11082602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 11092602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11102602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 11112602c32fSVidya Sagar reg-names = "ctl"; 11122602c32fSVidya Sagar 11132602c32fSVidya Sagar #phy-cells = <0>; 11142602c32fSVidya Sagar }; 11152602c32fSVidya Sagar 11162602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 11172602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11182602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 11192602c32fSVidya Sagar reg-names = "ctl"; 11202602c32fSVidya Sagar 11212602c32fSVidya Sagar #phy-cells = <0>; 11222602c32fSVidya Sagar }; 11232602c32fSVidya Sagar 11242602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 11252602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11262602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 11272602c32fSVidya Sagar reg-names = "ctl"; 11282602c32fSVidya Sagar 11292602c32fSVidya Sagar #phy-cells = <0>; 11302602c32fSVidya Sagar }; 11312602c32fSVidya Sagar 11322602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 11332602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11342602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 11352602c32fSVidya Sagar reg-names = "ctl"; 11362602c32fSVidya Sagar 11372602c32fSVidya Sagar #phy-cells = <0>; 11382602c32fSVidya Sagar }; 11392602c32fSVidya Sagar 11402602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 11412602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11422602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 11432602c32fSVidya Sagar reg-names = "ctl"; 11442602c32fSVidya Sagar 11452602c32fSVidya Sagar #phy-cells = <0>; 11462602c32fSVidya Sagar }; 11472602c32fSVidya Sagar 11482602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 11492602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11502602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 11512602c32fSVidya Sagar reg-names = "ctl"; 11522602c32fSVidya Sagar 11532602c32fSVidya Sagar #phy-cells = <0>; 11542602c32fSVidya Sagar }; 11552602c32fSVidya Sagar 11562602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 11572602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11582602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 11592602c32fSVidya Sagar reg-names = "ctl"; 11602602c32fSVidya Sagar 11612602c32fSVidya Sagar #phy-cells = <0>; 11622602c32fSVidya Sagar }; 11632602c32fSVidya Sagar 11642602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 11652602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11662602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 11672602c32fSVidya Sagar reg-names = "ctl"; 11682602c32fSVidya Sagar 11692602c32fSVidya Sagar #phy-cells = <0>; 11702602c32fSVidya Sagar }; 11712602c32fSVidya Sagar 11722602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 11732602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11742602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 11752602c32fSVidya Sagar reg-names = "ctl"; 11762602c32fSVidya Sagar 11772602c32fSVidya Sagar #phy-cells = <0>; 11782602c32fSVidya Sagar }; 11792602c32fSVidya Sagar 11802602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 11812602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11822602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 11832602c32fSVidya Sagar reg-names = "ctl"; 11842602c32fSVidya Sagar 11852602c32fSVidya Sagar #phy-cells = <0>; 11862602c32fSVidya Sagar }; 11872602c32fSVidya Sagar 11882602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 11892602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11902602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 11912602c32fSVidya Sagar reg-names = "ctl"; 11922602c32fSVidya Sagar 11932602c32fSVidya Sagar #phy-cells = <0>; 11942602c32fSVidya Sagar }; 11952602c32fSVidya Sagar 11962602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 11972602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11982602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 11992602c32fSVidya Sagar reg-names = "ctl"; 12002602c32fSVidya Sagar 12012602c32fSVidya Sagar #phy-cells = <0>; 12022602c32fSVidya Sagar }; 12032602c32fSVidya Sagar 1204a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1205a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 12061741e187SDipen Patel reg = <0x0c150000 0x90000>; 1207a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1208a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1209a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1210a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1211a38570c2SMikko Perttunen /* 1212a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1213a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1214a38570c2SMikko Perttunen */ 1215a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 12165425fb15SMikko Perttunen #mbox-cells = <2>; 12175425fb15SMikko Perttunen }; 12185425fb15SMikko Perttunen 12195425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1220d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12215425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 12225425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 12235425fb15SMikko Perttunen #address-cells = <1>; 12245425fb15SMikko Perttunen #size-cells = <0>; 12255425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 12265425fb15SMikko Perttunen clock-names = "div-clk"; 12275425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 12285425fb15SMikko Perttunen reset-names = "i2c"; 12295425fb15SMikko Perttunen status = "disabled"; 12305425fb15SMikko Perttunen }; 12315425fb15SMikko Perttunen 12325425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1233d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12345425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 12355425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 12365425fb15SMikko Perttunen #address-cells = <1>; 12375425fb15SMikko Perttunen #size-cells = <0>; 12385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 12395425fb15SMikko Perttunen clock-names = "div-clk"; 12405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 12415425fb15SMikko Perttunen reset-names = "i2c"; 12425425fb15SMikko Perttunen status = "disabled"; 12435425fb15SMikko Perttunen }; 12445425fb15SMikko Perttunen 12455425fb15SMikko Perttunen uartc: serial@c280000 { 12465425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12475425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 12485425fb15SMikko Perttunen reg-shift = <2>; 12495425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 12505425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 12515425fb15SMikko Perttunen clock-names = "serial"; 12525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 12535425fb15SMikko Perttunen reset-names = "serial"; 12545425fb15SMikko Perttunen status = "disabled"; 12555425fb15SMikko Perttunen }; 12565425fb15SMikko Perttunen 12575425fb15SMikko Perttunen uartg: serial@c290000 { 12585425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12595425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 12605425fb15SMikko Perttunen reg-shift = <2>; 12615425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 12625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 12635425fb15SMikko Perttunen clock-names = "serial"; 12645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 12655425fb15SMikko Perttunen reset-names = "serial"; 12665425fb15SMikko Perttunen status = "disabled"; 12675425fb15SMikko Perttunen }; 12685425fb15SMikko Perttunen 126937e5a31dSThierry Reding rtc: rtc@c2a0000 { 127037e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 127137e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 127237e5a31dSThierry Reding interrupt-parent = <&pmc>; 127337e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 127437e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 127537e5a31dSThierry Reding clock-names = "rtc"; 127637e5a31dSThierry Reding status = "disabled"; 127737e5a31dSThierry Reding }; 127837e5a31dSThierry Reding 12794d286331SThierry Reding gpio_aon: gpio@c2f0000 { 12804d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 12814d286331SThierry Reding reg-names = "security", "gpio"; 12824d286331SThierry Reding reg = <0xc2f0000 0x1000>, 12834d286331SThierry Reding <0xc2f1000 0x1000>; 128475b5608aSThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 12854d286331SThierry Reding gpio-controller; 12864d286331SThierry Reding #gpio-cells = <2>; 12874d286331SThierry Reding interrupt-controller; 12884d286331SThierry Reding #interrupt-cells = <2>; 12894d286331SThierry Reding }; 12904d286331SThierry Reding 12916a574ec7SThierry Reding pwm4: pwm@c340000 { 12926a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 12936a574ec7SThierry Reding "nvidia,tegra186-pwm"; 12946a574ec7SThierry Reding reg = <0xc340000 0x10000>; 12956a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 12966a574ec7SThierry Reding clock-names = "pwm"; 12976a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 12986a574ec7SThierry Reding reset-names = "pwm"; 12996a574ec7SThierry Reding status = "disabled"; 13006a574ec7SThierry Reding #pwm-cells = <2>; 13016a574ec7SThierry Reding }; 13026a574ec7SThierry Reding 130338ecf1e5SThierry Reding pmc: pmc@c360000 { 13045425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 13055425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 13065425fb15SMikko Perttunen <0x0c370000 0x10000>, 13075425fb15SMikko Perttunen <0x0c380000 0x10000>, 13085425fb15SMikko Perttunen <0x0c390000 0x10000>, 13095425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 13105425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 131138ecf1e5SThierry Reding 131238ecf1e5SThierry Reding #interrupt-cells = <2>; 131338ecf1e5SThierry Reding interrupt-controller; 13145425fb15SMikko Perttunen }; 13153db6d3baSThierry Reding 1316c7289b1cSThierry Reding smmu: iommu@12000000 { 1317c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1318c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1319c7289b1cSThierry Reding <0x11000000 0x800000>; 1320c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1321c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1322c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1323c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1324c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1325c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1326c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1327c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1328c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1329c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1330c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1331c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1332c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1333c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1334c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1335c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1336c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1337c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1338c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1339c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1340c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1341c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1342c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1343c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1344c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1345c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1346c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1347c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1348c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1349c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1350c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1351c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1352c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1353c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1354c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1355c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1356c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1357c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1358c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1359c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1360c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1361c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1362c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1363c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1364c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1365c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1367c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1386c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1387c7289b1cSThierry Reding #global-interrupts = <2>; 1388c7289b1cSThierry Reding #iommu-cells = <1>; 1389c7289b1cSThierry Reding 1390c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1391c7289b1cSThierry Reding status = "okay"; 1392c7289b1cSThierry Reding }; 1393c7289b1cSThierry Reding 13943db6d3baSThierry Reding host1x@13e00000 { 1395ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 13963db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 13973db6d3baSThierry Reding <0x13e10000 0x10000>; 13983db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 13993db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 14003db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1401052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 14023db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 14033db6d3baSThierry Reding clock-names = "host1x"; 14043db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 14053db6d3baSThierry Reding reset-names = "host1x"; 14063db6d3baSThierry Reding 14073db6d3baSThierry Reding #address-cells = <1>; 14083db6d3baSThierry Reding #size-cells = <1>; 14093db6d3baSThierry Reding 14103db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1411d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1412d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1413c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 14143db6d3baSThierry Reding 14153db6d3baSThierry Reding display-hub@15200000 { 1416aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1417611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 14183db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 14193db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 14203db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 14213db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 14223db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 14233db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 14243db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 14253db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 14263db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 14273db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 14283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 14293db6d3baSThierry Reding clock-names = "disp", "hub"; 14303db6d3baSThierry Reding status = "disabled"; 14313db6d3baSThierry Reding 14323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14333db6d3baSThierry Reding 14343db6d3baSThierry Reding #address-cells = <1>; 14353db6d3baSThierry Reding #size-cells = <1>; 14363db6d3baSThierry Reding 14373db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 14383db6d3baSThierry Reding 14393db6d3baSThierry Reding display@15200000 { 14403db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14413db6d3baSThierry Reding reg = <0x15200000 0x10000>; 14423db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 14433db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 14443db6d3baSThierry Reding clock-names = "dc"; 14453db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 14463db6d3baSThierry Reding reset-names = "dc"; 14473db6d3baSThierry Reding 14483db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1449d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1450d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1451d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 14523db6d3baSThierry Reding 14533db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 14543db6d3baSThierry Reding nvidia,head = <0>; 14553db6d3baSThierry Reding }; 14563db6d3baSThierry Reding 14573db6d3baSThierry Reding display@15210000 { 14583db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14593db6d3baSThierry Reding reg = <0x15210000 0x10000>; 14603db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 14613db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 14623db6d3baSThierry Reding clock-names = "dc"; 14633db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 14643db6d3baSThierry Reding reset-names = "dc"; 14653db6d3baSThierry Reding 14663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1467d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1468d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1469d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 14703db6d3baSThierry Reding 14713db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 14723db6d3baSThierry Reding nvidia,head = <1>; 14733db6d3baSThierry Reding }; 14743db6d3baSThierry Reding 14753db6d3baSThierry Reding display@15220000 { 14763db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14773db6d3baSThierry Reding reg = <0x15220000 0x10000>; 14783db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 14793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 14803db6d3baSThierry Reding clock-names = "dc"; 14813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 14823db6d3baSThierry Reding reset-names = "dc"; 14833db6d3baSThierry Reding 14843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1485d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1486d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1487d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 14883db6d3baSThierry Reding 14893db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 14903db6d3baSThierry Reding nvidia,head = <2>; 14913db6d3baSThierry Reding }; 14923db6d3baSThierry Reding 14933db6d3baSThierry Reding display@15230000 { 14943db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14953db6d3baSThierry Reding reg = <0x15230000 0x10000>; 14963db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 14973db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 14983db6d3baSThierry Reding clock-names = "dc"; 14993db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 15003db6d3baSThierry Reding reset-names = "dc"; 15013db6d3baSThierry Reding 15023db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1503d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1504d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1505d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 15063db6d3baSThierry Reding 15073db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 15083db6d3baSThierry Reding nvidia,head = <3>; 15093db6d3baSThierry Reding }; 15103db6d3baSThierry Reding }; 15113db6d3baSThierry Reding 15128d424ec2SThierry Reding vic@15340000 { 15138d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 15148d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 15158d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 15168d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 15178d424ec2SThierry Reding clock-names = "vic"; 15188d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 15198d424ec2SThierry Reding reset-names = "vic"; 15208d424ec2SThierry Reding 15218d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1522d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1523d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1524d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1525c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 15268d424ec2SThierry Reding }; 15278d424ec2SThierry Reding 15283db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 15293db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15303db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 15313db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 15323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 15333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15343db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 15363db6d3baSThierry Reding reset-names = "dpaux"; 15373db6d3baSThierry Reding status = "disabled"; 15383db6d3baSThierry Reding 15393db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15403db6d3baSThierry Reding 15413db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 15423db6d3baSThierry Reding groups = "dpaux-io"; 15433db6d3baSThierry Reding function = "aux"; 15443db6d3baSThierry Reding }; 15453db6d3baSThierry Reding 15463db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 15473db6d3baSThierry Reding groups = "dpaux-io"; 15483db6d3baSThierry Reding function = "i2c"; 15493db6d3baSThierry Reding }; 15503db6d3baSThierry Reding 15513db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 15523db6d3baSThierry Reding groups = "dpaux-io"; 15533db6d3baSThierry Reding function = "off"; 15543db6d3baSThierry Reding }; 15553db6d3baSThierry Reding 15563db6d3baSThierry Reding i2c-bus { 15573db6d3baSThierry Reding #address-cells = <1>; 15583db6d3baSThierry Reding #size-cells = <0>; 15593db6d3baSThierry Reding }; 15603db6d3baSThierry Reding }; 15613db6d3baSThierry Reding 15623db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 15633db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15643db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 15653db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 15663db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 15673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15683db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15693db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 15703db6d3baSThierry Reding reset-names = "dpaux"; 15713db6d3baSThierry Reding status = "disabled"; 15723db6d3baSThierry Reding 15733db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15743db6d3baSThierry Reding 15753db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 15763db6d3baSThierry Reding groups = "dpaux-io"; 15773db6d3baSThierry Reding function = "aux"; 15783db6d3baSThierry Reding }; 15793db6d3baSThierry Reding 15803db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 15813db6d3baSThierry Reding groups = "dpaux-io"; 15823db6d3baSThierry Reding function = "i2c"; 15833db6d3baSThierry Reding }; 15843db6d3baSThierry Reding 15853db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 15863db6d3baSThierry Reding groups = "dpaux-io"; 15873db6d3baSThierry Reding function = "off"; 15883db6d3baSThierry Reding }; 15893db6d3baSThierry Reding 15903db6d3baSThierry Reding i2c-bus { 15913db6d3baSThierry Reding #address-cells = <1>; 15923db6d3baSThierry Reding #size-cells = <0>; 15933db6d3baSThierry Reding }; 15943db6d3baSThierry Reding }; 15953db6d3baSThierry Reding 15963db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 15973db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15983db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 15993db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 16003db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 16013db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 16023db6d3baSThierry Reding clock-names = "dpaux", "parent"; 16033db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 16043db6d3baSThierry Reding reset-names = "dpaux"; 16053db6d3baSThierry Reding status = "disabled"; 16063db6d3baSThierry Reding 16073db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16083db6d3baSThierry Reding 16093db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 16103db6d3baSThierry Reding groups = "dpaux-io"; 16113db6d3baSThierry Reding function = "aux"; 16123db6d3baSThierry Reding }; 16133db6d3baSThierry Reding 16143db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 16153db6d3baSThierry Reding groups = "dpaux-io"; 16163db6d3baSThierry Reding function = "i2c"; 16173db6d3baSThierry Reding }; 16183db6d3baSThierry Reding 16193db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 16203db6d3baSThierry Reding groups = "dpaux-io"; 16213db6d3baSThierry Reding function = "off"; 16223db6d3baSThierry Reding }; 16233db6d3baSThierry Reding 16243db6d3baSThierry Reding i2c-bus { 16253db6d3baSThierry Reding #address-cells = <1>; 16263db6d3baSThierry Reding #size-cells = <0>; 16273db6d3baSThierry Reding }; 16283db6d3baSThierry Reding }; 16293db6d3baSThierry Reding 16303db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 16313db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 16323db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 16333db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 16343db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 16353db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 16363db6d3baSThierry Reding clock-names = "dpaux", "parent"; 16373db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 16383db6d3baSThierry Reding reset-names = "dpaux"; 16393db6d3baSThierry Reding status = "disabled"; 16403db6d3baSThierry Reding 16413db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16423db6d3baSThierry Reding 16433db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 16443db6d3baSThierry Reding groups = "dpaux-io"; 16453db6d3baSThierry Reding function = "aux"; 16463db6d3baSThierry Reding }; 16473db6d3baSThierry Reding 16483db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 16493db6d3baSThierry Reding groups = "dpaux-io"; 16503db6d3baSThierry Reding function = "i2c"; 16513db6d3baSThierry Reding }; 16523db6d3baSThierry Reding 16533db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 16543db6d3baSThierry Reding groups = "dpaux-io"; 16553db6d3baSThierry Reding function = "off"; 16563db6d3baSThierry Reding }; 16573db6d3baSThierry Reding 16583db6d3baSThierry Reding i2c-bus { 16593db6d3baSThierry Reding #address-cells = <1>; 16603db6d3baSThierry Reding #size-cells = <0>; 16613db6d3baSThierry Reding }; 16623db6d3baSThierry Reding }; 16633db6d3baSThierry Reding 16643db6d3baSThierry Reding sor0: sor@15b00000 { 16653db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 16663db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 16673db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 16683db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 16693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 16703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 16713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16733db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 16743db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16753db6d3baSThierry Reding "pad"; 16763db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 16773db6d3baSThierry Reding reset-names = "sor"; 16783db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 16793db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 16803db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 16813db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16823db6d3baSThierry Reding status = "disabled"; 16833db6d3baSThierry Reding 16843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16853db6d3baSThierry Reding nvidia,interface = <0>; 16863db6d3baSThierry Reding }; 16873db6d3baSThierry Reding 16883db6d3baSThierry Reding sor1: sor@15b40000 { 16893db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1690939e7430SThierry Reding reg = <0x15b40000 0x40000>; 16913db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 16923db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 16933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 16943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 16953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16963db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16973db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 16983db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16993db6d3baSThierry Reding "pad"; 17003db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 17013db6d3baSThierry Reding reset-names = "sor"; 17023db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 17033db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 17043db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 17053db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17063db6d3baSThierry Reding status = "disabled"; 17073db6d3baSThierry Reding 17083db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17093db6d3baSThierry Reding nvidia,interface = <1>; 17103db6d3baSThierry Reding }; 17113db6d3baSThierry Reding 17123db6d3baSThierry Reding sor2: sor@15b80000 { 17133db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 17143db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 17153db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 17163db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 17173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 17183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 17193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17203db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 17223db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17233db6d3baSThierry Reding "pad"; 17243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 17253db6d3baSThierry Reding reset-names = "sor"; 17263db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 17273db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 17283db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 17293db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17303db6d3baSThierry Reding status = "disabled"; 17313db6d3baSThierry Reding 17323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17333db6d3baSThierry Reding nvidia,interface = <2>; 17343db6d3baSThierry Reding }; 17353db6d3baSThierry Reding 17363db6d3baSThierry Reding sor3: sor@15bc0000 { 17373db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 17383db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 17393db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 17403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 17413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 17423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 17433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17443db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 17463db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17473db6d3baSThierry Reding "pad"; 17483db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 17493db6d3baSThierry Reding reset-names = "sor"; 17503db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 17513db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 17523db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 17533db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17543db6d3baSThierry Reding status = "disabled"; 17553db6d3baSThierry Reding 17563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17573db6d3baSThierry Reding nvidia,interface = <3>; 17583db6d3baSThierry Reding }; 17593db6d3baSThierry Reding }; 17600f134e39SThierry Reding 17610f134e39SThierry Reding gpu@17000000 { 17620f134e39SThierry Reding compatible = "nvidia,gv11b"; 1763818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1764818ae79aSThierry Reding <0x18000000 0x1000000>; 17650f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 17660f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 17670f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 17680f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 17690f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 17700f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 17710f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 17720f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 17730f134e39SThierry Reding reset-names = "gpu"; 17740f134e39SThierry Reding dma-coherent; 17750f134e39SThierry Reding 17760f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 17770f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 17780f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 17790f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 17800f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 17810f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 17820f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 17830f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 17840f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 17850f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 17860f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 17870f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 17880f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 17890f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 17900f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 17910f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 17920f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 17930f134e39SThierry Reding }; 17945425fb15SMikko Perttunen }; 17955425fb15SMikko Perttunen 17962602c32fSVidya Sagar pcie@14100000 { 1797f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17982602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1799644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1800644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1801644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1802644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18032602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18042602c32fSVidya Sagar 18052602c32fSVidya Sagar status = "disabled"; 18062602c32fSVidya Sagar 18072602c32fSVidya Sagar #address-cells = <3>; 18082602c32fSVidya Sagar #size-cells = <2>; 18092602c32fSVidya Sagar device_type = "pci"; 18102602c32fSVidya Sagar num-lanes = <1>; 18112602c32fSVidya Sagar num-viewport = <8>; 18122602c32fSVidya Sagar linux,pci-domain = <1>; 18132602c32fSVidya Sagar 18142602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 18152602c32fSVidya Sagar clock-names = "core"; 18162602c32fSVidya Sagar 18172602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 18182602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 18192602c32fSVidya Sagar reset-names = "apb", "core"; 18202602c32fSVidya Sagar 18212602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18222602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18232602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18242602c32fSVidya Sagar 18252602c32fSVidya Sagar #interrupt-cells = <1>; 18262602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18272602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 18282602c32fSVidya Sagar 18292602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 18302602c32fSVidya Sagar 18312602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18322602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18332602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18342602c32fSVidya Sagar 18352602c32fSVidya Sagar bus-range = <0x0 0xff>; 1836d5237c7cSThierry Reding 18378a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 18388a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 18398a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1840d5237c7cSThierry Reding 1841d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1842d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1843*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1844*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE1>; 1845*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 1846*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 1847*ba02920cSVidya Sagar dma-coherent; 18482602c32fSVidya Sagar }; 18492602c32fSVidya Sagar 18502602c32fSVidya Sagar pcie@14120000 { 1851f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18522602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1853644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1854644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1855644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1856644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18572602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18582602c32fSVidya Sagar 18592602c32fSVidya Sagar status = "disabled"; 18602602c32fSVidya Sagar 18612602c32fSVidya Sagar #address-cells = <3>; 18622602c32fSVidya Sagar #size-cells = <2>; 18632602c32fSVidya Sagar device_type = "pci"; 18642602c32fSVidya Sagar num-lanes = <1>; 18652602c32fSVidya Sagar num-viewport = <8>; 18662602c32fSVidya Sagar linux,pci-domain = <2>; 18672602c32fSVidya Sagar 18682602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 18692602c32fSVidya Sagar clock-names = "core"; 18702602c32fSVidya Sagar 18712602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 18722602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 18732602c32fSVidya Sagar reset-names = "apb", "core"; 18742602c32fSVidya Sagar 18752602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18762602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18772602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18782602c32fSVidya Sagar 18792602c32fSVidya Sagar #interrupt-cells = <1>; 18802602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18812602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 18822602c32fSVidya Sagar 18832602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 18842602c32fSVidya Sagar 18852602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18862602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18872602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18882602c32fSVidya Sagar 18892602c32fSVidya Sagar bus-range = <0x0 0xff>; 1890d5237c7cSThierry Reding 18918a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 18928a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 18938a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1894d5237c7cSThierry Reding 1895d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1896d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1897*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1898*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE2>; 1899*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 1900*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 1901*ba02920cSVidya Sagar dma-coherent; 19022602c32fSVidya Sagar }; 19032602c32fSVidya Sagar 19042602c32fSVidya Sagar pcie@14140000 { 1905f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19062602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1907644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1908644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1909644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1910644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19112602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19122602c32fSVidya Sagar 19132602c32fSVidya Sagar status = "disabled"; 19142602c32fSVidya Sagar 19152602c32fSVidya Sagar #address-cells = <3>; 19162602c32fSVidya Sagar #size-cells = <2>; 19172602c32fSVidya Sagar device_type = "pci"; 19182602c32fSVidya Sagar num-lanes = <1>; 19192602c32fSVidya Sagar num-viewport = <8>; 19202602c32fSVidya Sagar linux,pci-domain = <3>; 19212602c32fSVidya Sagar 19222602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 19232602c32fSVidya Sagar clock-names = "core"; 19242602c32fSVidya Sagar 19252602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 19262602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 19272602c32fSVidya Sagar reset-names = "apb", "core"; 19282602c32fSVidya Sagar 19292602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19302602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19312602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19322602c32fSVidya Sagar 19332602c32fSVidya Sagar #interrupt-cells = <1>; 19342602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19352602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 19362602c32fSVidya Sagar 19372602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 19382602c32fSVidya Sagar 19392602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19402602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19412602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19422602c32fSVidya Sagar 19432602c32fSVidya Sagar bus-range = <0x0 0xff>; 1944d5237c7cSThierry Reding 19458a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 19468a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 19478a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1948d5237c7cSThierry Reding 1949d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1950d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1951*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1952*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE3>; 1953*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 1954*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 1955*ba02920cSVidya Sagar dma-coherent; 19562602c32fSVidya Sagar }; 19572602c32fSVidya Sagar 19582602c32fSVidya Sagar pcie@14160000 { 1959f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19602602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1961644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1962644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1963644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1964644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19652602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19662602c32fSVidya Sagar 19672602c32fSVidya Sagar status = "disabled"; 19682602c32fSVidya Sagar 19692602c32fSVidya Sagar #address-cells = <3>; 19702602c32fSVidya Sagar #size-cells = <2>; 19712602c32fSVidya Sagar device_type = "pci"; 19722602c32fSVidya Sagar num-lanes = <4>; 19732602c32fSVidya Sagar num-viewport = <8>; 19742602c32fSVidya Sagar linux,pci-domain = <4>; 19752602c32fSVidya Sagar 19762602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 19772602c32fSVidya Sagar clock-names = "core"; 19782602c32fSVidya Sagar 19792602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 19802602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 19812602c32fSVidya Sagar reset-names = "apb", "core"; 19822602c32fSVidya Sagar 19832602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19842602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19852602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19862602c32fSVidya Sagar 19872602c32fSVidya Sagar #interrupt-cells = <1>; 19882602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19892602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 19902602c32fSVidya Sagar 19912602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 19922602c32fSVidya Sagar 19932602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19942602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19952602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19962602c32fSVidya Sagar 19972602c32fSVidya Sagar bus-range = <0x0 0xff>; 1998d5237c7cSThierry Reding 19998a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 20008a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 20018a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2002d5237c7cSThierry Reding 2003d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2004d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2005*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2006*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2007*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2008*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2009*ba02920cSVidya Sagar dma-coherent; 20102602c32fSVidya Sagar }; 20112602c32fSVidya Sagar 20122602c32fSVidya Sagar pcie@14180000 { 2013f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 20142602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2015644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2016644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2017644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2018644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20192602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20202602c32fSVidya Sagar 20212602c32fSVidya Sagar status = "disabled"; 20222602c32fSVidya Sagar 20232602c32fSVidya Sagar #address-cells = <3>; 20242602c32fSVidya Sagar #size-cells = <2>; 20252602c32fSVidya Sagar device_type = "pci"; 20262602c32fSVidya Sagar num-lanes = <8>; 20272602c32fSVidya Sagar num-viewport = <8>; 20282602c32fSVidya Sagar linux,pci-domain = <0>; 20292602c32fSVidya Sagar 20302602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 20312602c32fSVidya Sagar clock-names = "core"; 20322602c32fSVidya Sagar 20332602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 20342602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 20352602c32fSVidya Sagar reset-names = "apb", "core"; 20362602c32fSVidya Sagar 20372602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20382602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20392602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20402602c32fSVidya Sagar 20412602c32fSVidya Sagar #interrupt-cells = <1>; 20422602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 20432602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 20442602c32fSVidya Sagar 20452602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 20462602c32fSVidya Sagar 20472602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 20482602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20492602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20502602c32fSVidya Sagar 20512602c32fSVidya Sagar bus-range = <0x0 0xff>; 2052d5237c7cSThierry Reding 20538a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 20548a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 20558a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2056d5237c7cSThierry Reding 2057d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2058d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2059*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2060*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2061*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2062*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2063*ba02920cSVidya Sagar dma-coherent; 20642602c32fSVidya Sagar }; 20652602c32fSVidya Sagar 20662602c32fSVidya Sagar pcie@141a0000 { 2067f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 20682602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2069644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2070644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2071644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2072644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20732602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20742602c32fSVidya Sagar 20752602c32fSVidya Sagar status = "disabled"; 20762602c32fSVidya Sagar 20772602c32fSVidya Sagar #address-cells = <3>; 20782602c32fSVidya Sagar #size-cells = <2>; 20792602c32fSVidya Sagar device_type = "pci"; 20802602c32fSVidya Sagar num-lanes = <8>; 20812602c32fSVidya Sagar num-viewport = <8>; 20822602c32fSVidya Sagar linux,pci-domain = <5>; 20832602c32fSVidya Sagar 2084dbb72e2cSVidya Sagar pinctrl-names = "default"; 2085dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2086dbb72e2cSVidya Sagar 20872602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 20882602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 20892602c32fSVidya Sagar clock-names = "core", "core_m"; 20902602c32fSVidya Sagar 20912602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 20922602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 20932602c32fSVidya Sagar reset-names = "apb", "core"; 20942602c32fSVidya Sagar 20952602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20962602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20972602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20982602c32fSVidya Sagar 20992602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 21002602c32fSVidya Sagar 21012602c32fSVidya Sagar #interrupt-cells = <1>; 21022602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21032602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 21042602c32fSVidya Sagar 21052602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21062602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21072602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21082602c32fSVidya Sagar 21092602c32fSVidya Sagar bus-range = <0x0 0xff>; 2110d5237c7cSThierry Reding 21118a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 21128a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 21138a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2114d5237c7cSThierry Reding 2115d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2116d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2117*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2118*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2119*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2120*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2121*ba02920cSVidya Sagar dma-coherent; 21222602c32fSVidya Sagar }; 21232602c32fSVidya Sagar 21240c988b73SVidya Sagar pcie_ep@14160000 { 21250c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 21260c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2127644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2128644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2129644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2130644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 21310c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 21320c988b73SVidya Sagar 21330c988b73SVidya Sagar status = "disabled"; 21340c988b73SVidya Sagar 21350c988b73SVidya Sagar num-lanes = <4>; 21360c988b73SVidya Sagar num-ib-windows = <2>; 21370c988b73SVidya Sagar num-ob-windows = <8>; 21380c988b73SVidya Sagar 21390c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 21400c988b73SVidya Sagar clock-names = "core"; 21410c988b73SVidya Sagar 21420c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 21430c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 21440c988b73SVidya Sagar reset-names = "apb", "core"; 21450c988b73SVidya Sagar 21460c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 21470c988b73SVidya Sagar interrupt-names = "intr"; 21480c988b73SVidya Sagar 21490c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 21500c988b73SVidya Sagar 21510c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 21520c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21530c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2154*ba02920cSVidya Sagar 2155*ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2156*ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2157*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2158*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2159*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2160*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2161*ba02920cSVidya Sagar dma-coherent; 21620c988b73SVidya Sagar }; 21630c988b73SVidya Sagar 21640c988b73SVidya Sagar pcie_ep@14180000 { 21650c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 21660c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2167644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2168644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2169644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2170644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 21710c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 21720c988b73SVidya Sagar 21730c988b73SVidya Sagar status = "disabled"; 21740c988b73SVidya Sagar 21750c988b73SVidya Sagar num-lanes = <8>; 21760c988b73SVidya Sagar num-ib-windows = <2>; 21770c988b73SVidya Sagar num-ob-windows = <8>; 21780c988b73SVidya Sagar 21790c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 21800c988b73SVidya Sagar clock-names = "core"; 21810c988b73SVidya Sagar 21820c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 21830c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 21840c988b73SVidya Sagar reset-names = "apb", "core"; 21850c988b73SVidya Sagar 21860c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 21870c988b73SVidya Sagar interrupt-names = "intr"; 21880c988b73SVidya Sagar 21890c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 21900c988b73SVidya Sagar 21910c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 21920c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21930c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2194*ba02920cSVidya Sagar 2195*ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2196*ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2197*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2198*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2199*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2200*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2201*ba02920cSVidya Sagar dma-coherent; 22020c988b73SVidya Sagar }; 22030c988b73SVidya Sagar 22040c988b73SVidya Sagar pcie_ep@141a0000 { 22050c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 22060c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2207644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2208644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2209644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2210644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 22110c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 22120c988b73SVidya Sagar 22130c988b73SVidya Sagar status = "disabled"; 22140c988b73SVidya Sagar 22150c988b73SVidya Sagar num-lanes = <8>; 22160c988b73SVidya Sagar num-ib-windows = <2>; 22170c988b73SVidya Sagar num-ob-windows = <8>; 22180c988b73SVidya Sagar 22190c988b73SVidya Sagar pinctrl-names = "default"; 22200c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 22210c988b73SVidya Sagar 22220c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 22230c988b73SVidya Sagar clock-names = "core"; 22240c988b73SVidya Sagar 22250c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 22260c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 22270c988b73SVidya Sagar reset-names = "apb", "core"; 22280c988b73SVidya Sagar 22290c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 22300c988b73SVidya Sagar interrupt-names = "intr"; 22310c988b73SVidya Sagar 22320c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 22330c988b73SVidya Sagar 22340c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 22350c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22360c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2237*ba02920cSVidya Sagar 2238*ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2239*ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2240*ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2241*ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2242*ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2243*ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2244*ba02920cSVidya Sagar dma-coherent; 22450c988b73SVidya Sagar }; 22460c988b73SVidya Sagar 2247e867fe41SThierry Reding sram@40000000 { 22485425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 22495425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 22505425fb15SMikko Perttunen #address-cells = <1>; 22515425fb15SMikko Perttunen #size-cells = <1>; 22525425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 22535425fb15SMikko Perttunen 2254e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 22555425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 22565425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 22575425fb15SMikko Perttunen pool; 22585425fb15SMikko Perttunen }; 22595425fb15SMikko Perttunen 2260e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 22615425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 22625425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 22635425fb15SMikko Perttunen pool; 22645425fb15SMikko Perttunen }; 22655425fb15SMikko Perttunen }; 22665425fb15SMikko Perttunen 22675425fb15SMikko Perttunen bpmp: bpmp { 22685425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 22695425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 22705425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 22715425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 22725425fb15SMikko Perttunen #clock-cells = <1>; 22735425fb15SMikko Perttunen #reset-cells = <1>; 22745425fb15SMikko Perttunen #power-domain-cells = <1>; 2275d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2276d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2277d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2278d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2279d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2280c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 22815425fb15SMikko Perttunen 22825425fb15SMikko Perttunen bpmp_i2c: i2c { 22835425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 22845425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 22855425fb15SMikko Perttunen #address-cells = <1>; 22865425fb15SMikko Perttunen #size-cells = <0>; 22875425fb15SMikko Perttunen }; 22885425fb15SMikko Perttunen 22895425fb15SMikko Perttunen bpmp_thermal: thermal { 22905425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 22915425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 22925425fb15SMikko Perttunen }; 22935425fb15SMikko Perttunen }; 22945425fb15SMikko Perttunen 22957780a034SMikko Perttunen cpus { 2296d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2297d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 22987780a034SMikko Perttunen #address-cells = <1>; 22997780a034SMikko Perttunen #size-cells = <0>; 23007780a034SMikko Perttunen 2301b45d322cSThierry Reding cpu0_0: cpu@0 { 230231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23037780a034SMikko Perttunen device_type = "cpu"; 2304b45d322cSThierry Reding reg = <0x000>; 23057780a034SMikko Perttunen enable-method = "psci"; 2306b45d322cSThierry Reding i-cache-size = <131072>; 2307b45d322cSThierry Reding i-cache-line-size = <64>; 2308b45d322cSThierry Reding i-cache-sets = <512>; 2309b45d322cSThierry Reding d-cache-size = <65536>; 2310b45d322cSThierry Reding d-cache-line-size = <64>; 2311b45d322cSThierry Reding d-cache-sets = <256>; 2312b45d322cSThierry Reding next-level-cache = <&l2c_0>; 23137780a034SMikko Perttunen }; 23147780a034SMikko Perttunen 2315b45d322cSThierry Reding cpu0_1: cpu@1 { 231631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23177780a034SMikko Perttunen device_type = "cpu"; 2318b45d322cSThierry Reding reg = <0x001>; 23197780a034SMikko Perttunen enable-method = "psci"; 2320b45d322cSThierry Reding i-cache-size = <131072>; 2321b45d322cSThierry Reding i-cache-line-size = <64>; 2322b45d322cSThierry Reding i-cache-sets = <512>; 2323b45d322cSThierry Reding d-cache-size = <65536>; 2324b45d322cSThierry Reding d-cache-line-size = <64>; 2325b45d322cSThierry Reding d-cache-sets = <256>; 2326b45d322cSThierry Reding next-level-cache = <&l2c_0>; 23277780a034SMikko Perttunen }; 23287780a034SMikko Perttunen 2329b45d322cSThierry Reding cpu1_0: cpu@100 { 233031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23317780a034SMikko Perttunen device_type = "cpu"; 23327780a034SMikko Perttunen reg = <0x100>; 23337780a034SMikko Perttunen enable-method = "psci"; 2334b45d322cSThierry Reding i-cache-size = <131072>; 2335b45d322cSThierry Reding i-cache-line-size = <64>; 2336b45d322cSThierry Reding i-cache-sets = <512>; 2337b45d322cSThierry Reding d-cache-size = <65536>; 2338b45d322cSThierry Reding d-cache-line-size = <64>; 2339b45d322cSThierry Reding d-cache-sets = <256>; 2340b45d322cSThierry Reding next-level-cache = <&l2c_1>; 23417780a034SMikko Perttunen }; 23427780a034SMikko Perttunen 2343b45d322cSThierry Reding cpu1_1: cpu@101 { 234431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23457780a034SMikko Perttunen device_type = "cpu"; 23467780a034SMikko Perttunen reg = <0x101>; 23477780a034SMikko Perttunen enable-method = "psci"; 2348b45d322cSThierry Reding i-cache-size = <131072>; 2349b45d322cSThierry Reding i-cache-line-size = <64>; 2350b45d322cSThierry Reding i-cache-sets = <512>; 2351b45d322cSThierry Reding d-cache-size = <65536>; 2352b45d322cSThierry Reding d-cache-line-size = <64>; 2353b45d322cSThierry Reding d-cache-sets = <256>; 2354b45d322cSThierry Reding next-level-cache = <&l2c_1>; 23557780a034SMikko Perttunen }; 23567780a034SMikko Perttunen 2357b45d322cSThierry Reding cpu2_0: cpu@200 { 235831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23597780a034SMikko Perttunen device_type = "cpu"; 23607780a034SMikko Perttunen reg = <0x200>; 23617780a034SMikko Perttunen enable-method = "psci"; 2362b45d322cSThierry Reding i-cache-size = <131072>; 2363b45d322cSThierry Reding i-cache-line-size = <64>; 2364b45d322cSThierry Reding i-cache-sets = <512>; 2365b45d322cSThierry Reding d-cache-size = <65536>; 2366b45d322cSThierry Reding d-cache-line-size = <64>; 2367b45d322cSThierry Reding d-cache-sets = <256>; 2368b45d322cSThierry Reding next-level-cache = <&l2c_2>; 23697780a034SMikko Perttunen }; 23707780a034SMikko Perttunen 2371b45d322cSThierry Reding cpu2_1: cpu@201 { 237231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23737780a034SMikko Perttunen device_type = "cpu"; 23747780a034SMikko Perttunen reg = <0x201>; 23757780a034SMikko Perttunen enable-method = "psci"; 2376b45d322cSThierry Reding i-cache-size = <131072>; 2377b45d322cSThierry Reding i-cache-line-size = <64>; 2378b45d322cSThierry Reding i-cache-sets = <512>; 2379b45d322cSThierry Reding d-cache-size = <65536>; 2380b45d322cSThierry Reding d-cache-line-size = <64>; 2381b45d322cSThierry Reding d-cache-sets = <256>; 2382b45d322cSThierry Reding next-level-cache = <&l2c_2>; 23837780a034SMikko Perttunen }; 23847780a034SMikko Perttunen 2385b45d322cSThierry Reding cpu3_0: cpu@300 { 238631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23877780a034SMikko Perttunen device_type = "cpu"; 2388b45d322cSThierry Reding reg = <0x300>; 23897780a034SMikko Perttunen enable-method = "psci"; 2390b45d322cSThierry Reding i-cache-size = <131072>; 2391b45d322cSThierry Reding i-cache-line-size = <64>; 2392b45d322cSThierry Reding i-cache-sets = <512>; 2393b45d322cSThierry Reding d-cache-size = <65536>; 2394b45d322cSThierry Reding d-cache-line-size = <64>; 2395b45d322cSThierry Reding d-cache-sets = <256>; 2396b45d322cSThierry Reding next-level-cache = <&l2c_3>; 23977780a034SMikko Perttunen }; 23987780a034SMikko Perttunen 2399b45d322cSThierry Reding cpu3_1: cpu@301 { 240031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 24017780a034SMikko Perttunen device_type = "cpu"; 2402b45d322cSThierry Reding reg = <0x301>; 24037780a034SMikko Perttunen enable-method = "psci"; 2404b45d322cSThierry Reding i-cache-size = <131072>; 2405b45d322cSThierry Reding i-cache-line-size = <64>; 2406b45d322cSThierry Reding i-cache-sets = <512>; 2407b45d322cSThierry Reding d-cache-size = <65536>; 2408b45d322cSThierry Reding d-cache-line-size = <64>; 2409b45d322cSThierry Reding d-cache-sets = <256>; 2410b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2411b45d322cSThierry Reding }; 2412b45d322cSThierry Reding 2413b45d322cSThierry Reding cpu-map { 2414b45d322cSThierry Reding cluster0 { 2415b45d322cSThierry Reding core0 { 2416b45d322cSThierry Reding cpu = <&cpu0_0>; 2417b45d322cSThierry Reding }; 2418b45d322cSThierry Reding 2419b45d322cSThierry Reding core1 { 2420b45d322cSThierry Reding cpu = <&cpu0_1>; 2421b45d322cSThierry Reding }; 2422b45d322cSThierry Reding }; 2423b45d322cSThierry Reding 2424b45d322cSThierry Reding cluster1 { 2425b45d322cSThierry Reding core0 { 2426b45d322cSThierry Reding cpu = <&cpu1_0>; 2427b45d322cSThierry Reding }; 2428b45d322cSThierry Reding 2429b45d322cSThierry Reding core1 { 2430b45d322cSThierry Reding cpu = <&cpu1_1>; 2431b45d322cSThierry Reding }; 2432b45d322cSThierry Reding }; 2433b45d322cSThierry Reding 2434b45d322cSThierry Reding cluster2 { 2435b45d322cSThierry Reding core0 { 2436b45d322cSThierry Reding cpu = <&cpu2_0>; 2437b45d322cSThierry Reding }; 2438b45d322cSThierry Reding 2439b45d322cSThierry Reding core1 { 2440b45d322cSThierry Reding cpu = <&cpu2_1>; 2441b45d322cSThierry Reding }; 2442b45d322cSThierry Reding }; 2443b45d322cSThierry Reding 2444b45d322cSThierry Reding cluster3 { 2445b45d322cSThierry Reding core0 { 2446b45d322cSThierry Reding cpu = <&cpu3_0>; 2447b45d322cSThierry Reding }; 2448b45d322cSThierry Reding 2449b45d322cSThierry Reding core1 { 2450b45d322cSThierry Reding cpu = <&cpu3_1>; 2451b45d322cSThierry Reding }; 2452b45d322cSThierry Reding }; 2453b45d322cSThierry Reding }; 2454b45d322cSThierry Reding 2455b45d322cSThierry Reding l2c_0: l2-cache0 { 2456b45d322cSThierry Reding cache-size = <2097152>; 2457b45d322cSThierry Reding cache-line-size = <64>; 2458b45d322cSThierry Reding cache-sets = <2048>; 2459b45d322cSThierry Reding next-level-cache = <&l3c>; 2460b45d322cSThierry Reding }; 2461b45d322cSThierry Reding 2462b45d322cSThierry Reding l2c_1: l2-cache1 { 2463b45d322cSThierry Reding cache-size = <2097152>; 2464b45d322cSThierry Reding cache-line-size = <64>; 2465b45d322cSThierry Reding cache-sets = <2048>; 2466b45d322cSThierry Reding next-level-cache = <&l3c>; 2467b45d322cSThierry Reding }; 2468b45d322cSThierry Reding 2469b45d322cSThierry Reding l2c_2: l2-cache2 { 2470b45d322cSThierry Reding cache-size = <2097152>; 2471b45d322cSThierry Reding cache-line-size = <64>; 2472b45d322cSThierry Reding cache-sets = <2048>; 2473b45d322cSThierry Reding next-level-cache = <&l3c>; 2474b45d322cSThierry Reding }; 2475b45d322cSThierry Reding 2476b45d322cSThierry Reding l2c_3: l2-cache3 { 2477b45d322cSThierry Reding cache-size = <2097152>; 2478b45d322cSThierry Reding cache-line-size = <64>; 2479b45d322cSThierry Reding cache-sets = <2048>; 2480b45d322cSThierry Reding next-level-cache = <&l3c>; 2481b45d322cSThierry Reding }; 2482b45d322cSThierry Reding 2483b45d322cSThierry Reding l3c: l3-cache { 2484b45d322cSThierry Reding cache-size = <4194304>; 2485b45d322cSThierry Reding cache-line-size = <64>; 2486b45d322cSThierry Reding cache-sets = <4096>; 24877780a034SMikko Perttunen }; 24887780a034SMikko Perttunen }; 24897780a034SMikko Perttunen 24909e79e58fSJon Hunter pmu { 24919e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 24929e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 24939e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 24949e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 24959e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 24969e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 24979e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 24989e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 24999e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 25009e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 25019e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 25029e79e58fSJon Hunter }; 25039e79e58fSJon Hunter 25047780a034SMikko Perttunen psci { 25057780a034SMikko Perttunen compatible = "arm,psci-1.0"; 25067780a034SMikko Perttunen status = "okay"; 25077780a034SMikko Perttunen method = "smc"; 25087780a034SMikko Perttunen }; 25097780a034SMikko Perttunen 25105b4f6323SSameer Pujar sound { 25115b4f6323SSameer Pujar status = "disabled"; 25125b4f6323SSameer Pujar 25135b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 25145b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 25155b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 25165b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 25175b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 25185b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 25195b4f6323SSameer Pujar assigned-clock-parents = <0>, 25205b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 25215b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 25225b4f6323SSameer Pujar /* 25235b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 25245b4f6323SSameer Pujar * for this to work and oscillate between base rates required 25255b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 25265b4f6323SSameer Pujar */ 25275b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 252834e0fc34SThierry Reding 252934e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 253034e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 253134e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 253234e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 25335b4f6323SSameer Pujar }; 25345b4f6323SSameer Pujar 2535a38570c2SMikko Perttunen tcu: tcu { 2536a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2537a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2538a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2539a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2540a38570c2SMikko Perttunen }; 2541a38570c2SMikko Perttunen 2542686ba009SThierry Reding thermal-zones { 2543686ba009SThierry Reding cpu { 2544686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2545686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2546686ba009SThierry Reding status = "disabled"; 2547686ba009SThierry Reding }; 2548686ba009SThierry Reding 2549686ba009SThierry Reding gpu { 2550686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2551686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2552686ba009SThierry Reding status = "disabled"; 2553686ba009SThierry Reding }; 2554686ba009SThierry Reding 2555686ba009SThierry Reding aux { 2556686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2557686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2558686ba009SThierry Reding status = "disabled"; 2559686ba009SThierry Reding }; 2560686ba009SThierry Reding 2561686ba009SThierry Reding pllx { 2562686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2563686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2564686ba009SThierry Reding status = "disabled"; 2565686ba009SThierry Reding }; 2566686ba009SThierry Reding 2567686ba009SThierry Reding ao { 2568686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2569686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2570686ba009SThierry Reding status = "disabled"; 2571686ba009SThierry Reding }; 2572686ba009SThierry Reding 2573686ba009SThierry Reding tj { 2574686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2575686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2576686ba009SThierry Reding status = "disabled"; 2577686ba009SThierry Reding }; 2578686ba009SThierry Reding }; 2579686ba009SThierry Reding 25805425fb15SMikko Perttunen timer { 25815425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 25825425fb15SMikko Perttunen interrupts = <GIC_PPI 13 25835425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 25845425fb15SMikko Perttunen <GIC_PPI 14 25855425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 25865425fb15SMikko Perttunen <GIC_PPI 11 25875425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 25885425fb15SMikko Perttunen <GIC_PPI 10 25895425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 25905425fb15SMikko Perttunen interrupt-parent = <&gic>; 2591b30be673SThierry Reding always-on; 25925425fb15SMikko Perttunen }; 25935425fb15SMikko Perttunen}; 2594