15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 26*a47e173eSSumit Gupta apbmisc: misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91*a47e173eSSumit Gupta cbb-noc@2300000 { 92*a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 93*a47e173eSSumit Gupta reg = <0x02300000 0x1000>; 94*a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95*a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96*a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 97*a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 98*a47e173eSSumit Gupta status = "okay"; 99*a47e173eSSumit Gupta }; 100*a47e173eSSumit Gupta 101*a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 102*a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 103*a47e173eSSumit Gupta reg = <0x2390000 0x1000>, 104*a47e173eSSumit Gupta <0x23a0000 0x1000>, 105*a47e173eSSumit Gupta <0x23b0000 0x1000>, 106*a47e173eSSumit Gupta <0x23c0000 0x1000>, 107*a47e173eSSumit Gupta <0x23d0000 0x1000>, 108*a47e173eSSumit Gupta <0x23e0000 0x1000>; 109*a47e173eSSumit Gupta status = "okay"; 110*a47e173eSSumit Gupta }; 111*a47e173eSSumit Gupta 112f89b58ceSMikko Perttunen ethernet@2490000 { 11319dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 11419dc772aSThierry Reding "nvidia,tegra186-eqos", 115f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 116f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 117f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 120f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 121f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 122f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 125f89b58ceSMikko Perttunen reset-names = "eqos"; 126d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 129c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 130f89b58ceSMikko Perttunen status = "disabled"; 131f89b58ceSMikko Perttunen 132f89b58ceSMikko Perttunen snps,write-requests = <1>; 133f89b58ceSMikko Perttunen snps,read-requests = <3>; 134f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 135f89b58ceSMikko Perttunen snps,txpbl = <16>; 136f89b58ceSMikko Perttunen snps,rxpbl = <8>; 137f89b58ceSMikko Perttunen }; 138f89b58ceSMikko Perttunen 139835553b3SAkhil R gpcdma: dma-controller@2600000 { 140835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 141835553b3SAkhil R "nvidia,tegra186-gpcdma"; 142835553b3SAkhil R reg = <0x2600000 0x210000>; 143835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144835553b3SAkhil R reset-names = "gpcdma"; 145835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176835553b3SAkhil R #dma-cells = <1>; 177835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178835553b3SAkhil R dma-coherent; 179835553b3SAkhil R status = "okay"; 180835553b3SAkhil R }; 181835553b3SAkhil R 1821aaa7698SThierry Reding aconnect@2900000 { 1835d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1845d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1855d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1865d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1875d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1885d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1895d2249ddSSameer Pujar #address-cells = <1>; 1905d2249ddSSameer Pujar #size-cells = <1>; 1915d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1925d2249ddSSameer Pujar status = "disabled"; 1935d2249ddSSameer Pujar 194177208f7SSameer Pujar adma: dma-controller@2930000 { 1955d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1965d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1975d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1985d2249ddSSameer Pujar interrupt-parent = <&agic>; 1995d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2005d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2015d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2025d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2105d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2115d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2125d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2135d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2145d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2155d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2165d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2175d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2185d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2195d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2205d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2215d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2225d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2235d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2245d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2255d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2265d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2275d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2285d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2295d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2305d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2315d2249ddSSameer Pujar #dma-cells = <1>; 2325d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2335d2249ddSSameer Pujar clock-names = "d_audio"; 2345d2249ddSSameer Pujar status = "disabled"; 2355d2249ddSSameer Pujar }; 2365d2249ddSSameer Pujar 2375d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2385d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2395d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2405d2249ddSSameer Pujar #interrupt-cells = <3>; 2415d2249ddSSameer Pujar interrupt-controller; 2425d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2435d2249ddSSameer Pujar <0x02a42000 0x2000>; 2445d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2455d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2465d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2475d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2485d2249ddSSameer Pujar clock-names = "clk"; 2495d2249ddSSameer Pujar status = "disabled"; 2505d2249ddSSameer Pujar }; 251177208f7SSameer Pujar 252177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 253177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 254177208f7SSameer Pujar "nvidia,tegra186-ahub"; 255177208f7SSameer Pujar reg = <0x02900800 0x800>; 256177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 257177208f7SSameer Pujar clock-names = "ahub"; 258177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260177208f7SSameer Pujar #address-cells = <1>; 261177208f7SSameer Pujar #size-cells = <1>; 262177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 263177208f7SSameer Pujar status = "disabled"; 264177208f7SSameer Pujar 265177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 266177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 267177208f7SSameer Pujar "nvidia,tegra186-admaif"; 268177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 269177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 270177208f7SSameer Pujar <&adma 2>, <&adma 2>, 271177208f7SSameer Pujar <&adma 3>, <&adma 3>, 272177208f7SSameer Pujar <&adma 4>, <&adma 4>, 273177208f7SSameer Pujar <&adma 5>, <&adma 5>, 274177208f7SSameer Pujar <&adma 6>, <&adma 6>, 275177208f7SSameer Pujar <&adma 7>, <&adma 7>, 276177208f7SSameer Pujar <&adma 8>, <&adma 8>, 277177208f7SSameer Pujar <&adma 9>, <&adma 9>, 278177208f7SSameer Pujar <&adma 10>, <&adma 10>, 279177208f7SSameer Pujar <&adma 11>, <&adma 11>, 280177208f7SSameer Pujar <&adma 12>, <&adma 12>, 281177208f7SSameer Pujar <&adma 13>, <&adma 13>, 282177208f7SSameer Pujar <&adma 14>, <&adma 14>, 283177208f7SSameer Pujar <&adma 15>, <&adma 15>, 284177208f7SSameer Pujar <&adma 16>, <&adma 16>, 285177208f7SSameer Pujar <&adma 17>, <&adma 17>, 286177208f7SSameer Pujar <&adma 18>, <&adma 18>, 287177208f7SSameer Pujar <&adma 19>, <&adma 19>, 288177208f7SSameer Pujar <&adma 20>, <&adma 20>; 289177208f7SSameer Pujar dma-names = "rx1", "tx1", 290177208f7SSameer Pujar "rx2", "tx2", 291177208f7SSameer Pujar "rx3", "tx3", 292177208f7SSameer Pujar "rx4", "tx4", 293177208f7SSameer Pujar "rx5", "tx5", 294177208f7SSameer Pujar "rx6", "tx6", 295177208f7SSameer Pujar "rx7", "tx7", 296177208f7SSameer Pujar "rx8", "tx8", 297177208f7SSameer Pujar "rx9", "tx9", 298177208f7SSameer Pujar "rx10", "tx10", 299177208f7SSameer Pujar "rx11", "tx11", 300177208f7SSameer Pujar "rx12", "tx12", 301177208f7SSameer Pujar "rx13", "tx13", 302177208f7SSameer Pujar "rx14", "tx14", 303177208f7SSameer Pujar "rx15", "tx15", 304177208f7SSameer Pujar "rx16", "tx16", 305177208f7SSameer Pujar "rx17", "tx17", 306177208f7SSameer Pujar "rx18", "tx18", 307177208f7SSameer Pujar "rx19", "tx19", 308177208f7SSameer Pujar "rx20", "tx20"; 309177208f7SSameer Pujar status = "disabled"; 310cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 313cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 314177208f7SSameer Pujar }; 315177208f7SSameer Pujar 316177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 317177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 318177208f7SSameer Pujar "nvidia,tegra210-i2s"; 319177208f7SSameer Pujar reg = <0x2901000 0x100>; 320177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 321177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 323177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325177208f7SSameer Pujar assigned-clock-rates = <1536000>; 326177208f7SSameer Pujar sound-name-prefix = "I2S1"; 327177208f7SSameer Pujar status = "disabled"; 328177208f7SSameer Pujar }; 329177208f7SSameer Pujar 330177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 331177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 332177208f7SSameer Pujar "nvidia,tegra210-i2s"; 333177208f7SSameer Pujar reg = <0x2901100 0x100>; 334177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 335177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 337177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339177208f7SSameer Pujar assigned-clock-rates = <1536000>; 340177208f7SSameer Pujar sound-name-prefix = "I2S2"; 341177208f7SSameer Pujar status = "disabled"; 342177208f7SSameer Pujar }; 343177208f7SSameer Pujar 344177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 345177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 346177208f7SSameer Pujar "nvidia,tegra210-i2s"; 347177208f7SSameer Pujar reg = <0x2901200 0x100>; 348177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 349177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <1536000>; 354177208f7SSameer Pujar sound-name-prefix = "I2S3"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar 358177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 359177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 360177208f7SSameer Pujar "nvidia,tegra210-i2s"; 361177208f7SSameer Pujar reg = <0x2901300 0x100>; 362177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 363177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 365177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367177208f7SSameer Pujar assigned-clock-rates = <1536000>; 368177208f7SSameer Pujar sound-name-prefix = "I2S4"; 369177208f7SSameer Pujar status = "disabled"; 370177208f7SSameer Pujar }; 371177208f7SSameer Pujar 372177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 373177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 374177208f7SSameer Pujar "nvidia,tegra210-i2s"; 375177208f7SSameer Pujar reg = <0x2901400 0x100>; 376177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 377177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 379177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381177208f7SSameer Pujar assigned-clock-rates = <1536000>; 382177208f7SSameer Pujar sound-name-prefix = "I2S5"; 383177208f7SSameer Pujar status = "disabled"; 384177208f7SSameer Pujar }; 385177208f7SSameer Pujar 386177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 387177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 388177208f7SSameer Pujar "nvidia,tegra210-i2s"; 389177208f7SSameer Pujar reg = <0x2901500 0x100>; 390177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 391177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <1536000>; 396177208f7SSameer Pujar sound-name-prefix = "I2S6"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399177208f7SSameer Pujar 400177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 401177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 402177208f7SSameer Pujar "nvidia,tegra210-dmic"; 403177208f7SSameer Pujar reg = <0x2904000 0x100>; 404177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405177208f7SSameer Pujar clock-names = "dmic"; 406177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408177208f7SSameer Pujar assigned-clock-rates = <3072000>; 409177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 410177208f7SSameer Pujar status = "disabled"; 411177208f7SSameer Pujar }; 412177208f7SSameer Pujar 413177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 414177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 415177208f7SSameer Pujar "nvidia,tegra210-dmic"; 416177208f7SSameer Pujar reg = <0x2904100 0x100>; 417177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418177208f7SSameer Pujar clock-names = "dmic"; 419177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421177208f7SSameer Pujar assigned-clock-rates = <3072000>; 422177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 423177208f7SSameer Pujar status = "disabled"; 424177208f7SSameer Pujar }; 425177208f7SSameer Pujar 426177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 427177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 428177208f7SSameer Pujar "nvidia,tegra210-dmic"; 429177208f7SSameer Pujar reg = <0x2904200 0x100>; 430177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431177208f7SSameer Pujar clock-names = "dmic"; 432177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434177208f7SSameer Pujar assigned-clock-rates = <3072000>; 435177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 436177208f7SSameer Pujar status = "disabled"; 437177208f7SSameer Pujar }; 438177208f7SSameer Pujar 439177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 440177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 441177208f7SSameer Pujar "nvidia,tegra210-dmic"; 442177208f7SSameer Pujar reg = <0x2904300 0x100>; 443177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444177208f7SSameer Pujar clock-names = "dmic"; 445177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447177208f7SSameer Pujar assigned-clock-rates = <3072000>; 448177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 449177208f7SSameer Pujar status = "disabled"; 450177208f7SSameer Pujar }; 451177208f7SSameer Pujar 452177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 453177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 454177208f7SSameer Pujar "nvidia,tegra186-dspk"; 455177208f7SSameer Pujar reg = <0x2905000 0x100>; 456177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457177208f7SSameer Pujar clock-names = "dspk"; 458177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460177208f7SSameer Pujar assigned-clock-rates = <12288000>; 461177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 462177208f7SSameer Pujar status = "disabled"; 463177208f7SSameer Pujar }; 464177208f7SSameer Pujar 465177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 466177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 467177208f7SSameer Pujar "nvidia,tegra186-dspk"; 468177208f7SSameer Pujar reg = <0x2905100 0x100>; 469177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470177208f7SSameer Pujar clock-names = "dspk"; 471177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473177208f7SSameer Pujar assigned-clock-rates = <12288000>; 474177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 475177208f7SSameer Pujar status = "disabled"; 476177208f7SSameer Pujar }; 477848f3290SSameer Pujar 478848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 479848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 480848f3290SSameer Pujar "nvidia,tegra210-sfc"; 481848f3290SSameer Pujar reg = <0x2902000 0x200>; 482848f3290SSameer Pujar sound-name-prefix = "SFC1"; 483848f3290SSameer Pujar status = "disabled"; 484848f3290SSameer Pujar }; 485848f3290SSameer Pujar 486848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 487848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 488848f3290SSameer Pujar "nvidia,tegra210-sfc"; 489848f3290SSameer Pujar reg = <0x2902200 0x200>; 490848f3290SSameer Pujar sound-name-prefix = "SFC2"; 491848f3290SSameer Pujar status = "disabled"; 492848f3290SSameer Pujar }; 493848f3290SSameer Pujar 494848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 495848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 496848f3290SSameer Pujar "nvidia,tegra210-sfc"; 497848f3290SSameer Pujar reg = <0x2902400 0x200>; 498848f3290SSameer Pujar sound-name-prefix = "SFC3"; 499848f3290SSameer Pujar status = "disabled"; 500848f3290SSameer Pujar }; 501848f3290SSameer Pujar 502848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 503848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 504848f3290SSameer Pujar "nvidia,tegra210-sfc"; 505848f3290SSameer Pujar reg = <0x2902600 0x200>; 506848f3290SSameer Pujar sound-name-prefix = "SFC4"; 507848f3290SSameer Pujar status = "disabled"; 508848f3290SSameer Pujar }; 509848f3290SSameer Pujar 510848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 511848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 512848f3290SSameer Pujar "nvidia,tegra210-mvc"; 513848f3290SSameer Pujar reg = <0x290a000 0x200>; 514848f3290SSameer Pujar sound-name-prefix = "MVC1"; 515848f3290SSameer Pujar status = "disabled"; 516848f3290SSameer Pujar }; 517848f3290SSameer Pujar 518848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 519848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 520848f3290SSameer Pujar "nvidia,tegra210-mvc"; 521848f3290SSameer Pujar reg = <0x290a200 0x200>; 522848f3290SSameer Pujar sound-name-prefix = "MVC2"; 523848f3290SSameer Pujar status = "disabled"; 524848f3290SSameer Pujar }; 525848f3290SSameer Pujar 526848f3290SSameer Pujar tegra_amx1: amx@2903000 { 527848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 528848f3290SSameer Pujar reg = <0x2903000 0x100>; 529848f3290SSameer Pujar sound-name-prefix = "AMX1"; 530848f3290SSameer Pujar status = "disabled"; 531848f3290SSameer Pujar }; 532848f3290SSameer Pujar 533848f3290SSameer Pujar tegra_amx2: amx@2903100 { 534848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 535848f3290SSameer Pujar reg = <0x2903100 0x100>; 536848f3290SSameer Pujar sound-name-prefix = "AMX2"; 537848f3290SSameer Pujar status = "disabled"; 538848f3290SSameer Pujar }; 539848f3290SSameer Pujar 540848f3290SSameer Pujar tegra_amx3: amx@2903200 { 541848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 542848f3290SSameer Pujar reg = <0x2903200 0x100>; 543848f3290SSameer Pujar sound-name-prefix = "AMX3"; 544848f3290SSameer Pujar status = "disabled"; 545848f3290SSameer Pujar }; 546848f3290SSameer Pujar 547848f3290SSameer Pujar tegra_amx4: amx@2903300 { 548848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 549848f3290SSameer Pujar reg = <0x2903300 0x100>; 550848f3290SSameer Pujar sound-name-prefix = "AMX4"; 551848f3290SSameer Pujar status = "disabled"; 552848f3290SSameer Pujar }; 553848f3290SSameer Pujar 554848f3290SSameer Pujar tegra_adx1: adx@2903800 { 555848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 556848f3290SSameer Pujar "nvidia,tegra210-adx"; 557848f3290SSameer Pujar reg = <0x2903800 0x100>; 558848f3290SSameer Pujar sound-name-prefix = "ADX1"; 559848f3290SSameer Pujar status = "disabled"; 560848f3290SSameer Pujar }; 561848f3290SSameer Pujar 562848f3290SSameer Pujar tegra_adx2: adx@2903900 { 563848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 564848f3290SSameer Pujar "nvidia,tegra210-adx"; 565848f3290SSameer Pujar reg = <0x2903900 0x100>; 566848f3290SSameer Pujar sound-name-prefix = "ADX2"; 567848f3290SSameer Pujar status = "disabled"; 568848f3290SSameer Pujar }; 569848f3290SSameer Pujar 570848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 571848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 572848f3290SSameer Pujar "nvidia,tegra210-adx"; 573848f3290SSameer Pujar reg = <0x2903a00 0x100>; 574848f3290SSameer Pujar sound-name-prefix = "ADX3"; 575848f3290SSameer Pujar status = "disabled"; 576848f3290SSameer Pujar }; 577848f3290SSameer Pujar 578848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 579848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 580848f3290SSameer Pujar "nvidia,tegra210-adx"; 581848f3290SSameer Pujar reg = <0x2903b00 0x100>; 582848f3290SSameer Pujar sound-name-prefix = "ADX4"; 583848f3290SSameer Pujar status = "disabled"; 584848f3290SSameer Pujar }; 585848f3290SSameer Pujar 5864b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5874b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 5884b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5894b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5904b6a1b7cSSameer Pujar #address-cells = <1>; 5914b6a1b7cSSameer Pujar #size-cells = <1>; 5924b6a1b7cSSameer Pujar ranges; 5934b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5944b6a1b7cSSameer Pujar status = "disabled"; 5954b6a1b7cSSameer Pujar 5964b6a1b7cSSameer Pujar equalizer@2908100 { 5974b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 5984b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5994b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 6004b6a1b7cSSameer Pujar }; 6014b6a1b7cSSameer Pujar 6024b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 6034b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 6044b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 6054b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 6064b6a1b7cSSameer Pujar }; 6074b6a1b7cSSameer Pujar }; 6084b6a1b7cSSameer Pujar 609848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 610848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 611848f3290SSameer Pujar "nvidia,tegra210-amixer"; 612848f3290SSameer Pujar reg = <0x290bb00 0x800>; 613848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 614848f3290SSameer Pujar status = "disabled"; 615848f3290SSameer Pujar }; 61647a08153SSameer Pujar 61747a08153SSameer Pujar tegra_asrc: asrc@2910000 { 61847a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 61947a08153SSameer Pujar "nvidia,tegra186-asrc"; 62047a08153SSameer Pujar reg = <0x2910000 0x2000>; 62147a08153SSameer Pujar sound-name-prefix = "ASRC1"; 62247a08153SSameer Pujar status = "disabled"; 62347a08153SSameer Pujar }; 624177208f7SSameer Pujar }; 6255d2249ddSSameer Pujar }; 6265d2249ddSSameer Pujar 627dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 628dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 629644c569dSThierry Reding reg = <0x2430000 0x17000>, 630644c569dSThierry Reding <0xc300000 0x4000>; 631dbb72e2cSVidya Sagar 632dbb72e2cSVidya Sagar status = "okay"; 633dbb72e2cSVidya Sagar 634dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 635dbb72e2cSVidya Sagar pex_rst { 636dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 637dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6396b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 641dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642dbb72e2cSVidya Sagar }; 643dbb72e2cSVidya Sagar }; 644dbb72e2cSVidya Sagar 645dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646dbb72e2cSVidya Sagar clkreq { 647dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 6506b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 652dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653dbb72e2cSVidya Sagar }; 654dbb72e2cSVidya Sagar }; 655dbb72e2cSVidya Sagar }; 656dbb72e2cSVidya Sagar 657be9b887fSThierry Reding mc: memory-controller@2c00000 { 658be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 659000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 660000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 661000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 662000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 663000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 664000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 665000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 666000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 667000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 668000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 669000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 670000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 671000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 672000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 673000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 674000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 675000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 676000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 677000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6808613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681d5237c7cSThierry Reding #interconnect-cells = <1>; 682be9b887fSThierry Reding status = "disabled"; 683be9b887fSThierry Reding 684be9b887fSThierry Reding #address-cells = <2>; 685be9b887fSThierry Reding #size-cells = <2>; 686be9b887fSThierry Reding 687be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690be9b887fSThierry Reding 691be9b887fSThierry Reding /* 692be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 693be9b887fSThierry Reding * controller selects the XBAR format used when memory 694be9b887fSThierry Reding * is accessed. This is used to transparently access 695be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 696be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 697be9b887fSThierry Reding * 698be9b887fSThierry Reding * As a consequence, the operating system must ensure 699be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 700be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 701be9b887fSThierry Reding * devices require access to the XBAR switch, their 702be9b887fSThierry Reding * drivers must set this bit explicitly. 703be9b887fSThierry Reding * 704be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 705be9b887fSThierry Reding */ 706be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707be9b887fSThierry Reding 708be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 709be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 710be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 711be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 712cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 714be9b887fSThierry Reding clock-names = "emc"; 715be9b887fSThierry Reding 716d5237c7cSThierry Reding #interconnect-cells = <0>; 717d5237c7cSThierry Reding 718be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 719be9b887fSThierry Reding }; 720be9b887fSThierry Reding }; 721be9b887fSThierry Reding 7225425fb15SMikko Perttunen uarta: serial@3100000 { 7235425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7245425fb15SMikko Perttunen reg = <0x03100000 0x40>; 7255425fb15SMikko Perttunen reg-shift = <2>; 7265425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7275425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7285425fb15SMikko Perttunen clock-names = "serial"; 7295425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7305425fb15SMikko Perttunen reset-names = "serial"; 7315425fb15SMikko Perttunen status = "disabled"; 7325425fb15SMikko Perttunen }; 7335425fb15SMikko Perttunen 7345425fb15SMikko Perttunen uartb: serial@3110000 { 7355425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7365425fb15SMikko Perttunen reg = <0x03110000 0x40>; 7375425fb15SMikko Perttunen reg-shift = <2>; 7385425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7395425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7405425fb15SMikko Perttunen clock-names = "serial"; 7415425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7425425fb15SMikko Perttunen reset-names = "serial"; 7435425fb15SMikko Perttunen status = "disabled"; 7445425fb15SMikko Perttunen }; 7455425fb15SMikko Perttunen 7465425fb15SMikko Perttunen uartd: serial@3130000 { 7475425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7485425fb15SMikko Perttunen reg = <0x03130000 0x40>; 7495425fb15SMikko Perttunen reg-shift = <2>; 7505425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7525425fb15SMikko Perttunen clock-names = "serial"; 7535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7545425fb15SMikko Perttunen reset-names = "serial"; 7555425fb15SMikko Perttunen status = "disabled"; 7565425fb15SMikko Perttunen }; 7575425fb15SMikko Perttunen 7585425fb15SMikko Perttunen uarte: serial@3140000 { 7595425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7605425fb15SMikko Perttunen reg = <0x03140000 0x40>; 7615425fb15SMikko Perttunen reg-shift = <2>; 7625425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7635425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7645425fb15SMikko Perttunen clock-names = "serial"; 7655425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7665425fb15SMikko Perttunen reset-names = "serial"; 7675425fb15SMikko Perttunen status = "disabled"; 7685425fb15SMikko Perttunen }; 7695425fb15SMikko Perttunen 7705425fb15SMikko Perttunen uartf: serial@3150000 { 7715425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7725425fb15SMikko Perttunen reg = <0x03150000 0x40>; 7735425fb15SMikko Perttunen reg-shift = <2>; 7745425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7755425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7765425fb15SMikko Perttunen clock-names = "serial"; 7775425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7785425fb15SMikko Perttunen reset-names = "serial"; 7795425fb15SMikko Perttunen status = "disabled"; 7805425fb15SMikko Perttunen }; 7815425fb15SMikko Perttunen 7825425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 783d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7845425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 7855425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 7865425fb15SMikko Perttunen #address-cells = <1>; 7875425fb15SMikko Perttunen #size-cells = <0>; 7885425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 7895425fb15SMikko Perttunen clock-names = "div-clk"; 7905425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 7915425fb15SMikko Perttunen reset-names = "i2c"; 7925425fb15SMikko Perttunen status = "disabled"; 7935425fb15SMikko Perttunen }; 7945425fb15SMikko Perttunen 7955425fb15SMikko Perttunen uarth: serial@3170000 { 7965425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7975425fb15SMikko Perttunen reg = <0x03170000 0x40>; 7985425fb15SMikko Perttunen reg-shift = <2>; 7995425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8005425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8015425fb15SMikko Perttunen clock-names = "serial"; 8025425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8035425fb15SMikko Perttunen reset-names = "serial"; 8045425fb15SMikko Perttunen status = "disabled"; 8055425fb15SMikko Perttunen }; 8065425fb15SMikko Perttunen 8075425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 808d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8095425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 8105425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8115425fb15SMikko Perttunen #address-cells = <1>; 8125425fb15SMikko Perttunen #size-cells = <0>; 8135425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8145425fb15SMikko Perttunen clock-names = "div-clk"; 8155425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8165425fb15SMikko Perttunen reset-names = "i2c"; 8175425fb15SMikko Perttunen status = "disabled"; 8185425fb15SMikko Perttunen }; 8195425fb15SMikko Perttunen 8205425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8215425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 822d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8235425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 8245425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8255425fb15SMikko Perttunen #address-cells = <1>; 8265425fb15SMikko Perttunen #size-cells = <0>; 8275425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8285425fb15SMikko Perttunen clock-names = "div-clk"; 8295425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8305425fb15SMikko Perttunen reset-names = "i2c"; 831a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 832a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 833a4131561SThierry Reding pinctrl-names = "default", "idle"; 8345425fb15SMikko Perttunen status = "disabled"; 8355425fb15SMikko Perttunen }; 8365425fb15SMikko Perttunen 8375425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8385425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 839d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8405425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 8415425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8425425fb15SMikko Perttunen #address-cells = <1>; 8435425fb15SMikko Perttunen #size-cells = <0>; 8445425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8455425fb15SMikko Perttunen clock-names = "div-clk"; 8465425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8475425fb15SMikko Perttunen reset-names = "i2c"; 848a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 849a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 850a4131561SThierry Reding pinctrl-names = "default", "idle"; 8515425fb15SMikko Perttunen status = "disabled"; 8525425fb15SMikko Perttunen }; 8535425fb15SMikko Perttunen 854a4131561SThierry Reding /* shares pads with dpaux2 */ 855a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 856d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8575425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 8585425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8595425fb15SMikko Perttunen #address-cells = <1>; 8605425fb15SMikko Perttunen #size-cells = <0>; 8615425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8625425fb15SMikko Perttunen clock-names = "div-clk"; 8635425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8645425fb15SMikko Perttunen reset-names = "i2c"; 865a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 866a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 867a4131561SThierry Reding pinctrl-names = "default", "idle"; 8685425fb15SMikko Perttunen status = "disabled"; 8695425fb15SMikko Perttunen }; 8705425fb15SMikko Perttunen 871a4131561SThierry Reding /* shares pads with dpaux3 */ 872a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 873d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8745425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 8755425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 8765425fb15SMikko Perttunen #address-cells = <1>; 8775425fb15SMikko Perttunen #size-cells = <0>; 8785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 8795425fb15SMikko Perttunen clock-names = "div-clk"; 8805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 8815425fb15SMikko Perttunen reset-names = "i2c"; 882a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 883a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 884a4131561SThierry Reding pinctrl-names = "default", "idle"; 8855425fb15SMikko Perttunen status = "disabled"; 8865425fb15SMikko Perttunen }; 8875425fb15SMikko Perttunen 88896ded827SSowjanya Komatineni spi@3270000 { 88996ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 89096ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 89196ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 89296ded827SSowjanya Komatineni #address-cells = <1>; 89396ded827SSowjanya Komatineni #size-cells = <0>; 89496ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 89596ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 89696ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 89796ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 89896ded827SSowjanya Komatineni reset-names = "qspi"; 89996ded827SSowjanya Komatineni status = "disabled"; 90096ded827SSowjanya Komatineni }; 90196ded827SSowjanya Komatineni 90296ded827SSowjanya Komatineni spi@3300000 { 90396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 90496ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 90596ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 90696ded827SSowjanya Komatineni #address-cells = <1>; 90796ded827SSowjanya Komatineni #size-cells = <0>; 90896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 90996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 91096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 91196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 91296ded827SSowjanya Komatineni reset-names = "qspi"; 91396ded827SSowjanya Komatineni status = "disabled"; 91496ded827SSowjanya Komatineni }; 91596ded827SSowjanya Komatineni 9166a574ec7SThierry Reding pwm1: pwm@3280000 { 9176a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9186a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9196a574ec7SThierry Reding reg = <0x3280000 0x10000>; 9206a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9216a574ec7SThierry Reding clock-names = "pwm"; 9226a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9236a574ec7SThierry Reding reset-names = "pwm"; 9246a574ec7SThierry Reding status = "disabled"; 9256a574ec7SThierry Reding #pwm-cells = <2>; 9266a574ec7SThierry Reding }; 9276a574ec7SThierry Reding 9286a574ec7SThierry Reding pwm2: pwm@3290000 { 9296a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9306a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9316a574ec7SThierry Reding reg = <0x3290000 0x10000>; 9326a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9336a574ec7SThierry Reding clock-names = "pwm"; 9346a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9356a574ec7SThierry Reding reset-names = "pwm"; 9366a574ec7SThierry Reding status = "disabled"; 9376a574ec7SThierry Reding #pwm-cells = <2>; 9386a574ec7SThierry Reding }; 9396a574ec7SThierry Reding 9406a574ec7SThierry Reding pwm3: pwm@32a0000 { 9416a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9426a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9436a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 9446a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9456a574ec7SThierry Reding clock-names = "pwm"; 9466a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9476a574ec7SThierry Reding reset-names = "pwm"; 9486a574ec7SThierry Reding status = "disabled"; 9496a574ec7SThierry Reding #pwm-cells = <2>; 9506a574ec7SThierry Reding }; 9516a574ec7SThierry Reding 9526a574ec7SThierry Reding pwm5: pwm@32c0000 { 9536a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9546a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9556a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 9566a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9576a574ec7SThierry Reding clock-names = "pwm"; 9586a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9596a574ec7SThierry Reding reset-names = "pwm"; 9606a574ec7SThierry Reding status = "disabled"; 9616a574ec7SThierry Reding #pwm-cells = <2>; 9626a574ec7SThierry Reding }; 9636a574ec7SThierry Reding 9646a574ec7SThierry Reding pwm6: pwm@32d0000 { 9656a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9666a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9676a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 9686a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 9696a574ec7SThierry Reding clock-names = "pwm"; 9706a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 9716a574ec7SThierry Reding reset-names = "pwm"; 9726a574ec7SThierry Reding status = "disabled"; 9736a574ec7SThierry Reding #pwm-cells = <2>; 9746a574ec7SThierry Reding }; 9756a574ec7SThierry Reding 9766a574ec7SThierry Reding pwm7: pwm@32e0000 { 9776a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9786a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9796a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 9806a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 9816a574ec7SThierry Reding clock-names = "pwm"; 9826a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 9836a574ec7SThierry Reding reset-names = "pwm"; 9846a574ec7SThierry Reding status = "disabled"; 9856a574ec7SThierry Reding #pwm-cells = <2>; 9866a574ec7SThierry Reding }; 9876a574ec7SThierry Reding 9886a574ec7SThierry Reding pwm8: pwm@32f0000 { 9896a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9906a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9916a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 9926a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 9936a574ec7SThierry Reding clock-names = "pwm"; 9946a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 9956a574ec7SThierry Reding reset-names = "pwm"; 9966a574ec7SThierry Reding status = "disabled"; 9976a574ec7SThierry Reding #pwm-cells = <2>; 9986a574ec7SThierry Reding }; 9996a574ec7SThierry Reding 100067bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10012c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10025425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 10035425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1004c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1005c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1006c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10077ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10087ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10097ac853baSAniruddha Rao assigned-clock-parents = 10107ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10117ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10125425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10135425fb15SMikko Perttunen reset-names = "sdhci"; 1014d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1015d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1016d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1017c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1018ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1019ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1020ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10214e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10224e0f1229SSowjanya Komatineni <0x07>; 10234e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10244e0f1229SSowjanya Komatineni <0x07>; 10254e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10274e0f1229SSowjanya Komatineni <0x07>; 10284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10304e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10314e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1032ff21087eSPrathamesh Shete sd-uhs-sdr25; 1033ff21087eSPrathamesh Shete sd-uhs-sdr50; 1034ff21087eSPrathamesh Shete sd-uhs-ddr50; 1035ff21087eSPrathamesh Shete sd-uhs-sdr104; 10365425fb15SMikko Perttunen status = "disabled"; 10375425fb15SMikko Perttunen }; 10385425fb15SMikko Perttunen 103967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10402c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10415425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 10425425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1043c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1044c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1045c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10467ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10477ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10487ac853baSAniruddha Rao assigned-clock-parents = 10497ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10507ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10515425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10525425fb15SMikko Perttunen reset-names = "sdhci"; 1053d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1054d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1055d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1056c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1057ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1058ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1059ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10644e0f1229SSowjanya Komatineni <0x07>; 10654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10674e0f1229SSowjanya Komatineni <0x07>; 10684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10694e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10704e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10714e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1072ff21087eSPrathamesh Shete sd-uhs-sdr25; 1073ff21087eSPrathamesh Shete sd-uhs-sdr50; 1074ff21087eSPrathamesh Shete sd-uhs-ddr50; 1075ff21087eSPrathamesh Shete sd-uhs-sdr104; 10765425fb15SMikko Perttunen status = "disabled"; 10775425fb15SMikko Perttunen }; 10785425fb15SMikko Perttunen 107967bb17f6SThierry Reding sdmmc4: mmc@3460000 { 10802c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10815425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 10825425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1083c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1084c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1085c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1086351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1087351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1088351648d0SSowjanya Komatineni assigned-clock-parents = 1089351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 10905425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 10915425fb15SMikko Perttunen reset-names = "sdhci"; 1092d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1093d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1094d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1095c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 10964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 10974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 10984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 10994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11004e0f1229SSowjanya Komatineni <0x0a>; 11014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11034e0f1229SSowjanya Komatineni <0x0a>; 11044e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11054e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11064e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1107c2fee443SPrathamesh Shete cap-mmc-highspeed; 1108c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1109c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1110c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1111c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1112dfd3cb6fSSowjanya Komatineni supports-cqe; 11135425fb15SMikko Perttunen status = "disabled"; 11145425fb15SMikko Perttunen }; 11155425fb15SMikko Perttunen 11164878cc0cSSameer Pujar hda@3510000 { 11174878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 11184878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 11194878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11204878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 112148f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 112248f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 112348f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11244878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1125146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1126146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11274878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1128d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1129d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1130d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1131c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11324878cc0cSSameer Pujar status = "disabled"; 11334878cc0cSSameer Pujar }; 11344878cc0cSSameer Pujar 1135fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1136fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1137fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1138fab7a039SJC Kuo <0x03540000 0x1000>; 1139fab7a039SJC Kuo reg-names = "padctl", "ao"; 11406450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1141fab7a039SJC Kuo 1142fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1143fab7a039SJC Kuo reset-names = "padctl"; 1144fab7a039SJC Kuo 1145fab7a039SJC Kuo status = "disabled"; 1146fab7a039SJC Kuo 1147fab7a039SJC Kuo pads { 1148fab7a039SJC Kuo usb2 { 1149fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1150fab7a039SJC Kuo clock-names = "trk"; 1151fab7a039SJC Kuo 1152fab7a039SJC Kuo lanes { 1153fab7a039SJC Kuo usb2-0 { 1154fab7a039SJC Kuo nvidia,function = "xusb"; 1155fab7a039SJC Kuo status = "disabled"; 1156fab7a039SJC Kuo #phy-cells = <0>; 1157fab7a039SJC Kuo }; 1158fab7a039SJC Kuo 1159fab7a039SJC Kuo usb2-1 { 1160fab7a039SJC Kuo nvidia,function = "xusb"; 1161fab7a039SJC Kuo status = "disabled"; 1162fab7a039SJC Kuo #phy-cells = <0>; 1163fab7a039SJC Kuo }; 1164fab7a039SJC Kuo 1165fab7a039SJC Kuo usb2-2 { 1166fab7a039SJC Kuo nvidia,function = "xusb"; 1167fab7a039SJC Kuo status = "disabled"; 1168fab7a039SJC Kuo #phy-cells = <0>; 1169fab7a039SJC Kuo }; 1170fab7a039SJC Kuo 1171fab7a039SJC Kuo usb2-3 { 1172fab7a039SJC Kuo nvidia,function = "xusb"; 1173fab7a039SJC Kuo status = "disabled"; 1174fab7a039SJC Kuo #phy-cells = <0>; 1175fab7a039SJC Kuo }; 1176fab7a039SJC Kuo }; 1177fab7a039SJC Kuo }; 1178fab7a039SJC Kuo 1179fab7a039SJC Kuo usb3 { 1180fab7a039SJC Kuo lanes { 1181fab7a039SJC Kuo usb3-0 { 1182fab7a039SJC Kuo nvidia,function = "xusb"; 1183fab7a039SJC Kuo status = "disabled"; 1184fab7a039SJC Kuo #phy-cells = <0>; 1185fab7a039SJC Kuo }; 1186fab7a039SJC Kuo 1187fab7a039SJC Kuo usb3-1 { 1188fab7a039SJC Kuo nvidia,function = "xusb"; 1189fab7a039SJC Kuo status = "disabled"; 1190fab7a039SJC Kuo #phy-cells = <0>; 1191fab7a039SJC Kuo }; 1192fab7a039SJC Kuo 1193fab7a039SJC Kuo usb3-2 { 1194fab7a039SJC Kuo nvidia,function = "xusb"; 1195fab7a039SJC Kuo status = "disabled"; 1196fab7a039SJC Kuo #phy-cells = <0>; 1197fab7a039SJC Kuo }; 1198fab7a039SJC Kuo 1199fab7a039SJC Kuo usb3-3 { 1200fab7a039SJC Kuo nvidia,function = "xusb"; 1201fab7a039SJC Kuo status = "disabled"; 1202fab7a039SJC Kuo #phy-cells = <0>; 1203fab7a039SJC Kuo }; 1204fab7a039SJC Kuo }; 1205fab7a039SJC Kuo }; 1206fab7a039SJC Kuo }; 1207fab7a039SJC Kuo 1208fab7a039SJC Kuo ports { 1209fab7a039SJC Kuo usb2-0 { 1210fab7a039SJC Kuo status = "disabled"; 1211fab7a039SJC Kuo }; 1212fab7a039SJC Kuo 1213fab7a039SJC Kuo usb2-1 { 1214fab7a039SJC Kuo status = "disabled"; 1215fab7a039SJC Kuo }; 1216fab7a039SJC Kuo 1217fab7a039SJC Kuo usb2-2 { 1218fab7a039SJC Kuo status = "disabled"; 1219fab7a039SJC Kuo }; 1220fab7a039SJC Kuo 1221fab7a039SJC Kuo usb2-3 { 1222fab7a039SJC Kuo status = "disabled"; 1223fab7a039SJC Kuo }; 1224fab7a039SJC Kuo 1225fab7a039SJC Kuo usb3-0 { 1226fab7a039SJC Kuo status = "disabled"; 1227fab7a039SJC Kuo }; 1228fab7a039SJC Kuo 1229fab7a039SJC Kuo usb3-1 { 1230fab7a039SJC Kuo status = "disabled"; 1231fab7a039SJC Kuo }; 1232fab7a039SJC Kuo 1233fab7a039SJC Kuo usb3-2 { 1234fab7a039SJC Kuo status = "disabled"; 1235fab7a039SJC Kuo }; 1236fab7a039SJC Kuo 1237fab7a039SJC Kuo usb3-3 { 1238fab7a039SJC Kuo status = "disabled"; 1239fab7a039SJC Kuo }; 1240fab7a039SJC Kuo }; 1241fab7a039SJC Kuo }; 1242fab7a039SJC Kuo 1243bc8788b2SNagarjuna Kristam usb@3550000 { 1244bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1245bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1246bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1247bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1248bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1249bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1250bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1251bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1252bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1253bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1254c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1255c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1256c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1257c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1258bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1259bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1260bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1261bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1262bc8788b2SNagarjuna Kristam status = "disabled"; 1263bc8788b2SNagarjuna Kristam }; 1264bc8788b2SNagarjuna Kristam 1265fab7a039SJC Kuo usb@3610000 { 1266fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1267fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1268fab7a039SJC Kuo <0x03600000 0x10000>; 1269fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1270fab7a039SJC Kuo 1271fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1272a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1273fab7a039SJC Kuo 1274fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1275fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1276fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1277fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1278fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1279fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1280fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1281fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1282fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1283fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1284fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1285fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1286fab7a039SJC Kuo "pll_e"; 1287c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1288c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1289c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1290c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1291fab7a039SJC Kuo 1292fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1293fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1294fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1295fab7a039SJC Kuo 1296fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1297fab7a039SJC Kuo status = "disabled"; 1298fab7a039SJC Kuo }; 1299fab7a039SJC Kuo 130009903c5eSJC Kuo fuse@3820000 { 130109903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 130209903c5eSJC Kuo reg = <0x03820000 0x10000>; 130309903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 130409903c5eSJC Kuo clock-names = "fuse"; 130509903c5eSJC Kuo }; 130609903c5eSJC Kuo 13075425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13085425fb15SMikko Perttunen compatible = "arm,gic-400"; 13095425fb15SMikko Perttunen #interrupt-cells = <3>; 13105425fb15SMikko Perttunen interrupt-controller; 13115425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 13125425fb15SMikko Perttunen <0x03882000 0x2000>, 13135425fb15SMikko Perttunen <0x03884000 0x2000>, 13145425fb15SMikko Perttunen <0x03886000 0x2000>; 13155425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13165425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13175425fb15SMikko Perttunen interrupt-parent = <&gic>; 13185425fb15SMikko Perttunen }; 13195425fb15SMikko Perttunen 1320badb80beSThierry Reding cec@3960000 { 1321badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1322badb80beSThierry Reding reg = <0x03960000 0x10000>; 1323badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1324badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1325badb80beSThierry Reding clock-names = "cec"; 1326badb80beSThierry Reding status = "disabled"; 1327badb80beSThierry Reding }; 1328badb80beSThierry Reding 13295425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1330cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13315425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1332a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1333a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1334a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1335a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1336a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1337a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1338a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1339a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1340a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1341a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1342a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1343a38570c2SMikko Perttunen "shared7"; 1344a38570c2SMikko Perttunen #mbox-cells = <2>; 1345a38570c2SMikko Perttunen }; 1346a38570c2SMikko Perttunen 13472602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13482602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13492602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 13502602c32fSVidya Sagar reg-names = "ctl"; 13512602c32fSVidya Sagar 13522602c32fSVidya Sagar #phy-cells = <0>; 13532602c32fSVidya Sagar }; 13542602c32fSVidya Sagar 13552602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 13562602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13572602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 13582602c32fSVidya Sagar reg-names = "ctl"; 13592602c32fSVidya Sagar 13602602c32fSVidya Sagar #phy-cells = <0>; 13612602c32fSVidya Sagar }; 13622602c32fSVidya Sagar 13632602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 13642602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13652602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 13662602c32fSVidya Sagar reg-names = "ctl"; 13672602c32fSVidya Sagar 13682602c32fSVidya Sagar #phy-cells = <0>; 13692602c32fSVidya Sagar }; 13702602c32fSVidya Sagar 13712602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 13722602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13732602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 13742602c32fSVidya Sagar reg-names = "ctl"; 13752602c32fSVidya Sagar 13762602c32fSVidya Sagar #phy-cells = <0>; 13772602c32fSVidya Sagar }; 13782602c32fSVidya Sagar 13792602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 13802602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13812602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 13822602c32fSVidya Sagar reg-names = "ctl"; 13832602c32fSVidya Sagar 13842602c32fSVidya Sagar #phy-cells = <0>; 13852602c32fSVidya Sagar }; 13862602c32fSVidya Sagar 13872602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 13882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13892602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 13902602c32fSVidya Sagar reg-names = "ctl"; 13912602c32fSVidya Sagar 13922602c32fSVidya Sagar #phy-cells = <0>; 13932602c32fSVidya Sagar }; 13942602c32fSVidya Sagar 13952602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 13962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13972602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 13982602c32fSVidya Sagar reg-names = "ctl"; 13992602c32fSVidya Sagar 14002602c32fSVidya Sagar #phy-cells = <0>; 14012602c32fSVidya Sagar }; 14022602c32fSVidya Sagar 14032602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14052602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 14062602c32fSVidya Sagar reg-names = "ctl"; 14072602c32fSVidya Sagar 14082602c32fSVidya Sagar #phy-cells = <0>; 14092602c32fSVidya Sagar }; 14102602c32fSVidya Sagar 14112602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14132602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 14142602c32fSVidya Sagar reg-names = "ctl"; 14152602c32fSVidya Sagar 14162602c32fSVidya Sagar #phy-cells = <0>; 14172602c32fSVidya Sagar }; 14182602c32fSVidya Sagar 14192602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14212602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 14222602c32fSVidya Sagar reg-names = "ctl"; 14232602c32fSVidya Sagar 14242602c32fSVidya Sagar #phy-cells = <0>; 14252602c32fSVidya Sagar }; 14262602c32fSVidya Sagar 14272602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14292602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 14302602c32fSVidya Sagar reg-names = "ctl"; 14312602c32fSVidya Sagar 14322602c32fSVidya Sagar #phy-cells = <0>; 14332602c32fSVidya Sagar }; 14342602c32fSVidya Sagar 14352602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14372602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 14382602c32fSVidya Sagar reg-names = "ctl"; 14392602c32fSVidya Sagar 14402602c32fSVidya Sagar #phy-cells = <0>; 14412602c32fSVidya Sagar }; 14422602c32fSVidya Sagar 14432602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14452602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 14462602c32fSVidya Sagar reg-names = "ctl"; 14472602c32fSVidya Sagar 14482602c32fSVidya Sagar #phy-cells = <0>; 14492602c32fSVidya Sagar }; 14502602c32fSVidya Sagar 14512602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14532602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 14542602c32fSVidya Sagar reg-names = "ctl"; 14552602c32fSVidya Sagar 14562602c32fSVidya Sagar #phy-cells = <0>; 14572602c32fSVidya Sagar }; 14582602c32fSVidya Sagar 14592602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 14602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14612602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 14622602c32fSVidya Sagar reg-names = "ctl"; 14632602c32fSVidya Sagar 14642602c32fSVidya Sagar #phy-cells = <0>; 14652602c32fSVidya Sagar }; 14662602c32fSVidya Sagar 14672602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 14682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14692602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 14702602c32fSVidya Sagar reg-names = "ctl"; 14712602c32fSVidya Sagar 14722602c32fSVidya Sagar #phy-cells = <0>; 14732602c32fSVidya Sagar }; 14742602c32fSVidya Sagar 14752602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 14762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14772602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 14782602c32fSVidya Sagar reg-names = "ctl"; 14792602c32fSVidya Sagar 14802602c32fSVidya Sagar #phy-cells = <0>; 14812602c32fSVidya Sagar }; 14822602c32fSVidya Sagar 14832602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 14842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14852602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 14862602c32fSVidya Sagar reg-names = "ctl"; 14872602c32fSVidya Sagar 14882602c32fSVidya Sagar #phy-cells = <0>; 14892602c32fSVidya Sagar }; 14902602c32fSVidya Sagar 14912602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 14922602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14932602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 14942602c32fSVidya Sagar reg-names = "ctl"; 14952602c32fSVidya Sagar 14962602c32fSVidya Sagar #phy-cells = <0>; 14972602c32fSVidya Sagar }; 14982602c32fSVidya Sagar 14992602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15002602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15012602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 15022602c32fSVidya Sagar reg-names = "ctl"; 15032602c32fSVidya Sagar 15042602c32fSVidya Sagar #phy-cells = <0>; 15052602c32fSVidya Sagar }; 15062602c32fSVidya Sagar 1507*a47e173eSSumit Gupta sce-noc@b600000 { 1508*a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 1509*a47e173eSSumit Gupta reg = <0xb600000 0x1000>; 1510*a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1511*a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1512*a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1513*a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1514*a47e173eSSumit Gupta status = "okay"; 1515*a47e173eSSumit Gupta }; 1516*a47e173eSSumit Gupta 1517*a47e173eSSumit Gupta rce-noc@be00000 { 1518*a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 1519*a47e173eSSumit Gupta reg = <0xbe00000 0x1000>; 1520*a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1521*a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1522*a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1523*a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1524*a47e173eSSumit Gupta status = "okay"; 1525*a47e173eSSumit Gupta }; 1526*a47e173eSSumit Gupta 1527a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1528cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15291741e187SDipen Patel reg = <0x0c150000 0x90000>; 1530a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1531a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1532a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1533a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1534a38570c2SMikko Perttunen /* 1535a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1536a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1537a38570c2SMikko Perttunen */ 1538a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15395425fb15SMikko Perttunen #mbox-cells = <2>; 15405425fb15SMikko Perttunen }; 15415425fb15SMikko Perttunen 15425425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1543d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15445425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 15455425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 15465425fb15SMikko Perttunen #address-cells = <1>; 15475425fb15SMikko Perttunen #size-cells = <0>; 15485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 15495425fb15SMikko Perttunen clock-names = "div-clk"; 15505425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 15515425fb15SMikko Perttunen reset-names = "i2c"; 15525425fb15SMikko Perttunen status = "disabled"; 15535425fb15SMikko Perttunen }; 15545425fb15SMikko Perttunen 15555425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1556d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15575425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 15585425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 15595425fb15SMikko Perttunen #address-cells = <1>; 15605425fb15SMikko Perttunen #size-cells = <0>; 15615425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 15625425fb15SMikko Perttunen clock-names = "div-clk"; 15635425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 15645425fb15SMikko Perttunen reset-names = "i2c"; 15655425fb15SMikko Perttunen status = "disabled"; 15665425fb15SMikko Perttunen }; 15675425fb15SMikko Perttunen 15685425fb15SMikko Perttunen uartc: serial@c280000 { 15695425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 15705425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 15715425fb15SMikko Perttunen reg-shift = <2>; 15725425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 15735425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 15745425fb15SMikko Perttunen clock-names = "serial"; 15755425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 15765425fb15SMikko Perttunen reset-names = "serial"; 15775425fb15SMikko Perttunen status = "disabled"; 15785425fb15SMikko Perttunen }; 15795425fb15SMikko Perttunen 15805425fb15SMikko Perttunen uartg: serial@c290000 { 15815425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 15825425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 15835425fb15SMikko Perttunen reg-shift = <2>; 15845425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 15855425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 15865425fb15SMikko Perttunen clock-names = "serial"; 15875425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 15885425fb15SMikko Perttunen reset-names = "serial"; 15895425fb15SMikko Perttunen status = "disabled"; 15905425fb15SMikko Perttunen }; 15915425fb15SMikko Perttunen 159237e5a31dSThierry Reding rtc: rtc@c2a0000 { 159337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 159437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 159537e5a31dSThierry Reding interrupt-parent = <&pmc>; 159637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 159737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 159837e5a31dSThierry Reding clock-names = "rtc"; 159937e5a31dSThierry Reding status = "disabled"; 160037e5a31dSThierry Reding }; 160137e5a31dSThierry Reding 16024d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16034d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16044d286331SThierry Reding reg-names = "security", "gpio"; 16054d286331SThierry Reding reg = <0xc2f0000 0x1000>, 16064d286331SThierry Reding <0xc2f1000 0x1000>; 16070a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16080a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16090a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16100a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16114d286331SThierry Reding gpio-controller; 16124d286331SThierry Reding #gpio-cells = <2>; 16134d286331SThierry Reding interrupt-controller; 16144d286331SThierry Reding #interrupt-cells = <2>; 16154d286331SThierry Reding }; 16164d286331SThierry Reding 16176a574ec7SThierry Reding pwm4: pwm@c340000 { 16186a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16196a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16206a574ec7SThierry Reding reg = <0xc340000 0x10000>; 16216a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16226a574ec7SThierry Reding clock-names = "pwm"; 16236a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16246a574ec7SThierry Reding reset-names = "pwm"; 16256a574ec7SThierry Reding status = "disabled"; 16266a574ec7SThierry Reding #pwm-cells = <2>; 16276a574ec7SThierry Reding }; 16286a574ec7SThierry Reding 162938ecf1e5SThierry Reding pmc: pmc@c360000 { 16305425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 16315425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 16325425fb15SMikko Perttunen <0x0c370000 0x10000>, 16335425fb15SMikko Perttunen <0x0c380000 0x10000>, 16345425fb15SMikko Perttunen <0x0c390000 0x10000>, 16355425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 16365425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 163738ecf1e5SThierry Reding 163838ecf1e5SThierry Reding #interrupt-cells = <2>; 163938ecf1e5SThierry Reding interrupt-controller; 1640ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1641ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1642ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1643ff21087eSPrathamesh Shete }; 1644ff21087eSPrathamesh Shete 1645ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1646ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1647ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1648ff21087eSPrathamesh Shete }; 1649ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1650ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1651ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1652ff21087eSPrathamesh Shete }; 1653ff21087eSPrathamesh Shete 1654ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1655ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1656ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1657ff21087eSPrathamesh Shete }; 1658ff21087eSPrathamesh Shete 16595425fb15SMikko Perttunen }; 16603db6d3baSThierry Reding 1661*a47e173eSSumit Gupta aon-noc@c600000 { 1662*a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 1663*a47e173eSSumit Gupta reg = <0xc600000 0x1000>; 1664*a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1665*a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1666*a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1667*a47e173eSSumit Gupta status = "okay"; 1668*a47e173eSSumit Gupta }; 1669*a47e173eSSumit Gupta 1670*a47e173eSSumit Gupta bpmp-noc@d600000 { 1671*a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 1672*a47e173eSSumit Gupta reg = <0xd600000 0x1000>; 1673*a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1674*a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1675*a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1676*a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1677*a47e173eSSumit Gupta status = "okay"; 1678*a47e173eSSumit Gupta }; 1679*a47e173eSSumit Gupta 1680e762232fSJon Hunter iommu@10000000 { 1681e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1682e762232fSJon Hunter reg = <0x10000000 0x800000>; 1683e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1684e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1685e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1686e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1687e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1688e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1689e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1690e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1691e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1692e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1693e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1694e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1695e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1696e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1697e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1698e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1699e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1700e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1701e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1702e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1703e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1704e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1705e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1706e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1707e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1708e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1709e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1710e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1711e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1712e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1713e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1714e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1715e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1716e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1717e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1718e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1719e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1720e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1721e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1722e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1723e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1724e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1725e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1726e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1727e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1728e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1729e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1730e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1731e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1748e762232fSJon Hunter stream-match-mask = <0x7f80>; 1749e762232fSJon Hunter #global-interrupts = <1>; 1750e762232fSJon Hunter #iommu-cells = <1>; 1751e762232fSJon Hunter 1752e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1753ebea268eSJon Hunter status = "disabled"; 1754e762232fSJon Hunter }; 1755e762232fSJon Hunter 1756c7289b1cSThierry Reding smmu: iommu@12000000 { 1757c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1758c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1759c7289b1cSThierry Reding <0x11000000 0x800000>; 1760c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1761c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1762c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1763c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1764c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1765c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1766c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1767c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1768c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1769c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1770c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1771c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1772c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1773c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1774c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1775c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1776c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1777c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1778c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1779c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1780c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1781c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1782c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1783c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1784c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1785c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1786c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1787c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1788c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1789c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1790c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1791c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1792c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1793c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1794c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1795c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1796c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1797c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1798c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1799c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1800c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1801c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1802c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1803c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1804c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1805c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1807c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1826c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1827c7289b1cSThierry Reding #global-interrupts = <2>; 1828c7289b1cSThierry Reding #iommu-cells = <1>; 1829c7289b1cSThierry Reding 1830c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1831c7289b1cSThierry Reding status = "okay"; 1832c7289b1cSThierry Reding }; 1833c7289b1cSThierry Reding 18343db6d3baSThierry Reding host1x@13e00000 { 1835ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 18363db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 18373db6d3baSThierry Reding <0x13e10000 0x10000>; 18383db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 18393db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 18403db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1841052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 18423db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 18433db6d3baSThierry Reding clock-names = "host1x"; 18443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 18453db6d3baSThierry Reding reset-names = "host1x"; 18463db6d3baSThierry Reding 18473db6d3baSThierry Reding #address-cells = <1>; 18483db6d3baSThierry Reding #size-cells = <1>; 18493db6d3baSThierry Reding 18503db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1851d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1852d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1853c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 18543db6d3baSThierry Reding 185578a05873SMikko Perttunen nvdec@15140000 { 185678a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 185778a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 185878a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 185978a05873SMikko Perttunen clock-names = "nvdec"; 186078a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 186178a05873SMikko Perttunen reset-names = "nvdec"; 186278a05873SMikko Perttunen 186378a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 186478a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 186578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 186678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 186778a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 186878a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 186978a05873SMikko Perttunen dma-coherent; 187078a05873SMikko Perttunen 187178a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 187278a05873SMikko Perttunen }; 187378a05873SMikko Perttunen 18743db6d3baSThierry Reding display-hub@15200000 { 1875aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1876611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 18773db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 18783db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 18793db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 18803db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 18813db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 18823db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 18833db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 18843db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 18853db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 18863db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 18873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 18883db6d3baSThierry Reding clock-names = "disp", "hub"; 18893db6d3baSThierry Reding status = "disabled"; 18903db6d3baSThierry Reding 18913db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18923db6d3baSThierry Reding 18933db6d3baSThierry Reding #address-cells = <1>; 18943db6d3baSThierry Reding #size-cells = <1>; 18953db6d3baSThierry Reding 18963db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 18973db6d3baSThierry Reding 18983db6d3baSThierry Reding display@15200000 { 18993db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19003db6d3baSThierry Reding reg = <0x15200000 0x10000>; 19013db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19023db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19033db6d3baSThierry Reding clock-names = "dc"; 19043db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19053db6d3baSThierry Reding reset-names = "dc"; 19063db6d3baSThierry Reding 19073db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1908d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1909d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1910d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19113db6d3baSThierry Reding 19123db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19133db6d3baSThierry Reding nvidia,head = <0>; 19143db6d3baSThierry Reding }; 19153db6d3baSThierry Reding 19163db6d3baSThierry Reding display@15210000 { 19173db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19183db6d3baSThierry Reding reg = <0x15210000 0x10000>; 19193db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19203db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 19213db6d3baSThierry Reding clock-names = "dc"; 19223db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 19233db6d3baSThierry Reding reset-names = "dc"; 19243db6d3baSThierry Reding 19253db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1926d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1927d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1928d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19293db6d3baSThierry Reding 19303db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19313db6d3baSThierry Reding nvidia,head = <1>; 19323db6d3baSThierry Reding }; 19333db6d3baSThierry Reding 19343db6d3baSThierry Reding display@15220000 { 19353db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19363db6d3baSThierry Reding reg = <0x15220000 0x10000>; 19373db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 19383db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 19393db6d3baSThierry Reding clock-names = "dc"; 19403db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 19413db6d3baSThierry Reding reset-names = "dc"; 19423db6d3baSThierry Reding 19433db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1944d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1945d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1946d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19473db6d3baSThierry Reding 19483db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19493db6d3baSThierry Reding nvidia,head = <2>; 19503db6d3baSThierry Reding }; 19513db6d3baSThierry Reding 19523db6d3baSThierry Reding display@15230000 { 19533db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19543db6d3baSThierry Reding reg = <0x15230000 0x10000>; 19553db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 19563db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 19573db6d3baSThierry Reding clock-names = "dc"; 19583db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 19593db6d3baSThierry Reding reset-names = "dc"; 19603db6d3baSThierry Reding 19613db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1962d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1963d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1964d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19653db6d3baSThierry Reding 19663db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19673db6d3baSThierry Reding nvidia,head = <3>; 19683db6d3baSThierry Reding }; 19693db6d3baSThierry Reding }; 19703db6d3baSThierry Reding 19718d424ec2SThierry Reding vic@15340000 { 19728d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 19738d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 19748d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 19758d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 19768d424ec2SThierry Reding clock-names = "vic"; 19778d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 19788d424ec2SThierry Reding reset-names = "vic"; 19798d424ec2SThierry Reding 19808d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1981d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1982d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1983d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1984c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 1985a52280c8SJon Hunter dma-coherent; 19868d424ec2SThierry Reding }; 19878d424ec2SThierry Reding 1988f7eb2785SJon Hunter nvjpg@15380000 { 1989f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 1990f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1991f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1992f7eb2785SJon Hunter clock-names = "nvjpg"; 1993f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 1994f7eb2785SJon Hunter reset-names = "nvjpg"; 1995f7eb2785SJon Hunter 1996f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1997f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1998f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1999f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2000f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2001f7eb2785SJon Hunter dma-coherent; 2002f7eb2785SJon Hunter }; 2003f7eb2785SJon Hunter 200478a05873SMikko Perttunen nvdec@15480000 { 200578a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 200678a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 200778a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 200878a05873SMikko Perttunen clock-names = "nvdec"; 200978a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 201078a05873SMikko Perttunen reset-names = "nvdec"; 201178a05873SMikko Perttunen 201278a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 201378a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 201478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 201578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 201678a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 201778a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 201878a05873SMikko Perttunen dma-coherent; 201978a05873SMikko Perttunen 202078a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 202178a05873SMikko Perttunen }; 202278a05873SMikko Perttunen 2023f7eb2785SJon Hunter nvenc@154c0000 { 2024f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2025f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 2026f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2027f7eb2785SJon Hunter clock-names = "nvenc"; 2028f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2029f7eb2785SJon Hunter reset-names = "nvenc"; 2030f7eb2785SJon Hunter 2031f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2032f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2033f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2034f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2035f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2036f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2037f7eb2785SJon Hunter dma-coherent; 2038f7eb2785SJon Hunter 2039f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2040f7eb2785SJon Hunter }; 2041f7eb2785SJon Hunter 20423db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 20433db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 20443db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 20453db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 20463db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 20473db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 20483db6d3baSThierry Reding clock-names = "dpaux", "parent"; 20493db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 20503db6d3baSThierry Reding reset-names = "dpaux"; 20513db6d3baSThierry Reding status = "disabled"; 20523db6d3baSThierry Reding 20533db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20543db6d3baSThierry Reding 20553db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 20563db6d3baSThierry Reding groups = "dpaux-io"; 20573db6d3baSThierry Reding function = "aux"; 20583db6d3baSThierry Reding }; 20593db6d3baSThierry Reding 20603db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 20613db6d3baSThierry Reding groups = "dpaux-io"; 20623db6d3baSThierry Reding function = "i2c"; 20633db6d3baSThierry Reding }; 20643db6d3baSThierry Reding 20653db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 20663db6d3baSThierry Reding groups = "dpaux-io"; 20673db6d3baSThierry Reding function = "off"; 20683db6d3baSThierry Reding }; 20693db6d3baSThierry Reding 20703db6d3baSThierry Reding i2c-bus { 20713db6d3baSThierry Reding #address-cells = <1>; 20723db6d3baSThierry Reding #size-cells = <0>; 20733db6d3baSThierry Reding }; 20743db6d3baSThierry Reding }; 20753db6d3baSThierry Reding 20763db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 20773db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 20783db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 20793db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 20803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 20813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 20823db6d3baSThierry Reding clock-names = "dpaux", "parent"; 20833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 20843db6d3baSThierry Reding reset-names = "dpaux"; 20853db6d3baSThierry Reding status = "disabled"; 20863db6d3baSThierry Reding 20873db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20883db6d3baSThierry Reding 20893db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 20903db6d3baSThierry Reding groups = "dpaux-io"; 20913db6d3baSThierry Reding function = "aux"; 20923db6d3baSThierry Reding }; 20933db6d3baSThierry Reding 20943db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 20953db6d3baSThierry Reding groups = "dpaux-io"; 20963db6d3baSThierry Reding function = "i2c"; 20973db6d3baSThierry Reding }; 20983db6d3baSThierry Reding 20993db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21003db6d3baSThierry Reding groups = "dpaux-io"; 21013db6d3baSThierry Reding function = "off"; 21023db6d3baSThierry Reding }; 21033db6d3baSThierry Reding 21043db6d3baSThierry Reding i2c-bus { 21053db6d3baSThierry Reding #address-cells = <1>; 21063db6d3baSThierry Reding #size-cells = <0>; 21073db6d3baSThierry Reding }; 21083db6d3baSThierry Reding }; 21093db6d3baSThierry Reding 21103db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21113db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21123db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 21133db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21163db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21183db6d3baSThierry Reding reset-names = "dpaux"; 21193db6d3baSThierry Reding status = "disabled"; 21203db6d3baSThierry Reding 21213db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21223db6d3baSThierry Reding 21233db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 21243db6d3baSThierry Reding groups = "dpaux-io"; 21253db6d3baSThierry Reding function = "aux"; 21263db6d3baSThierry Reding }; 21273db6d3baSThierry Reding 21283db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 21293db6d3baSThierry Reding groups = "dpaux-io"; 21303db6d3baSThierry Reding function = "i2c"; 21313db6d3baSThierry Reding }; 21323db6d3baSThierry Reding 21333db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 21343db6d3baSThierry Reding groups = "dpaux-io"; 21353db6d3baSThierry Reding function = "off"; 21363db6d3baSThierry Reding }; 21373db6d3baSThierry Reding 21383db6d3baSThierry Reding i2c-bus { 21393db6d3baSThierry Reding #address-cells = <1>; 21403db6d3baSThierry Reding #size-cells = <0>; 21413db6d3baSThierry Reding }; 21423db6d3baSThierry Reding }; 21433db6d3baSThierry Reding 21443db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 21453db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21463db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 21473db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 21483db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 21493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21503db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21513db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 21523db6d3baSThierry Reding reset-names = "dpaux"; 21533db6d3baSThierry Reding status = "disabled"; 21543db6d3baSThierry Reding 21553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21563db6d3baSThierry Reding 21573db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 21583db6d3baSThierry Reding groups = "dpaux-io"; 21593db6d3baSThierry Reding function = "aux"; 21603db6d3baSThierry Reding }; 21613db6d3baSThierry Reding 21623db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 21633db6d3baSThierry Reding groups = "dpaux-io"; 21643db6d3baSThierry Reding function = "i2c"; 21653db6d3baSThierry Reding }; 21663db6d3baSThierry Reding 21673db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 21683db6d3baSThierry Reding groups = "dpaux-io"; 21693db6d3baSThierry Reding function = "off"; 21703db6d3baSThierry Reding }; 21713db6d3baSThierry Reding 21723db6d3baSThierry Reding i2c-bus { 21733db6d3baSThierry Reding #address-cells = <1>; 21743db6d3baSThierry Reding #size-cells = <0>; 21753db6d3baSThierry Reding }; 21763db6d3baSThierry Reding }; 21773db6d3baSThierry Reding 2178f7eb2785SJon Hunter nvenc@15a80000 { 2179f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2180f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2181f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2182f7eb2785SJon Hunter clock-names = "nvenc"; 2183f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2184f7eb2785SJon Hunter reset-names = "nvenc"; 2185f7eb2785SJon Hunter 2186f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2187f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2188f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2189f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2190f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2191f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2192f7eb2785SJon Hunter dma-coherent; 2193f7eb2785SJon Hunter 2194f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2195f7eb2785SJon Hunter }; 2196f7eb2785SJon Hunter 21973db6d3baSThierry Reding sor0: sor@15b00000 { 21983db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21993db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 22003db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22013db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22073db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22083db6d3baSThierry Reding "pad"; 22093db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22103db6d3baSThierry Reding reset-names = "sor"; 22113db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22123db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22133db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22143db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22153db6d3baSThierry Reding status = "disabled"; 22163db6d3baSThierry Reding 22173db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22183db6d3baSThierry Reding nvidia,interface = <0>; 22193db6d3baSThierry Reding }; 22203db6d3baSThierry Reding 22213db6d3baSThierry Reding sor1: sor@15b40000 { 22223db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2223939e7430SThierry Reding reg = <0x15b40000 0x40000>; 22243db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 22253db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 22263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 22273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 22283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 22313db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22323db6d3baSThierry Reding "pad"; 22333db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 22343db6d3baSThierry Reding reset-names = "sor"; 22353db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 22363db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 22373db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 22383db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22393db6d3baSThierry Reding status = "disabled"; 22403db6d3baSThierry Reding 22413db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22423db6d3baSThierry Reding nvidia,interface = <1>; 22433db6d3baSThierry Reding }; 22443db6d3baSThierry Reding 22453db6d3baSThierry Reding sor2: sor@15b80000 { 22463db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22473db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 22483db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 22493db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 22503db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 22513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 22523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 22553db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22563db6d3baSThierry Reding "pad"; 22573db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 22583db6d3baSThierry Reding reset-names = "sor"; 22593db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 22603db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 22613db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 22623db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22633db6d3baSThierry Reding status = "disabled"; 22643db6d3baSThierry Reding 22653db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22663db6d3baSThierry Reding nvidia,interface = <2>; 22673db6d3baSThierry Reding }; 22683db6d3baSThierry Reding 22693db6d3baSThierry Reding sor3: sor@15bc0000 { 22703db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22713db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 22723db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 22733db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 22743db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 22753db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 22763db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 22793db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22803db6d3baSThierry Reding "pad"; 22813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 22823db6d3baSThierry Reding reset-names = "sor"; 22833db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 22843db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 22853db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 22863db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22873db6d3baSThierry Reding status = "disabled"; 22883db6d3baSThierry Reding 22893db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22903db6d3baSThierry Reding nvidia,interface = <3>; 22913db6d3baSThierry Reding }; 22923db6d3baSThierry Reding }; 22930f134e39SThierry Reding 22940f134e39SThierry Reding gpu@17000000 { 22950f134e39SThierry Reding compatible = "nvidia,gv11b"; 2296818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2297818ae79aSThierry Reding <0x18000000 0x1000000>; 22980f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 22990f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 23000f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 23010f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 23020f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 23030f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 23040f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 23050f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 23060f134e39SThierry Reding reset-names = "gpu"; 23070f134e39SThierry Reding dma-coherent; 23080f134e39SThierry Reding 23090f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 23100f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 23110f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 23120f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 23130f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 23140f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 23150f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 23160f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 23170f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 23180f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 23190f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 23200f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 23210f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 23220f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 23230f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 23240f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 23250f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 23260f134e39SThierry Reding }; 23275425fb15SMikko Perttunen }; 23285425fb15SMikko Perttunen 23292602c32fSVidya Sagar pcie@14100000 { 2330f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23312602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2332644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2333644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2334644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2335644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23362602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23372602c32fSVidya Sagar 23382602c32fSVidya Sagar status = "disabled"; 23392602c32fSVidya Sagar 23402602c32fSVidya Sagar #address-cells = <3>; 23412602c32fSVidya Sagar #size-cells = <2>; 23422602c32fSVidya Sagar device_type = "pci"; 23432602c32fSVidya Sagar num-lanes = <1>; 23442602c32fSVidya Sagar linux,pci-domain = <1>; 23452602c32fSVidya Sagar 23462602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 23472602c32fSVidya Sagar clock-names = "core"; 23482602c32fSVidya Sagar 23492602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 23502602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 23512602c32fSVidya Sagar reset-names = "apb", "core"; 23522602c32fSVidya Sagar 23532602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23542602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23552602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23562602c32fSVidya Sagar 23572602c32fSVidya Sagar #interrupt-cells = <1>; 23582602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23592602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 23602602c32fSVidya Sagar 23612602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 23622602c32fSVidya Sagar 23632602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23642602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23652602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23662602c32fSVidya Sagar 23672602c32fSVidya Sagar bus-range = <0x0 0xff>; 2368d5237c7cSThierry Reding 23698a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23708a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 23718a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2372d5237c7cSThierry Reding 2373d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2374d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2375ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2376ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2377ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2378ba02920cSVidya Sagar dma-coherent; 23792602c32fSVidya Sagar }; 23802602c32fSVidya Sagar 23812602c32fSVidya Sagar pcie@14120000 { 2382f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23832602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2384644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2385644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2386644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2387644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23882602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23892602c32fSVidya Sagar 23902602c32fSVidya Sagar status = "disabled"; 23912602c32fSVidya Sagar 23922602c32fSVidya Sagar #address-cells = <3>; 23932602c32fSVidya Sagar #size-cells = <2>; 23942602c32fSVidya Sagar device_type = "pci"; 23952602c32fSVidya Sagar num-lanes = <1>; 23962602c32fSVidya Sagar linux,pci-domain = <2>; 23972602c32fSVidya Sagar 23982602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 23992602c32fSVidya Sagar clock-names = "core"; 24002602c32fSVidya Sagar 24012602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24022602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24032602c32fSVidya Sagar reset-names = "apb", "core"; 24042602c32fSVidya Sagar 24052602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24062602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24072602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24082602c32fSVidya Sagar 24092602c32fSVidya Sagar #interrupt-cells = <1>; 24102602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24112602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24122602c32fSVidya Sagar 24132602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24142602c32fSVidya Sagar 24152602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24162602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24172602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24182602c32fSVidya Sagar 24192602c32fSVidya Sagar bus-range = <0x0 0xff>; 2420d5237c7cSThierry Reding 24218a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24228a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24238a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2424d5237c7cSThierry Reding 2425d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2426d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2427ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2428ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2429ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2430ba02920cSVidya Sagar dma-coherent; 24312602c32fSVidya Sagar }; 24322602c32fSVidya Sagar 24332602c32fSVidya Sagar pcie@14140000 { 2434f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24352602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2436644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2437644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2438644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2439644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24402602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24412602c32fSVidya Sagar 24422602c32fSVidya Sagar status = "disabled"; 24432602c32fSVidya Sagar 24442602c32fSVidya Sagar #address-cells = <3>; 24452602c32fSVidya Sagar #size-cells = <2>; 24462602c32fSVidya Sagar device_type = "pci"; 24472602c32fSVidya Sagar num-lanes = <1>; 24482602c32fSVidya Sagar linux,pci-domain = <3>; 24492602c32fSVidya Sagar 24502602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 24512602c32fSVidya Sagar clock-names = "core"; 24522602c32fSVidya Sagar 24532602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 24542602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 24552602c32fSVidya Sagar reset-names = "apb", "core"; 24562602c32fSVidya Sagar 24572602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24582602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24592602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24602602c32fSVidya Sagar 24612602c32fSVidya Sagar #interrupt-cells = <1>; 24622602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24632602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 24642602c32fSVidya Sagar 24652602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 24662602c32fSVidya Sagar 24672602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24682602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24692602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24702602c32fSVidya Sagar 24712602c32fSVidya Sagar bus-range = <0x0 0xff>; 2472d5237c7cSThierry Reding 24738a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24748a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 24758a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2476d5237c7cSThierry Reding 2477d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2478d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2479ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2480ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2481ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2482ba02920cSVidya Sagar dma-coherent; 24832602c32fSVidya Sagar }; 24842602c32fSVidya Sagar 24852602c32fSVidya Sagar pcie@14160000 { 2486f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24872602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2488644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2489644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2490644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2491644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24922602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24932602c32fSVidya Sagar 24942602c32fSVidya Sagar status = "disabled"; 24952602c32fSVidya Sagar 24962602c32fSVidya Sagar #address-cells = <3>; 24972602c32fSVidya Sagar #size-cells = <2>; 24982602c32fSVidya Sagar device_type = "pci"; 24992602c32fSVidya Sagar num-lanes = <4>; 25002602c32fSVidya Sagar linux,pci-domain = <4>; 25012602c32fSVidya Sagar 25022602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25032602c32fSVidya Sagar clock-names = "core"; 25042602c32fSVidya Sagar 25052602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25062602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25072602c32fSVidya Sagar reset-names = "apb", "core"; 25082602c32fSVidya Sagar 25092602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25102602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25112602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25122602c32fSVidya Sagar 25132602c32fSVidya Sagar #interrupt-cells = <1>; 25142602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25152602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25162602c32fSVidya Sagar 25172602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25182602c32fSVidya Sagar 25192602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25202602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25212602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25222602c32fSVidya Sagar 25232602c32fSVidya Sagar bus-range = <0x0 0xff>; 2524d5237c7cSThierry Reding 25258a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25268a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25278a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2528d5237c7cSThierry Reding 2529d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2530d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2531ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2532ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2533ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2534ba02920cSVidya Sagar dma-coherent; 25352602c32fSVidya Sagar }; 25362602c32fSVidya Sagar 25372602c32fSVidya Sagar pcie@14180000 { 2538f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25392602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2540644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2541644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2542644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2543644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25442602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25452602c32fSVidya Sagar 25462602c32fSVidya Sagar status = "disabled"; 25472602c32fSVidya Sagar 25482602c32fSVidya Sagar #address-cells = <3>; 25492602c32fSVidya Sagar #size-cells = <2>; 25502602c32fSVidya Sagar device_type = "pci"; 25512602c32fSVidya Sagar num-lanes = <8>; 25522602c32fSVidya Sagar linux,pci-domain = <0>; 25532602c32fSVidya Sagar 25542602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 25552602c32fSVidya Sagar clock-names = "core"; 25562602c32fSVidya Sagar 25572602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 25582602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 25592602c32fSVidya Sagar reset-names = "apb", "core"; 25602602c32fSVidya Sagar 25612602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25622602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25632602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25642602c32fSVidya Sagar 25652602c32fSVidya Sagar #interrupt-cells = <1>; 25662602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25672602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 25682602c32fSVidya Sagar 25692602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 25702602c32fSVidya Sagar 25712602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25722602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25732602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25742602c32fSVidya Sagar 25752602c32fSVidya Sagar bus-range = <0x0 0xff>; 2576d5237c7cSThierry Reding 25778a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25788a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25798a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2580d5237c7cSThierry Reding 2581d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2582d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2583ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2584ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2585ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2586ba02920cSVidya Sagar dma-coherent; 25872602c32fSVidya Sagar }; 25882602c32fSVidya Sagar 25892602c32fSVidya Sagar pcie@141a0000 { 2590f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25912602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2592644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2593644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2594644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2595644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25962602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25972602c32fSVidya Sagar 25982602c32fSVidya Sagar status = "disabled"; 25992602c32fSVidya Sagar 26002602c32fSVidya Sagar #address-cells = <3>; 26012602c32fSVidya Sagar #size-cells = <2>; 26022602c32fSVidya Sagar device_type = "pci"; 26032602c32fSVidya Sagar num-lanes = <8>; 26042602c32fSVidya Sagar linux,pci-domain = <5>; 26052602c32fSVidya Sagar 2606dbb72e2cSVidya Sagar pinctrl-names = "default"; 2607dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2608dbb72e2cSVidya Sagar 2609c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2610c453cc9eSThierry Reding clock-names = "core"; 26112602c32fSVidya Sagar 26122602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26132602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26142602c32fSVidya Sagar reset-names = "apb", "core"; 26152602c32fSVidya Sagar 26162602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26172602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26182602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26192602c32fSVidya Sagar 26202602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 26212602c32fSVidya Sagar 26222602c32fSVidya Sagar #interrupt-cells = <1>; 26232602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26242602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 26252602c32fSVidya Sagar 26262602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26272602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26282602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26292602c32fSVidya Sagar 26302602c32fSVidya Sagar bus-range = <0x0 0xff>; 2631d5237c7cSThierry Reding 26328a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26338a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26348a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2635d5237c7cSThierry Reding 2636d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2637d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2638ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2639ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2640ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2641ba02920cSVidya Sagar dma-coherent; 26422602c32fSVidya Sagar }; 26432602c32fSVidya Sagar 2644b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2645bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 26460c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2647644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2648644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2649644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2650644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26510c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26520c988b73SVidya Sagar 26530c988b73SVidya Sagar status = "disabled"; 26540c988b73SVidya Sagar 26550c988b73SVidya Sagar num-lanes = <4>; 26560c988b73SVidya Sagar num-ib-windows = <2>; 26570c988b73SVidya Sagar num-ob-windows = <8>; 26580c988b73SVidya Sagar 26590c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 26600c988b73SVidya Sagar clock-names = "core"; 26610c988b73SVidya Sagar 26620c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 26630c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 26640c988b73SVidya Sagar reset-names = "apb", "core"; 26650c988b73SVidya Sagar 26660c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26670c988b73SVidya Sagar interrupt-names = "intr"; 26680c988b73SVidya Sagar 26690c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 26700c988b73SVidya Sagar 26710c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 26720c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26730c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2674ba02920cSVidya Sagar 2675ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2676ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2677ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2678ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2679ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2680ba02920cSVidya Sagar dma-coherent; 26810c988b73SVidya Sagar }; 26820c988b73SVidya Sagar 2683b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2684bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 26850c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2686644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2687644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2688644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2689644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26900c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26910c988b73SVidya Sagar 26920c988b73SVidya Sagar status = "disabled"; 26930c988b73SVidya Sagar 26940c988b73SVidya Sagar num-lanes = <8>; 26950c988b73SVidya Sagar num-ib-windows = <2>; 26960c988b73SVidya Sagar num-ob-windows = <8>; 26970c988b73SVidya Sagar 26980c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26990c988b73SVidya Sagar clock-names = "core"; 27000c988b73SVidya Sagar 27010c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 27020c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 27030c988b73SVidya Sagar reset-names = "apb", "core"; 27040c988b73SVidya Sagar 27050c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27060c988b73SVidya Sagar interrupt-names = "intr"; 27070c988b73SVidya Sagar 27080c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 27090c988b73SVidya Sagar 27100c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27110c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27120c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2713ba02920cSVidya Sagar 2714ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2715ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2716ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2717ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2718ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2719ba02920cSVidya Sagar dma-coherent; 27200c988b73SVidya Sagar }; 27210c988b73SVidya Sagar 2722b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2723bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27240c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2725644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2726644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2727644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2728644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27290c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27300c988b73SVidya Sagar 27310c988b73SVidya Sagar status = "disabled"; 27320c988b73SVidya Sagar 27330c988b73SVidya Sagar num-lanes = <8>; 27340c988b73SVidya Sagar num-ib-windows = <2>; 27350c988b73SVidya Sagar num-ob-windows = <8>; 27360c988b73SVidya Sagar 27370c988b73SVidya Sagar pinctrl-names = "default"; 27380c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 27390c988b73SVidya Sagar 27400c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 27410c988b73SVidya Sagar clock-names = "core"; 27420c988b73SVidya Sagar 27430c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27440c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27450c988b73SVidya Sagar reset-names = "apb", "core"; 27460c988b73SVidya Sagar 27470c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27480c988b73SVidya Sagar interrupt-names = "intr"; 27490c988b73SVidya Sagar 27500c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 27510c988b73SVidya Sagar 27520c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27530c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27540c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2755ba02920cSVidya Sagar 2756ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2757ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2758ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2759ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2760ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2761ba02920cSVidya Sagar dma-coherent; 27620c988b73SVidya Sagar }; 27630c988b73SVidya Sagar 2764e867fe41SThierry Reding sram@40000000 { 27655425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 27665425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 27675425fb15SMikko Perttunen #address-cells = <1>; 27685425fb15SMikko Perttunen #size-cells = <1>; 27695425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 277061192a9dSMikko Perttunen no-memory-wc; 27715425fb15SMikko Perttunen 2772e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 27735425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 27745425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 27755425fb15SMikko Perttunen pool; 27765425fb15SMikko Perttunen }; 27775425fb15SMikko Perttunen 2778e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 27795425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 27805425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 27815425fb15SMikko Perttunen pool; 27825425fb15SMikko Perttunen }; 27835425fb15SMikko Perttunen }; 27845425fb15SMikko Perttunen 27855425fb15SMikko Perttunen bpmp: bpmp { 27865425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 27875425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 27885425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 27897fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 27905425fb15SMikko Perttunen #clock-cells = <1>; 27915425fb15SMikko Perttunen #reset-cells = <1>; 27925425fb15SMikko Perttunen #power-domain-cells = <1>; 2793d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2794d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2795d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2796d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2797d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2798c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 27995425fb15SMikko Perttunen 28005425fb15SMikko Perttunen bpmp_i2c: i2c { 28015425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28025425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28035425fb15SMikko Perttunen #address-cells = <1>; 28045425fb15SMikko Perttunen #size-cells = <0>; 28055425fb15SMikko Perttunen }; 28065425fb15SMikko Perttunen 28075425fb15SMikko Perttunen bpmp_thermal: thermal { 28085425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28095425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28105425fb15SMikko Perttunen }; 28115425fb15SMikko Perttunen }; 28125425fb15SMikko Perttunen 28137780a034SMikko Perttunen cpus { 2814d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2815d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28167780a034SMikko Perttunen #address-cells = <1>; 28177780a034SMikko Perttunen #size-cells = <0>; 28187780a034SMikko Perttunen 2819b45d322cSThierry Reding cpu0_0: cpu@0 { 282031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28217780a034SMikko Perttunen device_type = "cpu"; 2822b45d322cSThierry Reding reg = <0x000>; 28237780a034SMikko Perttunen enable-method = "psci"; 2824b45d322cSThierry Reding i-cache-size = <131072>; 2825b45d322cSThierry Reding i-cache-line-size = <64>; 2826b45d322cSThierry Reding i-cache-sets = <512>; 2827b45d322cSThierry Reding d-cache-size = <65536>; 2828b45d322cSThierry Reding d-cache-line-size = <64>; 2829b45d322cSThierry Reding d-cache-sets = <256>; 2830b45d322cSThierry Reding next-level-cache = <&l2c_0>; 28317780a034SMikko Perttunen }; 28327780a034SMikko Perttunen 2833b45d322cSThierry Reding cpu0_1: cpu@1 { 283431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28357780a034SMikko Perttunen device_type = "cpu"; 2836b45d322cSThierry Reding reg = <0x001>; 28377780a034SMikko Perttunen enable-method = "psci"; 2838b45d322cSThierry Reding i-cache-size = <131072>; 2839b45d322cSThierry Reding i-cache-line-size = <64>; 2840b45d322cSThierry Reding i-cache-sets = <512>; 2841b45d322cSThierry Reding d-cache-size = <65536>; 2842b45d322cSThierry Reding d-cache-line-size = <64>; 2843b45d322cSThierry Reding d-cache-sets = <256>; 2844b45d322cSThierry Reding next-level-cache = <&l2c_0>; 28457780a034SMikko Perttunen }; 28467780a034SMikko Perttunen 2847b45d322cSThierry Reding cpu1_0: cpu@100 { 284831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28497780a034SMikko Perttunen device_type = "cpu"; 28507780a034SMikko Perttunen reg = <0x100>; 28517780a034SMikko Perttunen enable-method = "psci"; 2852b45d322cSThierry Reding i-cache-size = <131072>; 2853b45d322cSThierry Reding i-cache-line-size = <64>; 2854b45d322cSThierry Reding i-cache-sets = <512>; 2855b45d322cSThierry Reding d-cache-size = <65536>; 2856b45d322cSThierry Reding d-cache-line-size = <64>; 2857b45d322cSThierry Reding d-cache-sets = <256>; 2858b45d322cSThierry Reding next-level-cache = <&l2c_1>; 28597780a034SMikko Perttunen }; 28607780a034SMikko Perttunen 2861b45d322cSThierry Reding cpu1_1: cpu@101 { 286231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28637780a034SMikko Perttunen device_type = "cpu"; 28647780a034SMikko Perttunen reg = <0x101>; 28657780a034SMikko Perttunen enable-method = "psci"; 2866b45d322cSThierry Reding i-cache-size = <131072>; 2867b45d322cSThierry Reding i-cache-line-size = <64>; 2868b45d322cSThierry Reding i-cache-sets = <512>; 2869b45d322cSThierry Reding d-cache-size = <65536>; 2870b45d322cSThierry Reding d-cache-line-size = <64>; 2871b45d322cSThierry Reding d-cache-sets = <256>; 2872b45d322cSThierry Reding next-level-cache = <&l2c_1>; 28737780a034SMikko Perttunen }; 28747780a034SMikko Perttunen 2875b45d322cSThierry Reding cpu2_0: cpu@200 { 287631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28777780a034SMikko Perttunen device_type = "cpu"; 28787780a034SMikko Perttunen reg = <0x200>; 28797780a034SMikko Perttunen enable-method = "psci"; 2880b45d322cSThierry Reding i-cache-size = <131072>; 2881b45d322cSThierry Reding i-cache-line-size = <64>; 2882b45d322cSThierry Reding i-cache-sets = <512>; 2883b45d322cSThierry Reding d-cache-size = <65536>; 2884b45d322cSThierry Reding d-cache-line-size = <64>; 2885b45d322cSThierry Reding d-cache-sets = <256>; 2886b45d322cSThierry Reding next-level-cache = <&l2c_2>; 28877780a034SMikko Perttunen }; 28887780a034SMikko Perttunen 2889b45d322cSThierry Reding cpu2_1: cpu@201 { 289031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28917780a034SMikko Perttunen device_type = "cpu"; 28927780a034SMikko Perttunen reg = <0x201>; 28937780a034SMikko Perttunen enable-method = "psci"; 2894b45d322cSThierry Reding i-cache-size = <131072>; 2895b45d322cSThierry Reding i-cache-line-size = <64>; 2896b45d322cSThierry Reding i-cache-sets = <512>; 2897b45d322cSThierry Reding d-cache-size = <65536>; 2898b45d322cSThierry Reding d-cache-line-size = <64>; 2899b45d322cSThierry Reding d-cache-sets = <256>; 2900b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29017780a034SMikko Perttunen }; 29027780a034SMikko Perttunen 2903b45d322cSThierry Reding cpu3_0: cpu@300 { 290431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29057780a034SMikko Perttunen device_type = "cpu"; 2906b45d322cSThierry Reding reg = <0x300>; 29077780a034SMikko Perttunen enable-method = "psci"; 2908b45d322cSThierry Reding i-cache-size = <131072>; 2909b45d322cSThierry Reding i-cache-line-size = <64>; 2910b45d322cSThierry Reding i-cache-sets = <512>; 2911b45d322cSThierry Reding d-cache-size = <65536>; 2912b45d322cSThierry Reding d-cache-line-size = <64>; 2913b45d322cSThierry Reding d-cache-sets = <256>; 2914b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29157780a034SMikko Perttunen }; 29167780a034SMikko Perttunen 2917b45d322cSThierry Reding cpu3_1: cpu@301 { 291831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29197780a034SMikko Perttunen device_type = "cpu"; 2920b45d322cSThierry Reding reg = <0x301>; 29217780a034SMikko Perttunen enable-method = "psci"; 2922b45d322cSThierry Reding i-cache-size = <131072>; 2923b45d322cSThierry Reding i-cache-line-size = <64>; 2924b45d322cSThierry Reding i-cache-sets = <512>; 2925b45d322cSThierry Reding d-cache-size = <65536>; 2926b45d322cSThierry Reding d-cache-line-size = <64>; 2927b45d322cSThierry Reding d-cache-sets = <256>; 2928b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2929b45d322cSThierry Reding }; 2930b45d322cSThierry Reding 2931b45d322cSThierry Reding cpu-map { 2932b45d322cSThierry Reding cluster0 { 2933b45d322cSThierry Reding core0 { 2934b45d322cSThierry Reding cpu = <&cpu0_0>; 2935b45d322cSThierry Reding }; 2936b45d322cSThierry Reding 2937b45d322cSThierry Reding core1 { 2938b45d322cSThierry Reding cpu = <&cpu0_1>; 2939b45d322cSThierry Reding }; 2940b45d322cSThierry Reding }; 2941b45d322cSThierry Reding 2942b45d322cSThierry Reding cluster1 { 2943b45d322cSThierry Reding core0 { 2944b45d322cSThierry Reding cpu = <&cpu1_0>; 2945b45d322cSThierry Reding }; 2946b45d322cSThierry Reding 2947b45d322cSThierry Reding core1 { 2948b45d322cSThierry Reding cpu = <&cpu1_1>; 2949b45d322cSThierry Reding }; 2950b45d322cSThierry Reding }; 2951b45d322cSThierry Reding 2952b45d322cSThierry Reding cluster2 { 2953b45d322cSThierry Reding core0 { 2954b45d322cSThierry Reding cpu = <&cpu2_0>; 2955b45d322cSThierry Reding }; 2956b45d322cSThierry Reding 2957b45d322cSThierry Reding core1 { 2958b45d322cSThierry Reding cpu = <&cpu2_1>; 2959b45d322cSThierry Reding }; 2960b45d322cSThierry Reding }; 2961b45d322cSThierry Reding 2962b45d322cSThierry Reding cluster3 { 2963b45d322cSThierry Reding core0 { 2964b45d322cSThierry Reding cpu = <&cpu3_0>; 2965b45d322cSThierry Reding }; 2966b45d322cSThierry Reding 2967b45d322cSThierry Reding core1 { 2968b45d322cSThierry Reding cpu = <&cpu3_1>; 2969b45d322cSThierry Reding }; 2970b45d322cSThierry Reding }; 2971b45d322cSThierry Reding }; 2972b45d322cSThierry Reding 2973b45d322cSThierry Reding l2c_0: l2-cache0 { 2974b45d322cSThierry Reding cache-size = <2097152>; 2975b45d322cSThierry Reding cache-line-size = <64>; 2976b45d322cSThierry Reding cache-sets = <2048>; 2977b45d322cSThierry Reding next-level-cache = <&l3c>; 2978b45d322cSThierry Reding }; 2979b45d322cSThierry Reding 2980b45d322cSThierry Reding l2c_1: l2-cache1 { 2981b45d322cSThierry Reding cache-size = <2097152>; 2982b45d322cSThierry Reding cache-line-size = <64>; 2983b45d322cSThierry Reding cache-sets = <2048>; 2984b45d322cSThierry Reding next-level-cache = <&l3c>; 2985b45d322cSThierry Reding }; 2986b45d322cSThierry Reding 2987b45d322cSThierry Reding l2c_2: l2-cache2 { 2988b45d322cSThierry Reding cache-size = <2097152>; 2989b45d322cSThierry Reding cache-line-size = <64>; 2990b45d322cSThierry Reding cache-sets = <2048>; 2991b45d322cSThierry Reding next-level-cache = <&l3c>; 2992b45d322cSThierry Reding }; 2993b45d322cSThierry Reding 2994b45d322cSThierry Reding l2c_3: l2-cache3 { 2995b45d322cSThierry Reding cache-size = <2097152>; 2996b45d322cSThierry Reding cache-line-size = <64>; 2997b45d322cSThierry Reding cache-sets = <2048>; 2998b45d322cSThierry Reding next-level-cache = <&l3c>; 2999b45d322cSThierry Reding }; 3000b45d322cSThierry Reding 3001b45d322cSThierry Reding l3c: l3-cache { 3002b45d322cSThierry Reding cache-size = <4194304>; 3003b45d322cSThierry Reding cache-line-size = <64>; 3004b45d322cSThierry Reding cache-sets = <4096>; 30057780a034SMikko Perttunen }; 30067780a034SMikko Perttunen }; 30077780a034SMikko Perttunen 30089e79e58fSJon Hunter pmu { 3009f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 30109e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 30119e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 30129e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 30139e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 30149e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 30159e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 30169e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 30179e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 30189e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 30199e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 30209e79e58fSJon Hunter }; 30219e79e58fSJon Hunter 30227780a034SMikko Perttunen psci { 30237780a034SMikko Perttunen compatible = "arm,psci-1.0"; 30247780a034SMikko Perttunen status = "okay"; 30257780a034SMikko Perttunen method = "smc"; 30267780a034SMikko Perttunen }; 30277780a034SMikko Perttunen 30285b4f6323SSameer Pujar sound { 30295b4f6323SSameer Pujar status = "disabled"; 30305b4f6323SSameer Pujar 30315b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 30325b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 30335b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 30345b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 30355b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 30365b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 30375b4f6323SSameer Pujar assigned-clock-parents = <0>, 30385b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 30395b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 30405b4f6323SSameer Pujar /* 30415b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 30425b4f6323SSameer Pujar * for this to work and oscillate between base rates required 30435b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 30445b4f6323SSameer Pujar */ 30455b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 30465b4f6323SSameer Pujar }; 30475b4f6323SSameer Pujar 304899d9bde5SThierry Reding tcu: serial { 3049a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 3050a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3051a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3052a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 3053a38570c2SMikko Perttunen }; 3054a38570c2SMikko Perttunen 3055686ba009SThierry Reding thermal-zones { 3056fe57ff53SThierry Reding cpu-thermal { 3057fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3058686ba009SThierry Reding status = "disabled"; 3059686ba009SThierry Reding }; 3060686ba009SThierry Reding 3061fe57ff53SThierry Reding gpu-thermal { 3062fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3063686ba009SThierry Reding status = "disabled"; 3064686ba009SThierry Reding }; 3065686ba009SThierry Reding 3066fe57ff53SThierry Reding aux-thermal { 3067fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3068686ba009SThierry Reding status = "disabled"; 3069686ba009SThierry Reding }; 3070686ba009SThierry Reding 3071fe57ff53SThierry Reding pllx-thermal { 3072fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3073686ba009SThierry Reding status = "disabled"; 3074686ba009SThierry Reding }; 3075686ba009SThierry Reding 3076fe57ff53SThierry Reding ao-thermal { 3077fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3078686ba009SThierry Reding status = "disabled"; 3079686ba009SThierry Reding }; 3080686ba009SThierry Reding 3081fe57ff53SThierry Reding tj-thermal { 3082fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3083686ba009SThierry Reding status = "disabled"; 3084686ba009SThierry Reding }; 3085686ba009SThierry Reding }; 3086686ba009SThierry Reding 30875425fb15SMikko Perttunen timer { 30885425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 30895425fb15SMikko Perttunen interrupts = <GIC_PPI 13 30905425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 30915425fb15SMikko Perttunen <GIC_PPI 14 30925425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 30935425fb15SMikko Perttunen <GIC_PPI 11 30945425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 30955425fb15SMikko Perttunen <GIC_PPI 10 30965425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 30975425fb15SMikko Perttunen interrupt-parent = <&gic>; 3098b30be673SThierry Reding always-on; 30995425fb15SMikko Perttunen }; 31005425fb15SMikko Perttunen}; 3101