15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 65425fb15SMikko Perttunen#include <dt-bindings/reset/tegra194-reset.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 85425fb15SMikko Perttunen 95425fb15SMikko Perttunen/ { 105425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 115425fb15SMikko Perttunen interrupt-parent = <&gic>; 125425fb15SMikko Perttunen #address-cells = <2>; 135425fb15SMikko Perttunen #size-cells = <2>; 145425fb15SMikko Perttunen 155425fb15SMikko Perttunen /* control backbone */ 165425fb15SMikko Perttunen cbb { 175425fb15SMikko Perttunen compatible = "simple-bus"; 185425fb15SMikko Perttunen #address-cells = <1>; 195425fb15SMikko Perttunen #size-cells = <1>; 205425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 215425fb15SMikko Perttunen 22f69ce393SMikko Perttunen gpio: gpio@2200000 { 23f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 24f69ce393SMikko Perttunen reg-names = "security", "gpio"; 25f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 26f69ce393SMikko Perttunen <0x2210000 0x10000>; 27f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 28f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 29f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 30f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 31f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 32f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 33f69ce393SMikko Perttunen #interrupt-cells = <2>; 34f69ce393SMikko Perttunen interrupt-controller; 35f69ce393SMikko Perttunen #gpio-cells = <2>; 36f69ce393SMikko Perttunen gpio-controller; 37f69ce393SMikko Perttunen }; 38f69ce393SMikko Perttunen 39f89b58ceSMikko Perttunen ethernet@2490000 { 40f89b58ceSMikko Perttunen compatible = "nvidia,tegra186-eqos", 41f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 42f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 43f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 44f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 45f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 46f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 47f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 48f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 49f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 50f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 51f89b58ceSMikko Perttunen reset-names = "eqos"; 52f89b58ceSMikko Perttunen status = "disabled"; 53f89b58ceSMikko Perttunen 54f89b58ceSMikko Perttunen snps,write-requests = <1>; 55f89b58ceSMikko Perttunen snps,read-requests = <3>; 56f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 57f89b58ceSMikko Perttunen snps,txpbl = <16>; 58f89b58ceSMikko Perttunen snps,rxpbl = <8>; 59f89b58ceSMikko Perttunen }; 60f89b58ceSMikko Perttunen 615425fb15SMikko Perttunen uarta: serial@3100000 { 625425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 635425fb15SMikko Perttunen reg = <0x03100000 0x40>; 645425fb15SMikko Perttunen reg-shift = <2>; 655425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 665425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 675425fb15SMikko Perttunen clock-names = "serial"; 685425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 695425fb15SMikko Perttunen reset-names = "serial"; 705425fb15SMikko Perttunen status = "disabled"; 715425fb15SMikko Perttunen }; 725425fb15SMikko Perttunen 735425fb15SMikko Perttunen uartb: serial@3110000 { 745425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 755425fb15SMikko Perttunen reg = <0x03110000 0x40>; 765425fb15SMikko Perttunen reg-shift = <2>; 775425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 795425fb15SMikko Perttunen clock-names = "serial"; 805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 815425fb15SMikko Perttunen reset-names = "serial"; 825425fb15SMikko Perttunen status = "disabled"; 835425fb15SMikko Perttunen }; 845425fb15SMikko Perttunen 855425fb15SMikko Perttunen uartd: serial@3130000 { 865425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 875425fb15SMikko Perttunen reg = <0x03130000 0x40>; 885425fb15SMikko Perttunen reg-shift = <2>; 895425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 905425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 915425fb15SMikko Perttunen clock-names = "serial"; 925425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 935425fb15SMikko Perttunen reset-names = "serial"; 945425fb15SMikko Perttunen status = "disabled"; 955425fb15SMikko Perttunen }; 965425fb15SMikko Perttunen 975425fb15SMikko Perttunen uarte: serial@3140000 { 985425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 995425fb15SMikko Perttunen reg = <0x03140000 0x40>; 1005425fb15SMikko Perttunen reg-shift = <2>; 1015425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1025425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 1035425fb15SMikko Perttunen clock-names = "serial"; 1045425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 1055425fb15SMikko Perttunen reset-names = "serial"; 1065425fb15SMikko Perttunen status = "disabled"; 1075425fb15SMikko Perttunen }; 1085425fb15SMikko Perttunen 1095425fb15SMikko Perttunen uartf: serial@3150000 { 1105425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1115425fb15SMikko Perttunen reg = <0x03150000 0x40>; 1125425fb15SMikko Perttunen reg-shift = <2>; 1135425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 1155425fb15SMikko Perttunen clock-names = "serial"; 1165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 1175425fb15SMikko Perttunen reset-names = "serial"; 1185425fb15SMikko Perttunen status = "disabled"; 1195425fb15SMikko Perttunen }; 1205425fb15SMikko Perttunen 1215425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 122d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1235425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 1245425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1255425fb15SMikko Perttunen #address-cells = <1>; 1265425fb15SMikko Perttunen #size-cells = <0>; 1275425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 1285425fb15SMikko Perttunen clock-names = "div-clk"; 1295425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 1305425fb15SMikko Perttunen reset-names = "i2c"; 1315425fb15SMikko Perttunen status = "disabled"; 1325425fb15SMikko Perttunen }; 1335425fb15SMikko Perttunen 1345425fb15SMikko Perttunen uarth: serial@3170000 { 1355425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1365425fb15SMikko Perttunen reg = <0x03170000 0x40>; 1375425fb15SMikko Perttunen reg-shift = <2>; 1385425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 1395425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 1405425fb15SMikko Perttunen clock-names = "serial"; 1415425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 1425425fb15SMikko Perttunen reset-names = "serial"; 1435425fb15SMikko Perttunen status = "disabled"; 1445425fb15SMikko Perttunen }; 1455425fb15SMikko Perttunen 1465425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 147d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1485425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 1495425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1505425fb15SMikko Perttunen #address-cells = <1>; 1515425fb15SMikko Perttunen #size-cells = <0>; 1525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 1535425fb15SMikko Perttunen clock-names = "div-clk"; 1545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 1555425fb15SMikko Perttunen reset-names = "i2c"; 1565425fb15SMikko Perttunen status = "disabled"; 1575425fb15SMikko Perttunen }; 1585425fb15SMikko Perttunen 1595425fb15SMikko Perttunen /* shares pads with dpaux1 */ 1605425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 161d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1625425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 1635425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1645425fb15SMikko Perttunen #address-cells = <1>; 1655425fb15SMikko Perttunen #size-cells = <0>; 1665425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 1675425fb15SMikko Perttunen clock-names = "div-clk"; 1685425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 1695425fb15SMikko Perttunen reset-names = "i2c"; 1705425fb15SMikko Perttunen status = "disabled"; 1715425fb15SMikko Perttunen }; 1725425fb15SMikko Perttunen 1735425fb15SMikko Perttunen /* shares pads with dpaux0 */ 1745425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 175d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1765425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 1775425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1785425fb15SMikko Perttunen #address-cells = <1>; 1795425fb15SMikko Perttunen #size-cells = <0>; 1805425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 1815425fb15SMikko Perttunen clock-names = "div-clk"; 1825425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 1835425fb15SMikko Perttunen reset-names = "i2c"; 1845425fb15SMikko Perttunen status = "disabled"; 1855425fb15SMikko Perttunen }; 1865425fb15SMikko Perttunen 1875425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 188d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1895425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 1905425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1915425fb15SMikko Perttunen #address-cells = <1>; 1925425fb15SMikko Perttunen #size-cells = <0>; 1935425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 1945425fb15SMikko Perttunen clock-names = "div-clk"; 1955425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 1965425fb15SMikko Perttunen reset-names = "i2c"; 1975425fb15SMikko Perttunen status = "disabled"; 1985425fb15SMikko Perttunen }; 1995425fb15SMikko Perttunen 2005425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 201d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2025425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 2035425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2045425fb15SMikko Perttunen #address-cells = <1>; 2055425fb15SMikko Perttunen #size-cells = <0>; 2065425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 2075425fb15SMikko Perttunen clock-names = "div-clk"; 2085425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 2095425fb15SMikko Perttunen reset-names = "i2c"; 2105425fb15SMikko Perttunen status = "disabled"; 2115425fb15SMikko Perttunen }; 2125425fb15SMikko Perttunen 2136a574ec7SThierry Reding pwm1: pwm@3280000 { 2146a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2156a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2166a574ec7SThierry Reding reg = <0x3280000 0x10000>; 2176a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 2186a574ec7SThierry Reding clock-names = "pwm"; 2196a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 2206a574ec7SThierry Reding reset-names = "pwm"; 2216a574ec7SThierry Reding status = "disabled"; 2226a574ec7SThierry Reding #pwm-cells = <2>; 2236a574ec7SThierry Reding }; 2246a574ec7SThierry Reding 2256a574ec7SThierry Reding pwm2: pwm@3290000 { 2266a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2276a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2286a574ec7SThierry Reding reg = <0x3290000 0x10000>; 2296a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 2306a574ec7SThierry Reding clock-names = "pwm"; 2316a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 2326a574ec7SThierry Reding reset-names = "pwm"; 2336a574ec7SThierry Reding status = "disabled"; 2346a574ec7SThierry Reding #pwm-cells = <2>; 2356a574ec7SThierry Reding }; 2366a574ec7SThierry Reding 2376a574ec7SThierry Reding pwm3: pwm@32a0000 { 2386a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2396a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2406a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 2416a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 2426a574ec7SThierry Reding clock-names = "pwm"; 2436a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 2446a574ec7SThierry Reding reset-names = "pwm"; 2456a574ec7SThierry Reding status = "disabled"; 2466a574ec7SThierry Reding #pwm-cells = <2>; 2476a574ec7SThierry Reding }; 2486a574ec7SThierry Reding 2496a574ec7SThierry Reding pwm5: pwm@32c0000 { 2506a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2516a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2526a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 2536a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 2546a574ec7SThierry Reding clock-names = "pwm"; 2556a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 2566a574ec7SThierry Reding reset-names = "pwm"; 2576a574ec7SThierry Reding status = "disabled"; 2586a574ec7SThierry Reding #pwm-cells = <2>; 2596a574ec7SThierry Reding }; 2606a574ec7SThierry Reding 2616a574ec7SThierry Reding pwm6: pwm@32d0000 { 2626a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2636a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2646a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 2656a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 2666a574ec7SThierry Reding clock-names = "pwm"; 2676a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 2686a574ec7SThierry Reding reset-names = "pwm"; 2696a574ec7SThierry Reding status = "disabled"; 2706a574ec7SThierry Reding #pwm-cells = <2>; 2716a574ec7SThierry Reding }; 2726a574ec7SThierry Reding 2736a574ec7SThierry Reding pwm7: pwm@32e0000 { 2746a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2756a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2766a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 2776a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 2786a574ec7SThierry Reding clock-names = "pwm"; 2796a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 2806a574ec7SThierry Reding reset-names = "pwm"; 2816a574ec7SThierry Reding status = "disabled"; 2826a574ec7SThierry Reding #pwm-cells = <2>; 2836a574ec7SThierry Reding }; 2846a574ec7SThierry Reding 2856a574ec7SThierry Reding pwm8: pwm@32f0000 { 2866a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2876a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2886a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 2896a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 2906a574ec7SThierry Reding clock-names = "pwm"; 2916a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 2926a574ec7SThierry Reding reset-names = "pwm"; 2936a574ec7SThierry Reding status = "disabled"; 2946a574ec7SThierry Reding #pwm-cells = <2>; 2956a574ec7SThierry Reding }; 2966a574ec7SThierry Reding 2975425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 2985425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 2995425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 3005425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 3025425fb15SMikko Perttunen clock-names = "sdhci"; 3035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 3045425fb15SMikko Perttunen reset-names = "sdhci"; 3055425fb15SMikko Perttunen status = "disabled"; 3065425fb15SMikko Perttunen }; 3075425fb15SMikko Perttunen 3085425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 3095425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3105425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 3115425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 3125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 3135425fb15SMikko Perttunen clock-names = "sdhci"; 3145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 3155425fb15SMikko Perttunen reset-names = "sdhci"; 3165425fb15SMikko Perttunen status = "disabled"; 3175425fb15SMikko Perttunen }; 3185425fb15SMikko Perttunen 3195425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 3205425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3215425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 3225425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 3235425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 3245425fb15SMikko Perttunen clock-names = "sdhci"; 3255425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 3265425fb15SMikko Perttunen reset-names = "sdhci"; 3275425fb15SMikko Perttunen status = "disabled"; 3285425fb15SMikko Perttunen }; 3295425fb15SMikko Perttunen 3305425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 3315425fb15SMikko Perttunen compatible = "arm,gic-400"; 3325425fb15SMikko Perttunen #interrupt-cells = <3>; 3335425fb15SMikko Perttunen interrupt-controller; 3345425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 3355425fb15SMikko Perttunen <0x03882000 0x2000>, 3365425fb15SMikko Perttunen <0x03884000 0x2000>, 3375425fb15SMikko Perttunen <0x03886000 0x2000>; 3385425fb15SMikko Perttunen interrupts = <GIC_PPI 9 3395425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3405425fb15SMikko Perttunen interrupt-parent = <&gic>; 3415425fb15SMikko Perttunen }; 3425425fb15SMikko Perttunen 3435425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 3445425fb15SMikko Perttunen compatible = "nvidia,tegra186-hsp"; 3455425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 3465425fb15SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 3475425fb15SMikko Perttunen interrupt-names = "doorbell"; 3485425fb15SMikko Perttunen #mbox-cells = <2>; 3495425fb15SMikko Perttunen }; 3505425fb15SMikko Perttunen 3515425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 352d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3535425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 3545425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 3555425fb15SMikko Perttunen #address-cells = <1>; 3565425fb15SMikko Perttunen #size-cells = <0>; 3575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 3585425fb15SMikko Perttunen clock-names = "div-clk"; 3595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 3605425fb15SMikko Perttunen reset-names = "i2c"; 3615425fb15SMikko Perttunen status = "disabled"; 3625425fb15SMikko Perttunen }; 3635425fb15SMikko Perttunen 3645425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 365d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3665425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 3675425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3685425fb15SMikko Perttunen #address-cells = <1>; 3695425fb15SMikko Perttunen #size-cells = <0>; 3705425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 3715425fb15SMikko Perttunen clock-names = "div-clk"; 3725425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 3735425fb15SMikko Perttunen reset-names = "i2c"; 3745425fb15SMikko Perttunen status = "disabled"; 3755425fb15SMikko Perttunen }; 3765425fb15SMikko Perttunen 3775425fb15SMikko Perttunen uartc: serial@c280000 { 3785425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 3795425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 3805425fb15SMikko Perttunen reg-shift = <2>; 3815425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 3835425fb15SMikko Perttunen clock-names = "serial"; 3845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 3855425fb15SMikko Perttunen reset-names = "serial"; 3865425fb15SMikko Perttunen status = "disabled"; 3875425fb15SMikko Perttunen }; 3885425fb15SMikko Perttunen 3895425fb15SMikko Perttunen uartg: serial@c290000 { 3905425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 3915425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 3925425fb15SMikko Perttunen reg-shift = <2>; 3935425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 3955425fb15SMikko Perttunen clock-names = "serial"; 3965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 3975425fb15SMikko Perttunen reset-names = "serial"; 3985425fb15SMikko Perttunen status = "disabled"; 3995425fb15SMikko Perttunen }; 4005425fb15SMikko Perttunen 4016a574ec7SThierry Reding pwm4: pwm@c340000 { 4026a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4036a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4046a574ec7SThierry Reding reg = <0xc340000 0x10000>; 4056a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 4066a574ec7SThierry Reding clock-names = "pwm"; 4076a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 4086a574ec7SThierry Reding reset-names = "pwm"; 4096a574ec7SThierry Reding status = "disabled"; 4106a574ec7SThierry Reding #pwm-cells = <2>; 4116a574ec7SThierry Reding }; 4126a574ec7SThierry Reding 4135425fb15SMikko Perttunen pmc@c360000 { 4145425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 4155425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 4165425fb15SMikko Perttunen <0x0c370000 0x10000>, 4175425fb15SMikko Perttunen <0x0c380000 0x10000>, 4185425fb15SMikko Perttunen <0x0c390000 0x10000>, 4195425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 4205425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 4215425fb15SMikko Perttunen }; 4223db6d3baSThierry Reding 4233db6d3baSThierry Reding host1x@13e00000 { 4243db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 4253db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 4263db6d3baSThierry Reding <0x13e10000 0x10000>; 4273db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 4283db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 4293db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4303db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 4313db6d3baSThierry Reding clock-names = "host1x"; 4323db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 4333db6d3baSThierry Reding reset-names = "host1x"; 4343db6d3baSThierry Reding 4353db6d3baSThierry Reding #address-cells = <1>; 4363db6d3baSThierry Reding #size-cells = <1>; 4373db6d3baSThierry Reding 4383db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 4393db6d3baSThierry Reding 4403db6d3baSThierry Reding display-hub@15200000 { 4413db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 4423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 4433db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 4443db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 4453db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 4463db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 4473db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 4483db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 4493db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 4503db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 4513db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 4523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 4533db6d3baSThierry Reding clock-names = "disp", "hub"; 4543db6d3baSThierry Reding status = "disabled"; 4553db6d3baSThierry Reding 4563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 4573db6d3baSThierry Reding 4583db6d3baSThierry Reding #address-cells = <1>; 4593db6d3baSThierry Reding #size-cells = <1>; 4603db6d3baSThierry Reding 4613db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 4623db6d3baSThierry Reding 4633db6d3baSThierry Reding display@15200000 { 4643db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 4653db6d3baSThierry Reding reg = <0x15200000 0x10000>; 4663db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4673db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 4683db6d3baSThierry Reding clock-names = "dc"; 4693db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 4703db6d3baSThierry Reding reset-names = "dc"; 4713db6d3baSThierry Reding 4723db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 4733db6d3baSThierry Reding 4743db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 4753db6d3baSThierry Reding nvidia,head = <0>; 4763db6d3baSThierry Reding }; 4773db6d3baSThierry Reding 4783db6d3baSThierry Reding display@15210000 { 4793db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 4803db6d3baSThierry Reding reg = <0x15210000 0x10000>; 4813db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 4823db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 4833db6d3baSThierry Reding clock-names = "dc"; 4843db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 4853db6d3baSThierry Reding reset-names = "dc"; 4863db6d3baSThierry Reding 4873db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 4883db6d3baSThierry Reding 4893db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 4903db6d3baSThierry Reding nvidia,head = <1>; 4913db6d3baSThierry Reding }; 4923db6d3baSThierry Reding 4933db6d3baSThierry Reding display@15220000 { 4943db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 4953db6d3baSThierry Reding reg = <0x15220000 0x10000>; 4963db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4973db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 4983db6d3baSThierry Reding clock-names = "dc"; 4993db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 5003db6d3baSThierry Reding reset-names = "dc"; 5013db6d3baSThierry Reding 5023db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 5033db6d3baSThierry Reding 5043db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 5053db6d3baSThierry Reding nvidia,head = <2>; 5063db6d3baSThierry Reding }; 5073db6d3baSThierry Reding 5083db6d3baSThierry Reding display@15230000 { 5093db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 5103db6d3baSThierry Reding reg = <0x15230000 0x10000>; 5113db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 5123db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 5133db6d3baSThierry Reding clock-names = "dc"; 5143db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 5153db6d3baSThierry Reding reset-names = "dc"; 5163db6d3baSThierry Reding 5173db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 5183db6d3baSThierry Reding 5193db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 5203db6d3baSThierry Reding nvidia,head = <3>; 5213db6d3baSThierry Reding }; 5223db6d3baSThierry Reding }; 5233db6d3baSThierry Reding 5248d424ec2SThierry Reding vic@15340000 { 5258d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 5268d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 5278d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 5288d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 5298d424ec2SThierry Reding clock-names = "vic"; 5308d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 5318d424ec2SThierry Reding reset-names = "vic"; 5328d424ec2SThierry Reding 5338d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 5348d424ec2SThierry Reding }; 5358d424ec2SThierry Reding 5363db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 5373db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 5383db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 5393db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 5403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 5413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 5423db6d3baSThierry Reding clock-names = "dpaux", "parent"; 5433db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 5443db6d3baSThierry Reding reset-names = "dpaux"; 5453db6d3baSThierry Reding status = "disabled"; 5463db6d3baSThierry Reding 5473db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 5483db6d3baSThierry Reding 5493db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 5503db6d3baSThierry Reding groups = "dpaux-io"; 5513db6d3baSThierry Reding function = "aux"; 5523db6d3baSThierry Reding }; 5533db6d3baSThierry Reding 5543db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 5553db6d3baSThierry Reding groups = "dpaux-io"; 5563db6d3baSThierry Reding function = "i2c"; 5573db6d3baSThierry Reding }; 5583db6d3baSThierry Reding 5593db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 5603db6d3baSThierry Reding groups = "dpaux-io"; 5613db6d3baSThierry Reding function = "off"; 5623db6d3baSThierry Reding }; 5633db6d3baSThierry Reding 5643db6d3baSThierry Reding i2c-bus { 5653db6d3baSThierry Reding #address-cells = <1>; 5663db6d3baSThierry Reding #size-cells = <0>; 5673db6d3baSThierry Reding }; 5683db6d3baSThierry Reding }; 5693db6d3baSThierry Reding 5703db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 5713db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 5723db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 5733db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 5743db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 5753db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 5763db6d3baSThierry Reding clock-names = "dpaux", "parent"; 5773db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 5783db6d3baSThierry Reding reset-names = "dpaux"; 5793db6d3baSThierry Reding status = "disabled"; 5803db6d3baSThierry Reding 5813db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 5823db6d3baSThierry Reding 5833db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 5843db6d3baSThierry Reding groups = "dpaux-io"; 5853db6d3baSThierry Reding function = "aux"; 5863db6d3baSThierry Reding }; 5873db6d3baSThierry Reding 5883db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 5893db6d3baSThierry Reding groups = "dpaux-io"; 5903db6d3baSThierry Reding function = "i2c"; 5913db6d3baSThierry Reding }; 5923db6d3baSThierry Reding 5933db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 5943db6d3baSThierry Reding groups = "dpaux-io"; 5953db6d3baSThierry Reding function = "off"; 5963db6d3baSThierry Reding }; 5973db6d3baSThierry Reding 5983db6d3baSThierry Reding i2c-bus { 5993db6d3baSThierry Reding #address-cells = <1>; 6003db6d3baSThierry Reding #size-cells = <0>; 6013db6d3baSThierry Reding }; 6023db6d3baSThierry Reding }; 6033db6d3baSThierry Reding 6043db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 6053db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 6063db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 6073db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 6083db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 6093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 6103db6d3baSThierry Reding clock-names = "dpaux", "parent"; 6113db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 6123db6d3baSThierry Reding reset-names = "dpaux"; 6133db6d3baSThierry Reding status = "disabled"; 6143db6d3baSThierry Reding 6153db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 6163db6d3baSThierry Reding 6173db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 6183db6d3baSThierry Reding groups = "dpaux-io"; 6193db6d3baSThierry Reding function = "aux"; 6203db6d3baSThierry Reding }; 6213db6d3baSThierry Reding 6223db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 6233db6d3baSThierry Reding groups = "dpaux-io"; 6243db6d3baSThierry Reding function = "i2c"; 6253db6d3baSThierry Reding }; 6263db6d3baSThierry Reding 6273db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 6283db6d3baSThierry Reding groups = "dpaux-io"; 6293db6d3baSThierry Reding function = "off"; 6303db6d3baSThierry Reding }; 6313db6d3baSThierry Reding 6323db6d3baSThierry Reding i2c-bus { 6333db6d3baSThierry Reding #address-cells = <1>; 6343db6d3baSThierry Reding #size-cells = <0>; 6353db6d3baSThierry Reding }; 6363db6d3baSThierry Reding }; 6373db6d3baSThierry Reding 6383db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 6393db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 6403db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 6413db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 6423db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 6433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 6443db6d3baSThierry Reding clock-names = "dpaux", "parent"; 6453db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 6463db6d3baSThierry Reding reset-names = "dpaux"; 6473db6d3baSThierry Reding status = "disabled"; 6483db6d3baSThierry Reding 6493db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 6503db6d3baSThierry Reding 6513db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 6523db6d3baSThierry Reding groups = "dpaux-io"; 6533db6d3baSThierry Reding function = "aux"; 6543db6d3baSThierry Reding }; 6553db6d3baSThierry Reding 6563db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 6573db6d3baSThierry Reding groups = "dpaux-io"; 6583db6d3baSThierry Reding function = "i2c"; 6593db6d3baSThierry Reding }; 6603db6d3baSThierry Reding 6613db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 6623db6d3baSThierry Reding groups = "dpaux-io"; 6633db6d3baSThierry Reding function = "off"; 6643db6d3baSThierry Reding }; 6653db6d3baSThierry Reding 6663db6d3baSThierry Reding i2c-bus { 6673db6d3baSThierry Reding #address-cells = <1>; 6683db6d3baSThierry Reding #size-cells = <0>; 6693db6d3baSThierry Reding }; 6703db6d3baSThierry Reding }; 6713db6d3baSThierry Reding 6723db6d3baSThierry Reding sor0: sor@15b00000 { 6733db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 6743db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 6753db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 6763db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 6773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 6783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 6793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 6803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 6813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 6823db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 6833db6d3baSThierry Reding "pad"; 6843db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 6853db6d3baSThierry Reding reset-names = "sor"; 6863db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 6873db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 6883db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 6893db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 6903db6d3baSThierry Reding status = "disabled"; 6913db6d3baSThierry Reding 6923db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 6933db6d3baSThierry Reding nvidia,interface = <0>; 6943db6d3baSThierry Reding }; 6953db6d3baSThierry Reding 6963db6d3baSThierry Reding sor1: sor@15b40000 { 6973db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 6983db6d3baSThierry Reding reg = <0x155c0000 0x40000>; 6993db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 7003db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 7013db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 7023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 7033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 7043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 7053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 7063db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 7073db6d3baSThierry Reding "pad"; 7083db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 7093db6d3baSThierry Reding reset-names = "sor"; 7103db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 7113db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 7123db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 7133db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 7143db6d3baSThierry Reding status = "disabled"; 7153db6d3baSThierry Reding 7163db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 7173db6d3baSThierry Reding nvidia,interface = <1>; 7183db6d3baSThierry Reding }; 7193db6d3baSThierry Reding 7203db6d3baSThierry Reding sor2: sor@15b80000 { 7213db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 7223db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 7233db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 7243db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 7253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 7263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 7273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 7283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 7293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 7303db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 7313db6d3baSThierry Reding "pad"; 7323db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 7333db6d3baSThierry Reding reset-names = "sor"; 7343db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 7353db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 7363db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 7373db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 7383db6d3baSThierry Reding status = "disabled"; 7393db6d3baSThierry Reding 7403db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 7413db6d3baSThierry Reding nvidia,interface = <2>; 7423db6d3baSThierry Reding }; 7433db6d3baSThierry Reding 7443db6d3baSThierry Reding sor3: sor@15bc0000 { 7453db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 7463db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 7473db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 7483db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 7493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 7503db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 7513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 7523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 7533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 7543db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 7553db6d3baSThierry Reding "pad"; 7563db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 7573db6d3baSThierry Reding reset-names = "sor"; 7583db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 7593db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 7603db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 7613db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 7623db6d3baSThierry Reding status = "disabled"; 7633db6d3baSThierry Reding 7643db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 7653db6d3baSThierry Reding nvidia,interface = <3>; 7663db6d3baSThierry Reding }; 7673db6d3baSThierry Reding }; 7685425fb15SMikko Perttunen }; 7695425fb15SMikko Perttunen 7705425fb15SMikko Perttunen sysram@40000000 { 7715425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 7725425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 7735425fb15SMikko Perttunen #address-cells = <1>; 7745425fb15SMikko Perttunen #size-cells = <1>; 7755425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 7765425fb15SMikko Perttunen 7775425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 7785425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 7795425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 7805425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 7815425fb15SMikko Perttunen pool; 7825425fb15SMikko Perttunen }; 7835425fb15SMikko Perttunen 7845425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 7855425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 7865425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 7875425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 7885425fb15SMikko Perttunen pool; 7895425fb15SMikko Perttunen }; 7905425fb15SMikko Perttunen }; 7915425fb15SMikko Perttunen 7925425fb15SMikko Perttunen bpmp: bpmp { 7935425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 7945425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 7955425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 7965425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 7975425fb15SMikko Perttunen #clock-cells = <1>; 7985425fb15SMikko Perttunen #reset-cells = <1>; 7995425fb15SMikko Perttunen #power-domain-cells = <1>; 8005425fb15SMikko Perttunen 8015425fb15SMikko Perttunen bpmp_i2c: i2c { 8025425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 8035425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 8045425fb15SMikko Perttunen #address-cells = <1>; 8055425fb15SMikko Perttunen #size-cells = <0>; 8065425fb15SMikko Perttunen }; 8075425fb15SMikko Perttunen 8085425fb15SMikko Perttunen bpmp_thermal: thermal { 8095425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 8105425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 8115425fb15SMikko Perttunen }; 8125425fb15SMikko Perttunen }; 8135425fb15SMikko Perttunen 8147780a034SMikko Perttunen cpus { 8157780a034SMikko Perttunen #address-cells = <1>; 8167780a034SMikko Perttunen #size-cells = <0>; 8177780a034SMikko Perttunen 8187780a034SMikko Perttunen cpu@0 { 8197780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8207780a034SMikko Perttunen device_type = "cpu"; 8217780a034SMikko Perttunen reg = <0x10000>; 8227780a034SMikko Perttunen enable-method = "psci"; 8237780a034SMikko Perttunen }; 8247780a034SMikko Perttunen 8257780a034SMikko Perttunen cpu@1 { 8267780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8277780a034SMikko Perttunen device_type = "cpu"; 8287780a034SMikko Perttunen reg = <0x10001>; 8297780a034SMikko Perttunen enable-method = "psci"; 8307780a034SMikko Perttunen }; 8317780a034SMikko Perttunen 8327780a034SMikko Perttunen cpu@2 { 8337780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8347780a034SMikko Perttunen device_type = "cpu"; 8357780a034SMikko Perttunen reg = <0x100>; 8367780a034SMikko Perttunen enable-method = "psci"; 8377780a034SMikko Perttunen }; 8387780a034SMikko Perttunen 8397780a034SMikko Perttunen cpu@3 { 8407780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8417780a034SMikko Perttunen device_type = "cpu"; 8427780a034SMikko Perttunen reg = <0x101>; 8437780a034SMikko Perttunen enable-method = "psci"; 8447780a034SMikko Perttunen }; 8457780a034SMikko Perttunen 8467780a034SMikko Perttunen cpu@4 { 8477780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8487780a034SMikko Perttunen device_type = "cpu"; 8497780a034SMikko Perttunen reg = <0x200>; 8507780a034SMikko Perttunen enable-method = "psci"; 8517780a034SMikko Perttunen }; 8527780a034SMikko Perttunen 8537780a034SMikko Perttunen cpu@5 { 8547780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8557780a034SMikko Perttunen device_type = "cpu"; 8567780a034SMikko Perttunen reg = <0x201>; 8577780a034SMikko Perttunen enable-method = "psci"; 8587780a034SMikko Perttunen }; 8597780a034SMikko Perttunen 8607780a034SMikko Perttunen cpu@6 { 8617780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8627780a034SMikko Perttunen device_type = "cpu"; 8637780a034SMikko Perttunen reg = <0x10300>; 8647780a034SMikko Perttunen enable-method = "psci"; 8657780a034SMikko Perttunen }; 8667780a034SMikko Perttunen 8677780a034SMikko Perttunen cpu@7 { 8687780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 8697780a034SMikko Perttunen device_type = "cpu"; 8707780a034SMikko Perttunen reg = <0x10301>; 8717780a034SMikko Perttunen enable-method = "psci"; 8727780a034SMikko Perttunen }; 8737780a034SMikko Perttunen }; 8747780a034SMikko Perttunen 8757780a034SMikko Perttunen psci { 8767780a034SMikko Perttunen compatible = "arm,psci-1.0"; 8777780a034SMikko Perttunen status = "okay"; 8787780a034SMikko Perttunen method = "smc"; 8797780a034SMikko Perttunen }; 8807780a034SMikko Perttunen 8815425fb15SMikko Perttunen timer { 8825425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 8835425fb15SMikko Perttunen interrupts = <GIC_PPI 13 8845425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8855425fb15SMikko Perttunen <GIC_PPI 14 8865425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8875425fb15SMikko Perttunen <GIC_PPI 11 8885425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 8895425fb15SMikko Perttunen <GIC_PPI 10 8905425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 8915425fb15SMikko Perttunen interrupt-parent = <&gic>; 8925425fb15SMikko Perttunen }; 8935425fb15SMikko Perttunen}; 894