15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 2609903c5eSJC Kuo misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91f89b58ceSMikko Perttunen ethernet@2490000 { 9219dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9319dc772aSThierry Reding "nvidia,tegra186-eqos", 94f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 95f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 96f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 101f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 104f89b58ceSMikko Perttunen reset-names = "eqos"; 105d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 108c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 109f89b58ceSMikko Perttunen status = "disabled"; 110f89b58ceSMikko Perttunen 111f89b58ceSMikko Perttunen snps,write-requests = <1>; 112f89b58ceSMikko Perttunen snps,read-requests = <3>; 113f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 114f89b58ceSMikko Perttunen snps,txpbl = <16>; 115f89b58ceSMikko Perttunen snps,rxpbl = <8>; 116f89b58ceSMikko Perttunen }; 117f89b58ceSMikko Perttunen 118*835553b3SAkhil R gpcdma: dma-controller@2600000 { 119*835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 120*835553b3SAkhil R "nvidia,tegra186-gpcdma"; 121*835553b3SAkhil R reg = <0x2600000 0x210000>; 122*835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123*835553b3SAkhil R reset-names = "gpcdma"; 124*835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125*835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126*835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127*835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128*835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129*835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130*835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131*835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132*835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133*835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134*835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135*835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136*835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137*835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138*835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139*835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140*835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141*835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142*835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143*835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144*835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145*835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146*835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147*835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148*835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149*835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150*835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151*835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152*835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153*835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154*835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155*835553b3SAkhil R #dma-cells = <1>; 156*835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157*835553b3SAkhil R dma-coherent; 158*835553b3SAkhil R status = "okay"; 159*835553b3SAkhil R }; 160*835553b3SAkhil R 1611aaa7698SThierry Reding aconnect@2900000 { 1625d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1635d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1645d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1655d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1665d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1675d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1685d2249ddSSameer Pujar #address-cells = <1>; 1695d2249ddSSameer Pujar #size-cells = <1>; 1705d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1715d2249ddSSameer Pujar status = "disabled"; 1725d2249ddSSameer Pujar 173177208f7SSameer Pujar adma: dma-controller@2930000 { 1745d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1755d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1765d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1775d2249ddSSameer Pujar interrupt-parent = <&agic>; 1785d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1795d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1805d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1815d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1825d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1835d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1845d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1855d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1865d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1875d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1885d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1895d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1905d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1915d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1925d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1935d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1945d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1955d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1965d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1975d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1985d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1995d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2005d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2015d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2025d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2105d2249ddSSameer Pujar #dma-cells = <1>; 2115d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2125d2249ddSSameer Pujar clock-names = "d_audio"; 2135d2249ddSSameer Pujar status = "disabled"; 2145d2249ddSSameer Pujar }; 2155d2249ddSSameer Pujar 2165d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2175d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2185d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2195d2249ddSSameer Pujar #interrupt-cells = <3>; 2205d2249ddSSameer Pujar interrupt-controller; 2215d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2225d2249ddSSameer Pujar <0x02a42000 0x2000>; 2235d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2245d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2255d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2265d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2275d2249ddSSameer Pujar clock-names = "clk"; 2285d2249ddSSameer Pujar status = "disabled"; 2295d2249ddSSameer Pujar }; 230177208f7SSameer Pujar 231177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 232177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 233177208f7SSameer Pujar "nvidia,tegra186-ahub"; 234177208f7SSameer Pujar reg = <0x02900800 0x800>; 235177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 236177208f7SSameer Pujar clock-names = "ahub"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239177208f7SSameer Pujar #address-cells = <1>; 240177208f7SSameer Pujar #size-cells = <1>; 241177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 242177208f7SSameer Pujar status = "disabled"; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 246177208f7SSameer Pujar "nvidia,tegra186-admaif"; 247177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 248177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 249177208f7SSameer Pujar <&adma 2>, <&adma 2>, 250177208f7SSameer Pujar <&adma 3>, <&adma 3>, 251177208f7SSameer Pujar <&adma 4>, <&adma 4>, 252177208f7SSameer Pujar <&adma 5>, <&adma 5>, 253177208f7SSameer Pujar <&adma 6>, <&adma 6>, 254177208f7SSameer Pujar <&adma 7>, <&adma 7>, 255177208f7SSameer Pujar <&adma 8>, <&adma 8>, 256177208f7SSameer Pujar <&adma 9>, <&adma 9>, 257177208f7SSameer Pujar <&adma 10>, <&adma 10>, 258177208f7SSameer Pujar <&adma 11>, <&adma 11>, 259177208f7SSameer Pujar <&adma 12>, <&adma 12>, 260177208f7SSameer Pujar <&adma 13>, <&adma 13>, 261177208f7SSameer Pujar <&adma 14>, <&adma 14>, 262177208f7SSameer Pujar <&adma 15>, <&adma 15>, 263177208f7SSameer Pujar <&adma 16>, <&adma 16>, 264177208f7SSameer Pujar <&adma 17>, <&adma 17>, 265177208f7SSameer Pujar <&adma 18>, <&adma 18>, 266177208f7SSameer Pujar <&adma 19>, <&adma 19>, 267177208f7SSameer Pujar <&adma 20>, <&adma 20>; 268177208f7SSameer Pujar dma-names = "rx1", "tx1", 269177208f7SSameer Pujar "rx2", "tx2", 270177208f7SSameer Pujar "rx3", "tx3", 271177208f7SSameer Pujar "rx4", "tx4", 272177208f7SSameer Pujar "rx5", "tx5", 273177208f7SSameer Pujar "rx6", "tx6", 274177208f7SSameer Pujar "rx7", "tx7", 275177208f7SSameer Pujar "rx8", "tx8", 276177208f7SSameer Pujar "rx9", "tx9", 277177208f7SSameer Pujar "rx10", "tx10", 278177208f7SSameer Pujar "rx11", "tx11", 279177208f7SSameer Pujar "rx12", "tx12", 280177208f7SSameer Pujar "rx13", "tx13", 281177208f7SSameer Pujar "rx14", "tx14", 282177208f7SSameer Pujar "rx15", "tx15", 283177208f7SSameer Pujar "rx16", "tx16", 284177208f7SSameer Pujar "rx17", "tx17", 285177208f7SSameer Pujar "rx18", "tx18", 286177208f7SSameer Pujar "rx19", "tx19", 287177208f7SSameer Pujar "rx20", "tx20"; 288177208f7SSameer Pujar status = "disabled"; 289177208f7SSameer Pujar }; 290177208f7SSameer Pujar 291177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 292177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 293177208f7SSameer Pujar "nvidia,tegra210-i2s"; 294177208f7SSameer Pujar reg = <0x2901000 0x100>; 295177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 296177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 297177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 298177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 299177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 300177208f7SSameer Pujar assigned-clock-rates = <1536000>; 301177208f7SSameer Pujar sound-name-prefix = "I2S1"; 302177208f7SSameer Pujar status = "disabled"; 303177208f7SSameer Pujar }; 304177208f7SSameer Pujar 305177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 306177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 307177208f7SSameer Pujar "nvidia,tegra210-i2s"; 308177208f7SSameer Pujar reg = <0x2901100 0x100>; 309177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 310177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 311177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 312177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 313177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 314177208f7SSameer Pujar assigned-clock-rates = <1536000>; 315177208f7SSameer Pujar sound-name-prefix = "I2S2"; 316177208f7SSameer Pujar status = "disabled"; 317177208f7SSameer Pujar }; 318177208f7SSameer Pujar 319177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 320177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 321177208f7SSameer Pujar "nvidia,tegra210-i2s"; 322177208f7SSameer Pujar reg = <0x2901200 0x100>; 323177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 324177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 325177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 326177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 327177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 328177208f7SSameer Pujar assigned-clock-rates = <1536000>; 329177208f7SSameer Pujar sound-name-prefix = "I2S3"; 330177208f7SSameer Pujar status = "disabled"; 331177208f7SSameer Pujar }; 332177208f7SSameer Pujar 333177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 334177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 335177208f7SSameer Pujar "nvidia,tegra210-i2s"; 336177208f7SSameer Pujar reg = <0x2901300 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 338177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 339177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 340177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 341177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 342177208f7SSameer Pujar assigned-clock-rates = <1536000>; 343177208f7SSameer Pujar sound-name-prefix = "I2S4"; 344177208f7SSameer Pujar status = "disabled"; 345177208f7SSameer Pujar }; 346177208f7SSameer Pujar 347177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 348177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 349177208f7SSameer Pujar "nvidia,tegra210-i2s"; 350177208f7SSameer Pujar reg = <0x2901400 0x100>; 351177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 352177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 353177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 354177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 355177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 356177208f7SSameer Pujar assigned-clock-rates = <1536000>; 357177208f7SSameer Pujar sound-name-prefix = "I2S5"; 358177208f7SSameer Pujar status = "disabled"; 359177208f7SSameer Pujar }; 360177208f7SSameer Pujar 361177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 362177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 363177208f7SSameer Pujar "nvidia,tegra210-i2s"; 364177208f7SSameer Pujar reg = <0x2901500 0x100>; 365177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 366177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 367177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 368177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 369177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 370177208f7SSameer Pujar assigned-clock-rates = <1536000>; 371177208f7SSameer Pujar sound-name-prefix = "I2S6"; 372177208f7SSameer Pujar status = "disabled"; 373177208f7SSameer Pujar }; 374177208f7SSameer Pujar 375177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 376177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 377177208f7SSameer Pujar "nvidia,tegra210-dmic"; 378177208f7SSameer Pujar reg = <0x2904000 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 380177208f7SSameer Pujar clock-names = "dmic"; 381177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 382177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 383177208f7SSameer Pujar assigned-clock-rates = <3072000>; 384177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 385177208f7SSameer Pujar status = "disabled"; 386177208f7SSameer Pujar }; 387177208f7SSameer Pujar 388177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 389177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 390177208f7SSameer Pujar "nvidia,tegra210-dmic"; 391177208f7SSameer Pujar reg = <0x2904100 0x100>; 392177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 393177208f7SSameer Pujar clock-names = "dmic"; 394177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 395177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 396177208f7SSameer Pujar assigned-clock-rates = <3072000>; 397177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 398177208f7SSameer Pujar status = "disabled"; 399177208f7SSameer Pujar }; 400177208f7SSameer Pujar 401177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 402177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 403177208f7SSameer Pujar "nvidia,tegra210-dmic"; 404177208f7SSameer Pujar reg = <0x2904200 0x100>; 405177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 406177208f7SSameer Pujar clock-names = "dmic"; 407177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 408177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 409177208f7SSameer Pujar assigned-clock-rates = <3072000>; 410177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 411177208f7SSameer Pujar status = "disabled"; 412177208f7SSameer Pujar }; 413177208f7SSameer Pujar 414177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 415177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 416177208f7SSameer Pujar "nvidia,tegra210-dmic"; 417177208f7SSameer Pujar reg = <0x2904300 0x100>; 418177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 419177208f7SSameer Pujar clock-names = "dmic"; 420177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 421177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 422177208f7SSameer Pujar assigned-clock-rates = <3072000>; 423177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 424177208f7SSameer Pujar status = "disabled"; 425177208f7SSameer Pujar }; 426177208f7SSameer Pujar 427177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 428177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 429177208f7SSameer Pujar "nvidia,tegra186-dspk"; 430177208f7SSameer Pujar reg = <0x2905000 0x100>; 431177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 432177208f7SSameer Pujar clock-names = "dspk"; 433177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 434177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 435177208f7SSameer Pujar assigned-clock-rates = <12288000>; 436177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 437177208f7SSameer Pujar status = "disabled"; 438177208f7SSameer Pujar }; 439177208f7SSameer Pujar 440177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 441177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 442177208f7SSameer Pujar "nvidia,tegra186-dspk"; 443177208f7SSameer Pujar reg = <0x2905100 0x100>; 444177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 445177208f7SSameer Pujar clock-names = "dspk"; 446177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 447177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 448177208f7SSameer Pujar assigned-clock-rates = <12288000>; 449177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 450177208f7SSameer Pujar status = "disabled"; 451177208f7SSameer Pujar }; 452848f3290SSameer Pujar 453848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 454848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 455848f3290SSameer Pujar "nvidia,tegra210-sfc"; 456848f3290SSameer Pujar reg = <0x2902000 0x200>; 457848f3290SSameer Pujar sound-name-prefix = "SFC1"; 458848f3290SSameer Pujar status = "disabled"; 459848f3290SSameer Pujar }; 460848f3290SSameer Pujar 461848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 462848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 463848f3290SSameer Pujar "nvidia,tegra210-sfc"; 464848f3290SSameer Pujar reg = <0x2902200 0x200>; 465848f3290SSameer Pujar sound-name-prefix = "SFC2"; 466848f3290SSameer Pujar status = "disabled"; 467848f3290SSameer Pujar }; 468848f3290SSameer Pujar 469848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 470848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 471848f3290SSameer Pujar "nvidia,tegra210-sfc"; 472848f3290SSameer Pujar reg = <0x2902400 0x200>; 473848f3290SSameer Pujar sound-name-prefix = "SFC3"; 474848f3290SSameer Pujar status = "disabled"; 475848f3290SSameer Pujar }; 476848f3290SSameer Pujar 477848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 478848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 479848f3290SSameer Pujar "nvidia,tegra210-sfc"; 480848f3290SSameer Pujar reg = <0x2902600 0x200>; 481848f3290SSameer Pujar sound-name-prefix = "SFC4"; 482848f3290SSameer Pujar status = "disabled"; 483848f3290SSameer Pujar }; 484848f3290SSameer Pujar 485848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 486848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 487848f3290SSameer Pujar "nvidia,tegra210-mvc"; 488848f3290SSameer Pujar reg = <0x290a000 0x200>; 489848f3290SSameer Pujar sound-name-prefix = "MVC1"; 490848f3290SSameer Pujar status = "disabled"; 491848f3290SSameer Pujar }; 492848f3290SSameer Pujar 493848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 494848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 495848f3290SSameer Pujar "nvidia,tegra210-mvc"; 496848f3290SSameer Pujar reg = <0x290a200 0x200>; 497848f3290SSameer Pujar sound-name-prefix = "MVC2"; 498848f3290SSameer Pujar status = "disabled"; 499848f3290SSameer Pujar }; 500848f3290SSameer Pujar 501848f3290SSameer Pujar tegra_amx1: amx@2903000 { 502848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 503848f3290SSameer Pujar reg = <0x2903000 0x100>; 504848f3290SSameer Pujar sound-name-prefix = "AMX1"; 505848f3290SSameer Pujar status = "disabled"; 506848f3290SSameer Pujar }; 507848f3290SSameer Pujar 508848f3290SSameer Pujar tegra_amx2: amx@2903100 { 509848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 510848f3290SSameer Pujar reg = <0x2903100 0x100>; 511848f3290SSameer Pujar sound-name-prefix = "AMX2"; 512848f3290SSameer Pujar status = "disabled"; 513848f3290SSameer Pujar }; 514848f3290SSameer Pujar 515848f3290SSameer Pujar tegra_amx3: amx@2903200 { 516848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 517848f3290SSameer Pujar reg = <0x2903200 0x100>; 518848f3290SSameer Pujar sound-name-prefix = "AMX3"; 519848f3290SSameer Pujar status = "disabled"; 520848f3290SSameer Pujar }; 521848f3290SSameer Pujar 522848f3290SSameer Pujar tegra_amx4: amx@2903300 { 523848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 524848f3290SSameer Pujar reg = <0x2903300 0x100>; 525848f3290SSameer Pujar sound-name-prefix = "AMX4"; 526848f3290SSameer Pujar status = "disabled"; 527848f3290SSameer Pujar }; 528848f3290SSameer Pujar 529848f3290SSameer Pujar tegra_adx1: adx@2903800 { 530848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 531848f3290SSameer Pujar "nvidia,tegra210-adx"; 532848f3290SSameer Pujar reg = <0x2903800 0x100>; 533848f3290SSameer Pujar sound-name-prefix = "ADX1"; 534848f3290SSameer Pujar status = "disabled"; 535848f3290SSameer Pujar }; 536848f3290SSameer Pujar 537848f3290SSameer Pujar tegra_adx2: adx@2903900 { 538848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 539848f3290SSameer Pujar "nvidia,tegra210-adx"; 540848f3290SSameer Pujar reg = <0x2903900 0x100>; 541848f3290SSameer Pujar sound-name-prefix = "ADX2"; 542848f3290SSameer Pujar status = "disabled"; 543848f3290SSameer Pujar }; 544848f3290SSameer Pujar 545848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 546848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 547848f3290SSameer Pujar "nvidia,tegra210-adx"; 548848f3290SSameer Pujar reg = <0x2903a00 0x100>; 549848f3290SSameer Pujar sound-name-prefix = "ADX3"; 550848f3290SSameer Pujar status = "disabled"; 551848f3290SSameer Pujar }; 552848f3290SSameer Pujar 553848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 554848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 555848f3290SSameer Pujar "nvidia,tegra210-adx"; 556848f3290SSameer Pujar reg = <0x2903b00 0x100>; 557848f3290SSameer Pujar sound-name-prefix = "ADX4"; 558848f3290SSameer Pujar status = "disabled"; 559848f3290SSameer Pujar }; 560848f3290SSameer Pujar 561848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 562848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 563848f3290SSameer Pujar "nvidia,tegra210-amixer"; 564848f3290SSameer Pujar reg = <0x290bb00 0x800>; 565848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 566848f3290SSameer Pujar status = "disabled"; 567848f3290SSameer Pujar }; 568177208f7SSameer Pujar }; 5695d2249ddSSameer Pujar }; 5705d2249ddSSameer Pujar 571dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 572dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 573644c569dSThierry Reding reg = <0x2430000 0x17000>, 574644c569dSThierry Reding <0xc300000 0x4000>; 575dbb72e2cSVidya Sagar 576dbb72e2cSVidya Sagar status = "okay"; 577dbb72e2cSVidya Sagar 578dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 579dbb72e2cSVidya Sagar pex_rst { 580dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 581dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 582dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5836b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 584dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 585dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 586dbb72e2cSVidya Sagar }; 587dbb72e2cSVidya Sagar }; 588dbb72e2cSVidya Sagar 589dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 590dbb72e2cSVidya Sagar clkreq { 591dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 592dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 593dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5946b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 595dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 596dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 597dbb72e2cSVidya Sagar }; 598dbb72e2cSVidya Sagar }; 599dbb72e2cSVidya Sagar }; 600dbb72e2cSVidya Sagar 601be9b887fSThierry Reding mc: memory-controller@2c00000 { 602be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 603be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 604be9b887fSThierry Reding <0x02b80000 0x040000>, 605be9b887fSThierry Reding <0x01700000 0x100000>; 6068613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 607d5237c7cSThierry Reding #interconnect-cells = <1>; 608be9b887fSThierry Reding status = "disabled"; 609be9b887fSThierry Reding 610be9b887fSThierry Reding #address-cells = <2>; 611be9b887fSThierry Reding #size-cells = <2>; 612be9b887fSThierry Reding 613be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 614be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 615be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 616be9b887fSThierry Reding 617be9b887fSThierry Reding /* 618be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 619be9b887fSThierry Reding * controller selects the XBAR format used when memory 620be9b887fSThierry Reding * is accessed. This is used to transparently access 621be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 622be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 623be9b887fSThierry Reding * 624be9b887fSThierry Reding * As a consequence, the operating system must ensure 625be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 626be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 627be9b887fSThierry Reding * devices require access to the XBAR switch, their 628be9b887fSThierry Reding * drivers must set this bit explicitly. 629be9b887fSThierry Reding * 630be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 631be9b887fSThierry Reding */ 632be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 633be9b887fSThierry Reding 634be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 635be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 636be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 637be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 638cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 639be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 640be9b887fSThierry Reding clock-names = "emc"; 641be9b887fSThierry Reding 642d5237c7cSThierry Reding #interconnect-cells = <0>; 643d5237c7cSThierry Reding 644be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 645be9b887fSThierry Reding }; 646be9b887fSThierry Reding }; 647be9b887fSThierry Reding 6485425fb15SMikko Perttunen uarta: serial@3100000 { 6495425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6505425fb15SMikko Perttunen reg = <0x03100000 0x40>; 6515425fb15SMikko Perttunen reg-shift = <2>; 6525425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 6535425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 6545425fb15SMikko Perttunen clock-names = "serial"; 6555425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 6565425fb15SMikko Perttunen reset-names = "serial"; 6575425fb15SMikko Perttunen status = "disabled"; 6585425fb15SMikko Perttunen }; 6595425fb15SMikko Perttunen 6605425fb15SMikko Perttunen uartb: serial@3110000 { 6615425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6625425fb15SMikko Perttunen reg = <0x03110000 0x40>; 6635425fb15SMikko Perttunen reg-shift = <2>; 6645425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 6655425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 6665425fb15SMikko Perttunen clock-names = "serial"; 6675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 6685425fb15SMikko Perttunen reset-names = "serial"; 6695425fb15SMikko Perttunen status = "disabled"; 6705425fb15SMikko Perttunen }; 6715425fb15SMikko Perttunen 6725425fb15SMikko Perttunen uartd: serial@3130000 { 6735425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6745425fb15SMikko Perttunen reg = <0x03130000 0x40>; 6755425fb15SMikko Perttunen reg-shift = <2>; 6765425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 6775425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 6785425fb15SMikko Perttunen clock-names = "serial"; 6795425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 6805425fb15SMikko Perttunen reset-names = "serial"; 6815425fb15SMikko Perttunen status = "disabled"; 6825425fb15SMikko Perttunen }; 6835425fb15SMikko Perttunen 6845425fb15SMikko Perttunen uarte: serial@3140000 { 6855425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6865425fb15SMikko Perttunen reg = <0x03140000 0x40>; 6875425fb15SMikko Perttunen reg-shift = <2>; 6885425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 6895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 6905425fb15SMikko Perttunen clock-names = "serial"; 6915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 6925425fb15SMikko Perttunen reset-names = "serial"; 6935425fb15SMikko Perttunen status = "disabled"; 6945425fb15SMikko Perttunen }; 6955425fb15SMikko Perttunen 6965425fb15SMikko Perttunen uartf: serial@3150000 { 6975425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6985425fb15SMikko Perttunen reg = <0x03150000 0x40>; 6995425fb15SMikko Perttunen reg-shift = <2>; 7005425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7025425fb15SMikko Perttunen clock-names = "serial"; 7035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7045425fb15SMikko Perttunen reset-names = "serial"; 7055425fb15SMikko Perttunen status = "disabled"; 7065425fb15SMikko Perttunen }; 7075425fb15SMikko Perttunen 7085425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 709d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7105425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 7115425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 7125425fb15SMikko Perttunen #address-cells = <1>; 7135425fb15SMikko Perttunen #size-cells = <0>; 7145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 7155425fb15SMikko Perttunen clock-names = "div-clk"; 7165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 7175425fb15SMikko Perttunen reset-names = "i2c"; 7185425fb15SMikko Perttunen status = "disabled"; 7195425fb15SMikko Perttunen }; 7205425fb15SMikko Perttunen 7215425fb15SMikko Perttunen uarth: serial@3170000 { 7225425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7235425fb15SMikko Perttunen reg = <0x03170000 0x40>; 7245425fb15SMikko Perttunen reg-shift = <2>; 7255425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 7265425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 7275425fb15SMikko Perttunen clock-names = "serial"; 7285425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 7295425fb15SMikko Perttunen reset-names = "serial"; 7305425fb15SMikko Perttunen status = "disabled"; 7315425fb15SMikko Perttunen }; 7325425fb15SMikko Perttunen 7335425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 734d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7355425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 7365425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 7375425fb15SMikko Perttunen #address-cells = <1>; 7385425fb15SMikko Perttunen #size-cells = <0>; 7395425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 7405425fb15SMikko Perttunen clock-names = "div-clk"; 7415425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 7425425fb15SMikko Perttunen reset-names = "i2c"; 7435425fb15SMikko Perttunen status = "disabled"; 7445425fb15SMikko Perttunen }; 7455425fb15SMikko Perttunen 7465425fb15SMikko Perttunen /* shares pads with dpaux1 */ 7475425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 748d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7495425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 7505425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 7515425fb15SMikko Perttunen #address-cells = <1>; 7525425fb15SMikko Perttunen #size-cells = <0>; 7535425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 7545425fb15SMikko Perttunen clock-names = "div-clk"; 7555425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 7565425fb15SMikko Perttunen reset-names = "i2c"; 757a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 758a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 759a4131561SThierry Reding pinctrl-names = "default", "idle"; 7605425fb15SMikko Perttunen status = "disabled"; 7615425fb15SMikko Perttunen }; 7625425fb15SMikko Perttunen 7635425fb15SMikko Perttunen /* shares pads with dpaux0 */ 7645425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 765d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7665425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 7675425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7685425fb15SMikko Perttunen #address-cells = <1>; 7695425fb15SMikko Perttunen #size-cells = <0>; 7705425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 7715425fb15SMikko Perttunen clock-names = "div-clk"; 7725425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 7735425fb15SMikko Perttunen reset-names = "i2c"; 774a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 775a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 776a4131561SThierry Reding pinctrl-names = "default", "idle"; 7775425fb15SMikko Perttunen status = "disabled"; 7785425fb15SMikko Perttunen }; 7795425fb15SMikko Perttunen 780a4131561SThierry Reding /* shares pads with dpaux2 */ 781a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 782d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7835425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 7845425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 7855425fb15SMikko Perttunen #address-cells = <1>; 7865425fb15SMikko Perttunen #size-cells = <0>; 7875425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 7885425fb15SMikko Perttunen clock-names = "div-clk"; 7895425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 7905425fb15SMikko Perttunen reset-names = "i2c"; 791a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 792a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 793a4131561SThierry Reding pinctrl-names = "default", "idle"; 7945425fb15SMikko Perttunen status = "disabled"; 7955425fb15SMikko Perttunen }; 7965425fb15SMikko Perttunen 797a4131561SThierry Reding /* shares pads with dpaux3 */ 798a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 799d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8005425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 8015425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 8025425fb15SMikko Perttunen #address-cells = <1>; 8035425fb15SMikko Perttunen #size-cells = <0>; 8045425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 8055425fb15SMikko Perttunen clock-names = "div-clk"; 8065425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 8075425fb15SMikko Perttunen reset-names = "i2c"; 808a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 809a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 810a4131561SThierry Reding pinctrl-names = "default", "idle"; 8115425fb15SMikko Perttunen status = "disabled"; 8125425fb15SMikko Perttunen }; 8135425fb15SMikko Perttunen 81496ded827SSowjanya Komatineni spi@3270000 { 81596ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 81696ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 81796ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 81896ded827SSowjanya Komatineni #address-cells = <1>; 81996ded827SSowjanya Komatineni #size-cells = <0>; 82096ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 82196ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 82296ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 82396ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 82496ded827SSowjanya Komatineni reset-names = "qspi"; 82596ded827SSowjanya Komatineni status = "disabled"; 82696ded827SSowjanya Komatineni }; 82796ded827SSowjanya Komatineni 82896ded827SSowjanya Komatineni spi@3300000 { 82996ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 83096ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 83196ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 83296ded827SSowjanya Komatineni #address-cells = <1>; 83396ded827SSowjanya Komatineni #size-cells = <0>; 83496ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 83596ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 83696ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 83796ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 83896ded827SSowjanya Komatineni reset-names = "qspi"; 83996ded827SSowjanya Komatineni status = "disabled"; 84096ded827SSowjanya Komatineni }; 84196ded827SSowjanya Komatineni 8426a574ec7SThierry Reding pwm1: pwm@3280000 { 8436a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8446a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8456a574ec7SThierry Reding reg = <0x3280000 0x10000>; 8466a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 8476a574ec7SThierry Reding clock-names = "pwm"; 8486a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 8496a574ec7SThierry Reding reset-names = "pwm"; 8506a574ec7SThierry Reding status = "disabled"; 8516a574ec7SThierry Reding #pwm-cells = <2>; 8526a574ec7SThierry Reding }; 8536a574ec7SThierry Reding 8546a574ec7SThierry Reding pwm2: pwm@3290000 { 8556a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8566a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8576a574ec7SThierry Reding reg = <0x3290000 0x10000>; 8586a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 8596a574ec7SThierry Reding clock-names = "pwm"; 8606a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 8616a574ec7SThierry Reding reset-names = "pwm"; 8626a574ec7SThierry Reding status = "disabled"; 8636a574ec7SThierry Reding #pwm-cells = <2>; 8646a574ec7SThierry Reding }; 8656a574ec7SThierry Reding 8666a574ec7SThierry Reding pwm3: pwm@32a0000 { 8676a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8686a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8696a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 8706a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 8716a574ec7SThierry Reding clock-names = "pwm"; 8726a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 8736a574ec7SThierry Reding reset-names = "pwm"; 8746a574ec7SThierry Reding status = "disabled"; 8756a574ec7SThierry Reding #pwm-cells = <2>; 8766a574ec7SThierry Reding }; 8776a574ec7SThierry Reding 8786a574ec7SThierry Reding pwm5: pwm@32c0000 { 8796a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8806a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8816a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 8826a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 8836a574ec7SThierry Reding clock-names = "pwm"; 8846a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 8856a574ec7SThierry Reding reset-names = "pwm"; 8866a574ec7SThierry Reding status = "disabled"; 8876a574ec7SThierry Reding #pwm-cells = <2>; 8886a574ec7SThierry Reding }; 8896a574ec7SThierry Reding 8906a574ec7SThierry Reding pwm6: pwm@32d0000 { 8916a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8926a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8936a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 8946a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 8956a574ec7SThierry Reding clock-names = "pwm"; 8966a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 8976a574ec7SThierry Reding reset-names = "pwm"; 8986a574ec7SThierry Reding status = "disabled"; 8996a574ec7SThierry Reding #pwm-cells = <2>; 9006a574ec7SThierry Reding }; 9016a574ec7SThierry Reding 9026a574ec7SThierry Reding pwm7: pwm@32e0000 { 9036a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9046a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9056a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 9066a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 9076a574ec7SThierry Reding clock-names = "pwm"; 9086a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 9096a574ec7SThierry Reding reset-names = "pwm"; 9106a574ec7SThierry Reding status = "disabled"; 9116a574ec7SThierry Reding #pwm-cells = <2>; 9126a574ec7SThierry Reding }; 9136a574ec7SThierry Reding 9146a574ec7SThierry Reding pwm8: pwm@32f0000 { 9156a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9166a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9176a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 9186a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 9196a574ec7SThierry Reding clock-names = "pwm"; 9206a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 9216a574ec7SThierry Reding reset-names = "pwm"; 9226a574ec7SThierry Reding status = "disabled"; 9236a574ec7SThierry Reding #pwm-cells = <2>; 9246a574ec7SThierry Reding }; 9256a574ec7SThierry Reding 92667bb17f6SThierry Reding sdmmc1: mmc@3400000 { 9272c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9285425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 9295425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 930c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 931c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 932c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9335425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 9345425fb15SMikko Perttunen reset-names = "sdhci"; 935d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 936d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 937d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 938c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 939ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 940ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 941ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 9424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 9434e0f1229SSowjanya Komatineni <0x07>; 9444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9454e0f1229SSowjanya Komatineni <0x07>; 9464e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9474e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9484e0f1229SSowjanya Komatineni <0x07>; 9494e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9504e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9514e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9524e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 953ff21087eSPrathamesh Shete sd-uhs-sdr25; 954ff21087eSPrathamesh Shete sd-uhs-sdr50; 955ff21087eSPrathamesh Shete sd-uhs-ddr50; 956ff21087eSPrathamesh Shete sd-uhs-sdr104; 9575425fb15SMikko Perttunen status = "disabled"; 9585425fb15SMikko Perttunen }; 9595425fb15SMikko Perttunen 96067bb17f6SThierry Reding sdmmc3: mmc@3440000 { 9612c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9625425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 9635425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 964c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 965c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 966c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 9685425fb15SMikko Perttunen reset-names = "sdhci"; 969d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 970d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 971d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 972c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 973ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 974ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 975ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 9764e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 9774e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 9784e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 9794e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9804e0f1229SSowjanya Komatineni <0x07>; 9814e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9834e0f1229SSowjanya Komatineni <0x07>; 9844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9864e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9874e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 988ff21087eSPrathamesh Shete sd-uhs-sdr25; 989ff21087eSPrathamesh Shete sd-uhs-sdr50; 990ff21087eSPrathamesh Shete sd-uhs-ddr50; 991ff21087eSPrathamesh Shete sd-uhs-sdr104; 9925425fb15SMikko Perttunen status = "disabled"; 9935425fb15SMikko Perttunen }; 9945425fb15SMikko Perttunen 99567bb17f6SThierry Reding sdmmc4: mmc@3460000 { 9962c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9975425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 9985425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 999c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1000c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1001c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1002351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1003351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1004351648d0SSowjanya Komatineni assigned-clock-parents = 1005351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 10065425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 10075425fb15SMikko Perttunen reset-names = "sdhci"; 1008d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1009d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1010d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1011c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 10124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 10134e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 10144e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 10154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10164e0f1229SSowjanya Komatineni <0x0a>; 10174e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 10184e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10194e0f1229SSowjanya Komatineni <0x0a>; 10204e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 10214e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 10224e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1023c2fee443SPrathamesh Shete cap-mmc-highspeed; 1024c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1025c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1026c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1027c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1028dfd3cb6fSSowjanya Komatineni supports-cqe; 10295425fb15SMikko Perttunen status = "disabled"; 10305425fb15SMikko Perttunen }; 10315425fb15SMikko Perttunen 10324878cc0cSSameer Pujar hda@3510000 { 10334878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 10344878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 10354878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 10364878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 103748f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 103848f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 103948f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 10404878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1041146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1042146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 10434878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1044d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1045d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1046d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1047c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 10484878cc0cSSameer Pujar status = "disabled"; 10494878cc0cSSameer Pujar }; 10504878cc0cSSameer Pujar 1051fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1052fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1053fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1054fab7a039SJC Kuo <0x03540000 0x1000>; 1055fab7a039SJC Kuo reg-names = "padctl", "ao"; 10566450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1057fab7a039SJC Kuo 1058fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1059fab7a039SJC Kuo reset-names = "padctl"; 1060fab7a039SJC Kuo 1061fab7a039SJC Kuo status = "disabled"; 1062fab7a039SJC Kuo 1063fab7a039SJC Kuo pads { 1064fab7a039SJC Kuo usb2 { 1065fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1066fab7a039SJC Kuo clock-names = "trk"; 1067fab7a039SJC Kuo 1068fab7a039SJC Kuo lanes { 1069fab7a039SJC Kuo usb2-0 { 1070fab7a039SJC Kuo nvidia,function = "xusb"; 1071fab7a039SJC Kuo status = "disabled"; 1072fab7a039SJC Kuo #phy-cells = <0>; 1073fab7a039SJC Kuo }; 1074fab7a039SJC Kuo 1075fab7a039SJC Kuo usb2-1 { 1076fab7a039SJC Kuo nvidia,function = "xusb"; 1077fab7a039SJC Kuo status = "disabled"; 1078fab7a039SJC Kuo #phy-cells = <0>; 1079fab7a039SJC Kuo }; 1080fab7a039SJC Kuo 1081fab7a039SJC Kuo usb2-2 { 1082fab7a039SJC Kuo nvidia,function = "xusb"; 1083fab7a039SJC Kuo status = "disabled"; 1084fab7a039SJC Kuo #phy-cells = <0>; 1085fab7a039SJC Kuo }; 1086fab7a039SJC Kuo 1087fab7a039SJC Kuo usb2-3 { 1088fab7a039SJC Kuo nvidia,function = "xusb"; 1089fab7a039SJC Kuo status = "disabled"; 1090fab7a039SJC Kuo #phy-cells = <0>; 1091fab7a039SJC Kuo }; 1092fab7a039SJC Kuo }; 1093fab7a039SJC Kuo }; 1094fab7a039SJC Kuo 1095fab7a039SJC Kuo usb3 { 1096fab7a039SJC Kuo lanes { 1097fab7a039SJC Kuo usb3-0 { 1098fab7a039SJC Kuo nvidia,function = "xusb"; 1099fab7a039SJC Kuo status = "disabled"; 1100fab7a039SJC Kuo #phy-cells = <0>; 1101fab7a039SJC Kuo }; 1102fab7a039SJC Kuo 1103fab7a039SJC Kuo usb3-1 { 1104fab7a039SJC Kuo nvidia,function = "xusb"; 1105fab7a039SJC Kuo status = "disabled"; 1106fab7a039SJC Kuo #phy-cells = <0>; 1107fab7a039SJC Kuo }; 1108fab7a039SJC Kuo 1109fab7a039SJC Kuo usb3-2 { 1110fab7a039SJC Kuo nvidia,function = "xusb"; 1111fab7a039SJC Kuo status = "disabled"; 1112fab7a039SJC Kuo #phy-cells = <0>; 1113fab7a039SJC Kuo }; 1114fab7a039SJC Kuo 1115fab7a039SJC Kuo usb3-3 { 1116fab7a039SJC Kuo nvidia,function = "xusb"; 1117fab7a039SJC Kuo status = "disabled"; 1118fab7a039SJC Kuo #phy-cells = <0>; 1119fab7a039SJC Kuo }; 1120fab7a039SJC Kuo }; 1121fab7a039SJC Kuo }; 1122fab7a039SJC Kuo }; 1123fab7a039SJC Kuo 1124fab7a039SJC Kuo ports { 1125fab7a039SJC Kuo usb2-0 { 1126fab7a039SJC Kuo status = "disabled"; 1127fab7a039SJC Kuo }; 1128fab7a039SJC Kuo 1129fab7a039SJC Kuo usb2-1 { 1130fab7a039SJC Kuo status = "disabled"; 1131fab7a039SJC Kuo }; 1132fab7a039SJC Kuo 1133fab7a039SJC Kuo usb2-2 { 1134fab7a039SJC Kuo status = "disabled"; 1135fab7a039SJC Kuo }; 1136fab7a039SJC Kuo 1137fab7a039SJC Kuo usb2-3 { 1138fab7a039SJC Kuo status = "disabled"; 1139fab7a039SJC Kuo }; 1140fab7a039SJC Kuo 1141fab7a039SJC Kuo usb3-0 { 1142fab7a039SJC Kuo status = "disabled"; 1143fab7a039SJC Kuo }; 1144fab7a039SJC Kuo 1145fab7a039SJC Kuo usb3-1 { 1146fab7a039SJC Kuo status = "disabled"; 1147fab7a039SJC Kuo }; 1148fab7a039SJC Kuo 1149fab7a039SJC Kuo usb3-2 { 1150fab7a039SJC Kuo status = "disabled"; 1151fab7a039SJC Kuo }; 1152fab7a039SJC Kuo 1153fab7a039SJC Kuo usb3-3 { 1154fab7a039SJC Kuo status = "disabled"; 1155fab7a039SJC Kuo }; 1156fab7a039SJC Kuo }; 1157fab7a039SJC Kuo }; 1158fab7a039SJC Kuo 1159bc8788b2SNagarjuna Kristam usb@3550000 { 1160bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1161bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1162bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1163bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1164bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1165bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1166bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1167bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1168bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1169bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1170c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1171c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1172c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1173c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1174bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1175bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1176bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1177bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1178bc8788b2SNagarjuna Kristam status = "disabled"; 1179bc8788b2SNagarjuna Kristam }; 1180bc8788b2SNagarjuna Kristam 1181fab7a039SJC Kuo usb@3610000 { 1182fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1183fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1184fab7a039SJC Kuo <0x03600000 0x10000>; 1185fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1186fab7a039SJC Kuo 1187fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1188a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1189fab7a039SJC Kuo 1190fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1191fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1192fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1193fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1194fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1195fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1196fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1197fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1198fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1199fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1200fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1201fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1202fab7a039SJC Kuo "pll_e"; 1203c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1204c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1205c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1206c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1207fab7a039SJC Kuo 1208fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1209fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1210fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1211fab7a039SJC Kuo 1212fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1213fab7a039SJC Kuo status = "disabled"; 1214fab7a039SJC Kuo }; 1215fab7a039SJC Kuo 121609903c5eSJC Kuo fuse@3820000 { 121709903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 121809903c5eSJC Kuo reg = <0x03820000 0x10000>; 121909903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 122009903c5eSJC Kuo clock-names = "fuse"; 122109903c5eSJC Kuo }; 122209903c5eSJC Kuo 12235425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 12245425fb15SMikko Perttunen compatible = "arm,gic-400"; 12255425fb15SMikko Perttunen #interrupt-cells = <3>; 12265425fb15SMikko Perttunen interrupt-controller; 12275425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 12285425fb15SMikko Perttunen <0x03882000 0x2000>, 12295425fb15SMikko Perttunen <0x03884000 0x2000>, 12305425fb15SMikko Perttunen <0x03886000 0x2000>; 12315425fb15SMikko Perttunen interrupts = <GIC_PPI 9 12325425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 12335425fb15SMikko Perttunen interrupt-parent = <&gic>; 12345425fb15SMikko Perttunen }; 12355425fb15SMikko Perttunen 1236badb80beSThierry Reding cec@3960000 { 1237badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1238badb80beSThierry Reding reg = <0x03960000 0x10000>; 1239badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1240badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1241badb80beSThierry Reding clock-names = "cec"; 1242badb80beSThierry Reding status = "disabled"; 1243badb80beSThierry Reding }; 1244badb80beSThierry Reding 12455425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1246cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 12475425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1248a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1249a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1250a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1251a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1252a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1253a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1254a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1255a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1256a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1257a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1258a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1259a38570c2SMikko Perttunen "shared7"; 1260a38570c2SMikko Perttunen #mbox-cells = <2>; 1261a38570c2SMikko Perttunen }; 1262a38570c2SMikko Perttunen 12632602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 12642602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12652602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 12662602c32fSVidya Sagar reg-names = "ctl"; 12672602c32fSVidya Sagar 12682602c32fSVidya Sagar #phy-cells = <0>; 12692602c32fSVidya Sagar }; 12702602c32fSVidya Sagar 12712602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 12722602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12732602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 12742602c32fSVidya Sagar reg-names = "ctl"; 12752602c32fSVidya Sagar 12762602c32fSVidya Sagar #phy-cells = <0>; 12772602c32fSVidya Sagar }; 12782602c32fSVidya Sagar 12792602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 12802602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12812602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 12822602c32fSVidya Sagar reg-names = "ctl"; 12832602c32fSVidya Sagar 12842602c32fSVidya Sagar #phy-cells = <0>; 12852602c32fSVidya Sagar }; 12862602c32fSVidya Sagar 12872602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 12882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12892602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 12902602c32fSVidya Sagar reg-names = "ctl"; 12912602c32fSVidya Sagar 12922602c32fSVidya Sagar #phy-cells = <0>; 12932602c32fSVidya Sagar }; 12942602c32fSVidya Sagar 12952602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 12962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12972602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 12982602c32fSVidya Sagar reg-names = "ctl"; 12992602c32fSVidya Sagar 13002602c32fSVidya Sagar #phy-cells = <0>; 13012602c32fSVidya Sagar }; 13022602c32fSVidya Sagar 13032602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 13042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13052602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 13062602c32fSVidya Sagar reg-names = "ctl"; 13072602c32fSVidya Sagar 13082602c32fSVidya Sagar #phy-cells = <0>; 13092602c32fSVidya Sagar }; 13102602c32fSVidya Sagar 13112602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 13122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13132602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 13142602c32fSVidya Sagar reg-names = "ctl"; 13152602c32fSVidya Sagar 13162602c32fSVidya Sagar #phy-cells = <0>; 13172602c32fSVidya Sagar }; 13182602c32fSVidya Sagar 13192602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 13202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13212602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 13222602c32fSVidya Sagar reg-names = "ctl"; 13232602c32fSVidya Sagar 13242602c32fSVidya Sagar #phy-cells = <0>; 13252602c32fSVidya Sagar }; 13262602c32fSVidya Sagar 13272602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 13282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13292602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 13302602c32fSVidya Sagar reg-names = "ctl"; 13312602c32fSVidya Sagar 13322602c32fSVidya Sagar #phy-cells = <0>; 13332602c32fSVidya Sagar }; 13342602c32fSVidya Sagar 13352602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 13362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13372602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 13382602c32fSVidya Sagar reg-names = "ctl"; 13392602c32fSVidya Sagar 13402602c32fSVidya Sagar #phy-cells = <0>; 13412602c32fSVidya Sagar }; 13422602c32fSVidya Sagar 13432602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 13442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13452602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 13462602c32fSVidya Sagar reg-names = "ctl"; 13472602c32fSVidya Sagar 13482602c32fSVidya Sagar #phy-cells = <0>; 13492602c32fSVidya Sagar }; 13502602c32fSVidya Sagar 13512602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 13522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13532602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 13542602c32fSVidya Sagar reg-names = "ctl"; 13552602c32fSVidya Sagar 13562602c32fSVidya Sagar #phy-cells = <0>; 13572602c32fSVidya Sagar }; 13582602c32fSVidya Sagar 13592602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 13602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13612602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 13622602c32fSVidya Sagar reg-names = "ctl"; 13632602c32fSVidya Sagar 13642602c32fSVidya Sagar #phy-cells = <0>; 13652602c32fSVidya Sagar }; 13662602c32fSVidya Sagar 13672602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 13682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13692602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 13702602c32fSVidya Sagar reg-names = "ctl"; 13712602c32fSVidya Sagar 13722602c32fSVidya Sagar #phy-cells = <0>; 13732602c32fSVidya Sagar }; 13742602c32fSVidya Sagar 13752602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 13762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13772602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 13782602c32fSVidya Sagar reg-names = "ctl"; 13792602c32fSVidya Sagar 13802602c32fSVidya Sagar #phy-cells = <0>; 13812602c32fSVidya Sagar }; 13822602c32fSVidya Sagar 13832602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 13842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13852602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 13862602c32fSVidya Sagar reg-names = "ctl"; 13872602c32fSVidya Sagar 13882602c32fSVidya Sagar #phy-cells = <0>; 13892602c32fSVidya Sagar }; 13902602c32fSVidya Sagar 13912602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 13922602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13932602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 13942602c32fSVidya Sagar reg-names = "ctl"; 13952602c32fSVidya Sagar 13962602c32fSVidya Sagar #phy-cells = <0>; 13972602c32fSVidya Sagar }; 13982602c32fSVidya Sagar 13992602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 14002602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14012602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 14022602c32fSVidya Sagar reg-names = "ctl"; 14032602c32fSVidya Sagar 14042602c32fSVidya Sagar #phy-cells = <0>; 14052602c32fSVidya Sagar }; 14062602c32fSVidya Sagar 14072602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 14082602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14092602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 14102602c32fSVidya Sagar reg-names = "ctl"; 14112602c32fSVidya Sagar 14122602c32fSVidya Sagar #phy-cells = <0>; 14132602c32fSVidya Sagar }; 14142602c32fSVidya Sagar 14152602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 14162602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14172602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 14182602c32fSVidya Sagar reg-names = "ctl"; 14192602c32fSVidya Sagar 14202602c32fSVidya Sagar #phy-cells = <0>; 14212602c32fSVidya Sagar }; 14222602c32fSVidya Sagar 1423a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1424cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 14251741e187SDipen Patel reg = <0x0c150000 0x90000>; 1426a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1427a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1428a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1429a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1430a38570c2SMikko Perttunen /* 1431a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1432a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1433a38570c2SMikko Perttunen */ 1434a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 14355425fb15SMikko Perttunen #mbox-cells = <2>; 14365425fb15SMikko Perttunen }; 14375425fb15SMikko Perttunen 14385425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1439d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14405425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 14415425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 14425425fb15SMikko Perttunen #address-cells = <1>; 14435425fb15SMikko Perttunen #size-cells = <0>; 14445425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 14455425fb15SMikko Perttunen clock-names = "div-clk"; 14465425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 14475425fb15SMikko Perttunen reset-names = "i2c"; 14485425fb15SMikko Perttunen status = "disabled"; 14495425fb15SMikko Perttunen }; 14505425fb15SMikko Perttunen 14515425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1452d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14535425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 14545425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 14555425fb15SMikko Perttunen #address-cells = <1>; 14565425fb15SMikko Perttunen #size-cells = <0>; 14575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 14585425fb15SMikko Perttunen clock-names = "div-clk"; 14595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 14605425fb15SMikko Perttunen reset-names = "i2c"; 14615425fb15SMikko Perttunen status = "disabled"; 14625425fb15SMikko Perttunen }; 14635425fb15SMikko Perttunen 14645425fb15SMikko Perttunen uartc: serial@c280000 { 14655425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14665425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 14675425fb15SMikko Perttunen reg-shift = <2>; 14685425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 14695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 14705425fb15SMikko Perttunen clock-names = "serial"; 14715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 14725425fb15SMikko Perttunen reset-names = "serial"; 14735425fb15SMikko Perttunen status = "disabled"; 14745425fb15SMikko Perttunen }; 14755425fb15SMikko Perttunen 14765425fb15SMikko Perttunen uartg: serial@c290000 { 14775425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14785425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 14795425fb15SMikko Perttunen reg-shift = <2>; 14805425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 14815425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 14825425fb15SMikko Perttunen clock-names = "serial"; 14835425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 14845425fb15SMikko Perttunen reset-names = "serial"; 14855425fb15SMikko Perttunen status = "disabled"; 14865425fb15SMikko Perttunen }; 14875425fb15SMikko Perttunen 148837e5a31dSThierry Reding rtc: rtc@c2a0000 { 148937e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 149037e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 149137e5a31dSThierry Reding interrupt-parent = <&pmc>; 149237e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 149337e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 149437e5a31dSThierry Reding clock-names = "rtc"; 149537e5a31dSThierry Reding status = "disabled"; 149637e5a31dSThierry Reding }; 149737e5a31dSThierry Reding 14984d286331SThierry Reding gpio_aon: gpio@c2f0000 { 14994d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 15004d286331SThierry Reding reg-names = "security", "gpio"; 15014d286331SThierry Reding reg = <0xc2f0000 0x1000>, 15024d286331SThierry Reding <0xc2f1000 0x1000>; 15030a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 15040a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 15050a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 15060a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 15074d286331SThierry Reding gpio-controller; 15084d286331SThierry Reding #gpio-cells = <2>; 15094d286331SThierry Reding interrupt-controller; 15104d286331SThierry Reding #interrupt-cells = <2>; 15114d286331SThierry Reding }; 15124d286331SThierry Reding 15136a574ec7SThierry Reding pwm4: pwm@c340000 { 15146a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 15156a574ec7SThierry Reding "nvidia,tegra186-pwm"; 15166a574ec7SThierry Reding reg = <0xc340000 0x10000>; 15176a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 15186a574ec7SThierry Reding clock-names = "pwm"; 15196a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 15206a574ec7SThierry Reding reset-names = "pwm"; 15216a574ec7SThierry Reding status = "disabled"; 15226a574ec7SThierry Reding #pwm-cells = <2>; 15236a574ec7SThierry Reding }; 15246a574ec7SThierry Reding 152538ecf1e5SThierry Reding pmc: pmc@c360000 { 15265425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 15275425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 15285425fb15SMikko Perttunen <0x0c370000 0x10000>, 15295425fb15SMikko Perttunen <0x0c380000 0x10000>, 15305425fb15SMikko Perttunen <0x0c390000 0x10000>, 15315425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 15325425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 153338ecf1e5SThierry Reding 153438ecf1e5SThierry Reding #interrupt-cells = <2>; 153538ecf1e5SThierry Reding interrupt-controller; 1536ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1537ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1538ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1539ff21087eSPrathamesh Shete }; 1540ff21087eSPrathamesh Shete 1541ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1542ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1543ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1544ff21087eSPrathamesh Shete }; 1545ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1546ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1547ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1548ff21087eSPrathamesh Shete }; 1549ff21087eSPrathamesh Shete 1550ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1551ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1552ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1553ff21087eSPrathamesh Shete }; 1554ff21087eSPrathamesh Shete 15555425fb15SMikko Perttunen }; 15563db6d3baSThierry Reding 1557e762232fSJon Hunter iommu@10000000 { 1558e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1559e762232fSJon Hunter reg = <0x10000000 0x800000>; 1560e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1561e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1562e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1563e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1564e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1565e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1566e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1567e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1568e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1569e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1570e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1571e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1572e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1573e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1574e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1625e762232fSJon Hunter stream-match-mask = <0x7f80>; 1626e762232fSJon Hunter #global-interrupts = <1>; 1627e762232fSJon Hunter #iommu-cells = <1>; 1628e762232fSJon Hunter 1629e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1630e762232fSJon Hunter status = "okay"; 1631e762232fSJon Hunter }; 1632e762232fSJon Hunter 1633c7289b1cSThierry Reding smmu: iommu@12000000 { 1634c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1635c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1636c7289b1cSThierry Reding <0x11000000 0x800000>; 1637c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1638c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1639c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1640c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1641c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1642c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1643c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1644c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1645c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1646c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1647c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1648c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1649c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1650c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1651c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1653c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1661c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1703c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1704c7289b1cSThierry Reding #global-interrupts = <2>; 1705c7289b1cSThierry Reding #iommu-cells = <1>; 1706c7289b1cSThierry Reding 1707c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1708c7289b1cSThierry Reding status = "okay"; 1709c7289b1cSThierry Reding }; 1710c7289b1cSThierry Reding 17113db6d3baSThierry Reding host1x@13e00000 { 1712ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 17133db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 17143db6d3baSThierry Reding <0x13e10000 0x10000>; 17153db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 17163db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 17173db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1718052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 17193db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 17203db6d3baSThierry Reding clock-names = "host1x"; 17213db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 17223db6d3baSThierry Reding reset-names = "host1x"; 17233db6d3baSThierry Reding 17243db6d3baSThierry Reding #address-cells = <1>; 17253db6d3baSThierry Reding #size-cells = <1>; 17263db6d3baSThierry Reding 17273db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1728d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1729d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1730c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 17313db6d3baSThierry Reding 173278a05873SMikko Perttunen nvdec@15140000 { 173378a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 173478a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 173578a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 173678a05873SMikko Perttunen clock-names = "nvdec"; 173778a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 173878a05873SMikko Perttunen reset-names = "nvdec"; 173978a05873SMikko Perttunen 174078a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 174178a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 174278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 174378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 174478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 174578a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 174678a05873SMikko Perttunen dma-coherent; 174778a05873SMikko Perttunen 174878a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 174978a05873SMikko Perttunen }; 175078a05873SMikko Perttunen 17513db6d3baSThierry Reding display-hub@15200000 { 1752aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1753611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 17543db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 17553db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 17563db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 17573db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 17583db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 17593db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 17603db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 17613db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 17623db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 17633db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 17643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 17653db6d3baSThierry Reding clock-names = "disp", "hub"; 17663db6d3baSThierry Reding status = "disabled"; 17673db6d3baSThierry Reding 17683db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17693db6d3baSThierry Reding 17703db6d3baSThierry Reding #address-cells = <1>; 17713db6d3baSThierry Reding #size-cells = <1>; 17723db6d3baSThierry Reding 17733db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 17743db6d3baSThierry Reding 17753db6d3baSThierry Reding display@15200000 { 17763db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17773db6d3baSThierry Reding reg = <0x15200000 0x10000>; 17783db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 17793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 17803db6d3baSThierry Reding clock-names = "dc"; 17813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 17823db6d3baSThierry Reding reset-names = "dc"; 17833db6d3baSThierry Reding 17843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1785d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1786d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1787d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 17883db6d3baSThierry Reding 17893db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 17903db6d3baSThierry Reding nvidia,head = <0>; 17913db6d3baSThierry Reding }; 17923db6d3baSThierry Reding 17933db6d3baSThierry Reding display@15210000 { 17943db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17953db6d3baSThierry Reding reg = <0x15210000 0x10000>; 17963db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 17973db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 17983db6d3baSThierry Reding clock-names = "dc"; 17993db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 18003db6d3baSThierry Reding reset-names = "dc"; 18013db6d3baSThierry Reding 18023db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1803d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1804d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1805d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18063db6d3baSThierry Reding 18073db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18083db6d3baSThierry Reding nvidia,head = <1>; 18093db6d3baSThierry Reding }; 18103db6d3baSThierry Reding 18113db6d3baSThierry Reding display@15220000 { 18123db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 18133db6d3baSThierry Reding reg = <0x15220000 0x10000>; 18143db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 18153db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 18163db6d3baSThierry Reding clock-names = "dc"; 18173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 18183db6d3baSThierry Reding reset-names = "dc"; 18193db6d3baSThierry Reding 18203db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1821d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1822d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1823d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18243db6d3baSThierry Reding 18253db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18263db6d3baSThierry Reding nvidia,head = <2>; 18273db6d3baSThierry Reding }; 18283db6d3baSThierry Reding 18293db6d3baSThierry Reding display@15230000 { 18303db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 18313db6d3baSThierry Reding reg = <0x15230000 0x10000>; 18323db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 18333db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 18343db6d3baSThierry Reding clock-names = "dc"; 18353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 18363db6d3baSThierry Reding reset-names = "dc"; 18373db6d3baSThierry Reding 18383db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1839d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1840d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1841d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18423db6d3baSThierry Reding 18433db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18443db6d3baSThierry Reding nvidia,head = <3>; 18453db6d3baSThierry Reding }; 18463db6d3baSThierry Reding }; 18473db6d3baSThierry Reding 18488d424ec2SThierry Reding vic@15340000 { 18498d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 18508d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 18518d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 18528d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 18538d424ec2SThierry Reding clock-names = "vic"; 18548d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 18558d424ec2SThierry Reding reset-names = "vic"; 18568d424ec2SThierry Reding 18578d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1858d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1859d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1860d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1861c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 1862a52280c8SJon Hunter dma-coherent; 18638d424ec2SThierry Reding }; 18648d424ec2SThierry Reding 1865f7eb2785SJon Hunter nvjpg@15380000 { 1866f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 1867f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1868f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1869f7eb2785SJon Hunter clock-names = "nvjpg"; 1870f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 1871f7eb2785SJon Hunter reset-names = "nvjpg"; 1872f7eb2785SJon Hunter 1873f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1874f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1875f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1876f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1877f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 1878f7eb2785SJon Hunter dma-coherent; 1879f7eb2785SJon Hunter }; 1880f7eb2785SJon Hunter 188178a05873SMikko Perttunen nvdec@15480000 { 188278a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 188378a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 188478a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 188578a05873SMikko Perttunen clock-names = "nvdec"; 188678a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 188778a05873SMikko Perttunen reset-names = "nvdec"; 188878a05873SMikko Perttunen 188978a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 189078a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 189178a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 189278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 189378a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 189478a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 189578a05873SMikko Perttunen dma-coherent; 189678a05873SMikko Perttunen 189778a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 189878a05873SMikko Perttunen }; 189978a05873SMikko Perttunen 1900f7eb2785SJon Hunter nvenc@154c0000 { 1901f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 1902f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1903f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 1904f7eb2785SJon Hunter clock-names = "nvenc"; 1905f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 1906f7eb2785SJon Hunter reset-names = "nvenc"; 1907f7eb2785SJon Hunter 1908f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1909f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1910f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1911f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1912f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 1913f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 1914f7eb2785SJon Hunter dma-coherent; 1915f7eb2785SJon Hunter 1916f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 1917f7eb2785SJon Hunter }; 1918f7eb2785SJon Hunter 19193db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 19203db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19213db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 19223db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 19233db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 19243db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19253db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 19273db6d3baSThierry Reding reset-names = "dpaux"; 19283db6d3baSThierry Reding status = "disabled"; 19293db6d3baSThierry Reding 19303db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19313db6d3baSThierry Reding 19323db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 19333db6d3baSThierry Reding groups = "dpaux-io"; 19343db6d3baSThierry Reding function = "aux"; 19353db6d3baSThierry Reding }; 19363db6d3baSThierry Reding 19373db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 19383db6d3baSThierry Reding groups = "dpaux-io"; 19393db6d3baSThierry Reding function = "i2c"; 19403db6d3baSThierry Reding }; 19413db6d3baSThierry Reding 19423db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 19433db6d3baSThierry Reding groups = "dpaux-io"; 19443db6d3baSThierry Reding function = "off"; 19453db6d3baSThierry Reding }; 19463db6d3baSThierry Reding 19473db6d3baSThierry Reding i2c-bus { 19483db6d3baSThierry Reding #address-cells = <1>; 19493db6d3baSThierry Reding #size-cells = <0>; 19503db6d3baSThierry Reding }; 19513db6d3baSThierry Reding }; 19523db6d3baSThierry Reding 19533db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 19543db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19553db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 19563db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 19573db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 19583db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19593db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 19613db6d3baSThierry Reding reset-names = "dpaux"; 19623db6d3baSThierry Reding status = "disabled"; 19633db6d3baSThierry Reding 19643db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19653db6d3baSThierry Reding 19663db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 19673db6d3baSThierry Reding groups = "dpaux-io"; 19683db6d3baSThierry Reding function = "aux"; 19693db6d3baSThierry Reding }; 19703db6d3baSThierry Reding 19713db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 19723db6d3baSThierry Reding groups = "dpaux-io"; 19733db6d3baSThierry Reding function = "i2c"; 19743db6d3baSThierry Reding }; 19753db6d3baSThierry Reding 19763db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 19773db6d3baSThierry Reding groups = "dpaux-io"; 19783db6d3baSThierry Reding function = "off"; 19793db6d3baSThierry Reding }; 19803db6d3baSThierry Reding 19813db6d3baSThierry Reding i2c-bus { 19823db6d3baSThierry Reding #address-cells = <1>; 19833db6d3baSThierry Reding #size-cells = <0>; 19843db6d3baSThierry Reding }; 19853db6d3baSThierry Reding }; 19863db6d3baSThierry Reding 19873db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 19883db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19893db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 19903db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 19913db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 19923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19933db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19943db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 19953db6d3baSThierry Reding reset-names = "dpaux"; 19963db6d3baSThierry Reding status = "disabled"; 19973db6d3baSThierry Reding 19983db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19993db6d3baSThierry Reding 20003db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 20013db6d3baSThierry Reding groups = "dpaux-io"; 20023db6d3baSThierry Reding function = "aux"; 20033db6d3baSThierry Reding }; 20043db6d3baSThierry Reding 20053db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 20063db6d3baSThierry Reding groups = "dpaux-io"; 20073db6d3baSThierry Reding function = "i2c"; 20083db6d3baSThierry Reding }; 20093db6d3baSThierry Reding 20103db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 20113db6d3baSThierry Reding groups = "dpaux-io"; 20123db6d3baSThierry Reding function = "off"; 20133db6d3baSThierry Reding }; 20143db6d3baSThierry Reding 20153db6d3baSThierry Reding i2c-bus { 20163db6d3baSThierry Reding #address-cells = <1>; 20173db6d3baSThierry Reding #size-cells = <0>; 20183db6d3baSThierry Reding }; 20193db6d3baSThierry Reding }; 20203db6d3baSThierry Reding 20213db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 20223db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 20233db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 20243db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 20253db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 20263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 20273db6d3baSThierry Reding clock-names = "dpaux", "parent"; 20283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 20293db6d3baSThierry Reding reset-names = "dpaux"; 20303db6d3baSThierry Reding status = "disabled"; 20313db6d3baSThierry Reding 20323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20333db6d3baSThierry Reding 20343db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 20353db6d3baSThierry Reding groups = "dpaux-io"; 20363db6d3baSThierry Reding function = "aux"; 20373db6d3baSThierry Reding }; 20383db6d3baSThierry Reding 20393db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 20403db6d3baSThierry Reding groups = "dpaux-io"; 20413db6d3baSThierry Reding function = "i2c"; 20423db6d3baSThierry Reding }; 20433db6d3baSThierry Reding 20443db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 20453db6d3baSThierry Reding groups = "dpaux-io"; 20463db6d3baSThierry Reding function = "off"; 20473db6d3baSThierry Reding }; 20483db6d3baSThierry Reding 20493db6d3baSThierry Reding i2c-bus { 20503db6d3baSThierry Reding #address-cells = <1>; 20513db6d3baSThierry Reding #size-cells = <0>; 20523db6d3baSThierry Reding }; 20533db6d3baSThierry Reding }; 20543db6d3baSThierry Reding 2055f7eb2785SJon Hunter nvenc@15a80000 { 2056f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2057f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2058f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2059f7eb2785SJon Hunter clock-names = "nvenc"; 2060f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2061f7eb2785SJon Hunter reset-names = "nvenc"; 2062f7eb2785SJon Hunter 2063f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2064f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2065f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2066f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2067f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2068f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2069f7eb2785SJon Hunter dma-coherent; 2070f7eb2785SJon Hunter 2071f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2072f7eb2785SJon Hunter }; 2073f7eb2785SJon Hunter 20743db6d3baSThierry Reding sor0: sor@15b00000 { 20753db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20763db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 20773db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 20783db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 20793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 20803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 20813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 20843db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20853db6d3baSThierry Reding "pad"; 20863db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 20873db6d3baSThierry Reding reset-names = "sor"; 20883db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 20893db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 20903db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 20913db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 20923db6d3baSThierry Reding status = "disabled"; 20933db6d3baSThierry Reding 20943db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20953db6d3baSThierry Reding nvidia,interface = <0>; 20963db6d3baSThierry Reding }; 20973db6d3baSThierry Reding 20983db6d3baSThierry Reding sor1: sor@15b40000 { 20993db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2100939e7430SThierry Reding reg = <0x15b40000 0x40000>; 21013db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 21023db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 21033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 21043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 21053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 21083db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21093db6d3baSThierry Reding "pad"; 21103db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 21113db6d3baSThierry Reding reset-names = "sor"; 21123db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 21133db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 21143db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 21153db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21163db6d3baSThierry Reding status = "disabled"; 21173db6d3baSThierry Reding 21183db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21193db6d3baSThierry Reding nvidia,interface = <1>; 21203db6d3baSThierry Reding }; 21213db6d3baSThierry Reding 21223db6d3baSThierry Reding sor2: sor@15b80000 { 21233db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21243db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 21253db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 21263db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 21273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 21283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 21293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 21323db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21333db6d3baSThierry Reding "pad"; 21343db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 21353db6d3baSThierry Reding reset-names = "sor"; 21363db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 21373db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 21383db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 21393db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21403db6d3baSThierry Reding status = "disabled"; 21413db6d3baSThierry Reding 21423db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21433db6d3baSThierry Reding nvidia,interface = <2>; 21443db6d3baSThierry Reding }; 21453db6d3baSThierry Reding 21463db6d3baSThierry Reding sor3: sor@15bc0000 { 21473db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21483db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 21493db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 21503db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 21513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 21523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 21533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21553db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 21563db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21573db6d3baSThierry Reding "pad"; 21583db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 21593db6d3baSThierry Reding reset-names = "sor"; 21603db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 21613db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 21623db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 21633db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21643db6d3baSThierry Reding status = "disabled"; 21653db6d3baSThierry Reding 21663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21673db6d3baSThierry Reding nvidia,interface = <3>; 21683db6d3baSThierry Reding }; 21693db6d3baSThierry Reding }; 21700f134e39SThierry Reding 21710f134e39SThierry Reding gpu@17000000 { 21720f134e39SThierry Reding compatible = "nvidia,gv11b"; 2173818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2174818ae79aSThierry Reding <0x18000000 0x1000000>; 21750f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 21760f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 21770f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 21780f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 21790f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 21800f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 21810f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 21820f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 21830f134e39SThierry Reding reset-names = "gpu"; 21840f134e39SThierry Reding dma-coherent; 21850f134e39SThierry Reding 21860f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 21870f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 21880f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 21890f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 21900f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 21910f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 21920f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 21930f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 21940f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 21950f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 21960f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 21970f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 21980f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 21990f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 22000f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 22010f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 22020f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 22030f134e39SThierry Reding }; 22045425fb15SMikko Perttunen }; 22055425fb15SMikko Perttunen 22062602c32fSVidya Sagar pcie@14100000 { 2207f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22082602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2209644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2210644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2211644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2212644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22132602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22142602c32fSVidya Sagar 22152602c32fSVidya Sagar status = "disabled"; 22162602c32fSVidya Sagar 22172602c32fSVidya Sagar #address-cells = <3>; 22182602c32fSVidya Sagar #size-cells = <2>; 22192602c32fSVidya Sagar device_type = "pci"; 22202602c32fSVidya Sagar num-lanes = <1>; 22212602c32fSVidya Sagar linux,pci-domain = <1>; 22222602c32fSVidya Sagar 22232602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 22242602c32fSVidya Sagar clock-names = "core"; 22252602c32fSVidya Sagar 22262602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 22272602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 22282602c32fSVidya Sagar reset-names = "apb", "core"; 22292602c32fSVidya Sagar 22302602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22312602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22322602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22332602c32fSVidya Sagar 22342602c32fSVidya Sagar #interrupt-cells = <1>; 22352602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22362602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 22372602c32fSVidya Sagar 22382602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 22392602c32fSVidya Sagar 22402602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22412602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22422602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22432602c32fSVidya Sagar 22442602c32fSVidya Sagar bus-range = <0x0 0xff>; 2245d5237c7cSThierry Reding 22468a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22478a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22488a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2249d5237c7cSThierry Reding 2250d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2251d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2252ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2253ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2254ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2255ba02920cSVidya Sagar dma-coherent; 22562602c32fSVidya Sagar }; 22572602c32fSVidya Sagar 22582602c32fSVidya Sagar pcie@14120000 { 2259f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22602602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2261644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2262644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2263644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2264644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22652602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22662602c32fSVidya Sagar 22672602c32fSVidya Sagar status = "disabled"; 22682602c32fSVidya Sagar 22692602c32fSVidya Sagar #address-cells = <3>; 22702602c32fSVidya Sagar #size-cells = <2>; 22712602c32fSVidya Sagar device_type = "pci"; 22722602c32fSVidya Sagar num-lanes = <1>; 22732602c32fSVidya Sagar linux,pci-domain = <2>; 22742602c32fSVidya Sagar 22752602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 22762602c32fSVidya Sagar clock-names = "core"; 22772602c32fSVidya Sagar 22782602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 22792602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 22802602c32fSVidya Sagar reset-names = "apb", "core"; 22812602c32fSVidya Sagar 22822602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22832602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22842602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22852602c32fSVidya Sagar 22862602c32fSVidya Sagar #interrupt-cells = <1>; 22872602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22882602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 22892602c32fSVidya Sagar 22902602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 22912602c32fSVidya Sagar 22922602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22932602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22942602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22952602c32fSVidya Sagar 22962602c32fSVidya Sagar bus-range = <0x0 0xff>; 2297d5237c7cSThierry Reding 22988a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22998a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 23008a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2301d5237c7cSThierry Reding 2302d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2303d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2304ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2305ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2306ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2307ba02920cSVidya Sagar dma-coherent; 23082602c32fSVidya Sagar }; 23092602c32fSVidya Sagar 23102602c32fSVidya Sagar pcie@14140000 { 2311f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23122602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2313644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2314644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2315644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2316644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23172602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23182602c32fSVidya Sagar 23192602c32fSVidya Sagar status = "disabled"; 23202602c32fSVidya Sagar 23212602c32fSVidya Sagar #address-cells = <3>; 23222602c32fSVidya Sagar #size-cells = <2>; 23232602c32fSVidya Sagar device_type = "pci"; 23242602c32fSVidya Sagar num-lanes = <1>; 23252602c32fSVidya Sagar linux,pci-domain = <3>; 23262602c32fSVidya Sagar 23272602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 23282602c32fSVidya Sagar clock-names = "core"; 23292602c32fSVidya Sagar 23302602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 23312602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 23322602c32fSVidya Sagar reset-names = "apb", "core"; 23332602c32fSVidya Sagar 23342602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23352602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23362602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23372602c32fSVidya Sagar 23382602c32fSVidya Sagar #interrupt-cells = <1>; 23392602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23402602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 23412602c32fSVidya Sagar 23422602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 23432602c32fSVidya Sagar 23442602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23452602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23462602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23472602c32fSVidya Sagar 23482602c32fSVidya Sagar bus-range = <0x0 0xff>; 2349d5237c7cSThierry Reding 23508a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23518a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 23528a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2353d5237c7cSThierry Reding 2354d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2355d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2356ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2357ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2358ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2359ba02920cSVidya Sagar dma-coherent; 23602602c32fSVidya Sagar }; 23612602c32fSVidya Sagar 23622602c32fSVidya Sagar pcie@14160000 { 2363f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23642602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2365644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2366644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2367644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2368644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23692602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23702602c32fSVidya Sagar 23712602c32fSVidya Sagar status = "disabled"; 23722602c32fSVidya Sagar 23732602c32fSVidya Sagar #address-cells = <3>; 23742602c32fSVidya Sagar #size-cells = <2>; 23752602c32fSVidya Sagar device_type = "pci"; 23762602c32fSVidya Sagar num-lanes = <4>; 23772602c32fSVidya Sagar linux,pci-domain = <4>; 23782602c32fSVidya Sagar 23792602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 23802602c32fSVidya Sagar clock-names = "core"; 23812602c32fSVidya Sagar 23822602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 23832602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 23842602c32fSVidya Sagar reset-names = "apb", "core"; 23852602c32fSVidya Sagar 23862602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23872602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23882602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23892602c32fSVidya Sagar 23902602c32fSVidya Sagar #interrupt-cells = <1>; 23912602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23922602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 23932602c32fSVidya Sagar 23942602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 23952602c32fSVidya Sagar 23962602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23972602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23982602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23992602c32fSVidya Sagar 24002602c32fSVidya Sagar bus-range = <0x0 0xff>; 2401d5237c7cSThierry Reding 24028a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24038a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24048a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2405d5237c7cSThierry Reding 2406d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2407d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2408ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2409ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2410ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2411ba02920cSVidya Sagar dma-coherent; 24122602c32fSVidya Sagar }; 24132602c32fSVidya Sagar 24142602c32fSVidya Sagar pcie@14180000 { 2415f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24162602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2417644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2418644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2419644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2420644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24212602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24222602c32fSVidya Sagar 24232602c32fSVidya Sagar status = "disabled"; 24242602c32fSVidya Sagar 24252602c32fSVidya Sagar #address-cells = <3>; 24262602c32fSVidya Sagar #size-cells = <2>; 24272602c32fSVidya Sagar device_type = "pci"; 24282602c32fSVidya Sagar num-lanes = <8>; 24292602c32fSVidya Sagar linux,pci-domain = <0>; 24302602c32fSVidya Sagar 24312602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 24322602c32fSVidya Sagar clock-names = "core"; 24332602c32fSVidya Sagar 24342602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 24352602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 24362602c32fSVidya Sagar reset-names = "apb", "core"; 24372602c32fSVidya Sagar 24382602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24392602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24402602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24412602c32fSVidya Sagar 24422602c32fSVidya Sagar #interrupt-cells = <1>; 24432602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24442602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 24452602c32fSVidya Sagar 24462602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 24472602c32fSVidya Sagar 24482602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24492602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24502602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24512602c32fSVidya Sagar 24522602c32fSVidya Sagar bus-range = <0x0 0xff>; 2453d5237c7cSThierry Reding 24548a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24558a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24568a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2457d5237c7cSThierry Reding 2458d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2459d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2460ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2461ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2462ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2463ba02920cSVidya Sagar dma-coherent; 24642602c32fSVidya Sagar }; 24652602c32fSVidya Sagar 24662602c32fSVidya Sagar pcie@141a0000 { 2467f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24682602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2469644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2470644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2471644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2472644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24732602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24742602c32fSVidya Sagar 24752602c32fSVidya Sagar status = "disabled"; 24762602c32fSVidya Sagar 24772602c32fSVidya Sagar #address-cells = <3>; 24782602c32fSVidya Sagar #size-cells = <2>; 24792602c32fSVidya Sagar device_type = "pci"; 24802602c32fSVidya Sagar num-lanes = <8>; 24812602c32fSVidya Sagar linux,pci-domain = <5>; 24822602c32fSVidya Sagar 2483dbb72e2cSVidya Sagar pinctrl-names = "default"; 2484dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2485dbb72e2cSVidya Sagar 2486c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2487c453cc9eSThierry Reding clock-names = "core"; 24882602c32fSVidya Sagar 24892602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 24902602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 24912602c32fSVidya Sagar reset-names = "apb", "core"; 24922602c32fSVidya Sagar 24932602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24942602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24952602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24962602c32fSVidya Sagar 24972602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 24982602c32fSVidya Sagar 24992602c32fSVidya Sagar #interrupt-cells = <1>; 25002602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25012602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 25022602c32fSVidya Sagar 25032602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25042602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25052602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25062602c32fSVidya Sagar 25072602c32fSVidya Sagar bus-range = <0x0 0xff>; 2508d5237c7cSThierry Reding 25098a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25108a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25118a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2512d5237c7cSThierry Reding 2513d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2514d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2515ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2516ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2517ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2518ba02920cSVidya Sagar dma-coherent; 25192602c32fSVidya Sagar }; 25202602c32fSVidya Sagar 2521b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2522bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25230c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2524644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2525644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2526644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2527644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25280c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25290c988b73SVidya Sagar 25300c988b73SVidya Sagar status = "disabled"; 25310c988b73SVidya Sagar 25320c988b73SVidya Sagar num-lanes = <4>; 25330c988b73SVidya Sagar num-ib-windows = <2>; 25340c988b73SVidya Sagar num-ob-windows = <8>; 25350c988b73SVidya Sagar 25360c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25370c988b73SVidya Sagar clock-names = "core"; 25380c988b73SVidya Sagar 25390c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25400c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25410c988b73SVidya Sagar reset-names = "apb", "core"; 25420c988b73SVidya Sagar 25430c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25440c988b73SVidya Sagar interrupt-names = "intr"; 25450c988b73SVidya Sagar 25460c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 25470c988b73SVidya Sagar 25480c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25490c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25500c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2551ba02920cSVidya Sagar 2552ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2553ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2554ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2555ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2556ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2557ba02920cSVidya Sagar dma-coherent; 25580c988b73SVidya Sagar }; 25590c988b73SVidya Sagar 2560b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2561bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25620c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2563644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2564644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2565644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2566644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25670c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25680c988b73SVidya Sagar 25690c988b73SVidya Sagar status = "disabled"; 25700c988b73SVidya Sagar 25710c988b73SVidya Sagar num-lanes = <8>; 25720c988b73SVidya Sagar num-ib-windows = <2>; 25730c988b73SVidya Sagar num-ob-windows = <8>; 25740c988b73SVidya Sagar 25750c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 25760c988b73SVidya Sagar clock-names = "core"; 25770c988b73SVidya Sagar 25780c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 25790c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 25800c988b73SVidya Sagar reset-names = "apb", "core"; 25810c988b73SVidya Sagar 25820c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25830c988b73SVidya Sagar interrupt-names = "intr"; 25840c988b73SVidya Sagar 25850c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 25860c988b73SVidya Sagar 25870c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25880c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25890c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2590ba02920cSVidya Sagar 2591ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2592ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2593ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2594ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2595ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2596ba02920cSVidya Sagar dma-coherent; 25970c988b73SVidya Sagar }; 25980c988b73SVidya Sagar 2599b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2600bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 26010c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2602644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2603644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2604644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2605644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26060c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26070c988b73SVidya Sagar 26080c988b73SVidya Sagar status = "disabled"; 26090c988b73SVidya Sagar 26100c988b73SVidya Sagar num-lanes = <8>; 26110c988b73SVidya Sagar num-ib-windows = <2>; 26120c988b73SVidya Sagar num-ob-windows = <8>; 26130c988b73SVidya Sagar 26140c988b73SVidya Sagar pinctrl-names = "default"; 26150c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 26160c988b73SVidya Sagar 26170c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 26180c988b73SVidya Sagar clock-names = "core"; 26190c988b73SVidya Sagar 26200c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26210c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26220c988b73SVidya Sagar reset-names = "apb", "core"; 26230c988b73SVidya Sagar 26240c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26250c988b73SVidya Sagar interrupt-names = "intr"; 26260c988b73SVidya Sagar 26270c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 26280c988b73SVidya Sagar 26290c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 26300c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26310c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2632ba02920cSVidya Sagar 2633ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2634ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2635ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2636ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2637ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2638ba02920cSVidya Sagar dma-coherent; 26390c988b73SVidya Sagar }; 26400c988b73SVidya Sagar 2641e867fe41SThierry Reding sram@40000000 { 26425425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 26435425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 26445425fb15SMikko Perttunen #address-cells = <1>; 26455425fb15SMikko Perttunen #size-cells = <1>; 26465425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 26475425fb15SMikko Perttunen 2648e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 26495425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 26505425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 26515425fb15SMikko Perttunen pool; 26525425fb15SMikko Perttunen }; 26535425fb15SMikko Perttunen 2654e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 26555425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 26565425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 26575425fb15SMikko Perttunen pool; 26585425fb15SMikko Perttunen }; 26595425fb15SMikko Perttunen }; 26605425fb15SMikko Perttunen 26615425fb15SMikko Perttunen bpmp: bpmp { 26625425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 26635425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 26645425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 26657fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 26665425fb15SMikko Perttunen #clock-cells = <1>; 26675425fb15SMikko Perttunen #reset-cells = <1>; 26685425fb15SMikko Perttunen #power-domain-cells = <1>; 2669d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2670d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2671d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2672d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2673d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2674c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 26755425fb15SMikko Perttunen 26765425fb15SMikko Perttunen bpmp_i2c: i2c { 26775425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 26785425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 26795425fb15SMikko Perttunen #address-cells = <1>; 26805425fb15SMikko Perttunen #size-cells = <0>; 26815425fb15SMikko Perttunen }; 26825425fb15SMikko Perttunen 26835425fb15SMikko Perttunen bpmp_thermal: thermal { 26845425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 26855425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 26865425fb15SMikko Perttunen }; 26875425fb15SMikko Perttunen }; 26885425fb15SMikko Perttunen 26897780a034SMikko Perttunen cpus { 2690d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2691d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 26927780a034SMikko Perttunen #address-cells = <1>; 26937780a034SMikko Perttunen #size-cells = <0>; 26947780a034SMikko Perttunen 2695b45d322cSThierry Reding cpu0_0: cpu@0 { 269631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 26977780a034SMikko Perttunen device_type = "cpu"; 2698b45d322cSThierry Reding reg = <0x000>; 26997780a034SMikko Perttunen enable-method = "psci"; 2700b45d322cSThierry Reding i-cache-size = <131072>; 2701b45d322cSThierry Reding i-cache-line-size = <64>; 2702b45d322cSThierry Reding i-cache-sets = <512>; 2703b45d322cSThierry Reding d-cache-size = <65536>; 2704b45d322cSThierry Reding d-cache-line-size = <64>; 2705b45d322cSThierry Reding d-cache-sets = <256>; 2706b45d322cSThierry Reding next-level-cache = <&l2c_0>; 27077780a034SMikko Perttunen }; 27087780a034SMikko Perttunen 2709b45d322cSThierry Reding cpu0_1: cpu@1 { 271031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27117780a034SMikko Perttunen device_type = "cpu"; 2712b45d322cSThierry Reding reg = <0x001>; 27137780a034SMikko Perttunen enable-method = "psci"; 2714b45d322cSThierry Reding i-cache-size = <131072>; 2715b45d322cSThierry Reding i-cache-line-size = <64>; 2716b45d322cSThierry Reding i-cache-sets = <512>; 2717b45d322cSThierry Reding d-cache-size = <65536>; 2718b45d322cSThierry Reding d-cache-line-size = <64>; 2719b45d322cSThierry Reding d-cache-sets = <256>; 2720b45d322cSThierry Reding next-level-cache = <&l2c_0>; 27217780a034SMikko Perttunen }; 27227780a034SMikko Perttunen 2723b45d322cSThierry Reding cpu1_0: cpu@100 { 272431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27257780a034SMikko Perttunen device_type = "cpu"; 27267780a034SMikko Perttunen reg = <0x100>; 27277780a034SMikko Perttunen enable-method = "psci"; 2728b45d322cSThierry Reding i-cache-size = <131072>; 2729b45d322cSThierry Reding i-cache-line-size = <64>; 2730b45d322cSThierry Reding i-cache-sets = <512>; 2731b45d322cSThierry Reding d-cache-size = <65536>; 2732b45d322cSThierry Reding d-cache-line-size = <64>; 2733b45d322cSThierry Reding d-cache-sets = <256>; 2734b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27357780a034SMikko Perttunen }; 27367780a034SMikko Perttunen 2737b45d322cSThierry Reding cpu1_1: cpu@101 { 273831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27397780a034SMikko Perttunen device_type = "cpu"; 27407780a034SMikko Perttunen reg = <0x101>; 27417780a034SMikko Perttunen enable-method = "psci"; 2742b45d322cSThierry Reding i-cache-size = <131072>; 2743b45d322cSThierry Reding i-cache-line-size = <64>; 2744b45d322cSThierry Reding i-cache-sets = <512>; 2745b45d322cSThierry Reding d-cache-size = <65536>; 2746b45d322cSThierry Reding d-cache-line-size = <64>; 2747b45d322cSThierry Reding d-cache-sets = <256>; 2748b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27497780a034SMikko Perttunen }; 27507780a034SMikko Perttunen 2751b45d322cSThierry Reding cpu2_0: cpu@200 { 275231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27537780a034SMikko Perttunen device_type = "cpu"; 27547780a034SMikko Perttunen reg = <0x200>; 27557780a034SMikko Perttunen enable-method = "psci"; 2756b45d322cSThierry Reding i-cache-size = <131072>; 2757b45d322cSThierry Reding i-cache-line-size = <64>; 2758b45d322cSThierry Reding i-cache-sets = <512>; 2759b45d322cSThierry Reding d-cache-size = <65536>; 2760b45d322cSThierry Reding d-cache-line-size = <64>; 2761b45d322cSThierry Reding d-cache-sets = <256>; 2762b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27637780a034SMikko Perttunen }; 27647780a034SMikko Perttunen 2765b45d322cSThierry Reding cpu2_1: cpu@201 { 276631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27677780a034SMikko Perttunen device_type = "cpu"; 27687780a034SMikko Perttunen reg = <0x201>; 27697780a034SMikko Perttunen enable-method = "psci"; 2770b45d322cSThierry Reding i-cache-size = <131072>; 2771b45d322cSThierry Reding i-cache-line-size = <64>; 2772b45d322cSThierry Reding i-cache-sets = <512>; 2773b45d322cSThierry Reding d-cache-size = <65536>; 2774b45d322cSThierry Reding d-cache-line-size = <64>; 2775b45d322cSThierry Reding d-cache-sets = <256>; 2776b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27777780a034SMikko Perttunen }; 27787780a034SMikko Perttunen 2779b45d322cSThierry Reding cpu3_0: cpu@300 { 278031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27817780a034SMikko Perttunen device_type = "cpu"; 2782b45d322cSThierry Reding reg = <0x300>; 27837780a034SMikko Perttunen enable-method = "psci"; 2784b45d322cSThierry Reding i-cache-size = <131072>; 2785b45d322cSThierry Reding i-cache-line-size = <64>; 2786b45d322cSThierry Reding i-cache-sets = <512>; 2787b45d322cSThierry Reding d-cache-size = <65536>; 2788b45d322cSThierry Reding d-cache-line-size = <64>; 2789b45d322cSThierry Reding d-cache-sets = <256>; 2790b45d322cSThierry Reding next-level-cache = <&l2c_3>; 27917780a034SMikko Perttunen }; 27927780a034SMikko Perttunen 2793b45d322cSThierry Reding cpu3_1: cpu@301 { 279431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27957780a034SMikko Perttunen device_type = "cpu"; 2796b45d322cSThierry Reding reg = <0x301>; 27977780a034SMikko Perttunen enable-method = "psci"; 2798b45d322cSThierry Reding i-cache-size = <131072>; 2799b45d322cSThierry Reding i-cache-line-size = <64>; 2800b45d322cSThierry Reding i-cache-sets = <512>; 2801b45d322cSThierry Reding d-cache-size = <65536>; 2802b45d322cSThierry Reding d-cache-line-size = <64>; 2803b45d322cSThierry Reding d-cache-sets = <256>; 2804b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2805b45d322cSThierry Reding }; 2806b45d322cSThierry Reding 2807b45d322cSThierry Reding cpu-map { 2808b45d322cSThierry Reding cluster0 { 2809b45d322cSThierry Reding core0 { 2810b45d322cSThierry Reding cpu = <&cpu0_0>; 2811b45d322cSThierry Reding }; 2812b45d322cSThierry Reding 2813b45d322cSThierry Reding core1 { 2814b45d322cSThierry Reding cpu = <&cpu0_1>; 2815b45d322cSThierry Reding }; 2816b45d322cSThierry Reding }; 2817b45d322cSThierry Reding 2818b45d322cSThierry Reding cluster1 { 2819b45d322cSThierry Reding core0 { 2820b45d322cSThierry Reding cpu = <&cpu1_0>; 2821b45d322cSThierry Reding }; 2822b45d322cSThierry Reding 2823b45d322cSThierry Reding core1 { 2824b45d322cSThierry Reding cpu = <&cpu1_1>; 2825b45d322cSThierry Reding }; 2826b45d322cSThierry Reding }; 2827b45d322cSThierry Reding 2828b45d322cSThierry Reding cluster2 { 2829b45d322cSThierry Reding core0 { 2830b45d322cSThierry Reding cpu = <&cpu2_0>; 2831b45d322cSThierry Reding }; 2832b45d322cSThierry Reding 2833b45d322cSThierry Reding core1 { 2834b45d322cSThierry Reding cpu = <&cpu2_1>; 2835b45d322cSThierry Reding }; 2836b45d322cSThierry Reding }; 2837b45d322cSThierry Reding 2838b45d322cSThierry Reding cluster3 { 2839b45d322cSThierry Reding core0 { 2840b45d322cSThierry Reding cpu = <&cpu3_0>; 2841b45d322cSThierry Reding }; 2842b45d322cSThierry Reding 2843b45d322cSThierry Reding core1 { 2844b45d322cSThierry Reding cpu = <&cpu3_1>; 2845b45d322cSThierry Reding }; 2846b45d322cSThierry Reding }; 2847b45d322cSThierry Reding }; 2848b45d322cSThierry Reding 2849b45d322cSThierry Reding l2c_0: l2-cache0 { 2850b45d322cSThierry Reding cache-size = <2097152>; 2851b45d322cSThierry Reding cache-line-size = <64>; 2852b45d322cSThierry Reding cache-sets = <2048>; 2853b45d322cSThierry Reding next-level-cache = <&l3c>; 2854b45d322cSThierry Reding }; 2855b45d322cSThierry Reding 2856b45d322cSThierry Reding l2c_1: l2-cache1 { 2857b45d322cSThierry Reding cache-size = <2097152>; 2858b45d322cSThierry Reding cache-line-size = <64>; 2859b45d322cSThierry Reding cache-sets = <2048>; 2860b45d322cSThierry Reding next-level-cache = <&l3c>; 2861b45d322cSThierry Reding }; 2862b45d322cSThierry Reding 2863b45d322cSThierry Reding l2c_2: l2-cache2 { 2864b45d322cSThierry Reding cache-size = <2097152>; 2865b45d322cSThierry Reding cache-line-size = <64>; 2866b45d322cSThierry Reding cache-sets = <2048>; 2867b45d322cSThierry Reding next-level-cache = <&l3c>; 2868b45d322cSThierry Reding }; 2869b45d322cSThierry Reding 2870b45d322cSThierry Reding l2c_3: l2-cache3 { 2871b45d322cSThierry Reding cache-size = <2097152>; 2872b45d322cSThierry Reding cache-line-size = <64>; 2873b45d322cSThierry Reding cache-sets = <2048>; 2874b45d322cSThierry Reding next-level-cache = <&l3c>; 2875b45d322cSThierry Reding }; 2876b45d322cSThierry Reding 2877b45d322cSThierry Reding l3c: l3-cache { 2878b45d322cSThierry Reding cache-size = <4194304>; 2879b45d322cSThierry Reding cache-line-size = <64>; 2880b45d322cSThierry Reding cache-sets = <4096>; 28817780a034SMikko Perttunen }; 28827780a034SMikko Perttunen }; 28837780a034SMikko Perttunen 28849e79e58fSJon Hunter pmu { 28859e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 28869e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 28879e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 28889e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 28899e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 28909e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 28919e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 28929e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 28939e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 28949e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 28959e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 28969e79e58fSJon Hunter }; 28979e79e58fSJon Hunter 28987780a034SMikko Perttunen psci { 28997780a034SMikko Perttunen compatible = "arm,psci-1.0"; 29007780a034SMikko Perttunen status = "okay"; 29017780a034SMikko Perttunen method = "smc"; 29027780a034SMikko Perttunen }; 29037780a034SMikko Perttunen 29045b4f6323SSameer Pujar sound { 29055b4f6323SSameer Pujar status = "disabled"; 29065b4f6323SSameer Pujar 29075b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 29085b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 29095b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 29105b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 29115b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 29125b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 29135b4f6323SSameer Pujar assigned-clock-parents = <0>, 29145b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 29155b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 29165b4f6323SSameer Pujar /* 29175b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 29185b4f6323SSameer Pujar * for this to work and oscillate between base rates required 29195b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 29205b4f6323SSameer Pujar */ 29215b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 292234e0fc34SThierry Reding 292334e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 292434e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 292534e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 292634e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 29275b4f6323SSameer Pujar }; 29285b4f6323SSameer Pujar 292999d9bde5SThierry Reding tcu: serial { 2930a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2931a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2932a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2933a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2934a38570c2SMikko Perttunen }; 2935a38570c2SMikko Perttunen 2936686ba009SThierry Reding thermal-zones { 2937fe57ff53SThierry Reding cpu-thermal { 2938fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2939686ba009SThierry Reding status = "disabled"; 2940686ba009SThierry Reding }; 2941686ba009SThierry Reding 2942fe57ff53SThierry Reding gpu-thermal { 2943fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2944686ba009SThierry Reding status = "disabled"; 2945686ba009SThierry Reding }; 2946686ba009SThierry Reding 2947fe57ff53SThierry Reding aux-thermal { 2948fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2949686ba009SThierry Reding status = "disabled"; 2950686ba009SThierry Reding }; 2951686ba009SThierry Reding 2952fe57ff53SThierry Reding pllx-thermal { 2953fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2954686ba009SThierry Reding status = "disabled"; 2955686ba009SThierry Reding }; 2956686ba009SThierry Reding 2957fe57ff53SThierry Reding ao-thermal { 2958fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2959686ba009SThierry Reding status = "disabled"; 2960686ba009SThierry Reding }; 2961686ba009SThierry Reding 2962fe57ff53SThierry Reding tj-thermal { 2963fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2964686ba009SThierry Reding status = "disabled"; 2965686ba009SThierry Reding }; 2966686ba009SThierry Reding }; 2967686ba009SThierry Reding 29685425fb15SMikko Perttunen timer { 29695425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 29705425fb15SMikko Perttunen interrupts = <GIC_PPI 13 29715425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29725425fb15SMikko Perttunen <GIC_PPI 14 29735425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29745425fb15SMikko Perttunen <GIC_PPI 11 29755425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29765425fb15SMikko Perttunen <GIC_PPI 10 29775425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 29785425fb15SMikko Perttunen interrupt-parent = <&gic>; 2979b30be673SThierry Reding always-on; 29805425fb15SMikko Perttunen }; 29815425fb15SMikko Perttunen}; 2982