15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 65f89b58ceSMikko Perttunen status = "disabled"; 66f89b58ceSMikko Perttunen 67f89b58ceSMikko Perttunen snps,write-requests = <1>; 68f89b58ceSMikko Perttunen snps,read-requests = <3>; 69f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 70f89b58ceSMikko Perttunen snps,txpbl = <16>; 71f89b58ceSMikko Perttunen snps,rxpbl = <8>; 72f89b58ceSMikko Perttunen }; 73f89b58ceSMikko Perttunen 741aaa7698SThierry Reding aconnect@2900000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 765d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 775d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 785d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 795d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 805d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 815d2249ddSSameer Pujar #address-cells = <1>; 825d2249ddSSameer Pujar #size-cells = <1>; 835d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 845d2249ddSSameer Pujar status = "disabled"; 855d2249ddSSameer Pujar 865d2249ddSSameer Pujar dma-controller@2930000 { 875d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 885d2249ddSSameer Pujar "nvidia,tegra186-adma"; 895d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 905d2249ddSSameer Pujar interrupt-parent = <&agic>; 915d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1235d2249ddSSameer Pujar #dma-cells = <1>; 1245d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1255d2249ddSSameer Pujar clock-names = "d_audio"; 1265d2249ddSSameer Pujar status = "disabled"; 1275d2249ddSSameer Pujar }; 1285d2249ddSSameer Pujar 1295d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1315d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1325d2249ddSSameer Pujar #interrupt-cells = <3>; 1335d2249ddSSameer Pujar interrupt-controller; 1345d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1355d2249ddSSameer Pujar <0x02a42000 0x2000>; 1365d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1375d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1385d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 1435d2249ddSSameer Pujar }; 1445d2249ddSSameer Pujar 145dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 146dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 147644c569dSThierry Reding reg = <0x2430000 0x17000>, 148644c569dSThierry Reding <0xc300000 0x4000>; 149dbb72e2cSVidya Sagar 150dbb72e2cSVidya Sagar status = "okay"; 151dbb72e2cSVidya Sagar 152dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 153dbb72e2cSVidya Sagar pex_rst { 154dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 155dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 156dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 157dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 159dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 160dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 161dbb72e2cSVidya Sagar }; 162dbb72e2cSVidya Sagar }; 163dbb72e2cSVidya Sagar 164dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 165dbb72e2cSVidya Sagar clkreq { 166dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 167dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 168dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 169dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 170dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 171dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 172dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173dbb72e2cSVidya Sagar }; 174dbb72e2cSVidya Sagar }; 175dbb72e2cSVidya Sagar }; 176dbb72e2cSVidya Sagar 177be9b887fSThierry Reding mc: memory-controller@2c00000 { 178be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 179be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 180be9b887fSThierry Reding <0x02b80000 0x040000>, 181be9b887fSThierry Reding <0x01700000 0x100000>; 1828613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 183d5237c7cSThierry Reding #interconnect-cells = <1>; 184be9b887fSThierry Reding status = "disabled"; 185be9b887fSThierry Reding 186be9b887fSThierry Reding #address-cells = <2>; 187be9b887fSThierry Reding #size-cells = <2>; 188be9b887fSThierry Reding 189be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 190be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 191be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 192be9b887fSThierry Reding 193be9b887fSThierry Reding /* 194be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 195be9b887fSThierry Reding * controller selects the XBAR format used when memory 196be9b887fSThierry Reding * is accessed. This is used to transparently access 197be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 198be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 199be9b887fSThierry Reding * 200be9b887fSThierry Reding * As a consequence, the operating system must ensure 201be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 202be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 203be9b887fSThierry Reding * devices require access to the XBAR switch, their 204be9b887fSThierry Reding * drivers must set this bit explicitly. 205be9b887fSThierry Reding * 206be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 207be9b887fSThierry Reding */ 208be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 209be9b887fSThierry Reding 210be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 211be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 212be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 213be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 214be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 215be9b887fSThierry Reding clock-names = "emc"; 216be9b887fSThierry Reding 217d5237c7cSThierry Reding #interconnect-cells = <0>; 218d5237c7cSThierry Reding 219be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 220be9b887fSThierry Reding }; 221be9b887fSThierry Reding }; 222be9b887fSThierry Reding 2235425fb15SMikko Perttunen uarta: serial@3100000 { 2245425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2255425fb15SMikko Perttunen reg = <0x03100000 0x40>; 2265425fb15SMikko Perttunen reg-shift = <2>; 2275425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 2295425fb15SMikko Perttunen clock-names = "serial"; 2305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 2315425fb15SMikko Perttunen reset-names = "serial"; 2325425fb15SMikko Perttunen status = "disabled"; 2335425fb15SMikko Perttunen }; 2345425fb15SMikko Perttunen 2355425fb15SMikko Perttunen uartb: serial@3110000 { 2365425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2375425fb15SMikko Perttunen reg = <0x03110000 0x40>; 2385425fb15SMikko Perttunen reg-shift = <2>; 2395425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2405425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 2415425fb15SMikko Perttunen clock-names = "serial"; 2425425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 2435425fb15SMikko Perttunen reset-names = "serial"; 2445425fb15SMikko Perttunen status = "disabled"; 2455425fb15SMikko Perttunen }; 2465425fb15SMikko Perttunen 2475425fb15SMikko Perttunen uartd: serial@3130000 { 2485425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2495425fb15SMikko Perttunen reg = <0x03130000 0x40>; 2505425fb15SMikko Perttunen reg-shift = <2>; 2515425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 2535425fb15SMikko Perttunen clock-names = "serial"; 2545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 2555425fb15SMikko Perttunen reset-names = "serial"; 2565425fb15SMikko Perttunen status = "disabled"; 2575425fb15SMikko Perttunen }; 2585425fb15SMikko Perttunen 2595425fb15SMikko Perttunen uarte: serial@3140000 { 2605425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2615425fb15SMikko Perttunen reg = <0x03140000 0x40>; 2625425fb15SMikko Perttunen reg-shift = <2>; 2635425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2645425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 2655425fb15SMikko Perttunen clock-names = "serial"; 2665425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 2675425fb15SMikko Perttunen reset-names = "serial"; 2685425fb15SMikko Perttunen status = "disabled"; 2695425fb15SMikko Perttunen }; 2705425fb15SMikko Perttunen 2715425fb15SMikko Perttunen uartf: serial@3150000 { 2725425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2735425fb15SMikko Perttunen reg = <0x03150000 0x40>; 2745425fb15SMikko Perttunen reg-shift = <2>; 2755425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2765425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 2775425fb15SMikko Perttunen clock-names = "serial"; 2785425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 2795425fb15SMikko Perttunen reset-names = "serial"; 2805425fb15SMikko Perttunen status = "disabled"; 2815425fb15SMikko Perttunen }; 2825425fb15SMikko Perttunen 2835425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 284d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2855425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 2865425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2875425fb15SMikko Perttunen #address-cells = <1>; 2885425fb15SMikko Perttunen #size-cells = <0>; 2895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2905425fb15SMikko Perttunen clock-names = "div-clk"; 2915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2925425fb15SMikko Perttunen reset-names = "i2c"; 2935425fb15SMikko Perttunen status = "disabled"; 2945425fb15SMikko Perttunen }; 2955425fb15SMikko Perttunen 2965425fb15SMikko Perttunen uarth: serial@3170000 { 2975425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2985425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2995425fb15SMikko Perttunen reg-shift = <2>; 3005425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 3015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 3025425fb15SMikko Perttunen clock-names = "serial"; 3035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 3045425fb15SMikko Perttunen reset-names = "serial"; 3055425fb15SMikko Perttunen status = "disabled"; 3065425fb15SMikko Perttunen }; 3075425fb15SMikko Perttunen 3085425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 309d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3105425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 3115425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 3125425fb15SMikko Perttunen #address-cells = <1>; 3135425fb15SMikko Perttunen #size-cells = <0>; 3145425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 3155425fb15SMikko Perttunen clock-names = "div-clk"; 3165425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 3175425fb15SMikko Perttunen reset-names = "i2c"; 3185425fb15SMikko Perttunen status = "disabled"; 3195425fb15SMikko Perttunen }; 3205425fb15SMikko Perttunen 3215425fb15SMikko Perttunen /* shares pads with dpaux1 */ 3225425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 323d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3245425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 3255425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 3265425fb15SMikko Perttunen #address-cells = <1>; 3275425fb15SMikko Perttunen #size-cells = <0>; 3285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 3295425fb15SMikko Perttunen clock-names = "div-clk"; 3305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 3315425fb15SMikko Perttunen reset-names = "i2c"; 332a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 333a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 334a4131561SThierry Reding pinctrl-names = "default", "idle"; 3355425fb15SMikko Perttunen status = "disabled"; 3365425fb15SMikko Perttunen }; 3375425fb15SMikko Perttunen 3385425fb15SMikko Perttunen /* shares pads with dpaux0 */ 3395425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 340d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3415425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 3425425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3435425fb15SMikko Perttunen #address-cells = <1>; 3445425fb15SMikko Perttunen #size-cells = <0>; 3455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 3465425fb15SMikko Perttunen clock-names = "div-clk"; 3475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 3485425fb15SMikko Perttunen reset-names = "i2c"; 349a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 350a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 351a4131561SThierry Reding pinctrl-names = "default", "idle"; 3525425fb15SMikko Perttunen status = "disabled"; 3535425fb15SMikko Perttunen }; 3545425fb15SMikko Perttunen 355a4131561SThierry Reding /* shares pads with dpaux2 */ 356a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 357d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3585425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 3595425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 3605425fb15SMikko Perttunen #address-cells = <1>; 3615425fb15SMikko Perttunen #size-cells = <0>; 3625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 3635425fb15SMikko Perttunen clock-names = "div-clk"; 3645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 3655425fb15SMikko Perttunen reset-names = "i2c"; 366a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 367a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 368a4131561SThierry Reding pinctrl-names = "default", "idle"; 3695425fb15SMikko Perttunen status = "disabled"; 3705425fb15SMikko Perttunen }; 3715425fb15SMikko Perttunen 372a4131561SThierry Reding /* shares pads with dpaux3 */ 373a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 374d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3755425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 3765425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3775425fb15SMikko Perttunen #address-cells = <1>; 3785425fb15SMikko Perttunen #size-cells = <0>; 3795425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 3805425fb15SMikko Perttunen clock-names = "div-clk"; 3815425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 3825425fb15SMikko Perttunen reset-names = "i2c"; 383a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 384a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 385a4131561SThierry Reding pinctrl-names = "default", "idle"; 3865425fb15SMikko Perttunen status = "disabled"; 3875425fb15SMikko Perttunen }; 3885425fb15SMikko Perttunen 3896a574ec7SThierry Reding pwm1: pwm@3280000 { 3906a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3916a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3926a574ec7SThierry Reding reg = <0x3280000 0x10000>; 3936a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 3946a574ec7SThierry Reding clock-names = "pwm"; 3956a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 3966a574ec7SThierry Reding reset-names = "pwm"; 3976a574ec7SThierry Reding status = "disabled"; 3986a574ec7SThierry Reding #pwm-cells = <2>; 3996a574ec7SThierry Reding }; 4006a574ec7SThierry Reding 4016a574ec7SThierry Reding pwm2: pwm@3290000 { 4026a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4036a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4046a574ec7SThierry Reding reg = <0x3290000 0x10000>; 4056a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 4066a574ec7SThierry Reding clock-names = "pwm"; 4076a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 4086a574ec7SThierry Reding reset-names = "pwm"; 4096a574ec7SThierry Reding status = "disabled"; 4106a574ec7SThierry Reding #pwm-cells = <2>; 4116a574ec7SThierry Reding }; 4126a574ec7SThierry Reding 4136a574ec7SThierry Reding pwm3: pwm@32a0000 { 4146a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4156a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4166a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 4176a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 4186a574ec7SThierry Reding clock-names = "pwm"; 4196a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 4206a574ec7SThierry Reding reset-names = "pwm"; 4216a574ec7SThierry Reding status = "disabled"; 4226a574ec7SThierry Reding #pwm-cells = <2>; 4236a574ec7SThierry Reding }; 4246a574ec7SThierry Reding 4256a574ec7SThierry Reding pwm5: pwm@32c0000 { 4266a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4276a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4286a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 4296a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 4306a574ec7SThierry Reding clock-names = "pwm"; 4316a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 4326a574ec7SThierry Reding reset-names = "pwm"; 4336a574ec7SThierry Reding status = "disabled"; 4346a574ec7SThierry Reding #pwm-cells = <2>; 4356a574ec7SThierry Reding }; 4366a574ec7SThierry Reding 4376a574ec7SThierry Reding pwm6: pwm@32d0000 { 4386a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4396a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4406a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 4416a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 4426a574ec7SThierry Reding clock-names = "pwm"; 4436a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 4446a574ec7SThierry Reding reset-names = "pwm"; 4456a574ec7SThierry Reding status = "disabled"; 4466a574ec7SThierry Reding #pwm-cells = <2>; 4476a574ec7SThierry Reding }; 4486a574ec7SThierry Reding 4496a574ec7SThierry Reding pwm7: pwm@32e0000 { 4506a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4516a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4526a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 4536a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 4546a574ec7SThierry Reding clock-names = "pwm"; 4556a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 4566a574ec7SThierry Reding reset-names = "pwm"; 4576a574ec7SThierry Reding status = "disabled"; 4586a574ec7SThierry Reding #pwm-cells = <2>; 4596a574ec7SThierry Reding }; 4606a574ec7SThierry Reding 4616a574ec7SThierry Reding pwm8: pwm@32f0000 { 4626a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4636a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4646a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 4656a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 4666a574ec7SThierry Reding clock-names = "pwm"; 4676a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 4686a574ec7SThierry Reding reset-names = "pwm"; 4696a574ec7SThierry Reding status = "disabled"; 4706a574ec7SThierry Reding #pwm-cells = <2>; 4716a574ec7SThierry Reding }; 4726a574ec7SThierry Reding 47367bb17f6SThierry Reding sdmmc1: mmc@3400000 { 4742c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 4755425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 4765425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 4775425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 4785425fb15SMikko Perttunen clock-names = "sdhci"; 4795425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 4805425fb15SMikko Perttunen reset-names = "sdhci"; 481d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 482d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 483d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 4844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 4854e0f1229SSowjanya Komatineni <0x07>; 4864e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4874e0f1229SSowjanya Komatineni <0x07>; 4884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4894e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4904e0f1229SSowjanya Komatineni <0x07>; 4914e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4924e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4934e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4944e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4955425fb15SMikko Perttunen status = "disabled"; 4965425fb15SMikko Perttunen }; 4975425fb15SMikko Perttunen 49867bb17f6SThierry Reding sdmmc3: mmc@3440000 { 4992c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 5005425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 5015425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 5025425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 5035425fb15SMikko Perttunen clock-names = "sdhci"; 5045425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 5055425fb15SMikko Perttunen reset-names = "sdhci"; 506d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 507d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 508d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 5094e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 5104e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 5114e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 5124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5134e0f1229SSowjanya Komatineni <0x07>; 5144e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 5154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5164e0f1229SSowjanya Komatineni <0x07>; 5174e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 5184e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 5194e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 5204e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 5215425fb15SMikko Perttunen status = "disabled"; 5225425fb15SMikko Perttunen }; 5235425fb15SMikko Perttunen 52467bb17f6SThierry Reding sdmmc4: mmc@3460000 { 5252c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 5265425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 5275425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 5285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 5295425fb15SMikko Perttunen clock-names = "sdhci"; 530351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 531351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 532351648d0SSowjanya Komatineni assigned-clock-parents = 533351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 5345425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 5355425fb15SMikko Perttunen reset-names = "sdhci"; 536d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 537d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 538d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 5394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 5404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 5414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 5424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5434e0f1229SSowjanya Komatineni <0x0a>; 5444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 5454e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5464e0f1229SSowjanya Komatineni <0x0a>; 5474e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 5484e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 5494e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 550dfd3cb6fSSowjanya Komatineni supports-cqe; 5515425fb15SMikko Perttunen status = "disabled"; 5525425fb15SMikko Perttunen }; 5535425fb15SMikko Perttunen 5544878cc0cSSameer Pujar hda@3510000 { 5554878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 5564878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 5574878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 5584878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 5594878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 5604878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 5614878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 5624878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 5634878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 5644878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 5654878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 5664878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 567d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 568d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 569d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 5704878cc0cSSameer Pujar status = "disabled"; 5714878cc0cSSameer Pujar }; 5724878cc0cSSameer Pujar 573fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 574fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 575fab7a039SJC Kuo reg = <0x03520000 0x1000>, 576fab7a039SJC Kuo <0x03540000 0x1000>; 577fab7a039SJC Kuo reg-names = "padctl", "ao"; 578fab7a039SJC Kuo 579fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 580fab7a039SJC Kuo reset-names = "padctl"; 581fab7a039SJC Kuo 582fab7a039SJC Kuo status = "disabled"; 583fab7a039SJC Kuo 584fab7a039SJC Kuo pads { 585fab7a039SJC Kuo usb2 { 586fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 587fab7a039SJC Kuo clock-names = "trk"; 588fab7a039SJC Kuo 589fab7a039SJC Kuo lanes { 590fab7a039SJC Kuo usb2-0 { 591fab7a039SJC Kuo nvidia,function = "xusb"; 592fab7a039SJC Kuo status = "disabled"; 593fab7a039SJC Kuo #phy-cells = <0>; 594fab7a039SJC Kuo }; 595fab7a039SJC Kuo 596fab7a039SJC Kuo usb2-1 { 597fab7a039SJC Kuo nvidia,function = "xusb"; 598fab7a039SJC Kuo status = "disabled"; 599fab7a039SJC Kuo #phy-cells = <0>; 600fab7a039SJC Kuo }; 601fab7a039SJC Kuo 602fab7a039SJC Kuo usb2-2 { 603fab7a039SJC Kuo nvidia,function = "xusb"; 604fab7a039SJC Kuo status = "disabled"; 605fab7a039SJC Kuo #phy-cells = <0>; 606fab7a039SJC Kuo }; 607fab7a039SJC Kuo 608fab7a039SJC Kuo usb2-3 { 609fab7a039SJC Kuo nvidia,function = "xusb"; 610fab7a039SJC Kuo status = "disabled"; 611fab7a039SJC Kuo #phy-cells = <0>; 612fab7a039SJC Kuo }; 613fab7a039SJC Kuo }; 614fab7a039SJC Kuo }; 615fab7a039SJC Kuo 616fab7a039SJC Kuo usb3 { 617fab7a039SJC Kuo lanes { 618fab7a039SJC Kuo usb3-0 { 619fab7a039SJC Kuo nvidia,function = "xusb"; 620fab7a039SJC Kuo status = "disabled"; 621fab7a039SJC Kuo #phy-cells = <0>; 622fab7a039SJC Kuo }; 623fab7a039SJC Kuo 624fab7a039SJC Kuo usb3-1 { 625fab7a039SJC Kuo nvidia,function = "xusb"; 626fab7a039SJC Kuo status = "disabled"; 627fab7a039SJC Kuo #phy-cells = <0>; 628fab7a039SJC Kuo }; 629fab7a039SJC Kuo 630fab7a039SJC Kuo usb3-2 { 631fab7a039SJC Kuo nvidia,function = "xusb"; 632fab7a039SJC Kuo status = "disabled"; 633fab7a039SJC Kuo #phy-cells = <0>; 634fab7a039SJC Kuo }; 635fab7a039SJC Kuo 636fab7a039SJC Kuo usb3-3 { 637fab7a039SJC Kuo nvidia,function = "xusb"; 638fab7a039SJC Kuo status = "disabled"; 639fab7a039SJC Kuo #phy-cells = <0>; 640fab7a039SJC Kuo }; 641fab7a039SJC Kuo }; 642fab7a039SJC Kuo }; 643fab7a039SJC Kuo }; 644fab7a039SJC Kuo 645fab7a039SJC Kuo ports { 646fab7a039SJC Kuo usb2-0 { 647fab7a039SJC Kuo status = "disabled"; 648fab7a039SJC Kuo }; 649fab7a039SJC Kuo 650fab7a039SJC Kuo usb2-1 { 651fab7a039SJC Kuo status = "disabled"; 652fab7a039SJC Kuo }; 653fab7a039SJC Kuo 654fab7a039SJC Kuo usb2-2 { 655fab7a039SJC Kuo status = "disabled"; 656fab7a039SJC Kuo }; 657fab7a039SJC Kuo 658fab7a039SJC Kuo usb2-3 { 659fab7a039SJC Kuo status = "disabled"; 660fab7a039SJC Kuo }; 661fab7a039SJC Kuo 662fab7a039SJC Kuo usb3-0 { 663fab7a039SJC Kuo status = "disabled"; 664fab7a039SJC Kuo }; 665fab7a039SJC Kuo 666fab7a039SJC Kuo usb3-1 { 667fab7a039SJC Kuo status = "disabled"; 668fab7a039SJC Kuo }; 669fab7a039SJC Kuo 670fab7a039SJC Kuo usb3-2 { 671fab7a039SJC Kuo status = "disabled"; 672fab7a039SJC Kuo }; 673fab7a039SJC Kuo 674fab7a039SJC Kuo usb3-3 { 675fab7a039SJC Kuo status = "disabled"; 676fab7a039SJC Kuo }; 677fab7a039SJC Kuo }; 678fab7a039SJC Kuo }; 679fab7a039SJC Kuo 680bc8788b2SNagarjuna Kristam usb@3550000 { 681bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 682bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 683bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 684bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 685bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 686bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 687bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 688bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 689bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 690bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 691bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 692bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 693bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 694bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 695bc8788b2SNagarjuna Kristam status = "disabled"; 696bc8788b2SNagarjuna Kristam }; 697bc8788b2SNagarjuna Kristam 698fab7a039SJC Kuo usb@3610000 { 699fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 700fab7a039SJC Kuo reg = <0x03610000 0x40000>, 701fab7a039SJC Kuo <0x03600000 0x10000>; 702fab7a039SJC Kuo reg-names = "hcd", "fpci"; 703fab7a039SJC Kuo 704fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 705a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 706fab7a039SJC Kuo 707fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 708fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 709fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 710fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 711fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 712fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 713fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 714fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 715fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 716fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 717fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 718fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 719fab7a039SJC Kuo "pll_e"; 720fab7a039SJC Kuo 721fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 722fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 723fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 724fab7a039SJC Kuo 725fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 726fab7a039SJC Kuo status = "disabled"; 727fab7a039SJC Kuo }; 728fab7a039SJC Kuo 72909903c5eSJC Kuo fuse@3820000 { 73009903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 73109903c5eSJC Kuo reg = <0x03820000 0x10000>; 73209903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 73309903c5eSJC Kuo clock-names = "fuse"; 73409903c5eSJC Kuo }; 73509903c5eSJC Kuo 7365425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 7375425fb15SMikko Perttunen compatible = "arm,gic-400"; 7385425fb15SMikko Perttunen #interrupt-cells = <3>; 7395425fb15SMikko Perttunen interrupt-controller; 7405425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 7415425fb15SMikko Perttunen <0x03882000 0x2000>, 7425425fb15SMikko Perttunen <0x03884000 0x2000>, 7435425fb15SMikko Perttunen <0x03886000 0x2000>; 7445425fb15SMikko Perttunen interrupts = <GIC_PPI 9 7455425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 7465425fb15SMikko Perttunen interrupt-parent = <&gic>; 7475425fb15SMikko Perttunen }; 7485425fb15SMikko Perttunen 749badb80beSThierry Reding cec@3960000 { 750badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 751badb80beSThierry Reding reg = <0x03960000 0x10000>; 752badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 753badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 754badb80beSThierry Reding clock-names = "cec"; 755badb80beSThierry Reding status = "disabled"; 756badb80beSThierry Reding }; 757badb80beSThierry Reding 7585425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 759a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 7605425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 761a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 762a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 763a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 764a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 765a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 766a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 767a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 768a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 769a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 770a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 771a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 772a38570c2SMikko Perttunen "shared7"; 773a38570c2SMikko Perttunen #mbox-cells = <2>; 774a38570c2SMikko Perttunen }; 775a38570c2SMikko Perttunen 7762602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 7772602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7782602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 7792602c32fSVidya Sagar reg-names = "ctl"; 7802602c32fSVidya Sagar 7812602c32fSVidya Sagar #phy-cells = <0>; 7822602c32fSVidya Sagar }; 7832602c32fSVidya Sagar 7842602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 7852602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7862602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 7872602c32fSVidya Sagar reg-names = "ctl"; 7882602c32fSVidya Sagar 7892602c32fSVidya Sagar #phy-cells = <0>; 7902602c32fSVidya Sagar }; 7912602c32fSVidya Sagar 7922602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 7932602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7942602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 7952602c32fSVidya Sagar reg-names = "ctl"; 7962602c32fSVidya Sagar 7972602c32fSVidya Sagar #phy-cells = <0>; 7982602c32fSVidya Sagar }; 7992602c32fSVidya Sagar 8002602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 8012602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8022602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 8032602c32fSVidya Sagar reg-names = "ctl"; 8042602c32fSVidya Sagar 8052602c32fSVidya Sagar #phy-cells = <0>; 8062602c32fSVidya Sagar }; 8072602c32fSVidya Sagar 8082602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 8092602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8102602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 8112602c32fSVidya Sagar reg-names = "ctl"; 8122602c32fSVidya Sagar 8132602c32fSVidya Sagar #phy-cells = <0>; 8142602c32fSVidya Sagar }; 8152602c32fSVidya Sagar 8162602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 8172602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8182602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 8192602c32fSVidya Sagar reg-names = "ctl"; 8202602c32fSVidya Sagar 8212602c32fSVidya Sagar #phy-cells = <0>; 8222602c32fSVidya Sagar }; 8232602c32fSVidya Sagar 8242602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 8252602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8262602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 8272602c32fSVidya Sagar reg-names = "ctl"; 8282602c32fSVidya Sagar 8292602c32fSVidya Sagar #phy-cells = <0>; 8302602c32fSVidya Sagar }; 8312602c32fSVidya Sagar 8322602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 8332602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8342602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 8352602c32fSVidya Sagar reg-names = "ctl"; 8362602c32fSVidya Sagar 8372602c32fSVidya Sagar #phy-cells = <0>; 8382602c32fSVidya Sagar }; 8392602c32fSVidya Sagar 8402602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 8412602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8422602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 8432602c32fSVidya Sagar reg-names = "ctl"; 8442602c32fSVidya Sagar 8452602c32fSVidya Sagar #phy-cells = <0>; 8462602c32fSVidya Sagar }; 8472602c32fSVidya Sagar 8482602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 8492602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8502602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 8512602c32fSVidya Sagar reg-names = "ctl"; 8522602c32fSVidya Sagar 8532602c32fSVidya Sagar #phy-cells = <0>; 8542602c32fSVidya Sagar }; 8552602c32fSVidya Sagar 8562602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 8572602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8582602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 8592602c32fSVidya Sagar reg-names = "ctl"; 8602602c32fSVidya Sagar 8612602c32fSVidya Sagar #phy-cells = <0>; 8622602c32fSVidya Sagar }; 8632602c32fSVidya Sagar 8642602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 8652602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8662602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 8672602c32fSVidya Sagar reg-names = "ctl"; 8682602c32fSVidya Sagar 8692602c32fSVidya Sagar #phy-cells = <0>; 8702602c32fSVidya Sagar }; 8712602c32fSVidya Sagar 8722602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 8732602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8742602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 8752602c32fSVidya Sagar reg-names = "ctl"; 8762602c32fSVidya Sagar 8772602c32fSVidya Sagar #phy-cells = <0>; 8782602c32fSVidya Sagar }; 8792602c32fSVidya Sagar 8802602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 8812602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8822602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 8832602c32fSVidya Sagar reg-names = "ctl"; 8842602c32fSVidya Sagar 8852602c32fSVidya Sagar #phy-cells = <0>; 8862602c32fSVidya Sagar }; 8872602c32fSVidya Sagar 8882602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 8892602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8902602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 8912602c32fSVidya Sagar reg-names = "ctl"; 8922602c32fSVidya Sagar 8932602c32fSVidya Sagar #phy-cells = <0>; 8942602c32fSVidya Sagar }; 8952602c32fSVidya Sagar 8962602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 8972602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8982602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 8992602c32fSVidya Sagar reg-names = "ctl"; 9002602c32fSVidya Sagar 9012602c32fSVidya Sagar #phy-cells = <0>; 9022602c32fSVidya Sagar }; 9032602c32fSVidya Sagar 9042602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 9052602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9062602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 9072602c32fSVidya Sagar reg-names = "ctl"; 9082602c32fSVidya Sagar 9092602c32fSVidya Sagar #phy-cells = <0>; 9102602c32fSVidya Sagar }; 9112602c32fSVidya Sagar 9122602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 9132602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9142602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 9152602c32fSVidya Sagar reg-names = "ctl"; 9162602c32fSVidya Sagar 9172602c32fSVidya Sagar #phy-cells = <0>; 9182602c32fSVidya Sagar }; 9192602c32fSVidya Sagar 9202602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 9212602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9222602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 9232602c32fSVidya Sagar reg-names = "ctl"; 9242602c32fSVidya Sagar 9252602c32fSVidya Sagar #phy-cells = <0>; 9262602c32fSVidya Sagar }; 9272602c32fSVidya Sagar 9282602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 9292602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 9302602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 9312602c32fSVidya Sagar reg-names = "ctl"; 9322602c32fSVidya Sagar 9332602c32fSVidya Sagar #phy-cells = <0>; 9342602c32fSVidya Sagar }; 9352602c32fSVidya Sagar 936a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 937a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 938a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 939a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 940a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 941a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 942a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 943a38570c2SMikko Perttunen /* 944a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 945a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 946a38570c2SMikko Perttunen */ 947a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 9485425fb15SMikko Perttunen #mbox-cells = <2>; 9495425fb15SMikko Perttunen }; 9505425fb15SMikko Perttunen 9515425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 952d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9535425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 9545425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 9555425fb15SMikko Perttunen #address-cells = <1>; 9565425fb15SMikko Perttunen #size-cells = <0>; 9575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 9585425fb15SMikko Perttunen clock-names = "div-clk"; 9595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 9605425fb15SMikko Perttunen reset-names = "i2c"; 9615425fb15SMikko Perttunen status = "disabled"; 9625425fb15SMikko Perttunen }; 9635425fb15SMikko Perttunen 9645425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 965d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9665425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 9675425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 9685425fb15SMikko Perttunen #address-cells = <1>; 9695425fb15SMikko Perttunen #size-cells = <0>; 9705425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 9715425fb15SMikko Perttunen clock-names = "div-clk"; 9725425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 9735425fb15SMikko Perttunen reset-names = "i2c"; 9745425fb15SMikko Perttunen status = "disabled"; 9755425fb15SMikko Perttunen }; 9765425fb15SMikko Perttunen 9775425fb15SMikko Perttunen uartc: serial@c280000 { 9785425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9795425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 9805425fb15SMikko Perttunen reg-shift = <2>; 9815425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 9825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 9835425fb15SMikko Perttunen clock-names = "serial"; 9845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 9855425fb15SMikko Perttunen reset-names = "serial"; 9865425fb15SMikko Perttunen status = "disabled"; 9875425fb15SMikko Perttunen }; 9885425fb15SMikko Perttunen 9895425fb15SMikko Perttunen uartg: serial@c290000 { 9905425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9915425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 9925425fb15SMikko Perttunen reg-shift = <2>; 9935425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 9945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 9955425fb15SMikko Perttunen clock-names = "serial"; 9965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 9975425fb15SMikko Perttunen reset-names = "serial"; 9985425fb15SMikko Perttunen status = "disabled"; 9995425fb15SMikko Perttunen }; 10005425fb15SMikko Perttunen 100137e5a31dSThierry Reding rtc: rtc@c2a0000 { 100237e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 100337e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 100437e5a31dSThierry Reding interrupt-parent = <&pmc>; 100537e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 100637e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 100737e5a31dSThierry Reding clock-names = "rtc"; 100837e5a31dSThierry Reding status = "disabled"; 100937e5a31dSThierry Reding }; 101037e5a31dSThierry Reding 10114d286331SThierry Reding gpio_aon: gpio@c2f0000 { 10124d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 10134d286331SThierry Reding reg-names = "security", "gpio"; 10144d286331SThierry Reding reg = <0xc2f0000 0x1000>, 10154d286331SThierry Reding <0xc2f1000 0x1000>; 101675b5608aSThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 10174d286331SThierry Reding gpio-controller; 10184d286331SThierry Reding #gpio-cells = <2>; 10194d286331SThierry Reding interrupt-controller; 10204d286331SThierry Reding #interrupt-cells = <2>; 10214d286331SThierry Reding }; 10224d286331SThierry Reding 10236a574ec7SThierry Reding pwm4: pwm@c340000 { 10246a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10256a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10266a574ec7SThierry Reding reg = <0xc340000 0x10000>; 10276a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 10286a574ec7SThierry Reding clock-names = "pwm"; 10296a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 10306a574ec7SThierry Reding reset-names = "pwm"; 10316a574ec7SThierry Reding status = "disabled"; 10326a574ec7SThierry Reding #pwm-cells = <2>; 10336a574ec7SThierry Reding }; 10346a574ec7SThierry Reding 103538ecf1e5SThierry Reding pmc: pmc@c360000 { 10365425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 10375425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 10385425fb15SMikko Perttunen <0x0c370000 0x10000>, 10395425fb15SMikko Perttunen <0x0c380000 0x10000>, 10405425fb15SMikko Perttunen <0x0c390000 0x10000>, 10415425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 10425425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 104338ecf1e5SThierry Reding 104438ecf1e5SThierry Reding #interrupt-cells = <2>; 104538ecf1e5SThierry Reding interrupt-controller; 10465425fb15SMikko Perttunen }; 10473db6d3baSThierry Reding 10483db6d3baSThierry Reding host1x@13e00000 { 1049ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 10503db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 10513db6d3baSThierry Reding <0x13e10000 0x10000>; 10523db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 10533db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 10543db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1055052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 10563db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 10573db6d3baSThierry Reding clock-names = "host1x"; 10583db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 10593db6d3baSThierry Reding reset-names = "host1x"; 10603db6d3baSThierry Reding 10613db6d3baSThierry Reding #address-cells = <1>; 10623db6d3baSThierry Reding #size-cells = <1>; 10633db6d3baSThierry Reding 10643db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1065d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1066d5237c7cSThierry Reding interconnect-names = "dma-mem"; 10673db6d3baSThierry Reding 10683db6d3baSThierry Reding display-hub@15200000 { 1069aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1070611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 10713db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 10723db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 10733db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 10743db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 10753db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 10763db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 10773db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 10783db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 10793db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 10803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 10813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 10823db6d3baSThierry Reding clock-names = "disp", "hub"; 10833db6d3baSThierry Reding status = "disabled"; 10843db6d3baSThierry Reding 10853db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10863db6d3baSThierry Reding 10873db6d3baSThierry Reding #address-cells = <1>; 10883db6d3baSThierry Reding #size-cells = <1>; 10893db6d3baSThierry Reding 10903db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 10913db6d3baSThierry Reding 10923db6d3baSThierry Reding display@15200000 { 10933db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 10943db6d3baSThierry Reding reg = <0x15200000 0x10000>; 10953db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 10963db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 10973db6d3baSThierry Reding clock-names = "dc"; 10983db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 10993db6d3baSThierry Reding reset-names = "dc"; 11003db6d3baSThierry Reding 11013db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1102d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1103d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1104d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11053db6d3baSThierry Reding 11063db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11073db6d3baSThierry Reding nvidia,head = <0>; 11083db6d3baSThierry Reding }; 11093db6d3baSThierry Reding 11103db6d3baSThierry Reding display@15210000 { 11113db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11123db6d3baSThierry Reding reg = <0x15210000 0x10000>; 11133db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 11143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 11153db6d3baSThierry Reding clock-names = "dc"; 11163db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 11173db6d3baSThierry Reding reset-names = "dc"; 11183db6d3baSThierry Reding 11193db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1120d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1121d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1122d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11233db6d3baSThierry Reding 11243db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11253db6d3baSThierry Reding nvidia,head = <1>; 11263db6d3baSThierry Reding }; 11273db6d3baSThierry Reding 11283db6d3baSThierry Reding display@15220000 { 11293db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11303db6d3baSThierry Reding reg = <0x15220000 0x10000>; 11313db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 11323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 11333db6d3baSThierry Reding clock-names = "dc"; 11343db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 11353db6d3baSThierry Reding reset-names = "dc"; 11363db6d3baSThierry Reding 11373db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1138d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1139d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1140d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11413db6d3baSThierry Reding 11423db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11433db6d3baSThierry Reding nvidia,head = <2>; 11443db6d3baSThierry Reding }; 11453db6d3baSThierry Reding 11463db6d3baSThierry Reding display@15230000 { 11473db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11483db6d3baSThierry Reding reg = <0x15230000 0x10000>; 11493db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 11503db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 11513db6d3baSThierry Reding clock-names = "dc"; 11523db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 11533db6d3baSThierry Reding reset-names = "dc"; 11543db6d3baSThierry Reding 11553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1156d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1157d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1158d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 11593db6d3baSThierry Reding 11603db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11613db6d3baSThierry Reding nvidia,head = <3>; 11623db6d3baSThierry Reding }; 11633db6d3baSThierry Reding }; 11643db6d3baSThierry Reding 11658d424ec2SThierry Reding vic@15340000 { 11668d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 11678d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 11688d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 11698d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 11708d424ec2SThierry Reding clock-names = "vic"; 11718d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 11728d424ec2SThierry Reding reset-names = "vic"; 11738d424ec2SThierry Reding 11748d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1175d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1176d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1177d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 11788d424ec2SThierry Reding }; 11798d424ec2SThierry Reding 11803db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 11813db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 11823db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 11833db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 11843db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 11853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 11863db6d3baSThierry Reding clock-names = "dpaux", "parent"; 11873db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 11883db6d3baSThierry Reding reset-names = "dpaux"; 11893db6d3baSThierry Reding status = "disabled"; 11903db6d3baSThierry Reding 11913db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11923db6d3baSThierry Reding 11933db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 11943db6d3baSThierry Reding groups = "dpaux-io"; 11953db6d3baSThierry Reding function = "aux"; 11963db6d3baSThierry Reding }; 11973db6d3baSThierry Reding 11983db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 11993db6d3baSThierry Reding groups = "dpaux-io"; 12003db6d3baSThierry Reding function = "i2c"; 12013db6d3baSThierry Reding }; 12023db6d3baSThierry Reding 12033db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 12043db6d3baSThierry Reding groups = "dpaux-io"; 12053db6d3baSThierry Reding function = "off"; 12063db6d3baSThierry Reding }; 12073db6d3baSThierry Reding 12083db6d3baSThierry Reding i2c-bus { 12093db6d3baSThierry Reding #address-cells = <1>; 12103db6d3baSThierry Reding #size-cells = <0>; 12113db6d3baSThierry Reding }; 12123db6d3baSThierry Reding }; 12133db6d3baSThierry Reding 12143db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 12153db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12163db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 12173db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 12183db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 12193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12203db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12213db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 12223db6d3baSThierry Reding reset-names = "dpaux"; 12233db6d3baSThierry Reding status = "disabled"; 12243db6d3baSThierry Reding 12253db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12263db6d3baSThierry Reding 12273db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 12283db6d3baSThierry Reding groups = "dpaux-io"; 12293db6d3baSThierry Reding function = "aux"; 12303db6d3baSThierry Reding }; 12313db6d3baSThierry Reding 12323db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 12333db6d3baSThierry Reding groups = "dpaux-io"; 12343db6d3baSThierry Reding function = "i2c"; 12353db6d3baSThierry Reding }; 12363db6d3baSThierry Reding 12373db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 12383db6d3baSThierry Reding groups = "dpaux-io"; 12393db6d3baSThierry Reding function = "off"; 12403db6d3baSThierry Reding }; 12413db6d3baSThierry Reding 12423db6d3baSThierry Reding i2c-bus { 12433db6d3baSThierry Reding #address-cells = <1>; 12443db6d3baSThierry Reding #size-cells = <0>; 12453db6d3baSThierry Reding }; 12463db6d3baSThierry Reding }; 12473db6d3baSThierry Reding 12483db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 12493db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12503db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 12513db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 12523db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 12533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12543db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12553db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 12563db6d3baSThierry Reding reset-names = "dpaux"; 12573db6d3baSThierry Reding status = "disabled"; 12583db6d3baSThierry Reding 12593db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12603db6d3baSThierry Reding 12613db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 12623db6d3baSThierry Reding groups = "dpaux-io"; 12633db6d3baSThierry Reding function = "aux"; 12643db6d3baSThierry Reding }; 12653db6d3baSThierry Reding 12663db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 12673db6d3baSThierry Reding groups = "dpaux-io"; 12683db6d3baSThierry Reding function = "i2c"; 12693db6d3baSThierry Reding }; 12703db6d3baSThierry Reding 12713db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 12723db6d3baSThierry Reding groups = "dpaux-io"; 12733db6d3baSThierry Reding function = "off"; 12743db6d3baSThierry Reding }; 12753db6d3baSThierry Reding 12763db6d3baSThierry Reding i2c-bus { 12773db6d3baSThierry Reding #address-cells = <1>; 12783db6d3baSThierry Reding #size-cells = <0>; 12793db6d3baSThierry Reding }; 12803db6d3baSThierry Reding }; 12813db6d3baSThierry Reding 12823db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 12833db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12843db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 12853db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 12863db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 12873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12883db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12893db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 12903db6d3baSThierry Reding reset-names = "dpaux"; 12913db6d3baSThierry Reding status = "disabled"; 12923db6d3baSThierry Reding 12933db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12943db6d3baSThierry Reding 12953db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 12963db6d3baSThierry Reding groups = "dpaux-io"; 12973db6d3baSThierry Reding function = "aux"; 12983db6d3baSThierry Reding }; 12993db6d3baSThierry Reding 13003db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 13013db6d3baSThierry Reding groups = "dpaux-io"; 13023db6d3baSThierry Reding function = "i2c"; 13033db6d3baSThierry Reding }; 13043db6d3baSThierry Reding 13053db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 13063db6d3baSThierry Reding groups = "dpaux-io"; 13073db6d3baSThierry Reding function = "off"; 13083db6d3baSThierry Reding }; 13093db6d3baSThierry Reding 13103db6d3baSThierry Reding i2c-bus { 13113db6d3baSThierry Reding #address-cells = <1>; 13123db6d3baSThierry Reding #size-cells = <0>; 13133db6d3baSThierry Reding }; 13143db6d3baSThierry Reding }; 13153db6d3baSThierry Reding 13163db6d3baSThierry Reding sor0: sor@15b00000 { 13173db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13183db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 13193db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 13203db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 13213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 13223db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 13233db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13243db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 13263db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13273db6d3baSThierry Reding "pad"; 13283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 13293db6d3baSThierry Reding reset-names = "sor"; 13303db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 13313db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 13323db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 13333db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13343db6d3baSThierry Reding status = "disabled"; 13353db6d3baSThierry Reding 13363db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13373db6d3baSThierry Reding nvidia,interface = <0>; 13383db6d3baSThierry Reding }; 13393db6d3baSThierry Reding 13403db6d3baSThierry Reding sor1: sor@15b40000 { 13413db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1342939e7430SThierry Reding reg = <0x15b40000 0x40000>; 13433db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 13443db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 13453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 13463db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 13473db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13483db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 13503db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13513db6d3baSThierry Reding "pad"; 13523db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 13533db6d3baSThierry Reding reset-names = "sor"; 13543db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 13553db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 13563db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 13573db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13583db6d3baSThierry Reding status = "disabled"; 13593db6d3baSThierry Reding 13603db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13613db6d3baSThierry Reding nvidia,interface = <1>; 13623db6d3baSThierry Reding }; 13633db6d3baSThierry Reding 13643db6d3baSThierry Reding sor2: sor@15b80000 { 13653db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13663db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 13673db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 13683db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 13693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 13703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 13713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13733db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 13743db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13753db6d3baSThierry Reding "pad"; 13763db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 13773db6d3baSThierry Reding reset-names = "sor"; 13783db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 13793db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 13803db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 13813db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13823db6d3baSThierry Reding status = "disabled"; 13833db6d3baSThierry Reding 13843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13853db6d3baSThierry Reding nvidia,interface = <2>; 13863db6d3baSThierry Reding }; 13873db6d3baSThierry Reding 13883db6d3baSThierry Reding sor3: sor@15bc0000 { 13893db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13903db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 13913db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 13923db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 13933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 13943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 13953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13963db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13973db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 13983db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13993db6d3baSThierry Reding "pad"; 14003db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 14013db6d3baSThierry Reding reset-names = "sor"; 14023db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 14033db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 14043db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 14053db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 14063db6d3baSThierry Reding status = "disabled"; 14073db6d3baSThierry Reding 14083db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14093db6d3baSThierry Reding nvidia,interface = <3>; 14103db6d3baSThierry Reding }; 14113db6d3baSThierry Reding }; 14120f134e39SThierry Reding 14130f134e39SThierry Reding gpu@17000000 { 14140f134e39SThierry Reding compatible = "nvidia,gv11b"; 1415818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1416818ae79aSThierry Reding <0x18000000 0x1000000>; 14170f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 14180f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 14190f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 14200f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 14210f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 14220f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 14230f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 14240f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 14250f134e39SThierry Reding reset-names = "gpu"; 14260f134e39SThierry Reding dma-coherent; 14270f134e39SThierry Reding 14280f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 14290f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 14300f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 14310f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 14320f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 14330f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 14340f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 14350f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 14360f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 14370f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 14380f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 14390f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 14400f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 14410f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 14420f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 14430f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 14440f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 14450f134e39SThierry Reding }; 14465425fb15SMikko Perttunen }; 14475425fb15SMikko Perttunen 14482602c32fSVidya Sagar pcie@14100000 { 1449f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 14502602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1451644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1452644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1453644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1454644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14552602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14562602c32fSVidya Sagar 14572602c32fSVidya Sagar status = "disabled"; 14582602c32fSVidya Sagar 14592602c32fSVidya Sagar #address-cells = <3>; 14602602c32fSVidya Sagar #size-cells = <2>; 14612602c32fSVidya Sagar device_type = "pci"; 14622602c32fSVidya Sagar num-lanes = <1>; 14632602c32fSVidya Sagar num-viewport = <8>; 14642602c32fSVidya Sagar linux,pci-domain = <1>; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 14672602c32fSVidya Sagar clock-names = "core"; 14682602c32fSVidya Sagar 14692602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 14702602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 14712602c32fSVidya Sagar reset-names = "apb", "core"; 14722602c32fSVidya Sagar 14732602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14742602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14752602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14762602c32fSVidya Sagar 14772602c32fSVidya Sagar #interrupt-cells = <1>; 14782602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14792602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 14802602c32fSVidya Sagar 14812602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 14822602c32fSVidya Sagar 14832602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14842602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14852602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14862602c32fSVidya Sagar 14872602c32fSVidya Sagar bus-range = <0x0 0xff>; 1488d5237c7cSThierry Reding 14898a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 14908a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 14918a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1492d5237c7cSThierry Reding 1493d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1494d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1495d5237c7cSThierry Reding interconnect-names = "read", "write"; 14962602c32fSVidya Sagar }; 14972602c32fSVidya Sagar 14982602c32fSVidya Sagar pcie@14120000 { 1499f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15002602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1501644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1502644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1503644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1504644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15052602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15062602c32fSVidya Sagar 15072602c32fSVidya Sagar status = "disabled"; 15082602c32fSVidya Sagar 15092602c32fSVidya Sagar #address-cells = <3>; 15102602c32fSVidya Sagar #size-cells = <2>; 15112602c32fSVidya Sagar device_type = "pci"; 15122602c32fSVidya Sagar num-lanes = <1>; 15132602c32fSVidya Sagar num-viewport = <8>; 15142602c32fSVidya Sagar linux,pci-domain = <2>; 15152602c32fSVidya Sagar 15162602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 15172602c32fSVidya Sagar clock-names = "core"; 15182602c32fSVidya Sagar 15192602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 15202602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 15212602c32fSVidya Sagar reset-names = "apb", "core"; 15222602c32fSVidya Sagar 15232602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15242602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15252602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15262602c32fSVidya Sagar 15272602c32fSVidya Sagar #interrupt-cells = <1>; 15282602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15292602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 15302602c32fSVidya Sagar 15312602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 15322602c32fSVidya Sagar 15332602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15342602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15352602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15362602c32fSVidya Sagar 15372602c32fSVidya Sagar bus-range = <0x0 0xff>; 1538d5237c7cSThierry Reding 15398a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 15408a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 15418a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1542d5237c7cSThierry Reding 1543d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1544d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1545d5237c7cSThierry Reding interconnect-names = "read", "write"; 15462602c32fSVidya Sagar }; 15472602c32fSVidya Sagar 15482602c32fSVidya Sagar pcie@14140000 { 1549f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15502602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1551644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1552644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1553644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1554644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15552602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15562602c32fSVidya Sagar 15572602c32fSVidya Sagar status = "disabled"; 15582602c32fSVidya Sagar 15592602c32fSVidya Sagar #address-cells = <3>; 15602602c32fSVidya Sagar #size-cells = <2>; 15612602c32fSVidya Sagar device_type = "pci"; 15622602c32fSVidya Sagar num-lanes = <1>; 15632602c32fSVidya Sagar num-viewport = <8>; 15642602c32fSVidya Sagar linux,pci-domain = <3>; 15652602c32fSVidya Sagar 15662602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 15672602c32fSVidya Sagar clock-names = "core"; 15682602c32fSVidya Sagar 15692602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 15702602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 15712602c32fSVidya Sagar reset-names = "apb", "core"; 15722602c32fSVidya Sagar 15732602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15742602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15752602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15762602c32fSVidya Sagar 15772602c32fSVidya Sagar #interrupt-cells = <1>; 15782602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15792602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 15802602c32fSVidya Sagar 15812602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 15822602c32fSVidya Sagar 15832602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15842602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15852602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15862602c32fSVidya Sagar 15872602c32fSVidya Sagar bus-range = <0x0 0xff>; 1588d5237c7cSThierry Reding 15898a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 15908a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 15918a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1592d5237c7cSThierry Reding 1593d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1594d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1595d5237c7cSThierry Reding interconnect-names = "read", "write"; 15962602c32fSVidya Sagar }; 15972602c32fSVidya Sagar 15982602c32fSVidya Sagar pcie@14160000 { 1599f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 16002602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1601644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1602644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1603644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1604644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 16052602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16062602c32fSVidya Sagar 16072602c32fSVidya Sagar status = "disabled"; 16082602c32fSVidya Sagar 16092602c32fSVidya Sagar #address-cells = <3>; 16102602c32fSVidya Sagar #size-cells = <2>; 16112602c32fSVidya Sagar device_type = "pci"; 16122602c32fSVidya Sagar num-lanes = <4>; 16132602c32fSVidya Sagar num-viewport = <8>; 16142602c32fSVidya Sagar linux,pci-domain = <4>; 16152602c32fSVidya Sagar 16162602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 16172602c32fSVidya Sagar clock-names = "core"; 16182602c32fSVidya Sagar 16192602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 16202602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 16212602c32fSVidya Sagar reset-names = "apb", "core"; 16222602c32fSVidya Sagar 16232602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 16242602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 16252602c32fSVidya Sagar interrupt-names = "intr", "msi"; 16262602c32fSVidya Sagar 16272602c32fSVidya Sagar #interrupt-cells = <1>; 16282602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 16292602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 16302602c32fSVidya Sagar 16312602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 16322602c32fSVidya Sagar 16332602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 16342602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16352602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16362602c32fSVidya Sagar 16372602c32fSVidya Sagar bus-range = <0x0 0xff>; 1638d5237c7cSThierry Reding 16398a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 16408a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 16418a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1642d5237c7cSThierry Reding 1643d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1644d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1645d5237c7cSThierry Reding interconnect-names = "read", "write"; 16462602c32fSVidya Sagar }; 16472602c32fSVidya Sagar 16482602c32fSVidya Sagar pcie@14180000 { 1649f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 16502602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1651644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1652644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1653644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1654644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 16552602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16562602c32fSVidya Sagar 16572602c32fSVidya Sagar status = "disabled"; 16582602c32fSVidya Sagar 16592602c32fSVidya Sagar #address-cells = <3>; 16602602c32fSVidya Sagar #size-cells = <2>; 16612602c32fSVidya Sagar device_type = "pci"; 16622602c32fSVidya Sagar num-lanes = <8>; 16632602c32fSVidya Sagar num-viewport = <8>; 16642602c32fSVidya Sagar linux,pci-domain = <0>; 16652602c32fSVidya Sagar 16662602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 16672602c32fSVidya Sagar clock-names = "core"; 16682602c32fSVidya Sagar 16692602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 16702602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 16712602c32fSVidya Sagar reset-names = "apb", "core"; 16722602c32fSVidya Sagar 16732602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 16742602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 16752602c32fSVidya Sagar interrupt-names = "intr", "msi"; 16762602c32fSVidya Sagar 16772602c32fSVidya Sagar #interrupt-cells = <1>; 16782602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 16792602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 16802602c32fSVidya Sagar 16812602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 16822602c32fSVidya Sagar 16832602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 16842602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16852602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16862602c32fSVidya Sagar 16872602c32fSVidya Sagar bus-range = <0x0 0xff>; 1688d5237c7cSThierry Reding 16898a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 16908a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 16918a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1692d5237c7cSThierry Reding 1693d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1694d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1695d5237c7cSThierry Reding interconnect-names = "read", "write"; 16962602c32fSVidya Sagar }; 16972602c32fSVidya Sagar 16982602c32fSVidya Sagar pcie@141a0000 { 1699f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17002602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1701644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1702644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1703644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1704644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 17052602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 17062602c32fSVidya Sagar 17072602c32fSVidya Sagar status = "disabled"; 17082602c32fSVidya Sagar 17092602c32fSVidya Sagar #address-cells = <3>; 17102602c32fSVidya Sagar #size-cells = <2>; 17112602c32fSVidya Sagar device_type = "pci"; 17122602c32fSVidya Sagar num-lanes = <8>; 17132602c32fSVidya Sagar num-viewport = <8>; 17142602c32fSVidya Sagar linux,pci-domain = <5>; 17152602c32fSVidya Sagar 1716dbb72e2cSVidya Sagar pinctrl-names = "default"; 1717dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1718dbb72e2cSVidya Sagar 17192602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 17202602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 17212602c32fSVidya Sagar clock-names = "core", "core_m"; 17222602c32fSVidya Sagar 17232602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 17242602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 17252602c32fSVidya Sagar reset-names = "apb", "core"; 17262602c32fSVidya Sagar 17272602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17282602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17292602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17302602c32fSVidya Sagar 17312602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 17322602c32fSVidya Sagar 17332602c32fSVidya Sagar #interrupt-cells = <1>; 17342602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17352602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 17362602c32fSVidya Sagar 17372602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17382602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17392602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17402602c32fSVidya Sagar 17412602c32fSVidya Sagar bus-range = <0x0 0xff>; 1742d5237c7cSThierry Reding 17438a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 17448a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 17458a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1746d5237c7cSThierry Reding 1747d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1748d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1749d5237c7cSThierry Reding interconnect-names = "read", "write"; 17502602c32fSVidya Sagar }; 17512602c32fSVidya Sagar 17520c988b73SVidya Sagar pcie_ep@14160000 { 17530c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 17540c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1755644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1756644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1757644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1758644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 17590c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 17600c988b73SVidya Sagar 17610c988b73SVidya Sagar status = "disabled"; 17620c988b73SVidya Sagar 17630c988b73SVidya Sagar num-lanes = <4>; 17640c988b73SVidya Sagar num-ib-windows = <2>; 17650c988b73SVidya Sagar num-ob-windows = <8>; 17660c988b73SVidya Sagar 17670c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 17680c988b73SVidya Sagar clock-names = "core"; 17690c988b73SVidya Sagar 17700c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 17710c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 17720c988b73SVidya Sagar reset-names = "apb", "core"; 17730c988b73SVidya Sagar 17740c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 17750c988b73SVidya Sagar interrupt-names = "intr"; 17760c988b73SVidya Sagar 17770c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 17780c988b73SVidya Sagar 17790c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 17800c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17810c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17820c988b73SVidya Sagar }; 17830c988b73SVidya Sagar 17840c988b73SVidya Sagar pcie_ep@14180000 { 17850c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 17860c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1787644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1788644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1789644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1790644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 17910c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 17920c988b73SVidya Sagar 17930c988b73SVidya Sagar status = "disabled"; 17940c988b73SVidya Sagar 17950c988b73SVidya Sagar num-lanes = <8>; 17960c988b73SVidya Sagar num-ib-windows = <2>; 17970c988b73SVidya Sagar num-ob-windows = <8>; 17980c988b73SVidya Sagar 17990c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 18000c988b73SVidya Sagar clock-names = "core"; 18010c988b73SVidya Sagar 18020c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 18030c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 18040c988b73SVidya Sagar reset-names = "apb", "core"; 18050c988b73SVidya Sagar 18060c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 18070c988b73SVidya Sagar interrupt-names = "intr"; 18080c988b73SVidya Sagar 18090c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 18100c988b73SVidya Sagar 18110c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 18120c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18130c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18140c988b73SVidya Sagar }; 18150c988b73SVidya Sagar 18160c988b73SVidya Sagar pcie_ep@141a0000 { 18170c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 18180c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1819644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1820644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1821644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1822644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 18230c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 18240c988b73SVidya Sagar 18250c988b73SVidya Sagar status = "disabled"; 18260c988b73SVidya Sagar 18270c988b73SVidya Sagar num-lanes = <8>; 18280c988b73SVidya Sagar num-ib-windows = <2>; 18290c988b73SVidya Sagar num-ob-windows = <8>; 18300c988b73SVidya Sagar 18310c988b73SVidya Sagar pinctrl-names = "default"; 18320c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 18330c988b73SVidya Sagar 18340c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 18350c988b73SVidya Sagar clock-names = "core"; 18360c988b73SVidya Sagar 18370c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 18380c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 18390c988b73SVidya Sagar reset-names = "apb", "core"; 18400c988b73SVidya Sagar 18410c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 18420c988b73SVidya Sagar interrupt-names = "intr"; 18430c988b73SVidya Sagar 18440c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 18450c988b73SVidya Sagar 18460c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 18470c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18480c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18490c988b73SVidya Sagar }; 18500c988b73SVidya Sagar 1851e867fe41SThierry Reding sram@40000000 { 18525425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 18535425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 18545425fb15SMikko Perttunen #address-cells = <1>; 18555425fb15SMikko Perttunen #size-cells = <1>; 18565425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 18575425fb15SMikko Perttunen 1858e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 18595425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 18605425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 18615425fb15SMikko Perttunen pool; 18625425fb15SMikko Perttunen }; 18635425fb15SMikko Perttunen 1864e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 18655425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 18665425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 18675425fb15SMikko Perttunen pool; 18685425fb15SMikko Perttunen }; 18695425fb15SMikko Perttunen }; 18705425fb15SMikko Perttunen 18715425fb15SMikko Perttunen bpmp: bpmp { 18725425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 18735425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 18745425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 18755425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 18765425fb15SMikko Perttunen #clock-cells = <1>; 18775425fb15SMikko Perttunen #reset-cells = <1>; 18785425fb15SMikko Perttunen #power-domain-cells = <1>; 1879d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 1880d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 1881d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 1882d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 1883d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 18845425fb15SMikko Perttunen 18855425fb15SMikko Perttunen bpmp_i2c: i2c { 18865425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 18875425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 18885425fb15SMikko Perttunen #address-cells = <1>; 18895425fb15SMikko Perttunen #size-cells = <0>; 18905425fb15SMikko Perttunen }; 18915425fb15SMikko Perttunen 18925425fb15SMikko Perttunen bpmp_thermal: thermal { 18935425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 18945425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 18955425fb15SMikko Perttunen }; 18965425fb15SMikko Perttunen }; 18975425fb15SMikko Perttunen 18987780a034SMikko Perttunen cpus { 1899d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 1900d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 19017780a034SMikko Perttunen #address-cells = <1>; 19027780a034SMikko Perttunen #size-cells = <0>; 19037780a034SMikko Perttunen 1904b45d322cSThierry Reding cpu0_0: cpu@0 { 190531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19067780a034SMikko Perttunen device_type = "cpu"; 1907b45d322cSThierry Reding reg = <0x000>; 19087780a034SMikko Perttunen enable-method = "psci"; 1909b45d322cSThierry Reding i-cache-size = <131072>; 1910b45d322cSThierry Reding i-cache-line-size = <64>; 1911b45d322cSThierry Reding i-cache-sets = <512>; 1912b45d322cSThierry Reding d-cache-size = <65536>; 1913b45d322cSThierry Reding d-cache-line-size = <64>; 1914b45d322cSThierry Reding d-cache-sets = <256>; 1915b45d322cSThierry Reding next-level-cache = <&l2c_0>; 19167780a034SMikko Perttunen }; 19177780a034SMikko Perttunen 1918b45d322cSThierry Reding cpu0_1: cpu@1 { 191931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19207780a034SMikko Perttunen device_type = "cpu"; 1921b45d322cSThierry Reding reg = <0x001>; 19227780a034SMikko Perttunen enable-method = "psci"; 1923b45d322cSThierry Reding i-cache-size = <131072>; 1924b45d322cSThierry Reding i-cache-line-size = <64>; 1925b45d322cSThierry Reding i-cache-sets = <512>; 1926b45d322cSThierry Reding d-cache-size = <65536>; 1927b45d322cSThierry Reding d-cache-line-size = <64>; 1928b45d322cSThierry Reding d-cache-sets = <256>; 1929b45d322cSThierry Reding next-level-cache = <&l2c_0>; 19307780a034SMikko Perttunen }; 19317780a034SMikko Perttunen 1932b45d322cSThierry Reding cpu1_0: cpu@100 { 193331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19347780a034SMikko Perttunen device_type = "cpu"; 19357780a034SMikko Perttunen reg = <0x100>; 19367780a034SMikko Perttunen enable-method = "psci"; 1937b45d322cSThierry Reding i-cache-size = <131072>; 1938b45d322cSThierry Reding i-cache-line-size = <64>; 1939b45d322cSThierry Reding i-cache-sets = <512>; 1940b45d322cSThierry Reding d-cache-size = <65536>; 1941b45d322cSThierry Reding d-cache-line-size = <64>; 1942b45d322cSThierry Reding d-cache-sets = <256>; 1943b45d322cSThierry Reding next-level-cache = <&l2c_1>; 19447780a034SMikko Perttunen }; 19457780a034SMikko Perttunen 1946b45d322cSThierry Reding cpu1_1: cpu@101 { 194731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19487780a034SMikko Perttunen device_type = "cpu"; 19497780a034SMikko Perttunen reg = <0x101>; 19507780a034SMikko Perttunen enable-method = "psci"; 1951b45d322cSThierry Reding i-cache-size = <131072>; 1952b45d322cSThierry Reding i-cache-line-size = <64>; 1953b45d322cSThierry Reding i-cache-sets = <512>; 1954b45d322cSThierry Reding d-cache-size = <65536>; 1955b45d322cSThierry Reding d-cache-line-size = <64>; 1956b45d322cSThierry Reding d-cache-sets = <256>; 1957b45d322cSThierry Reding next-level-cache = <&l2c_1>; 19587780a034SMikko Perttunen }; 19597780a034SMikko Perttunen 1960b45d322cSThierry Reding cpu2_0: cpu@200 { 196131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19627780a034SMikko Perttunen device_type = "cpu"; 19637780a034SMikko Perttunen reg = <0x200>; 19647780a034SMikko Perttunen enable-method = "psci"; 1965b45d322cSThierry Reding i-cache-size = <131072>; 1966b45d322cSThierry Reding i-cache-line-size = <64>; 1967b45d322cSThierry Reding i-cache-sets = <512>; 1968b45d322cSThierry Reding d-cache-size = <65536>; 1969b45d322cSThierry Reding d-cache-line-size = <64>; 1970b45d322cSThierry Reding d-cache-sets = <256>; 1971b45d322cSThierry Reding next-level-cache = <&l2c_2>; 19727780a034SMikko Perttunen }; 19737780a034SMikko Perttunen 1974b45d322cSThierry Reding cpu2_1: cpu@201 { 197531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19767780a034SMikko Perttunen device_type = "cpu"; 19777780a034SMikko Perttunen reg = <0x201>; 19787780a034SMikko Perttunen enable-method = "psci"; 1979b45d322cSThierry Reding i-cache-size = <131072>; 1980b45d322cSThierry Reding i-cache-line-size = <64>; 1981b45d322cSThierry Reding i-cache-sets = <512>; 1982b45d322cSThierry Reding d-cache-size = <65536>; 1983b45d322cSThierry Reding d-cache-line-size = <64>; 1984b45d322cSThierry Reding d-cache-sets = <256>; 1985b45d322cSThierry Reding next-level-cache = <&l2c_2>; 19867780a034SMikko Perttunen }; 19877780a034SMikko Perttunen 1988b45d322cSThierry Reding cpu3_0: cpu@300 { 198931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 19907780a034SMikko Perttunen device_type = "cpu"; 1991b45d322cSThierry Reding reg = <0x300>; 19927780a034SMikko Perttunen enable-method = "psci"; 1993b45d322cSThierry Reding i-cache-size = <131072>; 1994b45d322cSThierry Reding i-cache-line-size = <64>; 1995b45d322cSThierry Reding i-cache-sets = <512>; 1996b45d322cSThierry Reding d-cache-size = <65536>; 1997b45d322cSThierry Reding d-cache-line-size = <64>; 1998b45d322cSThierry Reding d-cache-sets = <256>; 1999b45d322cSThierry Reding next-level-cache = <&l2c_3>; 20007780a034SMikko Perttunen }; 20017780a034SMikko Perttunen 2002b45d322cSThierry Reding cpu3_1: cpu@301 { 200331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 20047780a034SMikko Perttunen device_type = "cpu"; 2005b45d322cSThierry Reding reg = <0x301>; 20067780a034SMikko Perttunen enable-method = "psci"; 2007b45d322cSThierry Reding i-cache-size = <131072>; 2008b45d322cSThierry Reding i-cache-line-size = <64>; 2009b45d322cSThierry Reding i-cache-sets = <512>; 2010b45d322cSThierry Reding d-cache-size = <65536>; 2011b45d322cSThierry Reding d-cache-line-size = <64>; 2012b45d322cSThierry Reding d-cache-sets = <256>; 2013b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2014b45d322cSThierry Reding }; 2015b45d322cSThierry Reding 2016b45d322cSThierry Reding cpu-map { 2017b45d322cSThierry Reding cluster0 { 2018b45d322cSThierry Reding core0 { 2019b45d322cSThierry Reding cpu = <&cpu0_0>; 2020b45d322cSThierry Reding }; 2021b45d322cSThierry Reding 2022b45d322cSThierry Reding core1 { 2023b45d322cSThierry Reding cpu = <&cpu0_1>; 2024b45d322cSThierry Reding }; 2025b45d322cSThierry Reding }; 2026b45d322cSThierry Reding 2027b45d322cSThierry Reding cluster1 { 2028b45d322cSThierry Reding core0 { 2029b45d322cSThierry Reding cpu = <&cpu1_0>; 2030b45d322cSThierry Reding }; 2031b45d322cSThierry Reding 2032b45d322cSThierry Reding core1 { 2033b45d322cSThierry Reding cpu = <&cpu1_1>; 2034b45d322cSThierry Reding }; 2035b45d322cSThierry Reding }; 2036b45d322cSThierry Reding 2037b45d322cSThierry Reding cluster2 { 2038b45d322cSThierry Reding core0 { 2039b45d322cSThierry Reding cpu = <&cpu2_0>; 2040b45d322cSThierry Reding }; 2041b45d322cSThierry Reding 2042b45d322cSThierry Reding core1 { 2043b45d322cSThierry Reding cpu = <&cpu2_1>; 2044b45d322cSThierry Reding }; 2045b45d322cSThierry Reding }; 2046b45d322cSThierry Reding 2047b45d322cSThierry Reding cluster3 { 2048b45d322cSThierry Reding core0 { 2049b45d322cSThierry Reding cpu = <&cpu3_0>; 2050b45d322cSThierry Reding }; 2051b45d322cSThierry Reding 2052b45d322cSThierry Reding core1 { 2053b45d322cSThierry Reding cpu = <&cpu3_1>; 2054b45d322cSThierry Reding }; 2055b45d322cSThierry Reding }; 2056b45d322cSThierry Reding }; 2057b45d322cSThierry Reding 2058b45d322cSThierry Reding l2c_0: l2-cache0 { 2059b45d322cSThierry Reding cache-size = <2097152>; 2060b45d322cSThierry Reding cache-line-size = <64>; 2061b45d322cSThierry Reding cache-sets = <2048>; 2062b45d322cSThierry Reding next-level-cache = <&l3c>; 2063b45d322cSThierry Reding }; 2064b45d322cSThierry Reding 2065b45d322cSThierry Reding l2c_1: l2-cache1 { 2066b45d322cSThierry Reding cache-size = <2097152>; 2067b45d322cSThierry Reding cache-line-size = <64>; 2068b45d322cSThierry Reding cache-sets = <2048>; 2069b45d322cSThierry Reding next-level-cache = <&l3c>; 2070b45d322cSThierry Reding }; 2071b45d322cSThierry Reding 2072b45d322cSThierry Reding l2c_2: l2-cache2 { 2073b45d322cSThierry Reding cache-size = <2097152>; 2074b45d322cSThierry Reding cache-line-size = <64>; 2075b45d322cSThierry Reding cache-sets = <2048>; 2076b45d322cSThierry Reding next-level-cache = <&l3c>; 2077b45d322cSThierry Reding }; 2078b45d322cSThierry Reding 2079b45d322cSThierry Reding l2c_3: l2-cache3 { 2080b45d322cSThierry Reding cache-size = <2097152>; 2081b45d322cSThierry Reding cache-line-size = <64>; 2082b45d322cSThierry Reding cache-sets = <2048>; 2083b45d322cSThierry Reding next-level-cache = <&l3c>; 2084b45d322cSThierry Reding }; 2085b45d322cSThierry Reding 2086b45d322cSThierry Reding l3c: l3-cache { 2087b45d322cSThierry Reding cache-size = <4194304>; 2088b45d322cSThierry Reding cache-line-size = <64>; 2089b45d322cSThierry Reding cache-sets = <4096>; 20907780a034SMikko Perttunen }; 20917780a034SMikko Perttunen }; 20927780a034SMikko Perttunen 20937780a034SMikko Perttunen psci { 20947780a034SMikko Perttunen compatible = "arm,psci-1.0"; 20957780a034SMikko Perttunen status = "okay"; 20967780a034SMikko Perttunen method = "smc"; 20977780a034SMikko Perttunen }; 20987780a034SMikko Perttunen 2099a38570c2SMikko Perttunen tcu: tcu { 2100a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2101a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2102a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2103a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2104a38570c2SMikko Perttunen }; 2105a38570c2SMikko Perttunen 2106686ba009SThierry Reding thermal-zones { 2107686ba009SThierry Reding cpu { 2108686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2109686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2110686ba009SThierry Reding status = "disabled"; 2111686ba009SThierry Reding }; 2112686ba009SThierry Reding 2113686ba009SThierry Reding gpu { 2114686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2115686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2116686ba009SThierry Reding status = "disabled"; 2117686ba009SThierry Reding }; 2118686ba009SThierry Reding 2119686ba009SThierry Reding aux { 2120686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2121686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2122686ba009SThierry Reding status = "disabled"; 2123686ba009SThierry Reding }; 2124686ba009SThierry Reding 2125686ba009SThierry Reding pllx { 2126686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2127686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2128686ba009SThierry Reding status = "disabled"; 2129686ba009SThierry Reding }; 2130686ba009SThierry Reding 2131686ba009SThierry Reding ao { 2132686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2133686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2134686ba009SThierry Reding status = "disabled"; 2135686ba009SThierry Reding }; 2136686ba009SThierry Reding 2137686ba009SThierry Reding tj { 2138686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2139686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2140686ba009SThierry Reding status = "disabled"; 2141686ba009SThierry Reding }; 2142686ba009SThierry Reding }; 2143686ba009SThierry Reding 21445425fb15SMikko Perttunen timer { 21455425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 21465425fb15SMikko Perttunen interrupts = <GIC_PPI 13 21475425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21485425fb15SMikko Perttunen <GIC_PPI 14 21495425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21505425fb15SMikko Perttunen <GIC_PPI 11 21515425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 21525425fb15SMikko Perttunen <GIC_PPI 10 21535425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 21545425fb15SMikko Perttunen interrupt-parent = <&gic>; 2155b30be673SThierry Reding always-on; 21565425fb15SMikko Perttunen }; 21575425fb15SMikko Perttunen}; 2158