15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 2609903c5eSJC Kuo misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89f69ce393SMikko Perttunen }; 90f69ce393SMikko Perttunen 91f89b58ceSMikko Perttunen ethernet@2490000 { 9219dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9319dc772aSThierry Reding "nvidia,tegra186-eqos", 94f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 95f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 96f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 101f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 104f89b58ceSMikko Perttunen reset-names = "eqos"; 105d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 108c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 109f89b58ceSMikko Perttunen status = "disabled"; 110f89b58ceSMikko Perttunen 111f89b58ceSMikko Perttunen snps,write-requests = <1>; 112f89b58ceSMikko Perttunen snps,read-requests = <3>; 113f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 114f89b58ceSMikko Perttunen snps,txpbl = <16>; 115f89b58ceSMikko Perttunen snps,rxpbl = <8>; 116f89b58ceSMikko Perttunen }; 117f89b58ceSMikko Perttunen 118835553b3SAkhil R gpcdma: dma-controller@2600000 { 119835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 120835553b3SAkhil R "nvidia,tegra186-gpcdma"; 121835553b3SAkhil R reg = <0x2600000 0x210000>; 122835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123835553b3SAkhil R reset-names = "gpcdma"; 124835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155835553b3SAkhil R #dma-cells = <1>; 156835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157835553b3SAkhil R dma-coherent; 158835553b3SAkhil R status = "okay"; 159835553b3SAkhil R }; 160835553b3SAkhil R 1611aaa7698SThierry Reding aconnect@2900000 { 1625d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1635d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1645d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1655d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1665d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1675d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1685d2249ddSSameer Pujar #address-cells = <1>; 1695d2249ddSSameer Pujar #size-cells = <1>; 1705d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1715d2249ddSSameer Pujar status = "disabled"; 1725d2249ddSSameer Pujar 173177208f7SSameer Pujar adma: dma-controller@2930000 { 1745d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1755d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1765d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1775d2249ddSSameer Pujar interrupt-parent = <&agic>; 1785d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1795d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1805d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1815d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1825d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1835d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1845d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1855d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1865d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1875d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1885d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1895d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1905d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1915d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1925d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1935d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1945d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1955d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1965d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1975d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1985d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1995d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2005d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2015d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2025d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2105d2249ddSSameer Pujar #dma-cells = <1>; 2115d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2125d2249ddSSameer Pujar clock-names = "d_audio"; 2135d2249ddSSameer Pujar status = "disabled"; 2145d2249ddSSameer Pujar }; 2155d2249ddSSameer Pujar 2165d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2175d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2185d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2195d2249ddSSameer Pujar #interrupt-cells = <3>; 2205d2249ddSSameer Pujar interrupt-controller; 2215d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2225d2249ddSSameer Pujar <0x02a42000 0x2000>; 2235d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2245d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2255d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2265d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2275d2249ddSSameer Pujar clock-names = "clk"; 2285d2249ddSSameer Pujar status = "disabled"; 2295d2249ddSSameer Pujar }; 230177208f7SSameer Pujar 231177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 232177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 233177208f7SSameer Pujar "nvidia,tegra186-ahub"; 234177208f7SSameer Pujar reg = <0x02900800 0x800>; 235177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 236177208f7SSameer Pujar clock-names = "ahub"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239177208f7SSameer Pujar #address-cells = <1>; 240177208f7SSameer Pujar #size-cells = <1>; 241177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 242177208f7SSameer Pujar status = "disabled"; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 246177208f7SSameer Pujar "nvidia,tegra186-admaif"; 247177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 248177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 249177208f7SSameer Pujar <&adma 2>, <&adma 2>, 250177208f7SSameer Pujar <&adma 3>, <&adma 3>, 251177208f7SSameer Pujar <&adma 4>, <&adma 4>, 252177208f7SSameer Pujar <&adma 5>, <&adma 5>, 253177208f7SSameer Pujar <&adma 6>, <&adma 6>, 254177208f7SSameer Pujar <&adma 7>, <&adma 7>, 255177208f7SSameer Pujar <&adma 8>, <&adma 8>, 256177208f7SSameer Pujar <&adma 9>, <&adma 9>, 257177208f7SSameer Pujar <&adma 10>, <&adma 10>, 258177208f7SSameer Pujar <&adma 11>, <&adma 11>, 259177208f7SSameer Pujar <&adma 12>, <&adma 12>, 260177208f7SSameer Pujar <&adma 13>, <&adma 13>, 261177208f7SSameer Pujar <&adma 14>, <&adma 14>, 262177208f7SSameer Pujar <&adma 15>, <&adma 15>, 263177208f7SSameer Pujar <&adma 16>, <&adma 16>, 264177208f7SSameer Pujar <&adma 17>, <&adma 17>, 265177208f7SSameer Pujar <&adma 18>, <&adma 18>, 266177208f7SSameer Pujar <&adma 19>, <&adma 19>, 267177208f7SSameer Pujar <&adma 20>, <&adma 20>; 268177208f7SSameer Pujar dma-names = "rx1", "tx1", 269177208f7SSameer Pujar "rx2", "tx2", 270177208f7SSameer Pujar "rx3", "tx3", 271177208f7SSameer Pujar "rx4", "tx4", 272177208f7SSameer Pujar "rx5", "tx5", 273177208f7SSameer Pujar "rx6", "tx6", 274177208f7SSameer Pujar "rx7", "tx7", 275177208f7SSameer Pujar "rx8", "tx8", 276177208f7SSameer Pujar "rx9", "tx9", 277177208f7SSameer Pujar "rx10", "tx10", 278177208f7SSameer Pujar "rx11", "tx11", 279177208f7SSameer Pujar "rx12", "tx12", 280177208f7SSameer Pujar "rx13", "tx13", 281177208f7SSameer Pujar "rx14", "tx14", 282177208f7SSameer Pujar "rx15", "tx15", 283177208f7SSameer Pujar "rx16", "tx16", 284177208f7SSameer Pujar "rx17", "tx17", 285177208f7SSameer Pujar "rx18", "tx18", 286177208f7SSameer Pujar "rx19", "tx19", 287177208f7SSameer Pujar "rx20", "tx20"; 288177208f7SSameer Pujar status = "disabled"; 289cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 292cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 293177208f7SSameer Pujar }; 294177208f7SSameer Pujar 295177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 296177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 297177208f7SSameer Pujar "nvidia,tegra210-i2s"; 298177208f7SSameer Pujar reg = <0x2901000 0x100>; 299177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 300177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 302177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304177208f7SSameer Pujar assigned-clock-rates = <1536000>; 305177208f7SSameer Pujar sound-name-prefix = "I2S1"; 306177208f7SSameer Pujar status = "disabled"; 307177208f7SSameer Pujar }; 308177208f7SSameer Pujar 309177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 310177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 311177208f7SSameer Pujar "nvidia,tegra210-i2s"; 312177208f7SSameer Pujar reg = <0x2901100 0x100>; 313177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 314177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 316177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318177208f7SSameer Pujar assigned-clock-rates = <1536000>; 319177208f7SSameer Pujar sound-name-prefix = "I2S2"; 320177208f7SSameer Pujar status = "disabled"; 321177208f7SSameer Pujar }; 322177208f7SSameer Pujar 323177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 324177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 325177208f7SSameer Pujar "nvidia,tegra210-i2s"; 326177208f7SSameer Pujar reg = <0x2901200 0x100>; 327177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 328177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 330177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332177208f7SSameer Pujar assigned-clock-rates = <1536000>; 333177208f7SSameer Pujar sound-name-prefix = "I2S3"; 334177208f7SSameer Pujar status = "disabled"; 335177208f7SSameer Pujar }; 336177208f7SSameer Pujar 337177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 338177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 339177208f7SSameer Pujar "nvidia,tegra210-i2s"; 340177208f7SSameer Pujar reg = <0x2901300 0x100>; 341177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 342177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 344177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346177208f7SSameer Pujar assigned-clock-rates = <1536000>; 347177208f7SSameer Pujar sound-name-prefix = "I2S4"; 348177208f7SSameer Pujar status = "disabled"; 349177208f7SSameer Pujar }; 350177208f7SSameer Pujar 351177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 352177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 353177208f7SSameer Pujar "nvidia,tegra210-i2s"; 354177208f7SSameer Pujar reg = <0x2901400 0x100>; 355177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 356177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 358177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360177208f7SSameer Pujar assigned-clock-rates = <1536000>; 361177208f7SSameer Pujar sound-name-prefix = "I2S5"; 362177208f7SSameer Pujar status = "disabled"; 363177208f7SSameer Pujar }; 364177208f7SSameer Pujar 365177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 366177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 367177208f7SSameer Pujar "nvidia,tegra210-i2s"; 368177208f7SSameer Pujar reg = <0x2901500 0x100>; 369177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 370177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 372177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374177208f7SSameer Pujar assigned-clock-rates = <1536000>; 375177208f7SSameer Pujar sound-name-prefix = "I2S6"; 376177208f7SSameer Pujar status = "disabled"; 377177208f7SSameer Pujar }; 378177208f7SSameer Pujar 379177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 380177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 381177208f7SSameer Pujar "nvidia,tegra210-dmic"; 382177208f7SSameer Pujar reg = <0x2904000 0x100>; 383177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384177208f7SSameer Pujar clock-names = "dmic"; 385177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387177208f7SSameer Pujar assigned-clock-rates = <3072000>; 388177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 389177208f7SSameer Pujar status = "disabled"; 390177208f7SSameer Pujar }; 391177208f7SSameer Pujar 392177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 393177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 394177208f7SSameer Pujar "nvidia,tegra210-dmic"; 395177208f7SSameer Pujar reg = <0x2904100 0x100>; 396177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397177208f7SSameer Pujar clock-names = "dmic"; 398177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400177208f7SSameer Pujar assigned-clock-rates = <3072000>; 401177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 402177208f7SSameer Pujar status = "disabled"; 403177208f7SSameer Pujar }; 404177208f7SSameer Pujar 405177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 406177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 407177208f7SSameer Pujar "nvidia,tegra210-dmic"; 408177208f7SSameer Pujar reg = <0x2904200 0x100>; 409177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410177208f7SSameer Pujar clock-names = "dmic"; 411177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413177208f7SSameer Pujar assigned-clock-rates = <3072000>; 414177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 415177208f7SSameer Pujar status = "disabled"; 416177208f7SSameer Pujar }; 417177208f7SSameer Pujar 418177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 419177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 420177208f7SSameer Pujar "nvidia,tegra210-dmic"; 421177208f7SSameer Pujar reg = <0x2904300 0x100>; 422177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423177208f7SSameer Pujar clock-names = "dmic"; 424177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426177208f7SSameer Pujar assigned-clock-rates = <3072000>; 427177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 428177208f7SSameer Pujar status = "disabled"; 429177208f7SSameer Pujar }; 430177208f7SSameer Pujar 431177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 432177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 433177208f7SSameer Pujar "nvidia,tegra186-dspk"; 434177208f7SSameer Pujar reg = <0x2905000 0x100>; 435177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436177208f7SSameer Pujar clock-names = "dspk"; 437177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439177208f7SSameer Pujar assigned-clock-rates = <12288000>; 440177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 441177208f7SSameer Pujar status = "disabled"; 442177208f7SSameer Pujar }; 443177208f7SSameer Pujar 444177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 445177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 446177208f7SSameer Pujar "nvidia,tegra186-dspk"; 447177208f7SSameer Pujar reg = <0x2905100 0x100>; 448177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449177208f7SSameer Pujar clock-names = "dspk"; 450177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452177208f7SSameer Pujar assigned-clock-rates = <12288000>; 453177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 454177208f7SSameer Pujar status = "disabled"; 455177208f7SSameer Pujar }; 456848f3290SSameer Pujar 457848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 458848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 459848f3290SSameer Pujar "nvidia,tegra210-sfc"; 460848f3290SSameer Pujar reg = <0x2902000 0x200>; 461848f3290SSameer Pujar sound-name-prefix = "SFC1"; 462848f3290SSameer Pujar status = "disabled"; 463848f3290SSameer Pujar }; 464848f3290SSameer Pujar 465848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 466848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 467848f3290SSameer Pujar "nvidia,tegra210-sfc"; 468848f3290SSameer Pujar reg = <0x2902200 0x200>; 469848f3290SSameer Pujar sound-name-prefix = "SFC2"; 470848f3290SSameer Pujar status = "disabled"; 471848f3290SSameer Pujar }; 472848f3290SSameer Pujar 473848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 474848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 475848f3290SSameer Pujar "nvidia,tegra210-sfc"; 476848f3290SSameer Pujar reg = <0x2902400 0x200>; 477848f3290SSameer Pujar sound-name-prefix = "SFC3"; 478848f3290SSameer Pujar status = "disabled"; 479848f3290SSameer Pujar }; 480848f3290SSameer Pujar 481848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 482848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 483848f3290SSameer Pujar "nvidia,tegra210-sfc"; 484848f3290SSameer Pujar reg = <0x2902600 0x200>; 485848f3290SSameer Pujar sound-name-prefix = "SFC4"; 486848f3290SSameer Pujar status = "disabled"; 487848f3290SSameer Pujar }; 488848f3290SSameer Pujar 489848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 490848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 491848f3290SSameer Pujar "nvidia,tegra210-mvc"; 492848f3290SSameer Pujar reg = <0x290a000 0x200>; 493848f3290SSameer Pujar sound-name-prefix = "MVC1"; 494848f3290SSameer Pujar status = "disabled"; 495848f3290SSameer Pujar }; 496848f3290SSameer Pujar 497848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 498848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 499848f3290SSameer Pujar "nvidia,tegra210-mvc"; 500848f3290SSameer Pujar reg = <0x290a200 0x200>; 501848f3290SSameer Pujar sound-name-prefix = "MVC2"; 502848f3290SSameer Pujar status = "disabled"; 503848f3290SSameer Pujar }; 504848f3290SSameer Pujar 505848f3290SSameer Pujar tegra_amx1: amx@2903000 { 506848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 507848f3290SSameer Pujar reg = <0x2903000 0x100>; 508848f3290SSameer Pujar sound-name-prefix = "AMX1"; 509848f3290SSameer Pujar status = "disabled"; 510848f3290SSameer Pujar }; 511848f3290SSameer Pujar 512848f3290SSameer Pujar tegra_amx2: amx@2903100 { 513848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 514848f3290SSameer Pujar reg = <0x2903100 0x100>; 515848f3290SSameer Pujar sound-name-prefix = "AMX2"; 516848f3290SSameer Pujar status = "disabled"; 517848f3290SSameer Pujar }; 518848f3290SSameer Pujar 519848f3290SSameer Pujar tegra_amx3: amx@2903200 { 520848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 521848f3290SSameer Pujar reg = <0x2903200 0x100>; 522848f3290SSameer Pujar sound-name-prefix = "AMX3"; 523848f3290SSameer Pujar status = "disabled"; 524848f3290SSameer Pujar }; 525848f3290SSameer Pujar 526848f3290SSameer Pujar tegra_amx4: amx@2903300 { 527848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 528848f3290SSameer Pujar reg = <0x2903300 0x100>; 529848f3290SSameer Pujar sound-name-prefix = "AMX4"; 530848f3290SSameer Pujar status = "disabled"; 531848f3290SSameer Pujar }; 532848f3290SSameer Pujar 533848f3290SSameer Pujar tegra_adx1: adx@2903800 { 534848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 535848f3290SSameer Pujar "nvidia,tegra210-adx"; 536848f3290SSameer Pujar reg = <0x2903800 0x100>; 537848f3290SSameer Pujar sound-name-prefix = "ADX1"; 538848f3290SSameer Pujar status = "disabled"; 539848f3290SSameer Pujar }; 540848f3290SSameer Pujar 541848f3290SSameer Pujar tegra_adx2: adx@2903900 { 542848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 543848f3290SSameer Pujar "nvidia,tegra210-adx"; 544848f3290SSameer Pujar reg = <0x2903900 0x100>; 545848f3290SSameer Pujar sound-name-prefix = "ADX2"; 546848f3290SSameer Pujar status = "disabled"; 547848f3290SSameer Pujar }; 548848f3290SSameer Pujar 549848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 550848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 551848f3290SSameer Pujar "nvidia,tegra210-adx"; 552848f3290SSameer Pujar reg = <0x2903a00 0x100>; 553848f3290SSameer Pujar sound-name-prefix = "ADX3"; 554848f3290SSameer Pujar status = "disabled"; 555848f3290SSameer Pujar }; 556848f3290SSameer Pujar 557848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 558848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 559848f3290SSameer Pujar "nvidia,tegra210-adx"; 560848f3290SSameer Pujar reg = <0x2903b00 0x100>; 561848f3290SSameer Pujar sound-name-prefix = "ADX4"; 562848f3290SSameer Pujar status = "disabled"; 563848f3290SSameer Pujar }; 564848f3290SSameer Pujar 565848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 566848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 567848f3290SSameer Pujar "nvidia,tegra210-amixer"; 568848f3290SSameer Pujar reg = <0x290bb00 0x800>; 569848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 570848f3290SSameer Pujar status = "disabled"; 571848f3290SSameer Pujar }; 572177208f7SSameer Pujar }; 5735d2249ddSSameer Pujar }; 5745d2249ddSSameer Pujar 575dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 576dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 577644c569dSThierry Reding reg = <0x2430000 0x17000>, 578644c569dSThierry Reding <0xc300000 0x4000>; 579dbb72e2cSVidya Sagar 580dbb72e2cSVidya Sagar status = "okay"; 581dbb72e2cSVidya Sagar 582dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 583dbb72e2cSVidya Sagar pex_rst { 584dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 585dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 586dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5876b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 588dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 589dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 590dbb72e2cSVidya Sagar }; 591dbb72e2cSVidya Sagar }; 592dbb72e2cSVidya Sagar 593dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 594dbb72e2cSVidya Sagar clkreq { 595dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 596dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 597dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5986b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 599dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 600dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 601dbb72e2cSVidya Sagar }; 602dbb72e2cSVidya Sagar }; 603dbb72e2cSVidya Sagar }; 604dbb72e2cSVidya Sagar 605be9b887fSThierry Reding mc: memory-controller@2c00000 { 606be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 607be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 608be9b887fSThierry Reding <0x02b80000 0x040000>, 609be9b887fSThierry Reding <0x01700000 0x100000>; 6108613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 611d5237c7cSThierry Reding #interconnect-cells = <1>; 612be9b887fSThierry Reding status = "disabled"; 613be9b887fSThierry Reding 614be9b887fSThierry Reding #address-cells = <2>; 615be9b887fSThierry Reding #size-cells = <2>; 616be9b887fSThierry Reding 617be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 618be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 619be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 620be9b887fSThierry Reding 621be9b887fSThierry Reding /* 622be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 623be9b887fSThierry Reding * controller selects the XBAR format used when memory 624be9b887fSThierry Reding * is accessed. This is used to transparently access 625be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 626be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 627be9b887fSThierry Reding * 628be9b887fSThierry Reding * As a consequence, the operating system must ensure 629be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 630be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 631be9b887fSThierry Reding * devices require access to the XBAR switch, their 632be9b887fSThierry Reding * drivers must set this bit explicitly. 633be9b887fSThierry Reding * 634be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 635be9b887fSThierry Reding */ 636be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 637be9b887fSThierry Reding 638be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 639be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 640be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 641be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 642cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 643be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 644be9b887fSThierry Reding clock-names = "emc"; 645be9b887fSThierry Reding 646d5237c7cSThierry Reding #interconnect-cells = <0>; 647d5237c7cSThierry Reding 648be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 649be9b887fSThierry Reding }; 650be9b887fSThierry Reding }; 651be9b887fSThierry Reding 6525425fb15SMikko Perttunen uarta: serial@3100000 { 6535425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6545425fb15SMikko Perttunen reg = <0x03100000 0x40>; 6555425fb15SMikko Perttunen reg-shift = <2>; 6565425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 6575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 6585425fb15SMikko Perttunen clock-names = "serial"; 6595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 6605425fb15SMikko Perttunen reset-names = "serial"; 6615425fb15SMikko Perttunen status = "disabled"; 6625425fb15SMikko Perttunen }; 6635425fb15SMikko Perttunen 6645425fb15SMikko Perttunen uartb: serial@3110000 { 6655425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6665425fb15SMikko Perttunen reg = <0x03110000 0x40>; 6675425fb15SMikko Perttunen reg-shift = <2>; 6685425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 6695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 6705425fb15SMikko Perttunen clock-names = "serial"; 6715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 6725425fb15SMikko Perttunen reset-names = "serial"; 6735425fb15SMikko Perttunen status = "disabled"; 6745425fb15SMikko Perttunen }; 6755425fb15SMikko Perttunen 6765425fb15SMikko Perttunen uartd: serial@3130000 { 6775425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6785425fb15SMikko Perttunen reg = <0x03130000 0x40>; 6795425fb15SMikko Perttunen reg-shift = <2>; 6805425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 6815425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 6825425fb15SMikko Perttunen clock-names = "serial"; 6835425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 6845425fb15SMikko Perttunen reset-names = "serial"; 6855425fb15SMikko Perttunen status = "disabled"; 6865425fb15SMikko Perttunen }; 6875425fb15SMikko Perttunen 6885425fb15SMikko Perttunen uarte: serial@3140000 { 6895425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6905425fb15SMikko Perttunen reg = <0x03140000 0x40>; 6915425fb15SMikko Perttunen reg-shift = <2>; 6925425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 6935425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 6945425fb15SMikko Perttunen clock-names = "serial"; 6955425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 6965425fb15SMikko Perttunen reset-names = "serial"; 6975425fb15SMikko Perttunen status = "disabled"; 6985425fb15SMikko Perttunen }; 6995425fb15SMikko Perttunen 7005425fb15SMikko Perttunen uartf: serial@3150000 { 7015425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7025425fb15SMikko Perttunen reg = <0x03150000 0x40>; 7035425fb15SMikko Perttunen reg-shift = <2>; 7045425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7065425fb15SMikko Perttunen clock-names = "serial"; 7075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7085425fb15SMikko Perttunen reset-names = "serial"; 7095425fb15SMikko Perttunen status = "disabled"; 7105425fb15SMikko Perttunen }; 7115425fb15SMikko Perttunen 7125425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 713d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7145425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 7155425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 7165425fb15SMikko Perttunen #address-cells = <1>; 7175425fb15SMikko Perttunen #size-cells = <0>; 7185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 7195425fb15SMikko Perttunen clock-names = "div-clk"; 7205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 7215425fb15SMikko Perttunen reset-names = "i2c"; 7225425fb15SMikko Perttunen status = "disabled"; 7235425fb15SMikko Perttunen }; 7245425fb15SMikko Perttunen 7255425fb15SMikko Perttunen uarth: serial@3170000 { 7265425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7275425fb15SMikko Perttunen reg = <0x03170000 0x40>; 7285425fb15SMikko Perttunen reg-shift = <2>; 7295425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 7305425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 7315425fb15SMikko Perttunen clock-names = "serial"; 7325425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 7335425fb15SMikko Perttunen reset-names = "serial"; 7345425fb15SMikko Perttunen status = "disabled"; 7355425fb15SMikko Perttunen }; 7365425fb15SMikko Perttunen 7375425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 738d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7395425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 7405425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 7415425fb15SMikko Perttunen #address-cells = <1>; 7425425fb15SMikko Perttunen #size-cells = <0>; 7435425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 7445425fb15SMikko Perttunen clock-names = "div-clk"; 7455425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 7465425fb15SMikko Perttunen reset-names = "i2c"; 7475425fb15SMikko Perttunen status = "disabled"; 7485425fb15SMikko Perttunen }; 7495425fb15SMikko Perttunen 7505425fb15SMikko Perttunen /* shares pads with dpaux1 */ 7515425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 752d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7535425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 7545425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 7555425fb15SMikko Perttunen #address-cells = <1>; 7565425fb15SMikko Perttunen #size-cells = <0>; 7575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 7585425fb15SMikko Perttunen clock-names = "div-clk"; 7595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 7605425fb15SMikko Perttunen reset-names = "i2c"; 761a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 762a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 763a4131561SThierry Reding pinctrl-names = "default", "idle"; 7645425fb15SMikko Perttunen status = "disabled"; 7655425fb15SMikko Perttunen }; 7665425fb15SMikko Perttunen 7675425fb15SMikko Perttunen /* shares pads with dpaux0 */ 7685425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 769d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7705425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 7715425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7725425fb15SMikko Perttunen #address-cells = <1>; 7735425fb15SMikko Perttunen #size-cells = <0>; 7745425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 7755425fb15SMikko Perttunen clock-names = "div-clk"; 7765425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 7775425fb15SMikko Perttunen reset-names = "i2c"; 778a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 779a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 780a4131561SThierry Reding pinctrl-names = "default", "idle"; 7815425fb15SMikko Perttunen status = "disabled"; 7825425fb15SMikko Perttunen }; 7835425fb15SMikko Perttunen 784a4131561SThierry Reding /* shares pads with dpaux2 */ 785a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 786d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7875425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 7885425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 7895425fb15SMikko Perttunen #address-cells = <1>; 7905425fb15SMikko Perttunen #size-cells = <0>; 7915425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 7925425fb15SMikko Perttunen clock-names = "div-clk"; 7935425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 7945425fb15SMikko Perttunen reset-names = "i2c"; 795a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 796a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 797a4131561SThierry Reding pinctrl-names = "default", "idle"; 7985425fb15SMikko Perttunen status = "disabled"; 7995425fb15SMikko Perttunen }; 8005425fb15SMikko Perttunen 801a4131561SThierry Reding /* shares pads with dpaux3 */ 802a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 803d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8045425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 8055425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 8065425fb15SMikko Perttunen #address-cells = <1>; 8075425fb15SMikko Perttunen #size-cells = <0>; 8085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 8095425fb15SMikko Perttunen clock-names = "div-clk"; 8105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 8115425fb15SMikko Perttunen reset-names = "i2c"; 812a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 813a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 814a4131561SThierry Reding pinctrl-names = "default", "idle"; 8155425fb15SMikko Perttunen status = "disabled"; 8165425fb15SMikko Perttunen }; 8175425fb15SMikko Perttunen 81896ded827SSowjanya Komatineni spi@3270000 { 81996ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 82096ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 82196ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 82296ded827SSowjanya Komatineni #address-cells = <1>; 82396ded827SSowjanya Komatineni #size-cells = <0>; 82496ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 82596ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 82696ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 82796ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 82896ded827SSowjanya Komatineni reset-names = "qspi"; 82996ded827SSowjanya Komatineni status = "disabled"; 83096ded827SSowjanya Komatineni }; 83196ded827SSowjanya Komatineni 83296ded827SSowjanya Komatineni spi@3300000 { 83396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 83496ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 83596ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 83696ded827SSowjanya Komatineni #address-cells = <1>; 83796ded827SSowjanya Komatineni #size-cells = <0>; 83896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 83996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 84096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 84196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 84296ded827SSowjanya Komatineni reset-names = "qspi"; 84396ded827SSowjanya Komatineni status = "disabled"; 84496ded827SSowjanya Komatineni }; 84596ded827SSowjanya Komatineni 8466a574ec7SThierry Reding pwm1: pwm@3280000 { 8476a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8486a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8496a574ec7SThierry Reding reg = <0x3280000 0x10000>; 8506a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 8516a574ec7SThierry Reding clock-names = "pwm"; 8526a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 8536a574ec7SThierry Reding reset-names = "pwm"; 8546a574ec7SThierry Reding status = "disabled"; 8556a574ec7SThierry Reding #pwm-cells = <2>; 8566a574ec7SThierry Reding }; 8576a574ec7SThierry Reding 8586a574ec7SThierry Reding pwm2: pwm@3290000 { 8596a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8606a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8616a574ec7SThierry Reding reg = <0x3290000 0x10000>; 8626a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 8636a574ec7SThierry Reding clock-names = "pwm"; 8646a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 8656a574ec7SThierry Reding reset-names = "pwm"; 8666a574ec7SThierry Reding status = "disabled"; 8676a574ec7SThierry Reding #pwm-cells = <2>; 8686a574ec7SThierry Reding }; 8696a574ec7SThierry Reding 8706a574ec7SThierry Reding pwm3: pwm@32a0000 { 8716a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8726a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8736a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 8746a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 8756a574ec7SThierry Reding clock-names = "pwm"; 8766a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 8776a574ec7SThierry Reding reset-names = "pwm"; 8786a574ec7SThierry Reding status = "disabled"; 8796a574ec7SThierry Reding #pwm-cells = <2>; 8806a574ec7SThierry Reding }; 8816a574ec7SThierry Reding 8826a574ec7SThierry Reding pwm5: pwm@32c0000 { 8836a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8846a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8856a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 8866a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 8876a574ec7SThierry Reding clock-names = "pwm"; 8886a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 8896a574ec7SThierry Reding reset-names = "pwm"; 8906a574ec7SThierry Reding status = "disabled"; 8916a574ec7SThierry Reding #pwm-cells = <2>; 8926a574ec7SThierry Reding }; 8936a574ec7SThierry Reding 8946a574ec7SThierry Reding pwm6: pwm@32d0000 { 8956a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8966a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8976a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 8986a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 8996a574ec7SThierry Reding clock-names = "pwm"; 9006a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 9016a574ec7SThierry Reding reset-names = "pwm"; 9026a574ec7SThierry Reding status = "disabled"; 9036a574ec7SThierry Reding #pwm-cells = <2>; 9046a574ec7SThierry Reding }; 9056a574ec7SThierry Reding 9066a574ec7SThierry Reding pwm7: pwm@32e0000 { 9076a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9086a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9096a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 9106a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 9116a574ec7SThierry Reding clock-names = "pwm"; 9126a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 9136a574ec7SThierry Reding reset-names = "pwm"; 9146a574ec7SThierry Reding status = "disabled"; 9156a574ec7SThierry Reding #pwm-cells = <2>; 9166a574ec7SThierry Reding }; 9176a574ec7SThierry Reding 9186a574ec7SThierry Reding pwm8: pwm@32f0000 { 9196a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9206a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9216a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 9226a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 9236a574ec7SThierry Reding clock-names = "pwm"; 9246a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 9256a574ec7SThierry Reding reset-names = "pwm"; 9266a574ec7SThierry Reding status = "disabled"; 9276a574ec7SThierry Reding #pwm-cells = <2>; 9286a574ec7SThierry Reding }; 9296a574ec7SThierry Reding 93067bb17f6SThierry Reding sdmmc1: mmc@3400000 { 9312c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9325425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 9335425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 934c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 935c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 936c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 937*7ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 938*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 939*7ac853baSAniruddha Rao assigned-clock-parents = 940*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 941*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 9425425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 9435425fb15SMikko Perttunen reset-names = "sdhci"; 944d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 945d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 946d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 947c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 948ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 949ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 950ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 9514e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 9524e0f1229SSowjanya Komatineni <0x07>; 9534e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9544e0f1229SSowjanya Komatineni <0x07>; 9554e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9564e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9574e0f1229SSowjanya Komatineni <0x07>; 9584e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9594e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9604e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9614e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 962ff21087eSPrathamesh Shete sd-uhs-sdr25; 963ff21087eSPrathamesh Shete sd-uhs-sdr50; 964ff21087eSPrathamesh Shete sd-uhs-ddr50; 965ff21087eSPrathamesh Shete sd-uhs-sdr104; 9665425fb15SMikko Perttunen status = "disabled"; 9675425fb15SMikko Perttunen }; 9685425fb15SMikko Perttunen 96967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 9702c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9715425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 9725425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 973c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 974c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 975c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 976*7ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 977*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 978*7ac853baSAniruddha Rao assigned-clock-parents = 979*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 980*7ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 9815425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 9825425fb15SMikko Perttunen reset-names = "sdhci"; 983d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 984d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 985d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 986c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 987ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 988ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 989ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 9904e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 9914e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 9924e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 9934e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9944e0f1229SSowjanya Komatineni <0x07>; 9954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9974e0f1229SSowjanya Komatineni <0x07>; 9984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10004e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10014e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1002ff21087eSPrathamesh Shete sd-uhs-sdr25; 1003ff21087eSPrathamesh Shete sd-uhs-sdr50; 1004ff21087eSPrathamesh Shete sd-uhs-ddr50; 1005ff21087eSPrathamesh Shete sd-uhs-sdr104; 10065425fb15SMikko Perttunen status = "disabled"; 10075425fb15SMikko Perttunen }; 10085425fb15SMikko Perttunen 100967bb17f6SThierry Reding sdmmc4: mmc@3460000 { 10102c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10115425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 10125425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1013c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1014c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1015c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1016351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1017351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1018351648d0SSowjanya Komatineni assigned-clock-parents = 1019351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 10205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 10215425fb15SMikko Perttunen reset-names = "sdhci"; 1022d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1023d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1024d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1025c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 10264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 10274e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 10284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 10294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10304e0f1229SSowjanya Komatineni <0x0a>; 10314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 10324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10334e0f1229SSowjanya Komatineni <0x0a>; 10344e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 10354e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 10364e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1037c2fee443SPrathamesh Shete cap-mmc-highspeed; 1038c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1039c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1040c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1041c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1042dfd3cb6fSSowjanya Komatineni supports-cqe; 10435425fb15SMikko Perttunen status = "disabled"; 10445425fb15SMikko Perttunen }; 10455425fb15SMikko Perttunen 10464878cc0cSSameer Pujar hda@3510000 { 10474878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 10484878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 10494878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 10504878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 105148f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 105248f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 105348f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 10544878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1055146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1056146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 10574878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1058d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1059d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1060d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1061c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 10624878cc0cSSameer Pujar status = "disabled"; 10634878cc0cSSameer Pujar }; 10644878cc0cSSameer Pujar 1065fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1066fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1067fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1068fab7a039SJC Kuo <0x03540000 0x1000>; 1069fab7a039SJC Kuo reg-names = "padctl", "ao"; 10706450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1071fab7a039SJC Kuo 1072fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1073fab7a039SJC Kuo reset-names = "padctl"; 1074fab7a039SJC Kuo 1075fab7a039SJC Kuo status = "disabled"; 1076fab7a039SJC Kuo 1077fab7a039SJC Kuo pads { 1078fab7a039SJC Kuo usb2 { 1079fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1080fab7a039SJC Kuo clock-names = "trk"; 1081fab7a039SJC Kuo 1082fab7a039SJC Kuo lanes { 1083fab7a039SJC Kuo usb2-0 { 1084fab7a039SJC Kuo nvidia,function = "xusb"; 1085fab7a039SJC Kuo status = "disabled"; 1086fab7a039SJC Kuo #phy-cells = <0>; 1087fab7a039SJC Kuo }; 1088fab7a039SJC Kuo 1089fab7a039SJC Kuo usb2-1 { 1090fab7a039SJC Kuo nvidia,function = "xusb"; 1091fab7a039SJC Kuo status = "disabled"; 1092fab7a039SJC Kuo #phy-cells = <0>; 1093fab7a039SJC Kuo }; 1094fab7a039SJC Kuo 1095fab7a039SJC Kuo usb2-2 { 1096fab7a039SJC Kuo nvidia,function = "xusb"; 1097fab7a039SJC Kuo status = "disabled"; 1098fab7a039SJC Kuo #phy-cells = <0>; 1099fab7a039SJC Kuo }; 1100fab7a039SJC Kuo 1101fab7a039SJC Kuo usb2-3 { 1102fab7a039SJC Kuo nvidia,function = "xusb"; 1103fab7a039SJC Kuo status = "disabled"; 1104fab7a039SJC Kuo #phy-cells = <0>; 1105fab7a039SJC Kuo }; 1106fab7a039SJC Kuo }; 1107fab7a039SJC Kuo }; 1108fab7a039SJC Kuo 1109fab7a039SJC Kuo usb3 { 1110fab7a039SJC Kuo lanes { 1111fab7a039SJC Kuo usb3-0 { 1112fab7a039SJC Kuo nvidia,function = "xusb"; 1113fab7a039SJC Kuo status = "disabled"; 1114fab7a039SJC Kuo #phy-cells = <0>; 1115fab7a039SJC Kuo }; 1116fab7a039SJC Kuo 1117fab7a039SJC Kuo usb3-1 { 1118fab7a039SJC Kuo nvidia,function = "xusb"; 1119fab7a039SJC Kuo status = "disabled"; 1120fab7a039SJC Kuo #phy-cells = <0>; 1121fab7a039SJC Kuo }; 1122fab7a039SJC Kuo 1123fab7a039SJC Kuo usb3-2 { 1124fab7a039SJC Kuo nvidia,function = "xusb"; 1125fab7a039SJC Kuo status = "disabled"; 1126fab7a039SJC Kuo #phy-cells = <0>; 1127fab7a039SJC Kuo }; 1128fab7a039SJC Kuo 1129fab7a039SJC Kuo usb3-3 { 1130fab7a039SJC Kuo nvidia,function = "xusb"; 1131fab7a039SJC Kuo status = "disabled"; 1132fab7a039SJC Kuo #phy-cells = <0>; 1133fab7a039SJC Kuo }; 1134fab7a039SJC Kuo }; 1135fab7a039SJC Kuo }; 1136fab7a039SJC Kuo }; 1137fab7a039SJC Kuo 1138fab7a039SJC Kuo ports { 1139fab7a039SJC Kuo usb2-0 { 1140fab7a039SJC Kuo status = "disabled"; 1141fab7a039SJC Kuo }; 1142fab7a039SJC Kuo 1143fab7a039SJC Kuo usb2-1 { 1144fab7a039SJC Kuo status = "disabled"; 1145fab7a039SJC Kuo }; 1146fab7a039SJC Kuo 1147fab7a039SJC Kuo usb2-2 { 1148fab7a039SJC Kuo status = "disabled"; 1149fab7a039SJC Kuo }; 1150fab7a039SJC Kuo 1151fab7a039SJC Kuo usb2-3 { 1152fab7a039SJC Kuo status = "disabled"; 1153fab7a039SJC Kuo }; 1154fab7a039SJC Kuo 1155fab7a039SJC Kuo usb3-0 { 1156fab7a039SJC Kuo status = "disabled"; 1157fab7a039SJC Kuo }; 1158fab7a039SJC Kuo 1159fab7a039SJC Kuo usb3-1 { 1160fab7a039SJC Kuo status = "disabled"; 1161fab7a039SJC Kuo }; 1162fab7a039SJC Kuo 1163fab7a039SJC Kuo usb3-2 { 1164fab7a039SJC Kuo status = "disabled"; 1165fab7a039SJC Kuo }; 1166fab7a039SJC Kuo 1167fab7a039SJC Kuo usb3-3 { 1168fab7a039SJC Kuo status = "disabled"; 1169fab7a039SJC Kuo }; 1170fab7a039SJC Kuo }; 1171fab7a039SJC Kuo }; 1172fab7a039SJC Kuo 1173bc8788b2SNagarjuna Kristam usb@3550000 { 1174bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1175bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1176bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1177bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1178bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1179bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1180bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1181bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1182bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1183bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1184c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1185c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1186c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1187c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1188bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1189bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1190bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1191bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1192bc8788b2SNagarjuna Kristam status = "disabled"; 1193bc8788b2SNagarjuna Kristam }; 1194bc8788b2SNagarjuna Kristam 1195fab7a039SJC Kuo usb@3610000 { 1196fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1197fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1198fab7a039SJC Kuo <0x03600000 0x10000>; 1199fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1200fab7a039SJC Kuo 1201fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1202a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1203fab7a039SJC Kuo 1204fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1205fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1206fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1207fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1208fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1209fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1210fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1211fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1212fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1213fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1214fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1215fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1216fab7a039SJC Kuo "pll_e"; 1217c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1218c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1219c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1220c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1221fab7a039SJC Kuo 1222fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1223fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1224fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1225fab7a039SJC Kuo 1226fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1227fab7a039SJC Kuo status = "disabled"; 1228fab7a039SJC Kuo }; 1229fab7a039SJC Kuo 123009903c5eSJC Kuo fuse@3820000 { 123109903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 123209903c5eSJC Kuo reg = <0x03820000 0x10000>; 123309903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 123409903c5eSJC Kuo clock-names = "fuse"; 123509903c5eSJC Kuo }; 123609903c5eSJC Kuo 12375425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 12385425fb15SMikko Perttunen compatible = "arm,gic-400"; 12395425fb15SMikko Perttunen #interrupt-cells = <3>; 12405425fb15SMikko Perttunen interrupt-controller; 12415425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 12425425fb15SMikko Perttunen <0x03882000 0x2000>, 12435425fb15SMikko Perttunen <0x03884000 0x2000>, 12445425fb15SMikko Perttunen <0x03886000 0x2000>; 12455425fb15SMikko Perttunen interrupts = <GIC_PPI 9 12465425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 12475425fb15SMikko Perttunen interrupt-parent = <&gic>; 12485425fb15SMikko Perttunen }; 12495425fb15SMikko Perttunen 1250badb80beSThierry Reding cec@3960000 { 1251badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1252badb80beSThierry Reding reg = <0x03960000 0x10000>; 1253badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1254badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1255badb80beSThierry Reding clock-names = "cec"; 1256badb80beSThierry Reding status = "disabled"; 1257badb80beSThierry Reding }; 1258badb80beSThierry Reding 12595425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1260cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 12615425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1262a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1263a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1264a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1265a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1266a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1267a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1268a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1269a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1270a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1271a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1272a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1273a38570c2SMikko Perttunen "shared7"; 1274a38570c2SMikko Perttunen #mbox-cells = <2>; 1275a38570c2SMikko Perttunen }; 1276a38570c2SMikko Perttunen 12772602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 12782602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12792602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 12802602c32fSVidya Sagar reg-names = "ctl"; 12812602c32fSVidya Sagar 12822602c32fSVidya Sagar #phy-cells = <0>; 12832602c32fSVidya Sagar }; 12842602c32fSVidya Sagar 12852602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 12862602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12872602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 12882602c32fSVidya Sagar reg-names = "ctl"; 12892602c32fSVidya Sagar 12902602c32fSVidya Sagar #phy-cells = <0>; 12912602c32fSVidya Sagar }; 12922602c32fSVidya Sagar 12932602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 12942602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12952602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 12962602c32fSVidya Sagar reg-names = "ctl"; 12972602c32fSVidya Sagar 12982602c32fSVidya Sagar #phy-cells = <0>; 12992602c32fSVidya Sagar }; 13002602c32fSVidya Sagar 13012602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 13022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13032602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 13042602c32fSVidya Sagar reg-names = "ctl"; 13052602c32fSVidya Sagar 13062602c32fSVidya Sagar #phy-cells = <0>; 13072602c32fSVidya Sagar }; 13082602c32fSVidya Sagar 13092602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 13102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13112602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 13122602c32fSVidya Sagar reg-names = "ctl"; 13132602c32fSVidya Sagar 13142602c32fSVidya Sagar #phy-cells = <0>; 13152602c32fSVidya Sagar }; 13162602c32fSVidya Sagar 13172602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 13182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13192602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 13202602c32fSVidya Sagar reg-names = "ctl"; 13212602c32fSVidya Sagar 13222602c32fSVidya Sagar #phy-cells = <0>; 13232602c32fSVidya Sagar }; 13242602c32fSVidya Sagar 13252602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 13262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13272602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 13282602c32fSVidya Sagar reg-names = "ctl"; 13292602c32fSVidya Sagar 13302602c32fSVidya Sagar #phy-cells = <0>; 13312602c32fSVidya Sagar }; 13322602c32fSVidya Sagar 13332602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 13342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13352602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 13362602c32fSVidya Sagar reg-names = "ctl"; 13372602c32fSVidya Sagar 13382602c32fSVidya Sagar #phy-cells = <0>; 13392602c32fSVidya Sagar }; 13402602c32fSVidya Sagar 13412602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 13422602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13432602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 13442602c32fSVidya Sagar reg-names = "ctl"; 13452602c32fSVidya Sagar 13462602c32fSVidya Sagar #phy-cells = <0>; 13472602c32fSVidya Sagar }; 13482602c32fSVidya Sagar 13492602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 13502602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13512602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 13522602c32fSVidya Sagar reg-names = "ctl"; 13532602c32fSVidya Sagar 13542602c32fSVidya Sagar #phy-cells = <0>; 13552602c32fSVidya Sagar }; 13562602c32fSVidya Sagar 13572602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 13582602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13592602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 13602602c32fSVidya Sagar reg-names = "ctl"; 13612602c32fSVidya Sagar 13622602c32fSVidya Sagar #phy-cells = <0>; 13632602c32fSVidya Sagar }; 13642602c32fSVidya Sagar 13652602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 13662602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13672602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 13682602c32fSVidya Sagar reg-names = "ctl"; 13692602c32fSVidya Sagar 13702602c32fSVidya Sagar #phy-cells = <0>; 13712602c32fSVidya Sagar }; 13722602c32fSVidya Sagar 13732602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 13742602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13752602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 13762602c32fSVidya Sagar reg-names = "ctl"; 13772602c32fSVidya Sagar 13782602c32fSVidya Sagar #phy-cells = <0>; 13792602c32fSVidya Sagar }; 13802602c32fSVidya Sagar 13812602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 13822602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13832602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 13842602c32fSVidya Sagar reg-names = "ctl"; 13852602c32fSVidya Sagar 13862602c32fSVidya Sagar #phy-cells = <0>; 13872602c32fSVidya Sagar }; 13882602c32fSVidya Sagar 13892602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 13902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13912602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 13922602c32fSVidya Sagar reg-names = "ctl"; 13932602c32fSVidya Sagar 13942602c32fSVidya Sagar #phy-cells = <0>; 13952602c32fSVidya Sagar }; 13962602c32fSVidya Sagar 13972602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 13982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13992602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 14002602c32fSVidya Sagar reg-names = "ctl"; 14012602c32fSVidya Sagar 14022602c32fSVidya Sagar #phy-cells = <0>; 14032602c32fSVidya Sagar }; 14042602c32fSVidya Sagar 14052602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 14062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14072602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 14082602c32fSVidya Sagar reg-names = "ctl"; 14092602c32fSVidya Sagar 14102602c32fSVidya Sagar #phy-cells = <0>; 14112602c32fSVidya Sagar }; 14122602c32fSVidya Sagar 14132602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 14142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14152602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 14162602c32fSVidya Sagar reg-names = "ctl"; 14172602c32fSVidya Sagar 14182602c32fSVidya Sagar #phy-cells = <0>; 14192602c32fSVidya Sagar }; 14202602c32fSVidya Sagar 14212602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 14222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14232602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 14242602c32fSVidya Sagar reg-names = "ctl"; 14252602c32fSVidya Sagar 14262602c32fSVidya Sagar #phy-cells = <0>; 14272602c32fSVidya Sagar }; 14282602c32fSVidya Sagar 14292602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 14302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14312602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 14322602c32fSVidya Sagar reg-names = "ctl"; 14332602c32fSVidya Sagar 14342602c32fSVidya Sagar #phy-cells = <0>; 14352602c32fSVidya Sagar }; 14362602c32fSVidya Sagar 1437a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1438cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 14391741e187SDipen Patel reg = <0x0c150000 0x90000>; 1440a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1441a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1442a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1443a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1444a38570c2SMikko Perttunen /* 1445a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1446a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1447a38570c2SMikko Perttunen */ 1448a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 14495425fb15SMikko Perttunen #mbox-cells = <2>; 14505425fb15SMikko Perttunen }; 14515425fb15SMikko Perttunen 14525425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1453d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14545425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 14555425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 14565425fb15SMikko Perttunen #address-cells = <1>; 14575425fb15SMikko Perttunen #size-cells = <0>; 14585425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 14595425fb15SMikko Perttunen clock-names = "div-clk"; 14605425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 14615425fb15SMikko Perttunen reset-names = "i2c"; 14625425fb15SMikko Perttunen status = "disabled"; 14635425fb15SMikko Perttunen }; 14645425fb15SMikko Perttunen 14655425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1466d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 14675425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 14685425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 14695425fb15SMikko Perttunen #address-cells = <1>; 14705425fb15SMikko Perttunen #size-cells = <0>; 14715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 14725425fb15SMikko Perttunen clock-names = "div-clk"; 14735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 14745425fb15SMikko Perttunen reset-names = "i2c"; 14755425fb15SMikko Perttunen status = "disabled"; 14765425fb15SMikko Perttunen }; 14775425fb15SMikko Perttunen 14785425fb15SMikko Perttunen uartc: serial@c280000 { 14795425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14805425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 14815425fb15SMikko Perttunen reg-shift = <2>; 14825425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 14835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 14845425fb15SMikko Perttunen clock-names = "serial"; 14855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 14865425fb15SMikko Perttunen reset-names = "serial"; 14875425fb15SMikko Perttunen status = "disabled"; 14885425fb15SMikko Perttunen }; 14895425fb15SMikko Perttunen 14905425fb15SMikko Perttunen uartg: serial@c290000 { 14915425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14925425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 14935425fb15SMikko Perttunen reg-shift = <2>; 14945425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 14955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 14965425fb15SMikko Perttunen clock-names = "serial"; 14975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 14985425fb15SMikko Perttunen reset-names = "serial"; 14995425fb15SMikko Perttunen status = "disabled"; 15005425fb15SMikko Perttunen }; 15015425fb15SMikko Perttunen 150237e5a31dSThierry Reding rtc: rtc@c2a0000 { 150337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 150437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 150537e5a31dSThierry Reding interrupt-parent = <&pmc>; 150637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 150737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 150837e5a31dSThierry Reding clock-names = "rtc"; 150937e5a31dSThierry Reding status = "disabled"; 151037e5a31dSThierry Reding }; 151137e5a31dSThierry Reding 15124d286331SThierry Reding gpio_aon: gpio@c2f0000 { 15134d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 15144d286331SThierry Reding reg-names = "security", "gpio"; 15154d286331SThierry Reding reg = <0xc2f0000 0x1000>, 15164d286331SThierry Reding <0xc2f1000 0x1000>; 15170a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 15180a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 15190a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 15200a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 15214d286331SThierry Reding gpio-controller; 15224d286331SThierry Reding #gpio-cells = <2>; 15234d286331SThierry Reding interrupt-controller; 15244d286331SThierry Reding #interrupt-cells = <2>; 15254d286331SThierry Reding }; 15264d286331SThierry Reding 15276a574ec7SThierry Reding pwm4: pwm@c340000 { 15286a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 15296a574ec7SThierry Reding "nvidia,tegra186-pwm"; 15306a574ec7SThierry Reding reg = <0xc340000 0x10000>; 15316a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 15326a574ec7SThierry Reding clock-names = "pwm"; 15336a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 15346a574ec7SThierry Reding reset-names = "pwm"; 15356a574ec7SThierry Reding status = "disabled"; 15366a574ec7SThierry Reding #pwm-cells = <2>; 15376a574ec7SThierry Reding }; 15386a574ec7SThierry Reding 153938ecf1e5SThierry Reding pmc: pmc@c360000 { 15405425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 15415425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 15425425fb15SMikko Perttunen <0x0c370000 0x10000>, 15435425fb15SMikko Perttunen <0x0c380000 0x10000>, 15445425fb15SMikko Perttunen <0x0c390000 0x10000>, 15455425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 15465425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 154738ecf1e5SThierry Reding 154838ecf1e5SThierry Reding #interrupt-cells = <2>; 154938ecf1e5SThierry Reding interrupt-controller; 1550ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1551ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1552ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1553ff21087eSPrathamesh Shete }; 1554ff21087eSPrathamesh Shete 1555ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1556ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1557ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1558ff21087eSPrathamesh Shete }; 1559ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1560ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1561ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1562ff21087eSPrathamesh Shete }; 1563ff21087eSPrathamesh Shete 1564ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1565ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1566ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1567ff21087eSPrathamesh Shete }; 1568ff21087eSPrathamesh Shete 15695425fb15SMikko Perttunen }; 15703db6d3baSThierry Reding 1571e762232fSJon Hunter iommu@10000000 { 1572e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1573e762232fSJon Hunter reg = <0x10000000 0x800000>; 1574e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1575e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1576e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1577e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1578e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1579e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1580e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1581e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1582e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1583e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1584e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1585e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1586e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1587e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1588e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1589e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1590e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1591e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1592e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1593e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1594e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1595e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1596e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1597e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1598e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1599e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1600e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1601e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1602e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1603e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1604e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1605e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1606e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1607e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1608e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1609e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1610e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1611e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1612e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1613e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1614e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1615e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1616e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1617e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1618e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1619e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1620e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1621e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1622e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1623e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1639e762232fSJon Hunter stream-match-mask = <0x7f80>; 1640e762232fSJon Hunter #global-interrupts = <1>; 1641e762232fSJon Hunter #iommu-cells = <1>; 1642e762232fSJon Hunter 1643e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1644ebea268eSJon Hunter status = "disabled"; 1645e762232fSJon Hunter }; 1646e762232fSJon Hunter 1647c7289b1cSThierry Reding smmu: iommu@12000000 { 1648c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1649c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1650c7289b1cSThierry Reding <0x11000000 0x800000>; 1651c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1652c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1653c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1654c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1655c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1656c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1657c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1658c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1659c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1660c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1661c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1662c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1663c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1664c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1665c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1666c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1667c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1668c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1669c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1670c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1671c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1672c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1673c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1674c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1675c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1676c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1677c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1678c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1679c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1680c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1681c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1682c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1683c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1684c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1685c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1686c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1687c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1688c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1689c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1690c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1691c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1692c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1693c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1694c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1695c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1696c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1697c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1698c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1699c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1700c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1702c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1707c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1708c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1709c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1710c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1711c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1712c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1713c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1714c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1715c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1716c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1717c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1718c7289b1cSThierry Reding #global-interrupts = <2>; 1719c7289b1cSThierry Reding #iommu-cells = <1>; 1720c7289b1cSThierry Reding 1721c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1722c7289b1cSThierry Reding status = "okay"; 1723c7289b1cSThierry Reding }; 1724c7289b1cSThierry Reding 17253db6d3baSThierry Reding host1x@13e00000 { 1726ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 17273db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 17283db6d3baSThierry Reding <0x13e10000 0x10000>; 17293db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 17303db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 17313db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1732052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 17333db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 17343db6d3baSThierry Reding clock-names = "host1x"; 17353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 17363db6d3baSThierry Reding reset-names = "host1x"; 17373db6d3baSThierry Reding 17383db6d3baSThierry Reding #address-cells = <1>; 17393db6d3baSThierry Reding #size-cells = <1>; 17403db6d3baSThierry Reding 17413db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1742d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1743d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1744c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 17453db6d3baSThierry Reding 174678a05873SMikko Perttunen nvdec@15140000 { 174778a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 174878a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 174978a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 175078a05873SMikko Perttunen clock-names = "nvdec"; 175178a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 175278a05873SMikko Perttunen reset-names = "nvdec"; 175378a05873SMikko Perttunen 175478a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 175578a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 175678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 175778a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 175878a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 175978a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 176078a05873SMikko Perttunen dma-coherent; 176178a05873SMikko Perttunen 176278a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 176378a05873SMikko Perttunen }; 176478a05873SMikko Perttunen 17653db6d3baSThierry Reding display-hub@15200000 { 1766aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1767611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 17683db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 17693db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 17703db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 17713db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 17723db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 17733db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 17743db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 17753db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 17763db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 17773db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 17783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 17793db6d3baSThierry Reding clock-names = "disp", "hub"; 17803db6d3baSThierry Reding status = "disabled"; 17813db6d3baSThierry Reding 17823db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17833db6d3baSThierry Reding 17843db6d3baSThierry Reding #address-cells = <1>; 17853db6d3baSThierry Reding #size-cells = <1>; 17863db6d3baSThierry Reding 17873db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 17883db6d3baSThierry Reding 17893db6d3baSThierry Reding display@15200000 { 17903db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 17913db6d3baSThierry Reding reg = <0x15200000 0x10000>; 17923db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 17933db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 17943db6d3baSThierry Reding clock-names = "dc"; 17953db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 17963db6d3baSThierry Reding reset-names = "dc"; 17973db6d3baSThierry Reding 17983db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1799d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1800d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1801d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18023db6d3baSThierry Reding 18033db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18043db6d3baSThierry Reding nvidia,head = <0>; 18053db6d3baSThierry Reding }; 18063db6d3baSThierry Reding 18073db6d3baSThierry Reding display@15210000 { 18083db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 18093db6d3baSThierry Reding reg = <0x15210000 0x10000>; 18103db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 18113db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 18123db6d3baSThierry Reding clock-names = "dc"; 18133db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 18143db6d3baSThierry Reding reset-names = "dc"; 18153db6d3baSThierry Reding 18163db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1817d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1818d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1819d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18203db6d3baSThierry Reding 18213db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18223db6d3baSThierry Reding nvidia,head = <1>; 18233db6d3baSThierry Reding }; 18243db6d3baSThierry Reding 18253db6d3baSThierry Reding display@15220000 { 18263db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 18273db6d3baSThierry Reding reg = <0x15220000 0x10000>; 18283db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 18293db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 18303db6d3baSThierry Reding clock-names = "dc"; 18313db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 18323db6d3baSThierry Reding reset-names = "dc"; 18333db6d3baSThierry Reding 18343db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1835d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1836d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1837d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18383db6d3baSThierry Reding 18393db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18403db6d3baSThierry Reding nvidia,head = <2>; 18413db6d3baSThierry Reding }; 18423db6d3baSThierry Reding 18433db6d3baSThierry Reding display@15230000 { 18443db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 18453db6d3baSThierry Reding reg = <0x15230000 0x10000>; 18463db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 18473db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 18483db6d3baSThierry Reding clock-names = "dc"; 18493db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 18503db6d3baSThierry Reding reset-names = "dc"; 18513db6d3baSThierry Reding 18523db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1853d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1854d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1855d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 18563db6d3baSThierry Reding 18573db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 18583db6d3baSThierry Reding nvidia,head = <3>; 18593db6d3baSThierry Reding }; 18603db6d3baSThierry Reding }; 18613db6d3baSThierry Reding 18628d424ec2SThierry Reding vic@15340000 { 18638d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 18648d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 18658d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 18668d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 18678d424ec2SThierry Reding clock-names = "vic"; 18688d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 18698d424ec2SThierry Reding reset-names = "vic"; 18708d424ec2SThierry Reding 18718d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1872d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1873d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1874d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1875c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 1876a52280c8SJon Hunter dma-coherent; 18778d424ec2SThierry Reding }; 18788d424ec2SThierry Reding 1879f7eb2785SJon Hunter nvjpg@15380000 { 1880f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 1881f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1882f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1883f7eb2785SJon Hunter clock-names = "nvjpg"; 1884f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 1885f7eb2785SJon Hunter reset-names = "nvjpg"; 1886f7eb2785SJon Hunter 1887f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1888f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1889f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1890f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1891f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 1892f7eb2785SJon Hunter dma-coherent; 1893f7eb2785SJon Hunter }; 1894f7eb2785SJon Hunter 189578a05873SMikko Perttunen nvdec@15480000 { 189678a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 189778a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 189878a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 189978a05873SMikko Perttunen clock-names = "nvdec"; 190078a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 190178a05873SMikko Perttunen reset-names = "nvdec"; 190278a05873SMikko Perttunen 190378a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 190478a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 190578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 190678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 190778a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 190878a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 190978a05873SMikko Perttunen dma-coherent; 191078a05873SMikko Perttunen 191178a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 191278a05873SMikko Perttunen }; 191378a05873SMikko Perttunen 1914f7eb2785SJon Hunter nvenc@154c0000 { 1915f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 1916f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1917f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 1918f7eb2785SJon Hunter clock-names = "nvenc"; 1919f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 1920f7eb2785SJon Hunter reset-names = "nvenc"; 1921f7eb2785SJon Hunter 1922f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1923f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1924f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1925f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1926f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 1927f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 1928f7eb2785SJon Hunter dma-coherent; 1929f7eb2785SJon Hunter 1930f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 1931f7eb2785SJon Hunter }; 1932f7eb2785SJon Hunter 19333db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 19343db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19353db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 19363db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 19373db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 19383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19393db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19403db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 19413db6d3baSThierry Reding reset-names = "dpaux"; 19423db6d3baSThierry Reding status = "disabled"; 19433db6d3baSThierry Reding 19443db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19453db6d3baSThierry Reding 19463db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 19473db6d3baSThierry Reding groups = "dpaux-io"; 19483db6d3baSThierry Reding function = "aux"; 19493db6d3baSThierry Reding }; 19503db6d3baSThierry Reding 19513db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 19523db6d3baSThierry Reding groups = "dpaux-io"; 19533db6d3baSThierry Reding function = "i2c"; 19543db6d3baSThierry Reding }; 19553db6d3baSThierry Reding 19563db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 19573db6d3baSThierry Reding groups = "dpaux-io"; 19583db6d3baSThierry Reding function = "off"; 19593db6d3baSThierry Reding }; 19603db6d3baSThierry Reding 19613db6d3baSThierry Reding i2c-bus { 19623db6d3baSThierry Reding #address-cells = <1>; 19633db6d3baSThierry Reding #size-cells = <0>; 19643db6d3baSThierry Reding }; 19653db6d3baSThierry Reding }; 19663db6d3baSThierry Reding 19673db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 19683db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 19693db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 19703db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 19713db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 19723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 19733db6d3baSThierry Reding clock-names = "dpaux", "parent"; 19743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 19753db6d3baSThierry Reding reset-names = "dpaux"; 19763db6d3baSThierry Reding status = "disabled"; 19773db6d3baSThierry Reding 19783db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19793db6d3baSThierry Reding 19803db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 19813db6d3baSThierry Reding groups = "dpaux-io"; 19823db6d3baSThierry Reding function = "aux"; 19833db6d3baSThierry Reding }; 19843db6d3baSThierry Reding 19853db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 19863db6d3baSThierry Reding groups = "dpaux-io"; 19873db6d3baSThierry Reding function = "i2c"; 19883db6d3baSThierry Reding }; 19893db6d3baSThierry Reding 19903db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 19913db6d3baSThierry Reding groups = "dpaux-io"; 19923db6d3baSThierry Reding function = "off"; 19933db6d3baSThierry Reding }; 19943db6d3baSThierry Reding 19953db6d3baSThierry Reding i2c-bus { 19963db6d3baSThierry Reding #address-cells = <1>; 19973db6d3baSThierry Reding #size-cells = <0>; 19983db6d3baSThierry Reding }; 19993db6d3baSThierry Reding }; 20003db6d3baSThierry Reding 20013db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 20023db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 20033db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 20043db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 20053db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 20063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 20073db6d3baSThierry Reding clock-names = "dpaux", "parent"; 20083db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 20093db6d3baSThierry Reding reset-names = "dpaux"; 20103db6d3baSThierry Reding status = "disabled"; 20113db6d3baSThierry Reding 20123db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20133db6d3baSThierry Reding 20143db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 20153db6d3baSThierry Reding groups = "dpaux-io"; 20163db6d3baSThierry Reding function = "aux"; 20173db6d3baSThierry Reding }; 20183db6d3baSThierry Reding 20193db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 20203db6d3baSThierry Reding groups = "dpaux-io"; 20213db6d3baSThierry Reding function = "i2c"; 20223db6d3baSThierry Reding }; 20233db6d3baSThierry Reding 20243db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 20253db6d3baSThierry Reding groups = "dpaux-io"; 20263db6d3baSThierry Reding function = "off"; 20273db6d3baSThierry Reding }; 20283db6d3baSThierry Reding 20293db6d3baSThierry Reding i2c-bus { 20303db6d3baSThierry Reding #address-cells = <1>; 20313db6d3baSThierry Reding #size-cells = <0>; 20323db6d3baSThierry Reding }; 20333db6d3baSThierry Reding }; 20343db6d3baSThierry Reding 20353db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 20363db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 20373db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 20383db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 20393db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 20403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 20413db6d3baSThierry Reding clock-names = "dpaux", "parent"; 20423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 20433db6d3baSThierry Reding reset-names = "dpaux"; 20443db6d3baSThierry Reding status = "disabled"; 20453db6d3baSThierry Reding 20463db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 20473db6d3baSThierry Reding 20483db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 20493db6d3baSThierry Reding groups = "dpaux-io"; 20503db6d3baSThierry Reding function = "aux"; 20513db6d3baSThierry Reding }; 20523db6d3baSThierry Reding 20533db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 20543db6d3baSThierry Reding groups = "dpaux-io"; 20553db6d3baSThierry Reding function = "i2c"; 20563db6d3baSThierry Reding }; 20573db6d3baSThierry Reding 20583db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 20593db6d3baSThierry Reding groups = "dpaux-io"; 20603db6d3baSThierry Reding function = "off"; 20613db6d3baSThierry Reding }; 20623db6d3baSThierry Reding 20633db6d3baSThierry Reding i2c-bus { 20643db6d3baSThierry Reding #address-cells = <1>; 20653db6d3baSThierry Reding #size-cells = <0>; 20663db6d3baSThierry Reding }; 20673db6d3baSThierry Reding }; 20683db6d3baSThierry Reding 2069f7eb2785SJon Hunter nvenc@15a80000 { 2070f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2071f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2072f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2073f7eb2785SJon Hunter clock-names = "nvenc"; 2074f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2075f7eb2785SJon Hunter reset-names = "nvenc"; 2076f7eb2785SJon Hunter 2077f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2078f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2079f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2080f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2081f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2082f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2083f7eb2785SJon Hunter dma-coherent; 2084f7eb2785SJon Hunter 2085f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2086f7eb2785SJon Hunter }; 2087f7eb2785SJon Hunter 20883db6d3baSThierry Reding sor0: sor@15b00000 { 20893db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 20903db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 20913db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 20923db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 20933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 20943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 20953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 20963db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 20973db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 20983db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 20993db6d3baSThierry Reding "pad"; 21003db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 21013db6d3baSThierry Reding reset-names = "sor"; 21023db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 21033db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 21043db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 21053db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21063db6d3baSThierry Reding status = "disabled"; 21073db6d3baSThierry Reding 21083db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21093db6d3baSThierry Reding nvidia,interface = <0>; 21103db6d3baSThierry Reding }; 21113db6d3baSThierry Reding 21123db6d3baSThierry Reding sor1: sor@15b40000 { 21133db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2114939e7430SThierry Reding reg = <0x15b40000 0x40000>; 21153db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 21163db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 21173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 21183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 21193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21203db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 21223db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21233db6d3baSThierry Reding "pad"; 21243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 21253db6d3baSThierry Reding reset-names = "sor"; 21263db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 21273db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 21283db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 21293db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21303db6d3baSThierry Reding status = "disabled"; 21313db6d3baSThierry Reding 21323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21333db6d3baSThierry Reding nvidia,interface = <1>; 21343db6d3baSThierry Reding }; 21353db6d3baSThierry Reding 21363db6d3baSThierry Reding sor2: sor@15b80000 { 21373db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21383db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 21393db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 21403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 21413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 21423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 21433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21443db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 21463db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21473db6d3baSThierry Reding "pad"; 21483db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 21493db6d3baSThierry Reding reset-names = "sor"; 21503db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 21513db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 21523db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 21533db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21543db6d3baSThierry Reding status = "disabled"; 21553db6d3baSThierry Reding 21563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21573db6d3baSThierry Reding nvidia,interface = <2>; 21583db6d3baSThierry Reding }; 21593db6d3baSThierry Reding 21603db6d3baSThierry Reding sor3: sor@15bc0000 { 21613db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 21623db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 21633db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 21643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 21653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 21663db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 21673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 21683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 21693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 21703db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 21713db6d3baSThierry Reding "pad"; 21723db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 21733db6d3baSThierry Reding reset-names = "sor"; 21743db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 21753db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 21763db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 21773db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 21783db6d3baSThierry Reding status = "disabled"; 21793db6d3baSThierry Reding 21803db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21813db6d3baSThierry Reding nvidia,interface = <3>; 21823db6d3baSThierry Reding }; 21833db6d3baSThierry Reding }; 21840f134e39SThierry Reding 21850f134e39SThierry Reding gpu@17000000 { 21860f134e39SThierry Reding compatible = "nvidia,gv11b"; 2187818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2188818ae79aSThierry Reding <0x18000000 0x1000000>; 21890f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 21900f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 21910f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 21920f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 21930f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 21940f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 21950f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 21960f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 21970f134e39SThierry Reding reset-names = "gpu"; 21980f134e39SThierry Reding dma-coherent; 21990f134e39SThierry Reding 22000f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 22010f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 22020f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 22030f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 22040f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 22050f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 22060f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 22070f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 22080f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 22090f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 22100f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 22110f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 22120f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 22130f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 22140f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 22150f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 22160f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 22170f134e39SThierry Reding }; 22185425fb15SMikko Perttunen }; 22195425fb15SMikko Perttunen 22202602c32fSVidya Sagar pcie@14100000 { 2221f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22222602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2223644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2224644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2225644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2226644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22272602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22282602c32fSVidya Sagar 22292602c32fSVidya Sagar status = "disabled"; 22302602c32fSVidya Sagar 22312602c32fSVidya Sagar #address-cells = <3>; 22322602c32fSVidya Sagar #size-cells = <2>; 22332602c32fSVidya Sagar device_type = "pci"; 22342602c32fSVidya Sagar num-lanes = <1>; 22352602c32fSVidya Sagar linux,pci-domain = <1>; 22362602c32fSVidya Sagar 22372602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 22382602c32fSVidya Sagar clock-names = "core"; 22392602c32fSVidya Sagar 22402602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 22412602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 22422602c32fSVidya Sagar reset-names = "apb", "core"; 22432602c32fSVidya Sagar 22442602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22452602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22462602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22472602c32fSVidya Sagar 22482602c32fSVidya Sagar #interrupt-cells = <1>; 22492602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22502602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 22512602c32fSVidya Sagar 22522602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 22532602c32fSVidya Sagar 22542602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22552602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22562602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22572602c32fSVidya Sagar 22582602c32fSVidya Sagar bus-range = <0x0 0xff>; 2259d5237c7cSThierry Reding 22608a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 22618a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 22628a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2263d5237c7cSThierry Reding 2264d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2265d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2266ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2267ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2268ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2269ba02920cSVidya Sagar dma-coherent; 22702602c32fSVidya Sagar }; 22712602c32fSVidya Sagar 22722602c32fSVidya Sagar pcie@14120000 { 2273f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22742602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2275644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2276644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2277644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2278644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22792602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22802602c32fSVidya Sagar 22812602c32fSVidya Sagar status = "disabled"; 22822602c32fSVidya Sagar 22832602c32fSVidya Sagar #address-cells = <3>; 22842602c32fSVidya Sagar #size-cells = <2>; 22852602c32fSVidya Sagar device_type = "pci"; 22862602c32fSVidya Sagar num-lanes = <1>; 22872602c32fSVidya Sagar linux,pci-domain = <2>; 22882602c32fSVidya Sagar 22892602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 22902602c32fSVidya Sagar clock-names = "core"; 22912602c32fSVidya Sagar 22922602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 22932602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 22942602c32fSVidya Sagar reset-names = "apb", "core"; 22952602c32fSVidya Sagar 22962602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22972602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22982602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22992602c32fSVidya Sagar 23002602c32fSVidya Sagar #interrupt-cells = <1>; 23012602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23022602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 23032602c32fSVidya Sagar 23042602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 23052602c32fSVidya Sagar 23062602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23072602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23082602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23092602c32fSVidya Sagar 23102602c32fSVidya Sagar bus-range = <0x0 0xff>; 2311d5237c7cSThierry Reding 23128a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23138a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 23148a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2315d5237c7cSThierry Reding 2316d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2317d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2318ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2319ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2320ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2321ba02920cSVidya Sagar dma-coherent; 23222602c32fSVidya Sagar }; 23232602c32fSVidya Sagar 23242602c32fSVidya Sagar pcie@14140000 { 2325f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23262602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2327644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2328644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2329644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2330644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23312602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23322602c32fSVidya Sagar 23332602c32fSVidya Sagar status = "disabled"; 23342602c32fSVidya Sagar 23352602c32fSVidya Sagar #address-cells = <3>; 23362602c32fSVidya Sagar #size-cells = <2>; 23372602c32fSVidya Sagar device_type = "pci"; 23382602c32fSVidya Sagar num-lanes = <1>; 23392602c32fSVidya Sagar linux,pci-domain = <3>; 23402602c32fSVidya Sagar 23412602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 23422602c32fSVidya Sagar clock-names = "core"; 23432602c32fSVidya Sagar 23442602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 23452602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 23462602c32fSVidya Sagar reset-names = "apb", "core"; 23472602c32fSVidya Sagar 23482602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23492602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23502602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23512602c32fSVidya Sagar 23522602c32fSVidya Sagar #interrupt-cells = <1>; 23532602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23542602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 23552602c32fSVidya Sagar 23562602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 23572602c32fSVidya Sagar 23582602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23592602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23602602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23612602c32fSVidya Sagar 23622602c32fSVidya Sagar bus-range = <0x0 0xff>; 2363d5237c7cSThierry Reding 23648a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23658a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 23668a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2367d5237c7cSThierry Reding 2368d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2369d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2370ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2371ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2372ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2373ba02920cSVidya Sagar dma-coherent; 23742602c32fSVidya Sagar }; 23752602c32fSVidya Sagar 23762602c32fSVidya Sagar pcie@14160000 { 2377f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23782602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2379644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2380644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2381644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2382644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23832602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23842602c32fSVidya Sagar 23852602c32fSVidya Sagar status = "disabled"; 23862602c32fSVidya Sagar 23872602c32fSVidya Sagar #address-cells = <3>; 23882602c32fSVidya Sagar #size-cells = <2>; 23892602c32fSVidya Sagar device_type = "pci"; 23902602c32fSVidya Sagar num-lanes = <4>; 23912602c32fSVidya Sagar linux,pci-domain = <4>; 23922602c32fSVidya Sagar 23932602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 23942602c32fSVidya Sagar clock-names = "core"; 23952602c32fSVidya Sagar 23962602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 23972602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 23982602c32fSVidya Sagar reset-names = "apb", "core"; 23992602c32fSVidya Sagar 24002602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24012602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24022602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24032602c32fSVidya Sagar 24042602c32fSVidya Sagar #interrupt-cells = <1>; 24052602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24062602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 24072602c32fSVidya Sagar 24082602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 24092602c32fSVidya Sagar 24102602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24112602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24122602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24132602c32fSVidya Sagar 24142602c32fSVidya Sagar bus-range = <0x0 0xff>; 2415d5237c7cSThierry Reding 24168a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24178a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24188a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2419d5237c7cSThierry Reding 2420d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2421d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2422ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2423ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2424ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2425ba02920cSVidya Sagar dma-coherent; 24262602c32fSVidya Sagar }; 24272602c32fSVidya Sagar 24282602c32fSVidya Sagar pcie@14180000 { 2429f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24302602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2431644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2432644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2433644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2434644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24352602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24362602c32fSVidya Sagar 24372602c32fSVidya Sagar status = "disabled"; 24382602c32fSVidya Sagar 24392602c32fSVidya Sagar #address-cells = <3>; 24402602c32fSVidya Sagar #size-cells = <2>; 24412602c32fSVidya Sagar device_type = "pci"; 24422602c32fSVidya Sagar num-lanes = <8>; 24432602c32fSVidya Sagar linux,pci-domain = <0>; 24442602c32fSVidya Sagar 24452602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 24462602c32fSVidya Sagar clock-names = "core"; 24472602c32fSVidya Sagar 24482602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 24492602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 24502602c32fSVidya Sagar reset-names = "apb", "core"; 24512602c32fSVidya Sagar 24522602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24532602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24542602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24552602c32fSVidya Sagar 24562602c32fSVidya Sagar #interrupt-cells = <1>; 24572602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24582602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 24592602c32fSVidya Sagar 24602602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 24612602c32fSVidya Sagar 24622602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24632602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24642602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24652602c32fSVidya Sagar 24662602c32fSVidya Sagar bus-range = <0x0 0xff>; 2467d5237c7cSThierry Reding 24688a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 24698a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 24708a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2471d5237c7cSThierry Reding 2472d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2473d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2474ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2475ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2476ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2477ba02920cSVidya Sagar dma-coherent; 24782602c32fSVidya Sagar }; 24792602c32fSVidya Sagar 24802602c32fSVidya Sagar pcie@141a0000 { 2481f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24822602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2483644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2484644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2485644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2486644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24872602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24882602c32fSVidya Sagar 24892602c32fSVidya Sagar status = "disabled"; 24902602c32fSVidya Sagar 24912602c32fSVidya Sagar #address-cells = <3>; 24922602c32fSVidya Sagar #size-cells = <2>; 24932602c32fSVidya Sagar device_type = "pci"; 24942602c32fSVidya Sagar num-lanes = <8>; 24952602c32fSVidya Sagar linux,pci-domain = <5>; 24962602c32fSVidya Sagar 2497dbb72e2cSVidya Sagar pinctrl-names = "default"; 2498dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2499dbb72e2cSVidya Sagar 2500c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2501c453cc9eSThierry Reding clock-names = "core"; 25022602c32fSVidya Sagar 25032602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 25042602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 25052602c32fSVidya Sagar reset-names = "apb", "core"; 25062602c32fSVidya Sagar 25072602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25082602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25092602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25102602c32fSVidya Sagar 25112602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 25122602c32fSVidya Sagar 25132602c32fSVidya Sagar #interrupt-cells = <1>; 25142602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25152602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 25162602c32fSVidya Sagar 25172602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25182602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25192602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25202602c32fSVidya Sagar 25212602c32fSVidya Sagar bus-range = <0x0 0xff>; 2522d5237c7cSThierry Reding 25238a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25248a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25258a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2526d5237c7cSThierry Reding 2527d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2528d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2529ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2530ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2531ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2532ba02920cSVidya Sagar dma-coherent; 25332602c32fSVidya Sagar }; 25342602c32fSVidya Sagar 2535b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2536bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25370c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2538644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2539644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2540644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2541644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25420c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25430c988b73SVidya Sagar 25440c988b73SVidya Sagar status = "disabled"; 25450c988b73SVidya Sagar 25460c988b73SVidya Sagar num-lanes = <4>; 25470c988b73SVidya Sagar num-ib-windows = <2>; 25480c988b73SVidya Sagar num-ob-windows = <8>; 25490c988b73SVidya Sagar 25500c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25510c988b73SVidya Sagar clock-names = "core"; 25520c988b73SVidya Sagar 25530c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25540c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25550c988b73SVidya Sagar reset-names = "apb", "core"; 25560c988b73SVidya Sagar 25570c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25580c988b73SVidya Sagar interrupt-names = "intr"; 25590c988b73SVidya Sagar 25600c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 25610c988b73SVidya Sagar 25620c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 25630c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25640c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2565ba02920cSVidya Sagar 2566ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2567ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2568ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2569ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2570ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2571ba02920cSVidya Sagar dma-coherent; 25720c988b73SVidya Sagar }; 25730c988b73SVidya Sagar 2574b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2575bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 25760c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2577644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2578644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2579644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2580644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25810c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25820c988b73SVidya Sagar 25830c988b73SVidya Sagar status = "disabled"; 25840c988b73SVidya Sagar 25850c988b73SVidya Sagar num-lanes = <8>; 25860c988b73SVidya Sagar num-ib-windows = <2>; 25870c988b73SVidya Sagar num-ob-windows = <8>; 25880c988b73SVidya Sagar 25890c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 25900c988b73SVidya Sagar clock-names = "core"; 25910c988b73SVidya Sagar 25920c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 25930c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 25940c988b73SVidya Sagar reset-names = "apb", "core"; 25950c988b73SVidya Sagar 25960c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25970c988b73SVidya Sagar interrupt-names = "intr"; 25980c988b73SVidya Sagar 25990c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 26000c988b73SVidya Sagar 26010c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 26020c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26030c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2604ba02920cSVidya Sagar 2605ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2606ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2607ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2608ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2609ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2610ba02920cSVidya Sagar dma-coherent; 26110c988b73SVidya Sagar }; 26120c988b73SVidya Sagar 2613b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2614bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 26150c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2616644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2617644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2618644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2619644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26200c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26210c988b73SVidya Sagar 26220c988b73SVidya Sagar status = "disabled"; 26230c988b73SVidya Sagar 26240c988b73SVidya Sagar num-lanes = <8>; 26250c988b73SVidya Sagar num-ib-windows = <2>; 26260c988b73SVidya Sagar num-ob-windows = <8>; 26270c988b73SVidya Sagar 26280c988b73SVidya Sagar pinctrl-names = "default"; 26290c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 26300c988b73SVidya Sagar 26310c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 26320c988b73SVidya Sagar clock-names = "core"; 26330c988b73SVidya Sagar 26340c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26350c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26360c988b73SVidya Sagar reset-names = "apb", "core"; 26370c988b73SVidya Sagar 26380c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26390c988b73SVidya Sagar interrupt-names = "intr"; 26400c988b73SVidya Sagar 26410c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 26420c988b73SVidya Sagar 26430c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 26440c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26450c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2646ba02920cSVidya Sagar 2647ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2648ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2649ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2650ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2651ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2652ba02920cSVidya Sagar dma-coherent; 26530c988b73SVidya Sagar }; 26540c988b73SVidya Sagar 2655e867fe41SThierry Reding sram@40000000 { 26565425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 26575425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 26585425fb15SMikko Perttunen #address-cells = <1>; 26595425fb15SMikko Perttunen #size-cells = <1>; 26605425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 26615425fb15SMikko Perttunen 2662e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 26635425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 26645425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 26655425fb15SMikko Perttunen pool; 26665425fb15SMikko Perttunen }; 26675425fb15SMikko Perttunen 2668e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 26695425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 26705425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 26715425fb15SMikko Perttunen pool; 26725425fb15SMikko Perttunen }; 26735425fb15SMikko Perttunen }; 26745425fb15SMikko Perttunen 26755425fb15SMikko Perttunen bpmp: bpmp { 26765425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 26775425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 26785425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 26797fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 26805425fb15SMikko Perttunen #clock-cells = <1>; 26815425fb15SMikko Perttunen #reset-cells = <1>; 26825425fb15SMikko Perttunen #power-domain-cells = <1>; 2683d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2684d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2685d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2686d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2687d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2688c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 26895425fb15SMikko Perttunen 26905425fb15SMikko Perttunen bpmp_i2c: i2c { 26915425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 26925425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 26935425fb15SMikko Perttunen #address-cells = <1>; 26945425fb15SMikko Perttunen #size-cells = <0>; 26955425fb15SMikko Perttunen }; 26965425fb15SMikko Perttunen 26975425fb15SMikko Perttunen bpmp_thermal: thermal { 26985425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 26995425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 27005425fb15SMikko Perttunen }; 27015425fb15SMikko Perttunen }; 27025425fb15SMikko Perttunen 27037780a034SMikko Perttunen cpus { 2704d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2705d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 27067780a034SMikko Perttunen #address-cells = <1>; 27077780a034SMikko Perttunen #size-cells = <0>; 27087780a034SMikko Perttunen 2709b45d322cSThierry Reding cpu0_0: cpu@0 { 271031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27117780a034SMikko Perttunen device_type = "cpu"; 2712b45d322cSThierry Reding reg = <0x000>; 27137780a034SMikko Perttunen enable-method = "psci"; 2714b45d322cSThierry Reding i-cache-size = <131072>; 2715b45d322cSThierry Reding i-cache-line-size = <64>; 2716b45d322cSThierry Reding i-cache-sets = <512>; 2717b45d322cSThierry Reding d-cache-size = <65536>; 2718b45d322cSThierry Reding d-cache-line-size = <64>; 2719b45d322cSThierry Reding d-cache-sets = <256>; 2720b45d322cSThierry Reding next-level-cache = <&l2c_0>; 27217780a034SMikko Perttunen }; 27227780a034SMikko Perttunen 2723b45d322cSThierry Reding cpu0_1: cpu@1 { 272431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27257780a034SMikko Perttunen device_type = "cpu"; 2726b45d322cSThierry Reding reg = <0x001>; 27277780a034SMikko Perttunen enable-method = "psci"; 2728b45d322cSThierry Reding i-cache-size = <131072>; 2729b45d322cSThierry Reding i-cache-line-size = <64>; 2730b45d322cSThierry Reding i-cache-sets = <512>; 2731b45d322cSThierry Reding d-cache-size = <65536>; 2732b45d322cSThierry Reding d-cache-line-size = <64>; 2733b45d322cSThierry Reding d-cache-sets = <256>; 2734b45d322cSThierry Reding next-level-cache = <&l2c_0>; 27357780a034SMikko Perttunen }; 27367780a034SMikko Perttunen 2737b45d322cSThierry Reding cpu1_0: cpu@100 { 273831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27397780a034SMikko Perttunen device_type = "cpu"; 27407780a034SMikko Perttunen reg = <0x100>; 27417780a034SMikko Perttunen enable-method = "psci"; 2742b45d322cSThierry Reding i-cache-size = <131072>; 2743b45d322cSThierry Reding i-cache-line-size = <64>; 2744b45d322cSThierry Reding i-cache-sets = <512>; 2745b45d322cSThierry Reding d-cache-size = <65536>; 2746b45d322cSThierry Reding d-cache-line-size = <64>; 2747b45d322cSThierry Reding d-cache-sets = <256>; 2748b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27497780a034SMikko Perttunen }; 27507780a034SMikko Perttunen 2751b45d322cSThierry Reding cpu1_1: cpu@101 { 275231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27537780a034SMikko Perttunen device_type = "cpu"; 27547780a034SMikko Perttunen reg = <0x101>; 27557780a034SMikko Perttunen enable-method = "psci"; 2756b45d322cSThierry Reding i-cache-size = <131072>; 2757b45d322cSThierry Reding i-cache-line-size = <64>; 2758b45d322cSThierry Reding i-cache-sets = <512>; 2759b45d322cSThierry Reding d-cache-size = <65536>; 2760b45d322cSThierry Reding d-cache-line-size = <64>; 2761b45d322cSThierry Reding d-cache-sets = <256>; 2762b45d322cSThierry Reding next-level-cache = <&l2c_1>; 27637780a034SMikko Perttunen }; 27647780a034SMikko Perttunen 2765b45d322cSThierry Reding cpu2_0: cpu@200 { 276631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27677780a034SMikko Perttunen device_type = "cpu"; 27687780a034SMikko Perttunen reg = <0x200>; 27697780a034SMikko Perttunen enable-method = "psci"; 2770b45d322cSThierry Reding i-cache-size = <131072>; 2771b45d322cSThierry Reding i-cache-line-size = <64>; 2772b45d322cSThierry Reding i-cache-sets = <512>; 2773b45d322cSThierry Reding d-cache-size = <65536>; 2774b45d322cSThierry Reding d-cache-line-size = <64>; 2775b45d322cSThierry Reding d-cache-sets = <256>; 2776b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27777780a034SMikko Perttunen }; 27787780a034SMikko Perttunen 2779b45d322cSThierry Reding cpu2_1: cpu@201 { 278031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27817780a034SMikko Perttunen device_type = "cpu"; 27827780a034SMikko Perttunen reg = <0x201>; 27837780a034SMikko Perttunen enable-method = "psci"; 2784b45d322cSThierry Reding i-cache-size = <131072>; 2785b45d322cSThierry Reding i-cache-line-size = <64>; 2786b45d322cSThierry Reding i-cache-sets = <512>; 2787b45d322cSThierry Reding d-cache-size = <65536>; 2788b45d322cSThierry Reding d-cache-line-size = <64>; 2789b45d322cSThierry Reding d-cache-sets = <256>; 2790b45d322cSThierry Reding next-level-cache = <&l2c_2>; 27917780a034SMikko Perttunen }; 27927780a034SMikko Perttunen 2793b45d322cSThierry Reding cpu3_0: cpu@300 { 279431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 27957780a034SMikko Perttunen device_type = "cpu"; 2796b45d322cSThierry Reding reg = <0x300>; 27977780a034SMikko Perttunen enable-method = "psci"; 2798b45d322cSThierry Reding i-cache-size = <131072>; 2799b45d322cSThierry Reding i-cache-line-size = <64>; 2800b45d322cSThierry Reding i-cache-sets = <512>; 2801b45d322cSThierry Reding d-cache-size = <65536>; 2802b45d322cSThierry Reding d-cache-line-size = <64>; 2803b45d322cSThierry Reding d-cache-sets = <256>; 2804b45d322cSThierry Reding next-level-cache = <&l2c_3>; 28057780a034SMikko Perttunen }; 28067780a034SMikko Perttunen 2807b45d322cSThierry Reding cpu3_1: cpu@301 { 280831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28097780a034SMikko Perttunen device_type = "cpu"; 2810b45d322cSThierry Reding reg = <0x301>; 28117780a034SMikko Perttunen enable-method = "psci"; 2812b45d322cSThierry Reding i-cache-size = <131072>; 2813b45d322cSThierry Reding i-cache-line-size = <64>; 2814b45d322cSThierry Reding i-cache-sets = <512>; 2815b45d322cSThierry Reding d-cache-size = <65536>; 2816b45d322cSThierry Reding d-cache-line-size = <64>; 2817b45d322cSThierry Reding d-cache-sets = <256>; 2818b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2819b45d322cSThierry Reding }; 2820b45d322cSThierry Reding 2821b45d322cSThierry Reding cpu-map { 2822b45d322cSThierry Reding cluster0 { 2823b45d322cSThierry Reding core0 { 2824b45d322cSThierry Reding cpu = <&cpu0_0>; 2825b45d322cSThierry Reding }; 2826b45d322cSThierry Reding 2827b45d322cSThierry Reding core1 { 2828b45d322cSThierry Reding cpu = <&cpu0_1>; 2829b45d322cSThierry Reding }; 2830b45d322cSThierry Reding }; 2831b45d322cSThierry Reding 2832b45d322cSThierry Reding cluster1 { 2833b45d322cSThierry Reding core0 { 2834b45d322cSThierry Reding cpu = <&cpu1_0>; 2835b45d322cSThierry Reding }; 2836b45d322cSThierry Reding 2837b45d322cSThierry Reding core1 { 2838b45d322cSThierry Reding cpu = <&cpu1_1>; 2839b45d322cSThierry Reding }; 2840b45d322cSThierry Reding }; 2841b45d322cSThierry Reding 2842b45d322cSThierry Reding cluster2 { 2843b45d322cSThierry Reding core0 { 2844b45d322cSThierry Reding cpu = <&cpu2_0>; 2845b45d322cSThierry Reding }; 2846b45d322cSThierry Reding 2847b45d322cSThierry Reding core1 { 2848b45d322cSThierry Reding cpu = <&cpu2_1>; 2849b45d322cSThierry Reding }; 2850b45d322cSThierry Reding }; 2851b45d322cSThierry Reding 2852b45d322cSThierry Reding cluster3 { 2853b45d322cSThierry Reding core0 { 2854b45d322cSThierry Reding cpu = <&cpu3_0>; 2855b45d322cSThierry Reding }; 2856b45d322cSThierry Reding 2857b45d322cSThierry Reding core1 { 2858b45d322cSThierry Reding cpu = <&cpu3_1>; 2859b45d322cSThierry Reding }; 2860b45d322cSThierry Reding }; 2861b45d322cSThierry Reding }; 2862b45d322cSThierry Reding 2863b45d322cSThierry Reding l2c_0: l2-cache0 { 2864b45d322cSThierry Reding cache-size = <2097152>; 2865b45d322cSThierry Reding cache-line-size = <64>; 2866b45d322cSThierry Reding cache-sets = <2048>; 2867b45d322cSThierry Reding next-level-cache = <&l3c>; 2868b45d322cSThierry Reding }; 2869b45d322cSThierry Reding 2870b45d322cSThierry Reding l2c_1: l2-cache1 { 2871b45d322cSThierry Reding cache-size = <2097152>; 2872b45d322cSThierry Reding cache-line-size = <64>; 2873b45d322cSThierry Reding cache-sets = <2048>; 2874b45d322cSThierry Reding next-level-cache = <&l3c>; 2875b45d322cSThierry Reding }; 2876b45d322cSThierry Reding 2877b45d322cSThierry Reding l2c_2: l2-cache2 { 2878b45d322cSThierry Reding cache-size = <2097152>; 2879b45d322cSThierry Reding cache-line-size = <64>; 2880b45d322cSThierry Reding cache-sets = <2048>; 2881b45d322cSThierry Reding next-level-cache = <&l3c>; 2882b45d322cSThierry Reding }; 2883b45d322cSThierry Reding 2884b45d322cSThierry Reding l2c_3: l2-cache3 { 2885b45d322cSThierry Reding cache-size = <2097152>; 2886b45d322cSThierry Reding cache-line-size = <64>; 2887b45d322cSThierry Reding cache-sets = <2048>; 2888b45d322cSThierry Reding next-level-cache = <&l3c>; 2889b45d322cSThierry Reding }; 2890b45d322cSThierry Reding 2891b45d322cSThierry Reding l3c: l3-cache { 2892b45d322cSThierry Reding cache-size = <4194304>; 2893b45d322cSThierry Reding cache-line-size = <64>; 2894b45d322cSThierry Reding cache-sets = <4096>; 28957780a034SMikko Perttunen }; 28967780a034SMikko Perttunen }; 28977780a034SMikko Perttunen 28989e79e58fSJon Hunter pmu { 2899f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 29009e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 29019e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 29029e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 29039e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 29049e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 29059e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 29069e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 29079e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 29089e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 29099e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 29109e79e58fSJon Hunter }; 29119e79e58fSJon Hunter 29127780a034SMikko Perttunen psci { 29137780a034SMikko Perttunen compatible = "arm,psci-1.0"; 29147780a034SMikko Perttunen status = "okay"; 29157780a034SMikko Perttunen method = "smc"; 29167780a034SMikko Perttunen }; 29177780a034SMikko Perttunen 29185b4f6323SSameer Pujar sound { 29195b4f6323SSameer Pujar status = "disabled"; 29205b4f6323SSameer Pujar 29215b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 29225b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 29235b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 29245b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 29255b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 29265b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 29275b4f6323SSameer Pujar assigned-clock-parents = <0>, 29285b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 29295b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 29305b4f6323SSameer Pujar /* 29315b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 29325b4f6323SSameer Pujar * for this to work and oscillate between base rates required 29335b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 29345b4f6323SSameer Pujar */ 29355b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 29365b4f6323SSameer Pujar }; 29375b4f6323SSameer Pujar 293899d9bde5SThierry Reding tcu: serial { 2939a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2940a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2941a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2942a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2943a38570c2SMikko Perttunen }; 2944a38570c2SMikko Perttunen 2945686ba009SThierry Reding thermal-zones { 2946fe57ff53SThierry Reding cpu-thermal { 2947fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2948686ba009SThierry Reding status = "disabled"; 2949686ba009SThierry Reding }; 2950686ba009SThierry Reding 2951fe57ff53SThierry Reding gpu-thermal { 2952fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2953686ba009SThierry Reding status = "disabled"; 2954686ba009SThierry Reding }; 2955686ba009SThierry Reding 2956fe57ff53SThierry Reding aux-thermal { 2957fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2958686ba009SThierry Reding status = "disabled"; 2959686ba009SThierry Reding }; 2960686ba009SThierry Reding 2961fe57ff53SThierry Reding pllx-thermal { 2962fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2963686ba009SThierry Reding status = "disabled"; 2964686ba009SThierry Reding }; 2965686ba009SThierry Reding 2966fe57ff53SThierry Reding ao-thermal { 2967fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 2968686ba009SThierry Reding status = "disabled"; 2969686ba009SThierry Reding }; 2970686ba009SThierry Reding 2971fe57ff53SThierry Reding tj-thermal { 2972fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2973686ba009SThierry Reding status = "disabled"; 2974686ba009SThierry Reding }; 2975686ba009SThierry Reding }; 2976686ba009SThierry Reding 29775425fb15SMikko Perttunen timer { 29785425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 29795425fb15SMikko Perttunen interrupts = <GIC_PPI 13 29805425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29815425fb15SMikko Perttunen <GIC_PPI 14 29825425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29835425fb15SMikko Perttunen <GIC_PPI 11 29845425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 29855425fb15SMikko Perttunen <GIC_PPI 10 29865425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 29875425fb15SMikko Perttunen interrupt-parent = <&gic>; 2988b30be673SThierry Reding always-on; 29895425fb15SMikko Perttunen }; 29905425fb15SMikko Perttunen}; 2991