15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 26a47e173eSSumit Gupta apbmisc: misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 89*6f380a4eSThierry Reding gpio-ranges = <&pinmux 0 0 169>; 90f69ce393SMikko Perttunen }; 91f69ce393SMikko Perttunen 92a47e173eSSumit Gupta cbb-noc@2300000 { 93a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 94a47e173eSSumit Gupta reg = <0x02300000 0x1000>; 95a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 96a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 97a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 98a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 99a47e173eSSumit Gupta status = "okay"; 100a47e173eSSumit Gupta }; 101a47e173eSSumit Gupta 102a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 103a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 104a47e173eSSumit Gupta reg = <0x2390000 0x1000>, 105a47e173eSSumit Gupta <0x23a0000 0x1000>, 106a47e173eSSumit Gupta <0x23b0000 0x1000>, 107a47e173eSSumit Gupta <0x23c0000 0x1000>, 108a47e173eSSumit Gupta <0x23d0000 0x1000>, 109a47e173eSSumit Gupta <0x23e0000 0x1000>; 110a47e173eSSumit Gupta status = "okay"; 111a47e173eSSumit Gupta }; 112a47e173eSSumit Gupta 113f89b58ceSMikko Perttunen ethernet@2490000 { 11419dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 11519dc772aSThierry Reding "nvidia,tegra186-eqos", 116f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 117f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 118f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 119f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 120f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 121f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 122f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 123f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 124f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 125f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 126f89b58ceSMikko Perttunen reset-names = "eqos"; 127d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 128d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 129d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 130c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 131f89b58ceSMikko Perttunen status = "disabled"; 132f89b58ceSMikko Perttunen 133f89b58ceSMikko Perttunen snps,write-requests = <1>; 134f89b58ceSMikko Perttunen snps,read-requests = <3>; 135f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 136f89b58ceSMikko Perttunen snps,txpbl = <16>; 137f89b58ceSMikko Perttunen snps,rxpbl = <8>; 138f89b58ceSMikko Perttunen }; 139f89b58ceSMikko Perttunen 140835553b3SAkhil R gpcdma: dma-controller@2600000 { 141835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 142835553b3SAkhil R "nvidia,tegra186-gpcdma"; 143835553b3SAkhil R reg = <0x2600000 0x210000>; 144835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 145835553b3SAkhil R reset-names = "gpcdma"; 146835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 147835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 148835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 155835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 156835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 157835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 158835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 159835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 160835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 161835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 162835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 163835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 164835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 165835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 166835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 167835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 168835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 169835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 170835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 171835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 172835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 173835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 174835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 175835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 176835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 177835553b3SAkhil R #dma-cells = <1>; 178835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 179835553b3SAkhil R dma-coherent; 180835553b3SAkhil R status = "okay"; 181835553b3SAkhil R }; 182835553b3SAkhil R 1831aaa7698SThierry Reding aconnect@2900000 { 1845d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1855d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1865d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1875d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1885d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1895d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1905d2249ddSSameer Pujar #address-cells = <1>; 1915d2249ddSSameer Pujar #size-cells = <1>; 1925d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1935d2249ddSSameer Pujar status = "disabled"; 1945d2249ddSSameer Pujar 195177208f7SSameer Pujar adma: dma-controller@2930000 { 1965d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1975d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1985d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1995d2249ddSSameer Pujar interrupt-parent = <&agic>; 2005d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2015d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2025d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2105d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2115d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2125d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2135d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2145d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2155d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2165d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2175d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2185d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2195d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2205d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2215d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2225d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2235d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2245d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2255d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2265d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2275d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2285d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2295d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2305d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2315d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2325d2249ddSSameer Pujar #dma-cells = <1>; 2335d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2345d2249ddSSameer Pujar clock-names = "d_audio"; 2355d2249ddSSameer Pujar status = "disabled"; 2365d2249ddSSameer Pujar }; 2375d2249ddSSameer Pujar 2385d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2395d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2405d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2415d2249ddSSameer Pujar #interrupt-cells = <3>; 2425d2249ddSSameer Pujar interrupt-controller; 2435d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2445d2249ddSSameer Pujar <0x02a42000 0x2000>; 2455d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2465d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2475d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2485d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2495d2249ddSSameer Pujar clock-names = "clk"; 2505d2249ddSSameer Pujar status = "disabled"; 2515d2249ddSSameer Pujar }; 252177208f7SSameer Pujar 253177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 254177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 255177208f7SSameer Pujar "nvidia,tegra186-ahub"; 256177208f7SSameer Pujar reg = <0x02900800 0x800>; 257177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 258177208f7SSameer Pujar clock-names = "ahub"; 259177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 260177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 261177208f7SSameer Pujar #address-cells = <1>; 262177208f7SSameer Pujar #size-cells = <1>; 263177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 264177208f7SSameer Pujar status = "disabled"; 265177208f7SSameer Pujar 266177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 267177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 268177208f7SSameer Pujar "nvidia,tegra186-admaif"; 269177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 270177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 271177208f7SSameer Pujar <&adma 2>, <&adma 2>, 272177208f7SSameer Pujar <&adma 3>, <&adma 3>, 273177208f7SSameer Pujar <&adma 4>, <&adma 4>, 274177208f7SSameer Pujar <&adma 5>, <&adma 5>, 275177208f7SSameer Pujar <&adma 6>, <&adma 6>, 276177208f7SSameer Pujar <&adma 7>, <&adma 7>, 277177208f7SSameer Pujar <&adma 8>, <&adma 8>, 278177208f7SSameer Pujar <&adma 9>, <&adma 9>, 279177208f7SSameer Pujar <&adma 10>, <&adma 10>, 280177208f7SSameer Pujar <&adma 11>, <&adma 11>, 281177208f7SSameer Pujar <&adma 12>, <&adma 12>, 282177208f7SSameer Pujar <&adma 13>, <&adma 13>, 283177208f7SSameer Pujar <&adma 14>, <&adma 14>, 284177208f7SSameer Pujar <&adma 15>, <&adma 15>, 285177208f7SSameer Pujar <&adma 16>, <&adma 16>, 286177208f7SSameer Pujar <&adma 17>, <&adma 17>, 287177208f7SSameer Pujar <&adma 18>, <&adma 18>, 288177208f7SSameer Pujar <&adma 19>, <&adma 19>, 289177208f7SSameer Pujar <&adma 20>, <&adma 20>; 290177208f7SSameer Pujar dma-names = "rx1", "tx1", 291177208f7SSameer Pujar "rx2", "tx2", 292177208f7SSameer Pujar "rx3", "tx3", 293177208f7SSameer Pujar "rx4", "tx4", 294177208f7SSameer Pujar "rx5", "tx5", 295177208f7SSameer Pujar "rx6", "tx6", 296177208f7SSameer Pujar "rx7", "tx7", 297177208f7SSameer Pujar "rx8", "tx8", 298177208f7SSameer Pujar "rx9", "tx9", 299177208f7SSameer Pujar "rx10", "tx10", 300177208f7SSameer Pujar "rx11", "tx11", 301177208f7SSameer Pujar "rx12", "tx12", 302177208f7SSameer Pujar "rx13", "tx13", 303177208f7SSameer Pujar "rx14", "tx14", 304177208f7SSameer Pujar "rx15", "tx15", 305177208f7SSameer Pujar "rx16", "tx16", 306177208f7SSameer Pujar "rx17", "tx17", 307177208f7SSameer Pujar "rx18", "tx18", 308177208f7SSameer Pujar "rx19", "tx19", 309177208f7SSameer Pujar "rx20", "tx20"; 310177208f7SSameer Pujar status = "disabled"; 311cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 312cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 313cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 314cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 315177208f7SSameer Pujar }; 316177208f7SSameer Pujar 317177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 318177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 319177208f7SSameer Pujar "nvidia,tegra210-i2s"; 320177208f7SSameer Pujar reg = <0x2901000 0x100>; 321177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 322177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 323177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 324177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 325177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326177208f7SSameer Pujar assigned-clock-rates = <1536000>; 327177208f7SSameer Pujar sound-name-prefix = "I2S1"; 328177208f7SSameer Pujar status = "disabled"; 329177208f7SSameer Pujar }; 330177208f7SSameer Pujar 331177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 332177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 333177208f7SSameer Pujar "nvidia,tegra210-i2s"; 334177208f7SSameer Pujar reg = <0x2901100 0x100>; 335177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 336177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 337177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 338177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 339177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 340177208f7SSameer Pujar assigned-clock-rates = <1536000>; 341177208f7SSameer Pujar sound-name-prefix = "I2S2"; 342177208f7SSameer Pujar status = "disabled"; 343177208f7SSameer Pujar }; 344177208f7SSameer Pujar 345177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 346177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 347177208f7SSameer Pujar "nvidia,tegra210-i2s"; 348177208f7SSameer Pujar reg = <0x2901200 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 350177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 351177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 352177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 353177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 354177208f7SSameer Pujar assigned-clock-rates = <1536000>; 355177208f7SSameer Pujar sound-name-prefix = "I2S3"; 356177208f7SSameer Pujar status = "disabled"; 357177208f7SSameer Pujar }; 358177208f7SSameer Pujar 359177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 360177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 361177208f7SSameer Pujar "nvidia,tegra210-i2s"; 362177208f7SSameer Pujar reg = <0x2901300 0x100>; 363177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 364177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 365177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 366177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 367177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 368177208f7SSameer Pujar assigned-clock-rates = <1536000>; 369177208f7SSameer Pujar sound-name-prefix = "I2S4"; 370177208f7SSameer Pujar status = "disabled"; 371177208f7SSameer Pujar }; 372177208f7SSameer Pujar 373177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 374177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 375177208f7SSameer Pujar "nvidia,tegra210-i2s"; 376177208f7SSameer Pujar reg = <0x2901400 0x100>; 377177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 378177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 379177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 380177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 381177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 382177208f7SSameer Pujar assigned-clock-rates = <1536000>; 383177208f7SSameer Pujar sound-name-prefix = "I2S5"; 384177208f7SSameer Pujar status = "disabled"; 385177208f7SSameer Pujar }; 386177208f7SSameer Pujar 387177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 388177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 389177208f7SSameer Pujar "nvidia,tegra210-i2s"; 390177208f7SSameer Pujar reg = <0x2901500 0x100>; 391177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 392177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 393177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 394177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 395177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 396177208f7SSameer Pujar assigned-clock-rates = <1536000>; 397177208f7SSameer Pujar sound-name-prefix = "I2S6"; 398177208f7SSameer Pujar status = "disabled"; 399177208f7SSameer Pujar }; 400177208f7SSameer Pujar 401177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 402177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 403177208f7SSameer Pujar "nvidia,tegra210-dmic"; 404177208f7SSameer Pujar reg = <0x2904000 0x100>; 405177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 406177208f7SSameer Pujar clock-names = "dmic"; 407177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 408177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 409177208f7SSameer Pujar assigned-clock-rates = <3072000>; 410177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 411177208f7SSameer Pujar status = "disabled"; 412177208f7SSameer Pujar }; 413177208f7SSameer Pujar 414177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 415177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 416177208f7SSameer Pujar "nvidia,tegra210-dmic"; 417177208f7SSameer Pujar reg = <0x2904100 0x100>; 418177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 419177208f7SSameer Pujar clock-names = "dmic"; 420177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 421177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 422177208f7SSameer Pujar assigned-clock-rates = <3072000>; 423177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 424177208f7SSameer Pujar status = "disabled"; 425177208f7SSameer Pujar }; 426177208f7SSameer Pujar 427177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 428177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 429177208f7SSameer Pujar "nvidia,tegra210-dmic"; 430177208f7SSameer Pujar reg = <0x2904200 0x100>; 431177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 432177208f7SSameer Pujar clock-names = "dmic"; 433177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 434177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 435177208f7SSameer Pujar assigned-clock-rates = <3072000>; 436177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 437177208f7SSameer Pujar status = "disabled"; 438177208f7SSameer Pujar }; 439177208f7SSameer Pujar 440177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 441177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 442177208f7SSameer Pujar "nvidia,tegra210-dmic"; 443177208f7SSameer Pujar reg = <0x2904300 0x100>; 444177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 445177208f7SSameer Pujar clock-names = "dmic"; 446177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 447177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 448177208f7SSameer Pujar assigned-clock-rates = <3072000>; 449177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 450177208f7SSameer Pujar status = "disabled"; 451177208f7SSameer Pujar }; 452177208f7SSameer Pujar 453177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 454177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 455177208f7SSameer Pujar "nvidia,tegra186-dspk"; 456177208f7SSameer Pujar reg = <0x2905000 0x100>; 457177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 458177208f7SSameer Pujar clock-names = "dspk"; 459177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 460177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 461177208f7SSameer Pujar assigned-clock-rates = <12288000>; 462177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 463177208f7SSameer Pujar status = "disabled"; 464177208f7SSameer Pujar }; 465177208f7SSameer Pujar 466177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 467177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 468177208f7SSameer Pujar "nvidia,tegra186-dspk"; 469177208f7SSameer Pujar reg = <0x2905100 0x100>; 470177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 471177208f7SSameer Pujar clock-names = "dspk"; 472177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 473177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 474177208f7SSameer Pujar assigned-clock-rates = <12288000>; 475177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 476177208f7SSameer Pujar status = "disabled"; 477177208f7SSameer Pujar }; 478848f3290SSameer Pujar 479848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 480848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 481848f3290SSameer Pujar "nvidia,tegra210-sfc"; 482848f3290SSameer Pujar reg = <0x2902000 0x200>; 483848f3290SSameer Pujar sound-name-prefix = "SFC1"; 484848f3290SSameer Pujar status = "disabled"; 485848f3290SSameer Pujar }; 486848f3290SSameer Pujar 487848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 488848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 489848f3290SSameer Pujar "nvidia,tegra210-sfc"; 490848f3290SSameer Pujar reg = <0x2902200 0x200>; 491848f3290SSameer Pujar sound-name-prefix = "SFC2"; 492848f3290SSameer Pujar status = "disabled"; 493848f3290SSameer Pujar }; 494848f3290SSameer Pujar 495848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 496848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 497848f3290SSameer Pujar "nvidia,tegra210-sfc"; 498848f3290SSameer Pujar reg = <0x2902400 0x200>; 499848f3290SSameer Pujar sound-name-prefix = "SFC3"; 500848f3290SSameer Pujar status = "disabled"; 501848f3290SSameer Pujar }; 502848f3290SSameer Pujar 503848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 504848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 505848f3290SSameer Pujar "nvidia,tegra210-sfc"; 506848f3290SSameer Pujar reg = <0x2902600 0x200>; 507848f3290SSameer Pujar sound-name-prefix = "SFC4"; 508848f3290SSameer Pujar status = "disabled"; 509848f3290SSameer Pujar }; 510848f3290SSameer Pujar 511848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 512848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 513848f3290SSameer Pujar "nvidia,tegra210-mvc"; 514848f3290SSameer Pujar reg = <0x290a000 0x200>; 515848f3290SSameer Pujar sound-name-prefix = "MVC1"; 516848f3290SSameer Pujar status = "disabled"; 517848f3290SSameer Pujar }; 518848f3290SSameer Pujar 519848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 520848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 521848f3290SSameer Pujar "nvidia,tegra210-mvc"; 522848f3290SSameer Pujar reg = <0x290a200 0x200>; 523848f3290SSameer Pujar sound-name-prefix = "MVC2"; 524848f3290SSameer Pujar status = "disabled"; 525848f3290SSameer Pujar }; 526848f3290SSameer Pujar 527848f3290SSameer Pujar tegra_amx1: amx@2903000 { 528848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 529848f3290SSameer Pujar reg = <0x2903000 0x100>; 530848f3290SSameer Pujar sound-name-prefix = "AMX1"; 531848f3290SSameer Pujar status = "disabled"; 532848f3290SSameer Pujar }; 533848f3290SSameer Pujar 534848f3290SSameer Pujar tegra_amx2: amx@2903100 { 535848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 536848f3290SSameer Pujar reg = <0x2903100 0x100>; 537848f3290SSameer Pujar sound-name-prefix = "AMX2"; 538848f3290SSameer Pujar status = "disabled"; 539848f3290SSameer Pujar }; 540848f3290SSameer Pujar 541848f3290SSameer Pujar tegra_amx3: amx@2903200 { 542848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 543848f3290SSameer Pujar reg = <0x2903200 0x100>; 544848f3290SSameer Pujar sound-name-prefix = "AMX3"; 545848f3290SSameer Pujar status = "disabled"; 546848f3290SSameer Pujar }; 547848f3290SSameer Pujar 548848f3290SSameer Pujar tegra_amx4: amx@2903300 { 549848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 550848f3290SSameer Pujar reg = <0x2903300 0x100>; 551848f3290SSameer Pujar sound-name-prefix = "AMX4"; 552848f3290SSameer Pujar status = "disabled"; 553848f3290SSameer Pujar }; 554848f3290SSameer Pujar 555848f3290SSameer Pujar tegra_adx1: adx@2903800 { 556848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 557848f3290SSameer Pujar "nvidia,tegra210-adx"; 558848f3290SSameer Pujar reg = <0x2903800 0x100>; 559848f3290SSameer Pujar sound-name-prefix = "ADX1"; 560848f3290SSameer Pujar status = "disabled"; 561848f3290SSameer Pujar }; 562848f3290SSameer Pujar 563848f3290SSameer Pujar tegra_adx2: adx@2903900 { 564848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 565848f3290SSameer Pujar "nvidia,tegra210-adx"; 566848f3290SSameer Pujar reg = <0x2903900 0x100>; 567848f3290SSameer Pujar sound-name-prefix = "ADX2"; 568848f3290SSameer Pujar status = "disabled"; 569848f3290SSameer Pujar }; 570848f3290SSameer Pujar 571848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 572848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 573848f3290SSameer Pujar "nvidia,tegra210-adx"; 574848f3290SSameer Pujar reg = <0x2903a00 0x100>; 575848f3290SSameer Pujar sound-name-prefix = "ADX3"; 576848f3290SSameer Pujar status = "disabled"; 577848f3290SSameer Pujar }; 578848f3290SSameer Pujar 579848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 580848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 581848f3290SSameer Pujar "nvidia,tegra210-adx"; 582848f3290SSameer Pujar reg = <0x2903b00 0x100>; 583848f3290SSameer Pujar sound-name-prefix = "ADX4"; 584848f3290SSameer Pujar status = "disabled"; 585848f3290SSameer Pujar }; 586848f3290SSameer Pujar 5874b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5884b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 5894b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5904b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5914b6a1b7cSSameer Pujar #address-cells = <1>; 5924b6a1b7cSSameer Pujar #size-cells = <1>; 5934b6a1b7cSSameer Pujar ranges; 5944b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5954b6a1b7cSSameer Pujar status = "disabled"; 5964b6a1b7cSSameer Pujar 5974b6a1b7cSSameer Pujar equalizer@2908100 { 5984b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 5994b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 6004b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 6014b6a1b7cSSameer Pujar }; 6024b6a1b7cSSameer Pujar 6034b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 6044b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 6054b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 6064b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 6074b6a1b7cSSameer Pujar }; 6084b6a1b7cSSameer Pujar }; 6094b6a1b7cSSameer Pujar 610848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 611848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 612848f3290SSameer Pujar "nvidia,tegra210-amixer"; 613848f3290SSameer Pujar reg = <0x290bb00 0x800>; 614848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 615848f3290SSameer Pujar status = "disabled"; 616848f3290SSameer Pujar }; 61747a08153SSameer Pujar 61847a08153SSameer Pujar tegra_asrc: asrc@2910000 { 61947a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 62047a08153SSameer Pujar "nvidia,tegra186-asrc"; 62147a08153SSameer Pujar reg = <0x2910000 0x2000>; 62247a08153SSameer Pujar sound-name-prefix = "ASRC1"; 62347a08153SSameer Pujar status = "disabled"; 62447a08153SSameer Pujar }; 625177208f7SSameer Pujar }; 6265d2249ddSSameer Pujar }; 6275d2249ddSSameer Pujar 628dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 629dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 630*6f380a4eSThierry Reding reg = <0x2430000 0x17000>; 631dbb72e2cSVidya Sagar status = "okay"; 632dbb72e2cSVidya Sagar 633dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 634dbb72e2cSVidya Sagar pex_rst { 635dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 636dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 637dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6386b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 639dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 640dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 641dbb72e2cSVidya Sagar }; 642dbb72e2cSVidya Sagar }; 643dbb72e2cSVidya Sagar 644dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 645dbb72e2cSVidya Sagar clkreq { 646dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 647dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 648dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 6496b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 650dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 651dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 652dbb72e2cSVidya Sagar }; 653dbb72e2cSVidya Sagar }; 654dbb72e2cSVidya Sagar }; 655dbb72e2cSVidya Sagar 656be9b887fSThierry Reding mc: memory-controller@2c00000 { 657be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 658000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 659000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 660000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 661000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 662000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 663000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 664000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 665000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 666000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 667000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 668000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 669000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 670000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 671000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 672000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 673000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 674000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 675000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 676000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 677000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 678000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6798613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 680d5237c7cSThierry Reding #interconnect-cells = <1>; 681be9b887fSThierry Reding status = "disabled"; 682be9b887fSThierry Reding 683be9b887fSThierry Reding #address-cells = <2>; 684be9b887fSThierry Reding #size-cells = <2>; 685be9b887fSThierry Reding 686be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 687be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 688be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 689be9b887fSThierry Reding 690be9b887fSThierry Reding /* 691be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 692be9b887fSThierry Reding * controller selects the XBAR format used when memory 693be9b887fSThierry Reding * is accessed. This is used to transparently access 694be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 695be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 696be9b887fSThierry Reding * 697be9b887fSThierry Reding * As a consequence, the operating system must ensure 698be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 699be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 700be9b887fSThierry Reding * devices require access to the XBAR switch, their 701be9b887fSThierry Reding * drivers must set this bit explicitly. 702be9b887fSThierry Reding * 703be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 704be9b887fSThierry Reding */ 705be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 706be9b887fSThierry Reding 707be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 708be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 709be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 710be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 711cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 712be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 713be9b887fSThierry Reding clock-names = "emc"; 714be9b887fSThierry Reding 715d5237c7cSThierry Reding #interconnect-cells = <0>; 716d5237c7cSThierry Reding 717be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 718be9b887fSThierry Reding }; 719be9b887fSThierry Reding }; 720be9b887fSThierry Reding 7215aa9083eSThierry Reding timer@3010000 { 7225aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 7235aa9083eSThierry Reding reg = <0x03010000 0x000e0000>; 7245aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7255aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7265aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7275aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7285aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7295aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7305aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7345aa9083eSThierry Reding status = "okay"; 7355aa9083eSThierry Reding }; 7365aa9083eSThierry Reding 7375425fb15SMikko Perttunen uarta: serial@3100000 { 7385425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7395425fb15SMikko Perttunen reg = <0x03100000 0x40>; 7405425fb15SMikko Perttunen reg-shift = <2>; 7415425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7425425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7435425fb15SMikko Perttunen clock-names = "serial"; 7445425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7455425fb15SMikko Perttunen reset-names = "serial"; 7465425fb15SMikko Perttunen status = "disabled"; 7475425fb15SMikko Perttunen }; 7485425fb15SMikko Perttunen 7495425fb15SMikko Perttunen uartb: serial@3110000 { 7505425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7515425fb15SMikko Perttunen reg = <0x03110000 0x40>; 7525425fb15SMikko Perttunen reg-shift = <2>; 7535425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7545425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7555425fb15SMikko Perttunen clock-names = "serial"; 7565425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7575425fb15SMikko Perttunen reset-names = "serial"; 7585425fb15SMikko Perttunen status = "disabled"; 7595425fb15SMikko Perttunen }; 7605425fb15SMikko Perttunen 7615425fb15SMikko Perttunen uartd: serial@3130000 { 7625425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7635425fb15SMikko Perttunen reg = <0x03130000 0x40>; 7645425fb15SMikko Perttunen reg-shift = <2>; 7655425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7665425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7675425fb15SMikko Perttunen clock-names = "serial"; 7685425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7695425fb15SMikko Perttunen reset-names = "serial"; 7705425fb15SMikko Perttunen status = "disabled"; 7715425fb15SMikko Perttunen }; 7725425fb15SMikko Perttunen 7735425fb15SMikko Perttunen uarte: serial@3140000 { 7745425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7755425fb15SMikko Perttunen reg = <0x03140000 0x40>; 7765425fb15SMikko Perttunen reg-shift = <2>; 7775425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7795425fb15SMikko Perttunen clock-names = "serial"; 7805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7815425fb15SMikko Perttunen reset-names = "serial"; 7825425fb15SMikko Perttunen status = "disabled"; 7835425fb15SMikko Perttunen }; 7845425fb15SMikko Perttunen 7855425fb15SMikko Perttunen uartf: serial@3150000 { 7865425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7875425fb15SMikko Perttunen reg = <0x03150000 0x40>; 7885425fb15SMikko Perttunen reg-shift = <2>; 7895425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7905425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7915425fb15SMikko Perttunen clock-names = "serial"; 7925425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7935425fb15SMikko Perttunen reset-names = "serial"; 7945425fb15SMikko Perttunen status = "disabled"; 7955425fb15SMikko Perttunen }; 7965425fb15SMikko Perttunen 7975425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 798d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7995425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 8005425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8015425fb15SMikko Perttunen #address-cells = <1>; 8025425fb15SMikko Perttunen #size-cells = <0>; 8035425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8045425fb15SMikko Perttunen clock-names = "div-clk"; 8055425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8065425fb15SMikko Perttunen reset-names = "i2c"; 8078e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8088e442805SAkhil R dma-coherent; 8098e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8108e442805SAkhil R dma-names = "rx", "tx"; 8115425fb15SMikko Perttunen status = "disabled"; 8125425fb15SMikko Perttunen }; 8135425fb15SMikko Perttunen 8145425fb15SMikko Perttunen uarth: serial@3170000 { 8155425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8165425fb15SMikko Perttunen reg = <0x03170000 0x40>; 8175425fb15SMikko Perttunen reg-shift = <2>; 8185425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8195425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8205425fb15SMikko Perttunen clock-names = "serial"; 8215425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8225425fb15SMikko Perttunen reset-names = "serial"; 8235425fb15SMikko Perttunen status = "disabled"; 8245425fb15SMikko Perttunen }; 8255425fb15SMikko Perttunen 8265425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 827d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8285425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 8295425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8305425fb15SMikko Perttunen #address-cells = <1>; 8315425fb15SMikko Perttunen #size-cells = <0>; 8325425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8335425fb15SMikko Perttunen clock-names = "div-clk"; 8345425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8355425fb15SMikko Perttunen reset-names = "i2c"; 8368e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8378e442805SAkhil R dma-coherent; 8388e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8398e442805SAkhil R dma-names = "rx", "tx"; 8405425fb15SMikko Perttunen status = "disabled"; 8415425fb15SMikko Perttunen }; 8425425fb15SMikko Perttunen 8435425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8445425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 845d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8465425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 8475425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8485425fb15SMikko Perttunen #address-cells = <1>; 8495425fb15SMikko Perttunen #size-cells = <0>; 8505425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8515425fb15SMikko Perttunen clock-names = "div-clk"; 8525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8535425fb15SMikko Perttunen reset-names = "i2c"; 854a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 855a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 856a4131561SThierry Reding pinctrl-names = "default", "idle"; 8578e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8588e442805SAkhil R dma-coherent; 8598e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8608e442805SAkhil R dma-names = "rx", "tx"; 8615425fb15SMikko Perttunen status = "disabled"; 8625425fb15SMikko Perttunen }; 8635425fb15SMikko Perttunen 8645425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8655425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 866d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8675425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 8685425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8695425fb15SMikko Perttunen #address-cells = <1>; 8705425fb15SMikko Perttunen #size-cells = <0>; 8715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8725425fb15SMikko Perttunen clock-names = "div-clk"; 8735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8745425fb15SMikko Perttunen reset-names = "i2c"; 875a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 876a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 877a4131561SThierry Reding pinctrl-names = "default", "idle"; 8788e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8798e442805SAkhil R dma-coherent; 8808e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8818e442805SAkhil R dma-names = "rx", "tx"; 8825425fb15SMikko Perttunen status = "disabled"; 8835425fb15SMikko Perttunen }; 8845425fb15SMikko Perttunen 885a4131561SThierry Reding /* shares pads with dpaux2 */ 886a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 887d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8885425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 8895425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8905425fb15SMikko Perttunen #address-cells = <1>; 8915425fb15SMikko Perttunen #size-cells = <0>; 8925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8935425fb15SMikko Perttunen clock-names = "div-clk"; 8945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8955425fb15SMikko Perttunen reset-names = "i2c"; 896a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 897a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 898a4131561SThierry Reding pinctrl-names = "default", "idle"; 8998e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9008e442805SAkhil R dma-coherent; 9018e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 9028e442805SAkhil R dma-names = "rx", "tx"; 9035425fb15SMikko Perttunen status = "disabled"; 9045425fb15SMikko Perttunen }; 9055425fb15SMikko Perttunen 906a4131561SThierry Reding /* shares pads with dpaux3 */ 907a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 908d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9095425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 9105425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9115425fb15SMikko Perttunen #address-cells = <1>; 9125425fb15SMikko Perttunen #size-cells = <0>; 9135425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9145425fb15SMikko Perttunen clock-names = "div-clk"; 9155425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9165425fb15SMikko Perttunen reset-names = "i2c"; 917a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 918a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 919a4131561SThierry Reding pinctrl-names = "default", "idle"; 9208e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9218e442805SAkhil R dma-coherent; 9228e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9238e442805SAkhil R dma-names = "rx", "tx"; 9245425fb15SMikko Perttunen status = "disabled"; 9255425fb15SMikko Perttunen }; 9265425fb15SMikko Perttunen 92796ded827SSowjanya Komatineni spi@3270000 { 92896ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 92996ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 93096ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 93196ded827SSowjanya Komatineni #address-cells = <1>; 93296ded827SSowjanya Komatineni #size-cells = <0>; 93396ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 93496ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 93596ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 93696ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 93796ded827SSowjanya Komatineni reset-names = "qspi"; 93896ded827SSowjanya Komatineni status = "disabled"; 93996ded827SSowjanya Komatineni }; 94096ded827SSowjanya Komatineni 94196ded827SSowjanya Komatineni spi@3300000 { 94296ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 94396ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 94496ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 94596ded827SSowjanya Komatineni #address-cells = <1>; 94696ded827SSowjanya Komatineni #size-cells = <0>; 94796ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 94896ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 94996ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 95096ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 95196ded827SSowjanya Komatineni reset-names = "qspi"; 95296ded827SSowjanya Komatineni status = "disabled"; 95396ded827SSowjanya Komatineni }; 95496ded827SSowjanya Komatineni 9556a574ec7SThierry Reding pwm1: pwm@3280000 { 9566a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9576a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9586a574ec7SThierry Reding reg = <0x3280000 0x10000>; 9596a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9606a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9616a574ec7SThierry Reding reset-names = "pwm"; 9626a574ec7SThierry Reding status = "disabled"; 9636a574ec7SThierry Reding #pwm-cells = <2>; 9646a574ec7SThierry Reding }; 9656a574ec7SThierry Reding 9666a574ec7SThierry Reding pwm2: pwm@3290000 { 9676a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9686a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9696a574ec7SThierry Reding reg = <0x3290000 0x10000>; 9706a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9716a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9726a574ec7SThierry Reding reset-names = "pwm"; 9736a574ec7SThierry Reding status = "disabled"; 9746a574ec7SThierry Reding #pwm-cells = <2>; 9756a574ec7SThierry Reding }; 9766a574ec7SThierry Reding 9776a574ec7SThierry Reding pwm3: pwm@32a0000 { 9786a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9796a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9806a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 9816a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9826a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9836a574ec7SThierry Reding reset-names = "pwm"; 9846a574ec7SThierry Reding status = "disabled"; 9856a574ec7SThierry Reding #pwm-cells = <2>; 9866a574ec7SThierry Reding }; 9876a574ec7SThierry Reding 9886a574ec7SThierry Reding pwm5: pwm@32c0000 { 9896a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9906a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9916a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 9926a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9936a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9946a574ec7SThierry Reding reset-names = "pwm"; 9956a574ec7SThierry Reding status = "disabled"; 9966a574ec7SThierry Reding #pwm-cells = <2>; 9976a574ec7SThierry Reding }; 9986a574ec7SThierry Reding 9996a574ec7SThierry Reding pwm6: pwm@32d0000 { 10006a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10016a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10026a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 10036a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 10046a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 10056a574ec7SThierry Reding reset-names = "pwm"; 10066a574ec7SThierry Reding status = "disabled"; 10076a574ec7SThierry Reding #pwm-cells = <2>; 10086a574ec7SThierry Reding }; 10096a574ec7SThierry Reding 10106a574ec7SThierry Reding pwm7: pwm@32e0000 { 10116a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10126a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10136a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 10146a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 10156a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 10166a574ec7SThierry Reding reset-names = "pwm"; 10176a574ec7SThierry Reding status = "disabled"; 10186a574ec7SThierry Reding #pwm-cells = <2>; 10196a574ec7SThierry Reding }; 10206a574ec7SThierry Reding 10216a574ec7SThierry Reding pwm8: pwm@32f0000 { 10226a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10236a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10246a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 10256a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10266a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10276a574ec7SThierry Reding reset-names = "pwm"; 10286a574ec7SThierry Reding status = "disabled"; 10296a574ec7SThierry Reding #pwm-cells = <2>; 10306a574ec7SThierry Reding }; 10316a574ec7SThierry Reding 103267bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10332c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10345425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 10355425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1036c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1037c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1038c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10397ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10407ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10417ac853baSAniruddha Rao assigned-clock-parents = 10427ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10437ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10445425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10455425fb15SMikko Perttunen reset-names = "sdhci"; 1046d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1047d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1048d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1049c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1050ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1051ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1052ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10534e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10544e0f1229SSowjanya Komatineni <0x07>; 10554e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10564e0f1229SSowjanya Komatineni <0x07>; 10574e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10584e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10594e0f1229SSowjanya Komatineni <0x07>; 10604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10624e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10634e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1064ff21087eSPrathamesh Shete sd-uhs-sdr25; 1065ff21087eSPrathamesh Shete sd-uhs-sdr50; 1066ff21087eSPrathamesh Shete sd-uhs-ddr50; 1067ff21087eSPrathamesh Shete sd-uhs-sdr104; 10685425fb15SMikko Perttunen status = "disabled"; 10695425fb15SMikko Perttunen }; 10705425fb15SMikko Perttunen 107167bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10722c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10735425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 10745425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1075c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1076c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1077c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10787ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10797ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10807ac853baSAniruddha Rao assigned-clock-parents = 10817ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10827ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10835425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10845425fb15SMikko Perttunen reset-names = "sdhci"; 1085d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1086d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1087d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1088c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1089ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1090ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1091ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10924e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10934e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10944e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10964e0f1229SSowjanya Komatineni <0x07>; 10974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10994e0f1229SSowjanya Komatineni <0x07>; 11004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 11014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 11024e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 11034e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1104ff21087eSPrathamesh Shete sd-uhs-sdr25; 1105ff21087eSPrathamesh Shete sd-uhs-sdr50; 1106ff21087eSPrathamesh Shete sd-uhs-ddr50; 1107ff21087eSPrathamesh Shete sd-uhs-sdr104; 11085425fb15SMikko Perttunen status = "disabled"; 11095425fb15SMikko Perttunen }; 11105425fb15SMikko Perttunen 111167bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11122c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 11135425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 11145425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1115c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1116c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1117c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1118351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1120351648d0SSowjanya Komatineni assigned-clock-parents = 1121351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11225425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11235425fb15SMikko Perttunen reset-names = "sdhci"; 1124d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1125d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1126d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1127c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11304e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11324e0f1229SSowjanya Komatineni <0x0a>; 11334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11354e0f1229SSowjanya Komatineni <0x0a>; 11364e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11374e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11384e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1139c2fee443SPrathamesh Shete cap-mmc-highspeed; 1140c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1141c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1142c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1143c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1144dfd3cb6fSSowjanya Komatineni supports-cqe; 11455425fb15SMikko Perttunen status = "disabled"; 11465425fb15SMikko Perttunen }; 11475425fb15SMikko Perttunen 11484878cc0cSSameer Pujar hda@3510000 { 11494878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 11504878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 11514878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11524878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 115348f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 115448f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 115548f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11564878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1157146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1158146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11594878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1160d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1161d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1162d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1163c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11644878cc0cSSameer Pujar status = "disabled"; 11654878cc0cSSameer Pujar }; 11664878cc0cSSameer Pujar 1167fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1168fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1169fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1170fab7a039SJC Kuo <0x03540000 0x1000>; 1171fab7a039SJC Kuo reg-names = "padctl", "ao"; 11726450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1173fab7a039SJC Kuo 1174fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1175fab7a039SJC Kuo reset-names = "padctl"; 1176fab7a039SJC Kuo 1177fab7a039SJC Kuo status = "disabled"; 1178fab7a039SJC Kuo 1179fab7a039SJC Kuo pads { 1180fab7a039SJC Kuo usb2 { 1181fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1182fab7a039SJC Kuo clock-names = "trk"; 1183fab7a039SJC Kuo 1184fab7a039SJC Kuo lanes { 1185fab7a039SJC Kuo usb2-0 { 1186fab7a039SJC Kuo nvidia,function = "xusb"; 1187fab7a039SJC Kuo status = "disabled"; 1188fab7a039SJC Kuo #phy-cells = <0>; 1189fab7a039SJC Kuo }; 1190fab7a039SJC Kuo 1191fab7a039SJC Kuo usb2-1 { 1192fab7a039SJC Kuo nvidia,function = "xusb"; 1193fab7a039SJC Kuo status = "disabled"; 1194fab7a039SJC Kuo #phy-cells = <0>; 1195fab7a039SJC Kuo }; 1196fab7a039SJC Kuo 1197fab7a039SJC Kuo usb2-2 { 1198fab7a039SJC Kuo nvidia,function = "xusb"; 1199fab7a039SJC Kuo status = "disabled"; 1200fab7a039SJC Kuo #phy-cells = <0>; 1201fab7a039SJC Kuo }; 1202fab7a039SJC Kuo 1203fab7a039SJC Kuo usb2-3 { 1204fab7a039SJC Kuo nvidia,function = "xusb"; 1205fab7a039SJC Kuo status = "disabled"; 1206fab7a039SJC Kuo #phy-cells = <0>; 1207fab7a039SJC Kuo }; 1208fab7a039SJC Kuo }; 1209fab7a039SJC Kuo }; 1210fab7a039SJC Kuo 1211fab7a039SJC Kuo usb3 { 1212fab7a039SJC Kuo lanes { 1213fab7a039SJC Kuo usb3-0 { 1214fab7a039SJC Kuo nvidia,function = "xusb"; 1215fab7a039SJC Kuo status = "disabled"; 1216fab7a039SJC Kuo #phy-cells = <0>; 1217fab7a039SJC Kuo }; 1218fab7a039SJC Kuo 1219fab7a039SJC Kuo usb3-1 { 1220fab7a039SJC Kuo nvidia,function = "xusb"; 1221fab7a039SJC Kuo status = "disabled"; 1222fab7a039SJC Kuo #phy-cells = <0>; 1223fab7a039SJC Kuo }; 1224fab7a039SJC Kuo 1225fab7a039SJC Kuo usb3-2 { 1226fab7a039SJC Kuo nvidia,function = "xusb"; 1227fab7a039SJC Kuo status = "disabled"; 1228fab7a039SJC Kuo #phy-cells = <0>; 1229fab7a039SJC Kuo }; 1230fab7a039SJC Kuo 1231fab7a039SJC Kuo usb3-3 { 1232fab7a039SJC Kuo nvidia,function = "xusb"; 1233fab7a039SJC Kuo status = "disabled"; 1234fab7a039SJC Kuo #phy-cells = <0>; 1235fab7a039SJC Kuo }; 1236fab7a039SJC Kuo }; 1237fab7a039SJC Kuo }; 1238fab7a039SJC Kuo }; 1239fab7a039SJC Kuo 1240fab7a039SJC Kuo ports { 1241fab7a039SJC Kuo usb2-0 { 1242fab7a039SJC Kuo status = "disabled"; 1243fab7a039SJC Kuo }; 1244fab7a039SJC Kuo 1245fab7a039SJC Kuo usb2-1 { 1246fab7a039SJC Kuo status = "disabled"; 1247fab7a039SJC Kuo }; 1248fab7a039SJC Kuo 1249fab7a039SJC Kuo usb2-2 { 1250fab7a039SJC Kuo status = "disabled"; 1251fab7a039SJC Kuo }; 1252fab7a039SJC Kuo 1253fab7a039SJC Kuo usb2-3 { 1254fab7a039SJC Kuo status = "disabled"; 1255fab7a039SJC Kuo }; 1256fab7a039SJC Kuo 1257fab7a039SJC Kuo usb3-0 { 1258fab7a039SJC Kuo status = "disabled"; 1259fab7a039SJC Kuo }; 1260fab7a039SJC Kuo 1261fab7a039SJC Kuo usb3-1 { 1262fab7a039SJC Kuo status = "disabled"; 1263fab7a039SJC Kuo }; 1264fab7a039SJC Kuo 1265fab7a039SJC Kuo usb3-2 { 1266fab7a039SJC Kuo status = "disabled"; 1267fab7a039SJC Kuo }; 1268fab7a039SJC Kuo 1269fab7a039SJC Kuo usb3-3 { 1270fab7a039SJC Kuo status = "disabled"; 1271fab7a039SJC Kuo }; 1272fab7a039SJC Kuo }; 1273fab7a039SJC Kuo }; 1274fab7a039SJC Kuo 1275bc8788b2SNagarjuna Kristam usb@3550000 { 1276bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1277bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1278bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1279bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1280bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1281bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1282bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1283bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1284bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1285bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1286c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1287c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1288c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1289c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1290bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1291bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1292bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1293bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1294bc8788b2SNagarjuna Kristam status = "disabled"; 1295bc8788b2SNagarjuna Kristam }; 1296bc8788b2SNagarjuna Kristam 1297fab7a039SJC Kuo usb@3610000 { 1298fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1299fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1300fab7a039SJC Kuo <0x03600000 0x10000>; 1301fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1302fab7a039SJC Kuo 1303fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1304a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1305fab7a039SJC Kuo 1306fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1307fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1308fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1309fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1310fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1311fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1312fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1313fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1314fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1315fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1316fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1317fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1318fab7a039SJC Kuo "pll_e"; 1319c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1320c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1321c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1322c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1323fab7a039SJC Kuo 1324fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1325fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1326fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1327fab7a039SJC Kuo 1328fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1329fab7a039SJC Kuo status = "disabled"; 1330fab7a039SJC Kuo }; 1331fab7a039SJC Kuo 133209903c5eSJC Kuo fuse@3820000 { 133309903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 133409903c5eSJC Kuo reg = <0x03820000 0x10000>; 133509903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 133609903c5eSJC Kuo clock-names = "fuse"; 133709903c5eSJC Kuo }; 133809903c5eSJC Kuo 13395425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13405425fb15SMikko Perttunen compatible = "arm,gic-400"; 13415425fb15SMikko Perttunen #interrupt-cells = <3>; 13425425fb15SMikko Perttunen interrupt-controller; 13435425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 13445425fb15SMikko Perttunen <0x03882000 0x2000>, 13455425fb15SMikko Perttunen <0x03884000 0x2000>, 13465425fb15SMikko Perttunen <0x03886000 0x2000>; 13475425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13485425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13495425fb15SMikko Perttunen interrupt-parent = <&gic>; 13505425fb15SMikko Perttunen }; 13515425fb15SMikko Perttunen 1352badb80beSThierry Reding cec@3960000 { 1353badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1354badb80beSThierry Reding reg = <0x03960000 0x10000>; 1355badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1356badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1357badb80beSThierry Reding clock-names = "cec"; 1358badb80beSThierry Reding status = "disabled"; 1359badb80beSThierry Reding }; 1360badb80beSThierry Reding 13618fbd2d11SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 13628fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 13638fbd2d11SDipen Patel reg = <0x3aa0000 0x10000>; 13648fbd2d11SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 13658fbd2d11SDipen Patel nvidia,int-threshold = <1>; 13668fbd2d11SDipen Patel nvidia,slices = <11>; 13678fbd2d11SDipen Patel #timestamp-cells = <1>; 13688fbd2d11SDipen Patel status = "okay"; 13698fbd2d11SDipen Patel }; 13708fbd2d11SDipen Patel 13715425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1372cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13735425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1374a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1375a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1376a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1377a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1378a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1379a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1380a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1381a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1382a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1383a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1384a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1385a38570c2SMikko Perttunen "shared7"; 1386a38570c2SMikko Perttunen #mbox-cells = <2>; 1387a38570c2SMikko Perttunen }; 1388a38570c2SMikko Perttunen 13892602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13912602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 13922602c32fSVidya Sagar reg-names = "ctl"; 13932602c32fSVidya Sagar 13942602c32fSVidya Sagar #phy-cells = <0>; 13952602c32fSVidya Sagar }; 13962602c32fSVidya Sagar 13972602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 13982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13992602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 14002602c32fSVidya Sagar reg-names = "ctl"; 14012602c32fSVidya Sagar 14022602c32fSVidya Sagar #phy-cells = <0>; 14032602c32fSVidya Sagar }; 14042602c32fSVidya Sagar 14052602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 14062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14072602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 14082602c32fSVidya Sagar reg-names = "ctl"; 14092602c32fSVidya Sagar 14102602c32fSVidya Sagar #phy-cells = <0>; 14112602c32fSVidya Sagar }; 14122602c32fSVidya Sagar 14132602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14152602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 14162602c32fSVidya Sagar reg-names = "ctl"; 14172602c32fSVidya Sagar 14182602c32fSVidya Sagar #phy-cells = <0>; 14192602c32fSVidya Sagar }; 14202602c32fSVidya Sagar 14212602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14232602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 14242602c32fSVidya Sagar reg-names = "ctl"; 14252602c32fSVidya Sagar 14262602c32fSVidya Sagar #phy-cells = <0>; 14272602c32fSVidya Sagar }; 14282602c32fSVidya Sagar 14292602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14312602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 14322602c32fSVidya Sagar reg-names = "ctl"; 14332602c32fSVidya Sagar 14342602c32fSVidya Sagar #phy-cells = <0>; 14352602c32fSVidya Sagar }; 14362602c32fSVidya Sagar 14372602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14392602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 14402602c32fSVidya Sagar reg-names = "ctl"; 14412602c32fSVidya Sagar 14422602c32fSVidya Sagar #phy-cells = <0>; 14432602c32fSVidya Sagar }; 14442602c32fSVidya Sagar 14452602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14472602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 14482602c32fSVidya Sagar reg-names = "ctl"; 14492602c32fSVidya Sagar 14502602c32fSVidya Sagar #phy-cells = <0>; 14512602c32fSVidya Sagar }; 14522602c32fSVidya Sagar 14532602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14552602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 14562602c32fSVidya Sagar reg-names = "ctl"; 14572602c32fSVidya Sagar 14582602c32fSVidya Sagar #phy-cells = <0>; 14592602c32fSVidya Sagar }; 14602602c32fSVidya Sagar 14612602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14622602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14632602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 14642602c32fSVidya Sagar reg-names = "ctl"; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar #phy-cells = <0>; 14672602c32fSVidya Sagar }; 14682602c32fSVidya Sagar 14692602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14702602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14712602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 14722602c32fSVidya Sagar reg-names = "ctl"; 14732602c32fSVidya Sagar 14742602c32fSVidya Sagar #phy-cells = <0>; 14752602c32fSVidya Sagar }; 14762602c32fSVidya Sagar 14772602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14782602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14792602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 14802602c32fSVidya Sagar reg-names = "ctl"; 14812602c32fSVidya Sagar 14822602c32fSVidya Sagar #phy-cells = <0>; 14832602c32fSVidya Sagar }; 14842602c32fSVidya Sagar 14852602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14862602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14872602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 14882602c32fSVidya Sagar reg-names = "ctl"; 14892602c32fSVidya Sagar 14902602c32fSVidya Sagar #phy-cells = <0>; 14912602c32fSVidya Sagar }; 14922602c32fSVidya Sagar 14932602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14942602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14952602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 14962602c32fSVidya Sagar reg-names = "ctl"; 14972602c32fSVidya Sagar 14982602c32fSVidya Sagar #phy-cells = <0>; 14992602c32fSVidya Sagar }; 15002602c32fSVidya Sagar 15012602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 15022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15032602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 15042602c32fSVidya Sagar reg-names = "ctl"; 15052602c32fSVidya Sagar 15062602c32fSVidya Sagar #phy-cells = <0>; 15072602c32fSVidya Sagar }; 15082602c32fSVidya Sagar 15092602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 15102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15112602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 15122602c32fSVidya Sagar reg-names = "ctl"; 15132602c32fSVidya Sagar 15142602c32fSVidya Sagar #phy-cells = <0>; 15152602c32fSVidya Sagar }; 15162602c32fSVidya Sagar 15172602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15192602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 15202602c32fSVidya Sagar reg-names = "ctl"; 15212602c32fSVidya Sagar 15222602c32fSVidya Sagar #phy-cells = <0>; 15232602c32fSVidya Sagar }; 15242602c32fSVidya Sagar 15252602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15272602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 15282602c32fSVidya Sagar reg-names = "ctl"; 15292602c32fSVidya Sagar 15302602c32fSVidya Sagar #phy-cells = <0>; 15312602c32fSVidya Sagar }; 15322602c32fSVidya Sagar 15332602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15352602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 15362602c32fSVidya Sagar reg-names = "ctl"; 15372602c32fSVidya Sagar 15382602c32fSVidya Sagar #phy-cells = <0>; 15392602c32fSVidya Sagar }; 15402602c32fSVidya Sagar 15412602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15422602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15432602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 15442602c32fSVidya Sagar reg-names = "ctl"; 15452602c32fSVidya Sagar 15462602c32fSVidya Sagar #phy-cells = <0>; 15472602c32fSVidya Sagar }; 15482602c32fSVidya Sagar 1549a47e173eSSumit Gupta sce-noc@b600000 { 1550a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 1551a47e173eSSumit Gupta reg = <0xb600000 0x1000>; 1552a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1553a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1554a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1555a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1556a47e173eSSumit Gupta status = "okay"; 1557a47e173eSSumit Gupta }; 1558a47e173eSSumit Gupta 1559a47e173eSSumit Gupta rce-noc@be00000 { 1560a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 1561a47e173eSSumit Gupta reg = <0xbe00000 0x1000>; 1562a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1563a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1564a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1565a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1566a47e173eSSumit Gupta status = "okay"; 1567a47e173eSSumit Gupta }; 1568a47e173eSSumit Gupta 1569a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1570cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15711741e187SDipen Patel reg = <0x0c150000 0x90000>; 1572a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1573a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1574a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1575a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1576a38570c2SMikko Perttunen /* 1577a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1578a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1579a38570c2SMikko Perttunen */ 1580a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15815425fb15SMikko Perttunen #mbox-cells = <2>; 15825425fb15SMikko Perttunen }; 15835425fb15SMikko Perttunen 15848fbd2d11SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 15858fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 15868fbd2d11SDipen Patel reg = <0xc1e0000 0x10000>; 15878fbd2d11SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 15888fbd2d11SDipen Patel nvidia,int-threshold = <1>; 15898fbd2d11SDipen Patel nvidia,slices = <3>; 15908fbd2d11SDipen Patel #timestamp-cells = <1>; 15918fbd2d11SDipen Patel status = "okay"; 15928fbd2d11SDipen Patel }; 15938fbd2d11SDipen Patel 15945425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1595d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15965425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 15975425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 15985425fb15SMikko Perttunen #address-cells = <1>; 15995425fb15SMikko Perttunen #size-cells = <0>; 16005425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 16015425fb15SMikko Perttunen clock-names = "div-clk"; 16025425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 16035425fb15SMikko Perttunen reset-names = "i2c"; 16048e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16058e442805SAkhil R dma-coherent; 16068e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 16078e442805SAkhil R dma-names = "rx", "tx"; 16085425fb15SMikko Perttunen status = "disabled"; 16095425fb15SMikko Perttunen }; 16105425fb15SMikko Perttunen 16115425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1612d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 16135425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 16145425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16155425fb15SMikko Perttunen #address-cells = <1>; 16165425fb15SMikko Perttunen #size-cells = <0>; 16175425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16185425fb15SMikko Perttunen clock-names = "div-clk"; 16195425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16205425fb15SMikko Perttunen reset-names = "i2c"; 16218e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16228e442805SAkhil R dma-coherent; 16238e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16248e442805SAkhil R dma-names = "rx", "tx"; 16255425fb15SMikko Perttunen status = "disabled"; 16265425fb15SMikko Perttunen }; 16275425fb15SMikko Perttunen 16285425fb15SMikko Perttunen uartc: serial@c280000 { 16295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16305425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 16315425fb15SMikko Perttunen reg-shift = <2>; 16325425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16345425fb15SMikko Perttunen clock-names = "serial"; 16355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16365425fb15SMikko Perttunen reset-names = "serial"; 16375425fb15SMikko Perttunen status = "disabled"; 16385425fb15SMikko Perttunen }; 16395425fb15SMikko Perttunen 16405425fb15SMikko Perttunen uartg: serial@c290000 { 16415425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16425425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 16435425fb15SMikko Perttunen reg-shift = <2>; 16445425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16465425fb15SMikko Perttunen clock-names = "serial"; 16475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16485425fb15SMikko Perttunen reset-names = "serial"; 16495425fb15SMikko Perttunen status = "disabled"; 16505425fb15SMikko Perttunen }; 16515425fb15SMikko Perttunen 165237e5a31dSThierry Reding rtc: rtc@c2a0000 { 165337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 165437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 165537e5a31dSThierry Reding interrupt-parent = <&pmc>; 165637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 165737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 165837e5a31dSThierry Reding clock-names = "rtc"; 165937e5a31dSThierry Reding status = "disabled"; 166037e5a31dSThierry Reding }; 166137e5a31dSThierry Reding 16624d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16634d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16644d286331SThierry Reding reg-names = "security", "gpio"; 16654d286331SThierry Reding reg = <0xc2f0000 0x1000>, 16664d286331SThierry Reding <0xc2f1000 0x1000>; 16670a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16680a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16690a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16700a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16714d286331SThierry Reding gpio-controller; 16724d286331SThierry Reding #gpio-cells = <2>; 16734d286331SThierry Reding interrupt-controller; 16744d286331SThierry Reding #interrupt-cells = <2>; 1675*6f380a4eSThierry Reding gpio-range = <&pinmux_aon 0 0 30>; 1676*6f380a4eSThierry Reding }; 1677*6f380a4eSThierry Reding 1678*6f380a4eSThierry Reding pinmux_aon: pinmux@c300000 { 1679*6f380a4eSThierry Reding compatible = "nvidia,tegra194-pinmux-aon"; 1680*6f380a4eSThierry Reding reg = <0xc300000 0x4000>; 1681*6f380a4eSThierry Reding 1682*6f380a4eSThierry Reding status = "okay"; 16834d286331SThierry Reding }; 16844d286331SThierry Reding 16856a574ec7SThierry Reding pwm4: pwm@c340000 { 16866a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16876a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16886a574ec7SThierry Reding reg = <0xc340000 0x10000>; 16896a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16906a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16916a574ec7SThierry Reding reset-names = "pwm"; 16926a574ec7SThierry Reding status = "disabled"; 16936a574ec7SThierry Reding #pwm-cells = <2>; 16946a574ec7SThierry Reding }; 16956a574ec7SThierry Reding 169638ecf1e5SThierry Reding pmc: pmc@c360000 { 16975425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 16985425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 16995425fb15SMikko Perttunen <0x0c370000 0x10000>, 17005425fb15SMikko Perttunen <0x0c380000 0x10000>, 17015425fb15SMikko Perttunen <0x0c390000 0x10000>, 17025425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 17035425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 170438ecf1e5SThierry Reding 170538ecf1e5SThierry Reding #interrupt-cells = <2>; 170638ecf1e5SThierry Reding interrupt-controller; 1707ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1708ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1709ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1710ff21087eSPrathamesh Shete }; 1711ff21087eSPrathamesh Shete 1712ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1713ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1714ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1715ff21087eSPrathamesh Shete }; 1716ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1717ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1718ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1719ff21087eSPrathamesh Shete }; 1720ff21087eSPrathamesh Shete 1721ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1722ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1723ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1724ff21087eSPrathamesh Shete }; 1725ff21087eSPrathamesh Shete 17265425fb15SMikko Perttunen }; 17273db6d3baSThierry Reding 1728a47e173eSSumit Gupta aon-noc@c600000 { 1729a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 1730a47e173eSSumit Gupta reg = <0xc600000 0x1000>; 1731a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1732a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1733a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1734a47e173eSSumit Gupta status = "okay"; 1735a47e173eSSumit Gupta }; 1736a47e173eSSumit Gupta 1737a47e173eSSumit Gupta bpmp-noc@d600000 { 1738a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 1739a47e173eSSumit Gupta reg = <0xd600000 0x1000>; 1740a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1741a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1742a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1743a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1744a47e173eSSumit Gupta status = "okay"; 1745a47e173eSSumit Gupta }; 1746a47e173eSSumit Gupta 1747e762232fSJon Hunter iommu@10000000 { 1748e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1749e762232fSJon Hunter reg = <0x10000000 0x800000>; 1750e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1815e762232fSJon Hunter stream-match-mask = <0x7f80>; 1816e762232fSJon Hunter #global-interrupts = <1>; 1817e762232fSJon Hunter #iommu-cells = <1>; 1818e762232fSJon Hunter 1819e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1820ebea268eSJon Hunter status = "disabled"; 1821e762232fSJon Hunter }; 1822e762232fSJon Hunter 1823c7289b1cSThierry Reding smmu: iommu@12000000 { 1824c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1825c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1826c7289b1cSThierry Reding <0x11000000 0x800000>; 1827c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1829c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1893c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1894c7289b1cSThierry Reding #global-interrupts = <2>; 1895c7289b1cSThierry Reding #iommu-cells = <1>; 1896c7289b1cSThierry Reding 1897c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1898c7289b1cSThierry Reding status = "okay"; 1899c7289b1cSThierry Reding }; 1900c7289b1cSThierry Reding 19013db6d3baSThierry Reding host1x@13e00000 { 1902ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 19033db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 19043db6d3baSThierry Reding <0x13e10000 0x10000>; 19053db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 19063db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 19073db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1908052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 19093db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 19103db6d3baSThierry Reding clock-names = "host1x"; 19113db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 19123db6d3baSThierry Reding reset-names = "host1x"; 19133db6d3baSThierry Reding 19143db6d3baSThierry Reding #address-cells = <1>; 19153db6d3baSThierry Reding #size-cells = <1>; 19163db6d3baSThierry Reding 1917e25770feSMikko Perttunen ranges = <0x14800000 0x14800000 0x02800000>; 1918d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1919d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1920c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 19213db6d3baSThierry Reding 1922e30cf101SMikko Perttunen /* Context isolation domains */ 1923b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1924b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1925b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1926b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1927b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1928b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1929b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1930b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1931e30cf101SMikko Perttunen 193278a05873SMikko Perttunen nvdec@15140000 { 193378a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 193478a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 193578a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 193678a05873SMikko Perttunen clock-names = "nvdec"; 193778a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 193878a05873SMikko Perttunen reset-names = "nvdec"; 193978a05873SMikko Perttunen 194078a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 194178a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 194278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 194378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 194478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 194578a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 194678a05873SMikko Perttunen dma-coherent; 194778a05873SMikko Perttunen 194878a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 194978a05873SMikko Perttunen }; 195078a05873SMikko Perttunen 19513db6d3baSThierry Reding display-hub@15200000 { 1952aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1953611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 19543db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19553db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19563db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19573db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19583db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19593db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19603db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19613db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19623db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19633db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19653db6d3baSThierry Reding clock-names = "disp", "hub"; 19663db6d3baSThierry Reding status = "disabled"; 19673db6d3baSThierry Reding 19683db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19693db6d3baSThierry Reding 19703db6d3baSThierry Reding #address-cells = <1>; 19713db6d3baSThierry Reding #size-cells = <1>; 19723db6d3baSThierry Reding 19733db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 19743db6d3baSThierry Reding 19753db6d3baSThierry Reding display@15200000 { 19763db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19773db6d3baSThierry Reding reg = <0x15200000 0x10000>; 19783db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19803db6d3baSThierry Reding clock-names = "dc"; 19813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19823db6d3baSThierry Reding reset-names = "dc"; 19833db6d3baSThierry Reding 19843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1985d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1986d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1987d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19883db6d3baSThierry Reding 19893db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19903db6d3baSThierry Reding nvidia,head = <0>; 19913db6d3baSThierry Reding }; 19923db6d3baSThierry Reding 19933db6d3baSThierry Reding display@15210000 { 19943db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19953db6d3baSThierry Reding reg = <0x15210000 0x10000>; 19963db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19973db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 19983db6d3baSThierry Reding clock-names = "dc"; 19993db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 20003db6d3baSThierry Reding reset-names = "dc"; 20013db6d3baSThierry Reding 20023db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2003d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2004d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2005d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20063db6d3baSThierry Reding 20073db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20083db6d3baSThierry Reding nvidia,head = <1>; 20093db6d3baSThierry Reding }; 20103db6d3baSThierry Reding 20113db6d3baSThierry Reding display@15220000 { 20123db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20133db6d3baSThierry Reding reg = <0x15220000 0x10000>; 20143db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 20153db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 20163db6d3baSThierry Reding clock-names = "dc"; 20173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 20183db6d3baSThierry Reding reset-names = "dc"; 20193db6d3baSThierry Reding 20203db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2021d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2022d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2023d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20243db6d3baSThierry Reding 20253db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20263db6d3baSThierry Reding nvidia,head = <2>; 20273db6d3baSThierry Reding }; 20283db6d3baSThierry Reding 20293db6d3baSThierry Reding display@15230000 { 20303db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20313db6d3baSThierry Reding reg = <0x15230000 0x10000>; 20323db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20333db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20343db6d3baSThierry Reding clock-names = "dc"; 20353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20363db6d3baSThierry Reding reset-names = "dc"; 20373db6d3baSThierry Reding 20383db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2039d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2040d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2041d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20423db6d3baSThierry Reding 20433db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20443db6d3baSThierry Reding nvidia,head = <3>; 20453db6d3baSThierry Reding }; 20463db6d3baSThierry Reding }; 20473db6d3baSThierry Reding 20488d424ec2SThierry Reding vic@15340000 { 20498d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 20508d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 20518d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20528d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20538d424ec2SThierry Reding clock-names = "vic"; 20548d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20558d424ec2SThierry Reding reset-names = "vic"; 20568d424ec2SThierry Reding 20578d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2058d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2059d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2060d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2061c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2062a52280c8SJon Hunter dma-coherent; 20638d424ec2SThierry Reding }; 20648d424ec2SThierry Reding 2065f7eb2785SJon Hunter nvjpg@15380000 { 2066f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 2067f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 2068f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2069f7eb2785SJon Hunter clock-names = "nvjpg"; 2070f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2071f7eb2785SJon Hunter reset-names = "nvjpg"; 2072f7eb2785SJon Hunter 2073f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2074f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2075f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2076f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2077f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2078f7eb2785SJon Hunter dma-coherent; 2079f7eb2785SJon Hunter }; 2080f7eb2785SJon Hunter 208178a05873SMikko Perttunen nvdec@15480000 { 208278a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 208378a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 208478a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 208578a05873SMikko Perttunen clock-names = "nvdec"; 208678a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 208778a05873SMikko Perttunen reset-names = "nvdec"; 208878a05873SMikko Perttunen 208978a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 209078a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 209178a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 209278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 209378a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 209478a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 209578a05873SMikko Perttunen dma-coherent; 209678a05873SMikko Perttunen 209778a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 209878a05873SMikko Perttunen }; 209978a05873SMikko Perttunen 2100f7eb2785SJon Hunter nvenc@154c0000 { 2101f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2102f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 2103f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2104f7eb2785SJon Hunter clock-names = "nvenc"; 2105f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2106f7eb2785SJon Hunter reset-names = "nvenc"; 2107f7eb2785SJon Hunter 2108f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2109f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2110f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2111f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2112f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2113f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2114f7eb2785SJon Hunter dma-coherent; 2115f7eb2785SJon Hunter 2116f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2117f7eb2785SJon Hunter }; 2118f7eb2785SJon Hunter 21193db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21203db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21213db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 21223db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21233db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21243db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21253db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21273db6d3baSThierry Reding reset-names = "dpaux"; 21283db6d3baSThierry Reding status = "disabled"; 21293db6d3baSThierry Reding 21303db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21313db6d3baSThierry Reding 21323db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21333db6d3baSThierry Reding groups = "dpaux-io"; 21343db6d3baSThierry Reding function = "aux"; 21353db6d3baSThierry Reding }; 21363db6d3baSThierry Reding 21373db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21383db6d3baSThierry Reding groups = "dpaux-io"; 21393db6d3baSThierry Reding function = "i2c"; 21403db6d3baSThierry Reding }; 21413db6d3baSThierry Reding 21423db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21433db6d3baSThierry Reding groups = "dpaux-io"; 21443db6d3baSThierry Reding function = "off"; 21453db6d3baSThierry Reding }; 21463db6d3baSThierry Reding 21473db6d3baSThierry Reding i2c-bus { 21483db6d3baSThierry Reding #address-cells = <1>; 21493db6d3baSThierry Reding #size-cells = <0>; 21503db6d3baSThierry Reding }; 21513db6d3baSThierry Reding }; 21523db6d3baSThierry Reding 21533db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21543db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21553db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 21563db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21573db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21583db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21593db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21613db6d3baSThierry Reding reset-names = "dpaux"; 21623db6d3baSThierry Reding status = "disabled"; 21633db6d3baSThierry Reding 21643db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21653db6d3baSThierry Reding 21663db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21673db6d3baSThierry Reding groups = "dpaux-io"; 21683db6d3baSThierry Reding function = "aux"; 21693db6d3baSThierry Reding }; 21703db6d3baSThierry Reding 21713db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21723db6d3baSThierry Reding groups = "dpaux-io"; 21733db6d3baSThierry Reding function = "i2c"; 21743db6d3baSThierry Reding }; 21753db6d3baSThierry Reding 21763db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21773db6d3baSThierry Reding groups = "dpaux-io"; 21783db6d3baSThierry Reding function = "off"; 21793db6d3baSThierry Reding }; 21803db6d3baSThierry Reding 21813db6d3baSThierry Reding i2c-bus { 21823db6d3baSThierry Reding #address-cells = <1>; 21833db6d3baSThierry Reding #size-cells = <0>; 21843db6d3baSThierry Reding }; 21853db6d3baSThierry Reding }; 21863db6d3baSThierry Reding 21873db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21883db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21893db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 21903db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21913db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21933db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21943db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21953db6d3baSThierry Reding reset-names = "dpaux"; 21963db6d3baSThierry Reding status = "disabled"; 21973db6d3baSThierry Reding 21983db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21993db6d3baSThierry Reding 22003db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 22013db6d3baSThierry Reding groups = "dpaux-io"; 22023db6d3baSThierry Reding function = "aux"; 22033db6d3baSThierry Reding }; 22043db6d3baSThierry Reding 22053db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 22063db6d3baSThierry Reding groups = "dpaux-io"; 22073db6d3baSThierry Reding function = "i2c"; 22083db6d3baSThierry Reding }; 22093db6d3baSThierry Reding 22103db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 22113db6d3baSThierry Reding groups = "dpaux-io"; 22123db6d3baSThierry Reding function = "off"; 22133db6d3baSThierry Reding }; 22143db6d3baSThierry Reding 22153db6d3baSThierry Reding i2c-bus { 22163db6d3baSThierry Reding #address-cells = <1>; 22173db6d3baSThierry Reding #size-cells = <0>; 22183db6d3baSThierry Reding }; 22193db6d3baSThierry Reding }; 22203db6d3baSThierry Reding 22213db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22223db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 22233db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 22243db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22253db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22273db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22293db6d3baSThierry Reding reset-names = "dpaux"; 22303db6d3baSThierry Reding status = "disabled"; 22313db6d3baSThierry Reding 22323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22333db6d3baSThierry Reding 22343db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22353db6d3baSThierry Reding groups = "dpaux-io"; 22363db6d3baSThierry Reding function = "aux"; 22373db6d3baSThierry Reding }; 22383db6d3baSThierry Reding 22393db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22403db6d3baSThierry Reding groups = "dpaux-io"; 22413db6d3baSThierry Reding function = "i2c"; 22423db6d3baSThierry Reding }; 22433db6d3baSThierry Reding 22443db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22453db6d3baSThierry Reding groups = "dpaux-io"; 22463db6d3baSThierry Reding function = "off"; 22473db6d3baSThierry Reding }; 22483db6d3baSThierry Reding 22493db6d3baSThierry Reding i2c-bus { 22503db6d3baSThierry Reding #address-cells = <1>; 22513db6d3baSThierry Reding #size-cells = <0>; 22523db6d3baSThierry Reding }; 22533db6d3baSThierry Reding }; 22543db6d3baSThierry Reding 2255f7eb2785SJon Hunter nvenc@15a80000 { 2256f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2257f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2258f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2259f7eb2785SJon Hunter clock-names = "nvenc"; 2260f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2261f7eb2785SJon Hunter reset-names = "nvenc"; 2262f7eb2785SJon Hunter 2263f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2264f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2265f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2266f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2267f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2268f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2269f7eb2785SJon Hunter dma-coherent; 2270f7eb2785SJon Hunter 2271f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2272f7eb2785SJon Hunter }; 2273f7eb2785SJon Hunter 22743db6d3baSThierry Reding sor0: sor@15b00000 { 22753db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22763db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 22773db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22783db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22843db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22853db6d3baSThierry Reding "pad"; 22863db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22873db6d3baSThierry Reding reset-names = "sor"; 22883db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22893db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22903db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22913db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22923db6d3baSThierry Reding status = "disabled"; 22933db6d3baSThierry Reding 22943db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22953db6d3baSThierry Reding nvidia,interface = <0>; 22963db6d3baSThierry Reding }; 22973db6d3baSThierry Reding 22983db6d3baSThierry Reding sor1: sor@15b40000 { 22993db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2300939e7430SThierry Reding reg = <0x15b40000 0x40000>; 23013db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 23023db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 23033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 23043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 23053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 23083db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23093db6d3baSThierry Reding "pad"; 23103db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 23113db6d3baSThierry Reding reset-names = "sor"; 23123db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 23133db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 23143db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 23153db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23163db6d3baSThierry Reding status = "disabled"; 23173db6d3baSThierry Reding 23183db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23193db6d3baSThierry Reding nvidia,interface = <1>; 23203db6d3baSThierry Reding }; 23213db6d3baSThierry Reding 23223db6d3baSThierry Reding sor2: sor@15b80000 { 23233db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23243db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 23253db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23263db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23323db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23333db6d3baSThierry Reding "pad"; 23343db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23353db6d3baSThierry Reding reset-names = "sor"; 23363db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23373db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23383db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23393db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23403db6d3baSThierry Reding status = "disabled"; 23413db6d3baSThierry Reding 23423db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23433db6d3baSThierry Reding nvidia,interface = <2>; 23443db6d3baSThierry Reding }; 23453db6d3baSThierry Reding 23463db6d3baSThierry Reding sor3: sor@15bc0000 { 23473db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23483db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 23493db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23503db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23553db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23563db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23573db6d3baSThierry Reding "pad"; 23583db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23593db6d3baSThierry Reding reset-names = "sor"; 23603db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23613db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23623db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23633db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23643db6d3baSThierry Reding status = "disabled"; 23653db6d3baSThierry Reding 23663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23673db6d3baSThierry Reding nvidia,interface = <3>; 23683db6d3baSThierry Reding }; 23693db6d3baSThierry Reding }; 23700f134e39SThierry Reding 23710f134e39SThierry Reding gpu@17000000 { 23720f134e39SThierry Reding compatible = "nvidia,gv11b"; 2373818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2374818ae79aSThierry Reding <0x18000000 0x1000000>; 23750f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 23760f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 23770f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 23780f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 23790f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 23800f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 23810f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 23820f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 23830f134e39SThierry Reding reset-names = "gpu"; 23840f134e39SThierry Reding dma-coherent; 23850f134e39SThierry Reding 23860f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 23870f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 23880f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 23890f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 23900f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 23910f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 23920f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 23930f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 23940f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 23950f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 23960f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 23970f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 23980f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 23990f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 24000f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 24010f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 24020f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 24030f134e39SThierry Reding }; 24045425fb15SMikko Perttunen }; 24055425fb15SMikko Perttunen 24062602c32fSVidya Sagar pcie@14100000 { 2407f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24082602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2409644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2410644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2411644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2412644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24132602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24142602c32fSVidya Sagar 24152602c32fSVidya Sagar status = "disabled"; 24162602c32fSVidya Sagar 24172602c32fSVidya Sagar #address-cells = <3>; 24182602c32fSVidya Sagar #size-cells = <2>; 24192602c32fSVidya Sagar device_type = "pci"; 24202602c32fSVidya Sagar num-lanes = <1>; 24212602c32fSVidya Sagar linux,pci-domain = <1>; 24222602c32fSVidya Sagar 24232602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 24242602c32fSVidya Sagar clock-names = "core"; 24252602c32fSVidya Sagar 24262602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 24272602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 24282602c32fSVidya Sagar reset-names = "apb", "core"; 24292602c32fSVidya Sagar 24302602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24312602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24322602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24332602c32fSVidya Sagar 24342602c32fSVidya Sagar #interrupt-cells = <1>; 24352602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24362602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24372602c32fSVidya Sagar 24382602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 24392602c32fSVidya Sagar 24402602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24412602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24422602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24432602c32fSVidya Sagar 24442602c32fSVidya Sagar bus-range = <0x0 0xff>; 2445d5237c7cSThierry Reding 24468a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24478a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24488a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2449d5237c7cSThierry Reding 2450d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2451d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2452ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2453ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2454ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2455ba02920cSVidya Sagar dma-coherent; 24562602c32fSVidya Sagar }; 24572602c32fSVidya Sagar 24582602c32fSVidya Sagar pcie@14120000 { 2459f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24602602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2461644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2462644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2463644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2464644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24652602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24662602c32fSVidya Sagar 24672602c32fSVidya Sagar status = "disabled"; 24682602c32fSVidya Sagar 24692602c32fSVidya Sagar #address-cells = <3>; 24702602c32fSVidya Sagar #size-cells = <2>; 24712602c32fSVidya Sagar device_type = "pci"; 24722602c32fSVidya Sagar num-lanes = <1>; 24732602c32fSVidya Sagar linux,pci-domain = <2>; 24742602c32fSVidya Sagar 24752602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24762602c32fSVidya Sagar clock-names = "core"; 24772602c32fSVidya Sagar 24782602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24792602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24802602c32fSVidya Sagar reset-names = "apb", "core"; 24812602c32fSVidya Sagar 24822602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24832602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24842602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24852602c32fSVidya Sagar 24862602c32fSVidya Sagar #interrupt-cells = <1>; 24872602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24882602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24892602c32fSVidya Sagar 24902602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24912602c32fSVidya Sagar 24922602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24932602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24942602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24952602c32fSVidya Sagar 24962602c32fSVidya Sagar bus-range = <0x0 0xff>; 2497d5237c7cSThierry Reding 24988a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24998a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 25008a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2501d5237c7cSThierry Reding 2502d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2503d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2504ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2505ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2506ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2507ba02920cSVidya Sagar dma-coherent; 25082602c32fSVidya Sagar }; 25092602c32fSVidya Sagar 25102602c32fSVidya Sagar pcie@14140000 { 2511f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25122602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2513644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2514644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2515644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2516644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25172602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25182602c32fSVidya Sagar 25192602c32fSVidya Sagar status = "disabled"; 25202602c32fSVidya Sagar 25212602c32fSVidya Sagar #address-cells = <3>; 25222602c32fSVidya Sagar #size-cells = <2>; 25232602c32fSVidya Sagar device_type = "pci"; 25242602c32fSVidya Sagar num-lanes = <1>; 25252602c32fSVidya Sagar linux,pci-domain = <3>; 25262602c32fSVidya Sagar 25272602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 25282602c32fSVidya Sagar clock-names = "core"; 25292602c32fSVidya Sagar 25302602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 25312602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 25322602c32fSVidya Sagar reset-names = "apb", "core"; 25332602c32fSVidya Sagar 25342602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25352602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25362602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25372602c32fSVidya Sagar 25382602c32fSVidya Sagar #interrupt-cells = <1>; 25392602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25402602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 25412602c32fSVidya Sagar 25422602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 25432602c32fSVidya Sagar 25442602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25452602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25462602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25472602c32fSVidya Sagar 25482602c32fSVidya Sagar bus-range = <0x0 0xff>; 2549d5237c7cSThierry Reding 25508a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25518a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25528a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2553d5237c7cSThierry Reding 2554d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2555d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2556ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2557ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2558ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2559ba02920cSVidya Sagar dma-coherent; 25602602c32fSVidya Sagar }; 25612602c32fSVidya Sagar 25622602c32fSVidya Sagar pcie@14160000 { 2563f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25642602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2565644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2566644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2567644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2568644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25692602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25702602c32fSVidya Sagar 25712602c32fSVidya Sagar status = "disabled"; 25722602c32fSVidya Sagar 25732602c32fSVidya Sagar #address-cells = <3>; 25742602c32fSVidya Sagar #size-cells = <2>; 25752602c32fSVidya Sagar device_type = "pci"; 25762602c32fSVidya Sagar num-lanes = <4>; 25772602c32fSVidya Sagar linux,pci-domain = <4>; 25782602c32fSVidya Sagar 25792602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25802602c32fSVidya Sagar clock-names = "core"; 25812602c32fSVidya Sagar 25822602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25832602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25842602c32fSVidya Sagar reset-names = "apb", "core"; 25852602c32fSVidya Sagar 25862602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25872602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25882602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25892602c32fSVidya Sagar 25902602c32fSVidya Sagar #interrupt-cells = <1>; 25912602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25922602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25932602c32fSVidya Sagar 25942602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25952602c32fSVidya Sagar 25962602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25972602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25982602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25992602c32fSVidya Sagar 26002602c32fSVidya Sagar bus-range = <0x0 0xff>; 2601d5237c7cSThierry Reding 26028a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26038a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26048a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2605d5237c7cSThierry Reding 2606d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2607d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2608ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2609ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2610ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2611ba02920cSVidya Sagar dma-coherent; 26122602c32fSVidya Sagar }; 26132602c32fSVidya Sagar 26142602c32fSVidya Sagar pcie@14180000 { 2615f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26162602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2617644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2618644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2619644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2620644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26212602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26222602c32fSVidya Sagar 26232602c32fSVidya Sagar status = "disabled"; 26242602c32fSVidya Sagar 26252602c32fSVidya Sagar #address-cells = <3>; 26262602c32fSVidya Sagar #size-cells = <2>; 26272602c32fSVidya Sagar device_type = "pci"; 26282602c32fSVidya Sagar num-lanes = <8>; 26292602c32fSVidya Sagar linux,pci-domain = <0>; 26302602c32fSVidya Sagar 26312602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26322602c32fSVidya Sagar clock-names = "core"; 26332602c32fSVidya Sagar 26342602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26352602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26362602c32fSVidya Sagar reset-names = "apb", "core"; 26372602c32fSVidya Sagar 26382602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26392602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26402602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26412602c32fSVidya Sagar 26422602c32fSVidya Sagar #interrupt-cells = <1>; 26432602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26442602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26452602c32fSVidya Sagar 26462602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26472602c32fSVidya Sagar 26482602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26492602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26502602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26512602c32fSVidya Sagar 26522602c32fSVidya Sagar bus-range = <0x0 0xff>; 2653d5237c7cSThierry Reding 26548a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26558a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26568a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2657d5237c7cSThierry Reding 2658d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2659d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2660ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2661ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2662ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2663ba02920cSVidya Sagar dma-coherent; 26642602c32fSVidya Sagar }; 26652602c32fSVidya Sagar 26662602c32fSVidya Sagar pcie@141a0000 { 2667f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26682602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2669644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2670644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2671644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2672644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26732602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26742602c32fSVidya Sagar 26752602c32fSVidya Sagar status = "disabled"; 26762602c32fSVidya Sagar 26772602c32fSVidya Sagar #address-cells = <3>; 26782602c32fSVidya Sagar #size-cells = <2>; 26792602c32fSVidya Sagar device_type = "pci"; 26802602c32fSVidya Sagar num-lanes = <8>; 26812602c32fSVidya Sagar linux,pci-domain = <5>; 26822602c32fSVidya Sagar 2683dbb72e2cSVidya Sagar pinctrl-names = "default"; 2684dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2685dbb72e2cSVidya Sagar 2686c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2687c453cc9eSThierry Reding clock-names = "core"; 26882602c32fSVidya Sagar 26892602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26902602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26912602c32fSVidya Sagar reset-names = "apb", "core"; 26922602c32fSVidya Sagar 26932602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26942602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26952602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26962602c32fSVidya Sagar 26972602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 26982602c32fSVidya Sagar 26992602c32fSVidya Sagar #interrupt-cells = <1>; 27002602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 27012602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 27022602c32fSVidya Sagar 27032602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 27042602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27052602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 27062602c32fSVidya Sagar 27072602c32fSVidya Sagar bus-range = <0x0 0xff>; 2708d5237c7cSThierry Reding 27098a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 27108a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 27118a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2712d5237c7cSThierry Reding 2713d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2714d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2715ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2716ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2717ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2718ba02920cSVidya Sagar dma-coherent; 27192602c32fSVidya Sagar }; 27202602c32fSVidya Sagar 2721b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2722bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27230c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2724644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2725644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2726644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2727644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27280c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27290c988b73SVidya Sagar 27300c988b73SVidya Sagar status = "disabled"; 27310c988b73SVidya Sagar 27320c988b73SVidya Sagar num-lanes = <4>; 27330c988b73SVidya Sagar num-ib-windows = <2>; 27340c988b73SVidya Sagar num-ob-windows = <8>; 27350c988b73SVidya Sagar 27360c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 27370c988b73SVidya Sagar clock-names = "core"; 27380c988b73SVidya Sagar 27390c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 27400c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 27410c988b73SVidya Sagar reset-names = "apb", "core"; 27420c988b73SVidya Sagar 27430c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27440c988b73SVidya Sagar interrupt-names = "intr"; 27450c988b73SVidya Sagar 27460c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 27470c988b73SVidya Sagar 27480c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27490c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27500c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2751ba02920cSVidya Sagar 2752ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2753ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2754ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2755ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2756ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2757ba02920cSVidya Sagar dma-coherent; 27580c988b73SVidya Sagar }; 27590c988b73SVidya Sagar 2760b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2761bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27620c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2763644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2764644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2765644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2766644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27670c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27680c988b73SVidya Sagar 27690c988b73SVidya Sagar status = "disabled"; 27700c988b73SVidya Sagar 27710c988b73SVidya Sagar num-lanes = <8>; 27720c988b73SVidya Sagar num-ib-windows = <2>; 27730c988b73SVidya Sagar num-ob-windows = <8>; 27740c988b73SVidya Sagar 27750c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 27760c988b73SVidya Sagar clock-names = "core"; 27770c988b73SVidya Sagar 27780c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 27790c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 27800c988b73SVidya Sagar reset-names = "apb", "core"; 27810c988b73SVidya Sagar 27820c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27830c988b73SVidya Sagar interrupt-names = "intr"; 27840c988b73SVidya Sagar 27850c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 27860c988b73SVidya Sagar 27870c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27880c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27890c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2790ba02920cSVidya Sagar 2791ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2792ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2793ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2794ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2795ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2796ba02920cSVidya Sagar dma-coherent; 27970c988b73SVidya Sagar }; 27980c988b73SVidya Sagar 2799b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2800bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 28010c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2802644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2803644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2804644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2805644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 28060c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 28070c988b73SVidya Sagar 28080c988b73SVidya Sagar status = "disabled"; 28090c988b73SVidya Sagar 28100c988b73SVidya Sagar num-lanes = <8>; 28110c988b73SVidya Sagar num-ib-windows = <2>; 28120c988b73SVidya Sagar num-ob-windows = <8>; 28130c988b73SVidya Sagar 28140c988b73SVidya Sagar pinctrl-names = "default"; 28150c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 28160c988b73SVidya Sagar 28170c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 28180c988b73SVidya Sagar clock-names = "core"; 28190c988b73SVidya Sagar 28200c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 28210c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 28220c988b73SVidya Sagar reset-names = "apb", "core"; 28230c988b73SVidya Sagar 28240c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28250c988b73SVidya Sagar interrupt-names = "intr"; 28260c988b73SVidya Sagar 28270c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 28280c988b73SVidya Sagar 28290c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 28300c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 28310c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2832ba02920cSVidya Sagar 2833ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2834ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2835ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2836ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2837ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2838ba02920cSVidya Sagar dma-coherent; 28390c988b73SVidya Sagar }; 28400c988b73SVidya Sagar 2841e867fe41SThierry Reding sram@40000000 { 28425425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28435425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 28445425fb15SMikko Perttunen #address-cells = <1>; 28455425fb15SMikko Perttunen #size-cells = <1>; 28465425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 284761192a9dSMikko Perttunen no-memory-wc; 28485425fb15SMikko Perttunen 2849e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28505425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28515425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28525425fb15SMikko Perttunen pool; 28535425fb15SMikko Perttunen }; 28545425fb15SMikko Perttunen 2855e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28565425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28575425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28585425fb15SMikko Perttunen pool; 28595425fb15SMikko Perttunen }; 28605425fb15SMikko Perttunen }; 28615425fb15SMikko Perttunen 28625425fb15SMikko Perttunen bpmp: bpmp { 28635425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28645425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28655425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28667fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28675425fb15SMikko Perttunen #clock-cells = <1>; 28685425fb15SMikko Perttunen #reset-cells = <1>; 28695425fb15SMikko Perttunen #power-domain-cells = <1>; 2870d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2871d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2872d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2873d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2874d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2875c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28765425fb15SMikko Perttunen 28775425fb15SMikko Perttunen bpmp_i2c: i2c { 28785425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28795425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28805425fb15SMikko Perttunen #address-cells = <1>; 28815425fb15SMikko Perttunen #size-cells = <0>; 28825425fb15SMikko Perttunen }; 28835425fb15SMikko Perttunen 28845425fb15SMikko Perttunen bpmp_thermal: thermal { 28855425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28865425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28875425fb15SMikko Perttunen }; 28885425fb15SMikko Perttunen }; 28895425fb15SMikko Perttunen 28907780a034SMikko Perttunen cpus { 2891d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2892d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28937780a034SMikko Perttunen #address-cells = <1>; 28947780a034SMikko Perttunen #size-cells = <0>; 28957780a034SMikko Perttunen 2896b45d322cSThierry Reding cpu0_0: cpu@0 { 289731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28987780a034SMikko Perttunen device_type = "cpu"; 2899b45d322cSThierry Reding reg = <0x000>; 29007780a034SMikko Perttunen enable-method = "psci"; 2901b45d322cSThierry Reding i-cache-size = <131072>; 2902b45d322cSThierry Reding i-cache-line-size = <64>; 2903b45d322cSThierry Reding i-cache-sets = <512>; 2904b45d322cSThierry Reding d-cache-size = <65536>; 2905b45d322cSThierry Reding d-cache-line-size = <64>; 2906b45d322cSThierry Reding d-cache-sets = <256>; 2907b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29087780a034SMikko Perttunen }; 29097780a034SMikko Perttunen 2910b45d322cSThierry Reding cpu0_1: cpu@1 { 291131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29127780a034SMikko Perttunen device_type = "cpu"; 2913b45d322cSThierry Reding reg = <0x001>; 29147780a034SMikko Perttunen enable-method = "psci"; 2915b45d322cSThierry Reding i-cache-size = <131072>; 2916b45d322cSThierry Reding i-cache-line-size = <64>; 2917b45d322cSThierry Reding i-cache-sets = <512>; 2918b45d322cSThierry Reding d-cache-size = <65536>; 2919b45d322cSThierry Reding d-cache-line-size = <64>; 2920b45d322cSThierry Reding d-cache-sets = <256>; 2921b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29227780a034SMikko Perttunen }; 29237780a034SMikko Perttunen 2924b45d322cSThierry Reding cpu1_0: cpu@100 { 292531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29267780a034SMikko Perttunen device_type = "cpu"; 29277780a034SMikko Perttunen reg = <0x100>; 29287780a034SMikko Perttunen enable-method = "psci"; 2929b45d322cSThierry Reding i-cache-size = <131072>; 2930b45d322cSThierry Reding i-cache-line-size = <64>; 2931b45d322cSThierry Reding i-cache-sets = <512>; 2932b45d322cSThierry Reding d-cache-size = <65536>; 2933b45d322cSThierry Reding d-cache-line-size = <64>; 2934b45d322cSThierry Reding d-cache-sets = <256>; 2935b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29367780a034SMikko Perttunen }; 29377780a034SMikko Perttunen 2938b45d322cSThierry Reding cpu1_1: cpu@101 { 293931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29407780a034SMikko Perttunen device_type = "cpu"; 29417780a034SMikko Perttunen reg = <0x101>; 29427780a034SMikko Perttunen enable-method = "psci"; 2943b45d322cSThierry Reding i-cache-size = <131072>; 2944b45d322cSThierry Reding i-cache-line-size = <64>; 2945b45d322cSThierry Reding i-cache-sets = <512>; 2946b45d322cSThierry Reding d-cache-size = <65536>; 2947b45d322cSThierry Reding d-cache-line-size = <64>; 2948b45d322cSThierry Reding d-cache-sets = <256>; 2949b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29507780a034SMikko Perttunen }; 29517780a034SMikko Perttunen 2952b45d322cSThierry Reding cpu2_0: cpu@200 { 295331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29547780a034SMikko Perttunen device_type = "cpu"; 29557780a034SMikko Perttunen reg = <0x200>; 29567780a034SMikko Perttunen enable-method = "psci"; 2957b45d322cSThierry Reding i-cache-size = <131072>; 2958b45d322cSThierry Reding i-cache-line-size = <64>; 2959b45d322cSThierry Reding i-cache-sets = <512>; 2960b45d322cSThierry Reding d-cache-size = <65536>; 2961b45d322cSThierry Reding d-cache-line-size = <64>; 2962b45d322cSThierry Reding d-cache-sets = <256>; 2963b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29647780a034SMikko Perttunen }; 29657780a034SMikko Perttunen 2966b45d322cSThierry Reding cpu2_1: cpu@201 { 296731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29687780a034SMikko Perttunen device_type = "cpu"; 29697780a034SMikko Perttunen reg = <0x201>; 29707780a034SMikko Perttunen enable-method = "psci"; 2971b45d322cSThierry Reding i-cache-size = <131072>; 2972b45d322cSThierry Reding i-cache-line-size = <64>; 2973b45d322cSThierry Reding i-cache-sets = <512>; 2974b45d322cSThierry Reding d-cache-size = <65536>; 2975b45d322cSThierry Reding d-cache-line-size = <64>; 2976b45d322cSThierry Reding d-cache-sets = <256>; 2977b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29787780a034SMikko Perttunen }; 29797780a034SMikko Perttunen 2980b45d322cSThierry Reding cpu3_0: cpu@300 { 298131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29827780a034SMikko Perttunen device_type = "cpu"; 2983b45d322cSThierry Reding reg = <0x300>; 29847780a034SMikko Perttunen enable-method = "psci"; 2985b45d322cSThierry Reding i-cache-size = <131072>; 2986b45d322cSThierry Reding i-cache-line-size = <64>; 2987b45d322cSThierry Reding i-cache-sets = <512>; 2988b45d322cSThierry Reding d-cache-size = <65536>; 2989b45d322cSThierry Reding d-cache-line-size = <64>; 2990b45d322cSThierry Reding d-cache-sets = <256>; 2991b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29927780a034SMikko Perttunen }; 29937780a034SMikko Perttunen 2994b45d322cSThierry Reding cpu3_1: cpu@301 { 299531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29967780a034SMikko Perttunen device_type = "cpu"; 2997b45d322cSThierry Reding reg = <0x301>; 29987780a034SMikko Perttunen enable-method = "psci"; 2999b45d322cSThierry Reding i-cache-size = <131072>; 3000b45d322cSThierry Reding i-cache-line-size = <64>; 3001b45d322cSThierry Reding i-cache-sets = <512>; 3002b45d322cSThierry Reding d-cache-size = <65536>; 3003b45d322cSThierry Reding d-cache-line-size = <64>; 3004b45d322cSThierry Reding d-cache-sets = <256>; 3005b45d322cSThierry Reding next-level-cache = <&l2c_3>; 3006b45d322cSThierry Reding }; 3007b45d322cSThierry Reding 3008b45d322cSThierry Reding cpu-map { 3009b45d322cSThierry Reding cluster0 { 3010b45d322cSThierry Reding core0 { 3011b45d322cSThierry Reding cpu = <&cpu0_0>; 3012b45d322cSThierry Reding }; 3013b45d322cSThierry Reding 3014b45d322cSThierry Reding core1 { 3015b45d322cSThierry Reding cpu = <&cpu0_1>; 3016b45d322cSThierry Reding }; 3017b45d322cSThierry Reding }; 3018b45d322cSThierry Reding 3019b45d322cSThierry Reding cluster1 { 3020b45d322cSThierry Reding core0 { 3021b45d322cSThierry Reding cpu = <&cpu1_0>; 3022b45d322cSThierry Reding }; 3023b45d322cSThierry Reding 3024b45d322cSThierry Reding core1 { 3025b45d322cSThierry Reding cpu = <&cpu1_1>; 3026b45d322cSThierry Reding }; 3027b45d322cSThierry Reding }; 3028b45d322cSThierry Reding 3029b45d322cSThierry Reding cluster2 { 3030b45d322cSThierry Reding core0 { 3031b45d322cSThierry Reding cpu = <&cpu2_0>; 3032b45d322cSThierry Reding }; 3033b45d322cSThierry Reding 3034b45d322cSThierry Reding core1 { 3035b45d322cSThierry Reding cpu = <&cpu2_1>; 3036b45d322cSThierry Reding }; 3037b45d322cSThierry Reding }; 3038b45d322cSThierry Reding 3039b45d322cSThierry Reding cluster3 { 3040b45d322cSThierry Reding core0 { 3041b45d322cSThierry Reding cpu = <&cpu3_0>; 3042b45d322cSThierry Reding }; 3043b45d322cSThierry Reding 3044b45d322cSThierry Reding core1 { 3045b45d322cSThierry Reding cpu = <&cpu3_1>; 3046b45d322cSThierry Reding }; 3047b45d322cSThierry Reding }; 3048b45d322cSThierry Reding }; 3049b45d322cSThierry Reding 3050b45d322cSThierry Reding l2c_0: l2-cache0 { 3051b45d322cSThierry Reding cache-size = <2097152>; 3052b45d322cSThierry Reding cache-line-size = <64>; 3053b45d322cSThierry Reding cache-sets = <2048>; 3054b45d322cSThierry Reding next-level-cache = <&l3c>; 3055b45d322cSThierry Reding }; 3056b45d322cSThierry Reding 3057b45d322cSThierry Reding l2c_1: l2-cache1 { 3058b45d322cSThierry Reding cache-size = <2097152>; 3059b45d322cSThierry Reding cache-line-size = <64>; 3060b45d322cSThierry Reding cache-sets = <2048>; 3061b45d322cSThierry Reding next-level-cache = <&l3c>; 3062b45d322cSThierry Reding }; 3063b45d322cSThierry Reding 3064b45d322cSThierry Reding l2c_2: l2-cache2 { 3065b45d322cSThierry Reding cache-size = <2097152>; 3066b45d322cSThierry Reding cache-line-size = <64>; 3067b45d322cSThierry Reding cache-sets = <2048>; 3068b45d322cSThierry Reding next-level-cache = <&l3c>; 3069b45d322cSThierry Reding }; 3070b45d322cSThierry Reding 3071b45d322cSThierry Reding l2c_3: l2-cache3 { 3072b45d322cSThierry Reding cache-size = <2097152>; 3073b45d322cSThierry Reding cache-line-size = <64>; 3074b45d322cSThierry Reding cache-sets = <2048>; 3075b45d322cSThierry Reding next-level-cache = <&l3c>; 3076b45d322cSThierry Reding }; 3077b45d322cSThierry Reding 3078b45d322cSThierry Reding l3c: l3-cache { 3079b45d322cSThierry Reding cache-size = <4194304>; 3080b45d322cSThierry Reding cache-line-size = <64>; 3081b45d322cSThierry Reding cache-sets = <4096>; 30827780a034SMikko Perttunen }; 30837780a034SMikko Perttunen }; 30847780a034SMikko Perttunen 30859e79e58fSJon Hunter pmu { 3086f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 30879e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 30889e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 30899e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 30909e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 30919e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 30929e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 30939e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 30949e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 30959e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 30969e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 30979e79e58fSJon Hunter }; 30989e79e58fSJon Hunter 30997780a034SMikko Perttunen psci { 31007780a034SMikko Perttunen compatible = "arm,psci-1.0"; 31017780a034SMikko Perttunen status = "okay"; 31027780a034SMikko Perttunen method = "smc"; 31037780a034SMikko Perttunen }; 31047780a034SMikko Perttunen 31055b4f6323SSameer Pujar sound { 31065b4f6323SSameer Pujar status = "disabled"; 31075b4f6323SSameer Pujar 31085b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 31095b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31105b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 31115b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 31125b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 31135b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 31145b4f6323SSameer Pujar assigned-clock-parents = <0>, 31155b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 31165b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31175b4f6323SSameer Pujar /* 31185b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31195b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31205b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31215b4f6323SSameer Pujar */ 31225b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31235b4f6323SSameer Pujar }; 31245b4f6323SSameer Pujar 312599d9bde5SThierry Reding tcu: serial { 3126a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 3127a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3128a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3129a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 3130a38570c2SMikko Perttunen }; 3131a38570c2SMikko Perttunen 3132686ba009SThierry Reding thermal-zones { 3133fe57ff53SThierry Reding cpu-thermal { 3134fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3135686ba009SThierry Reding status = "disabled"; 3136686ba009SThierry Reding }; 3137686ba009SThierry Reding 3138fe57ff53SThierry Reding gpu-thermal { 3139fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3140686ba009SThierry Reding status = "disabled"; 3141686ba009SThierry Reding }; 3142686ba009SThierry Reding 3143fe57ff53SThierry Reding aux-thermal { 3144fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3145686ba009SThierry Reding status = "disabled"; 3146686ba009SThierry Reding }; 3147686ba009SThierry Reding 3148fe57ff53SThierry Reding pllx-thermal { 3149fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3150686ba009SThierry Reding status = "disabled"; 3151686ba009SThierry Reding }; 3152686ba009SThierry Reding 3153fe57ff53SThierry Reding ao-thermal { 3154fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3155686ba009SThierry Reding status = "disabled"; 3156686ba009SThierry Reding }; 3157686ba009SThierry Reding 3158fe57ff53SThierry Reding tj-thermal { 3159fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3160686ba009SThierry Reding status = "disabled"; 3161686ba009SThierry Reding }; 3162686ba009SThierry Reding }; 3163686ba009SThierry Reding 31645425fb15SMikko Perttunen timer { 31655425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31665425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31675425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31685425fb15SMikko Perttunen <GIC_PPI 14 31695425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31705425fb15SMikko Perttunen <GIC_PPI 11 31715425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31725425fb15SMikko Perttunen <GIC_PPI 10 31735425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31745425fb15SMikko Perttunen interrupt-parent = <&gic>; 3175b30be673SThierry Reding always-on; 31765425fb15SMikko Perttunen }; 31775425fb15SMikko Perttunen}; 3178