15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 65425fb15SMikko Perttunen#include <dt-bindings/reset/tegra194-reset.h> 75425fb15SMikko Perttunen 85425fb15SMikko Perttunen/ { 95425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 105425fb15SMikko Perttunen interrupt-parent = <&gic>; 115425fb15SMikko Perttunen #address-cells = <2>; 125425fb15SMikko Perttunen #size-cells = <2>; 135425fb15SMikko Perttunen 145425fb15SMikko Perttunen /* control backbone */ 155425fb15SMikko Perttunen cbb { 165425fb15SMikko Perttunen compatible = "simple-bus"; 175425fb15SMikko Perttunen #address-cells = <1>; 185425fb15SMikko Perttunen #size-cells = <1>; 195425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 205425fb15SMikko Perttunen 21f69ce393SMikko Perttunen gpio: gpio@2200000 { 22f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 23f69ce393SMikko Perttunen reg-names = "security", "gpio"; 24f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 25f69ce393SMikko Perttunen <0x2210000 0x10000>; 26f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 27f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 28f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 29f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 30f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 31f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 32f69ce393SMikko Perttunen #interrupt-cells = <2>; 33f69ce393SMikko Perttunen interrupt-controller; 34f69ce393SMikko Perttunen #gpio-cells = <2>; 35f69ce393SMikko Perttunen gpio-controller; 36f69ce393SMikko Perttunen }; 37f69ce393SMikko Perttunen 38f89b58ceSMikko Perttunen ethernet@2490000 { 39f89b58ceSMikko Perttunen compatible = "nvidia,tegra186-eqos", 40f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 41f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 42f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 43f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 44f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 45f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 46f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 47f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 48f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 49f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 50f89b58ceSMikko Perttunen reset-names = "eqos"; 51f89b58ceSMikko Perttunen status = "disabled"; 52f89b58ceSMikko Perttunen 53f89b58ceSMikko Perttunen snps,write-requests = <1>; 54f89b58ceSMikko Perttunen snps,read-requests = <3>; 55f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 56f89b58ceSMikko Perttunen snps,txpbl = <16>; 57f89b58ceSMikko Perttunen snps,rxpbl = <8>; 58f89b58ceSMikko Perttunen }; 59f89b58ceSMikko Perttunen 605425fb15SMikko Perttunen uarta: serial@3100000 { 615425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 625425fb15SMikko Perttunen reg = <0x03100000 0x40>; 635425fb15SMikko Perttunen reg-shift = <2>; 645425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 655425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 665425fb15SMikko Perttunen clock-names = "serial"; 675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 685425fb15SMikko Perttunen reset-names = "serial"; 695425fb15SMikko Perttunen status = "disabled"; 705425fb15SMikko Perttunen }; 715425fb15SMikko Perttunen 725425fb15SMikko Perttunen uartb: serial@3110000 { 735425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 745425fb15SMikko Perttunen reg = <0x03110000 0x40>; 755425fb15SMikko Perttunen reg-shift = <2>; 765425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 775425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 785425fb15SMikko Perttunen clock-names = "serial"; 795425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 805425fb15SMikko Perttunen reset-names = "serial"; 815425fb15SMikko Perttunen status = "disabled"; 825425fb15SMikko Perttunen }; 835425fb15SMikko Perttunen 845425fb15SMikko Perttunen uartd: serial@3130000 { 855425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 865425fb15SMikko Perttunen reg = <0x03130000 0x40>; 875425fb15SMikko Perttunen reg-shift = <2>; 885425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 905425fb15SMikko Perttunen clock-names = "serial"; 915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 925425fb15SMikko Perttunen reset-names = "serial"; 935425fb15SMikko Perttunen status = "disabled"; 945425fb15SMikko Perttunen }; 955425fb15SMikko Perttunen 965425fb15SMikko Perttunen uarte: serial@3140000 { 975425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 985425fb15SMikko Perttunen reg = <0x03140000 0x40>; 995425fb15SMikko Perttunen reg-shift = <2>; 1005425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 1025425fb15SMikko Perttunen clock-names = "serial"; 1035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 1045425fb15SMikko Perttunen reset-names = "serial"; 1055425fb15SMikko Perttunen status = "disabled"; 1065425fb15SMikko Perttunen }; 1075425fb15SMikko Perttunen 1085425fb15SMikko Perttunen uartf: serial@3150000 { 1095425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1105425fb15SMikko Perttunen reg = <0x03150000 0x40>; 1115425fb15SMikko Perttunen reg-shift = <2>; 1125425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1135425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 1145425fb15SMikko Perttunen clock-names = "serial"; 1155425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 1165425fb15SMikko Perttunen reset-names = "serial"; 1175425fb15SMikko Perttunen status = "disabled"; 1185425fb15SMikko Perttunen }; 1195425fb15SMikko Perttunen 1205425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 121d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1225425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 1235425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1245425fb15SMikko Perttunen #address-cells = <1>; 1255425fb15SMikko Perttunen #size-cells = <0>; 1265425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 1275425fb15SMikko Perttunen clock-names = "div-clk"; 1285425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 1295425fb15SMikko Perttunen reset-names = "i2c"; 1305425fb15SMikko Perttunen status = "disabled"; 1315425fb15SMikko Perttunen }; 1325425fb15SMikko Perttunen 1335425fb15SMikko Perttunen uarth: serial@3170000 { 1345425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1355425fb15SMikko Perttunen reg = <0x03170000 0x40>; 1365425fb15SMikko Perttunen reg-shift = <2>; 1375425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 1385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 1395425fb15SMikko Perttunen clock-names = "serial"; 1405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 1415425fb15SMikko Perttunen reset-names = "serial"; 1425425fb15SMikko Perttunen status = "disabled"; 1435425fb15SMikko Perttunen }; 1445425fb15SMikko Perttunen 1455425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 146d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1475425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 1485425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1495425fb15SMikko Perttunen #address-cells = <1>; 1505425fb15SMikko Perttunen #size-cells = <0>; 1515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 1525425fb15SMikko Perttunen clock-names = "div-clk"; 1535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 1545425fb15SMikko Perttunen reset-names = "i2c"; 1555425fb15SMikko Perttunen status = "disabled"; 1565425fb15SMikko Perttunen }; 1575425fb15SMikko Perttunen 1585425fb15SMikko Perttunen /* shares pads with dpaux1 */ 1595425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 160d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1615425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 1625425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1635425fb15SMikko Perttunen #address-cells = <1>; 1645425fb15SMikko Perttunen #size-cells = <0>; 1655425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 1665425fb15SMikko Perttunen clock-names = "div-clk"; 1675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 1685425fb15SMikko Perttunen reset-names = "i2c"; 1695425fb15SMikko Perttunen status = "disabled"; 1705425fb15SMikko Perttunen }; 1715425fb15SMikko Perttunen 1725425fb15SMikko Perttunen /* shares pads with dpaux0 */ 1735425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 174d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1755425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 1765425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1775425fb15SMikko Perttunen #address-cells = <1>; 1785425fb15SMikko Perttunen #size-cells = <0>; 1795425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 1805425fb15SMikko Perttunen clock-names = "div-clk"; 1815425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 1825425fb15SMikko Perttunen reset-names = "i2c"; 1835425fb15SMikko Perttunen status = "disabled"; 1845425fb15SMikko Perttunen }; 1855425fb15SMikko Perttunen 1865425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 187d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1885425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 1895425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1905425fb15SMikko Perttunen #address-cells = <1>; 1915425fb15SMikko Perttunen #size-cells = <0>; 1925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 1935425fb15SMikko Perttunen clock-names = "div-clk"; 1945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 1955425fb15SMikko Perttunen reset-names = "i2c"; 1965425fb15SMikko Perttunen status = "disabled"; 1975425fb15SMikko Perttunen }; 1985425fb15SMikko Perttunen 1995425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 200d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2015425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 2025425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2035425fb15SMikko Perttunen #address-cells = <1>; 2045425fb15SMikko Perttunen #size-cells = <0>; 2055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 2065425fb15SMikko Perttunen clock-names = "div-clk"; 2075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 2085425fb15SMikko Perttunen reset-names = "i2c"; 2095425fb15SMikko Perttunen status = "disabled"; 2105425fb15SMikko Perttunen }; 2115425fb15SMikko Perttunen 2126a574ec7SThierry Reding pwm1: pwm@3280000 { 2136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2156a574ec7SThierry Reding reg = <0x3280000 0x10000>; 2166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 2176a574ec7SThierry Reding clock-names = "pwm"; 2186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 2196a574ec7SThierry Reding reset-names = "pwm"; 2206a574ec7SThierry Reding status = "disabled"; 2216a574ec7SThierry Reding #pwm-cells = <2>; 2226a574ec7SThierry Reding }; 2236a574ec7SThierry Reding 2246a574ec7SThierry Reding pwm2: pwm@3290000 { 2256a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2266a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2276a574ec7SThierry Reding reg = <0x3290000 0x10000>; 2286a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 2296a574ec7SThierry Reding clock-names = "pwm"; 2306a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 2316a574ec7SThierry Reding reset-names = "pwm"; 2326a574ec7SThierry Reding status = "disabled"; 2336a574ec7SThierry Reding #pwm-cells = <2>; 2346a574ec7SThierry Reding }; 2356a574ec7SThierry Reding 2366a574ec7SThierry Reding pwm3: pwm@32a0000 { 2376a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2386a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2396a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 2406a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 2416a574ec7SThierry Reding clock-names = "pwm"; 2426a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 2436a574ec7SThierry Reding reset-names = "pwm"; 2446a574ec7SThierry Reding status = "disabled"; 2456a574ec7SThierry Reding #pwm-cells = <2>; 2466a574ec7SThierry Reding }; 2476a574ec7SThierry Reding 2486a574ec7SThierry Reding pwm5: pwm@32c0000 { 2496a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2506a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2516a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 2526a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 2536a574ec7SThierry Reding clock-names = "pwm"; 2546a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 2556a574ec7SThierry Reding reset-names = "pwm"; 2566a574ec7SThierry Reding status = "disabled"; 2576a574ec7SThierry Reding #pwm-cells = <2>; 2586a574ec7SThierry Reding }; 2596a574ec7SThierry Reding 2606a574ec7SThierry Reding pwm6: pwm@32d0000 { 2616a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2626a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2636a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 2646a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 2656a574ec7SThierry Reding clock-names = "pwm"; 2666a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 2676a574ec7SThierry Reding reset-names = "pwm"; 2686a574ec7SThierry Reding status = "disabled"; 2696a574ec7SThierry Reding #pwm-cells = <2>; 2706a574ec7SThierry Reding }; 2716a574ec7SThierry Reding 2726a574ec7SThierry Reding pwm7: pwm@32e0000 { 2736a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2746a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2756a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 2766a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 2776a574ec7SThierry Reding clock-names = "pwm"; 2786a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 2796a574ec7SThierry Reding reset-names = "pwm"; 2806a574ec7SThierry Reding status = "disabled"; 2816a574ec7SThierry Reding #pwm-cells = <2>; 2826a574ec7SThierry Reding }; 2836a574ec7SThierry Reding 2846a574ec7SThierry Reding pwm8: pwm@32f0000 { 2856a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2866a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2876a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 2886a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 2896a574ec7SThierry Reding clock-names = "pwm"; 2906a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 2916a574ec7SThierry Reding reset-names = "pwm"; 2926a574ec7SThierry Reding status = "disabled"; 2936a574ec7SThierry Reding #pwm-cells = <2>; 2946a574ec7SThierry Reding }; 2956a574ec7SThierry Reding 2965425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 2975425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 2985425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 2995425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3005425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 3015425fb15SMikko Perttunen clock-names = "sdhci"; 3025425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 3035425fb15SMikko Perttunen reset-names = "sdhci"; 3045425fb15SMikko Perttunen status = "disabled"; 3055425fb15SMikko Perttunen }; 3065425fb15SMikko Perttunen 3075425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 3085425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3095425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 3105425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 3115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 3125425fb15SMikko Perttunen clock-names = "sdhci"; 3135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 3145425fb15SMikko Perttunen reset-names = "sdhci"; 3155425fb15SMikko Perttunen status = "disabled"; 3165425fb15SMikko Perttunen }; 3175425fb15SMikko Perttunen 3185425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 3195425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3205425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 3215425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 3225425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 3235425fb15SMikko Perttunen clock-names = "sdhci"; 3245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 3255425fb15SMikko Perttunen reset-names = "sdhci"; 3265425fb15SMikko Perttunen status = "disabled"; 3275425fb15SMikko Perttunen }; 3285425fb15SMikko Perttunen 3295425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 3305425fb15SMikko Perttunen compatible = "arm,gic-400"; 3315425fb15SMikko Perttunen #interrupt-cells = <3>; 3325425fb15SMikko Perttunen interrupt-controller; 3335425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 3345425fb15SMikko Perttunen <0x03882000 0x2000>, 3355425fb15SMikko Perttunen <0x03884000 0x2000>, 3365425fb15SMikko Perttunen <0x03886000 0x2000>; 3375425fb15SMikko Perttunen interrupts = <GIC_PPI 9 3385425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 3395425fb15SMikko Perttunen interrupt-parent = <&gic>; 3405425fb15SMikko Perttunen }; 3415425fb15SMikko Perttunen 3425425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 3435425fb15SMikko Perttunen compatible = "nvidia,tegra186-hsp"; 3445425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 3455425fb15SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 3465425fb15SMikko Perttunen interrupt-names = "doorbell"; 3475425fb15SMikko Perttunen #mbox-cells = <2>; 3485425fb15SMikko Perttunen }; 3495425fb15SMikko Perttunen 3505425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 351d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3525425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 3535425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 3545425fb15SMikko Perttunen #address-cells = <1>; 3555425fb15SMikko Perttunen #size-cells = <0>; 3565425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 3575425fb15SMikko Perttunen clock-names = "div-clk"; 3585425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 3595425fb15SMikko Perttunen reset-names = "i2c"; 3605425fb15SMikko Perttunen status = "disabled"; 3615425fb15SMikko Perttunen }; 3625425fb15SMikko Perttunen 3635425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 364d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3655425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 3665425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3675425fb15SMikko Perttunen #address-cells = <1>; 3685425fb15SMikko Perttunen #size-cells = <0>; 3695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 3705425fb15SMikko Perttunen clock-names = "div-clk"; 3715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 3725425fb15SMikko Perttunen reset-names = "i2c"; 3735425fb15SMikko Perttunen status = "disabled"; 3745425fb15SMikko Perttunen }; 3755425fb15SMikko Perttunen 3765425fb15SMikko Perttunen uartc: serial@c280000 { 3775425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 3785425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 3795425fb15SMikko Perttunen reg-shift = <2>; 3805425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3815425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 3825425fb15SMikko Perttunen clock-names = "serial"; 3835425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 3845425fb15SMikko Perttunen reset-names = "serial"; 3855425fb15SMikko Perttunen status = "disabled"; 3865425fb15SMikko Perttunen }; 3875425fb15SMikko Perttunen 3885425fb15SMikko Perttunen uartg: serial@c290000 { 3895425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 3905425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 3915425fb15SMikko Perttunen reg-shift = <2>; 3925425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3935425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 3945425fb15SMikko Perttunen clock-names = "serial"; 3955425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 3965425fb15SMikko Perttunen reset-names = "serial"; 3975425fb15SMikko Perttunen status = "disabled"; 3985425fb15SMikko Perttunen }; 3995425fb15SMikko Perttunen 4006a574ec7SThierry Reding pwm4: pwm@c340000 { 4016a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4026a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4036a574ec7SThierry Reding reg = <0xc340000 0x10000>; 4046a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 4056a574ec7SThierry Reding clock-names = "pwm"; 4066a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 4076a574ec7SThierry Reding reset-names = "pwm"; 4086a574ec7SThierry Reding status = "disabled"; 4096a574ec7SThierry Reding #pwm-cells = <2>; 4106a574ec7SThierry Reding }; 4116a574ec7SThierry Reding 4125425fb15SMikko Perttunen pmc@c360000 { 4135425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 4145425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 4155425fb15SMikko Perttunen <0x0c370000 0x10000>, 4165425fb15SMikko Perttunen <0x0c380000 0x10000>, 4175425fb15SMikko Perttunen <0x0c390000 0x10000>, 4185425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 4195425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 4205425fb15SMikko Perttunen }; 4215425fb15SMikko Perttunen }; 4225425fb15SMikko Perttunen 4235425fb15SMikko Perttunen sysram@40000000 { 4245425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 4255425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 4265425fb15SMikko Perttunen #address-cells = <1>; 4275425fb15SMikko Perttunen #size-cells = <1>; 4285425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 4295425fb15SMikko Perttunen 4305425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 4315425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 4325425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 4335425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 4345425fb15SMikko Perttunen pool; 4355425fb15SMikko Perttunen }; 4365425fb15SMikko Perttunen 4375425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 4385425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 4395425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 4405425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 4415425fb15SMikko Perttunen pool; 4425425fb15SMikko Perttunen }; 4435425fb15SMikko Perttunen }; 4445425fb15SMikko Perttunen 4455425fb15SMikko Perttunen bpmp: bpmp { 4465425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 4475425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 4485425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 4495425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 4505425fb15SMikko Perttunen #clock-cells = <1>; 4515425fb15SMikko Perttunen #reset-cells = <1>; 4525425fb15SMikko Perttunen #power-domain-cells = <1>; 4535425fb15SMikko Perttunen 4545425fb15SMikko Perttunen bpmp_i2c: i2c { 4555425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 4565425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 4575425fb15SMikko Perttunen #address-cells = <1>; 4585425fb15SMikko Perttunen #size-cells = <0>; 4595425fb15SMikko Perttunen }; 4605425fb15SMikko Perttunen 4615425fb15SMikko Perttunen bpmp_thermal: thermal { 4625425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 4635425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 4645425fb15SMikko Perttunen }; 4655425fb15SMikko Perttunen }; 4665425fb15SMikko Perttunen 4677780a034SMikko Perttunen cpus { 4687780a034SMikko Perttunen #address-cells = <1>; 4697780a034SMikko Perttunen #size-cells = <0>; 4707780a034SMikko Perttunen 4717780a034SMikko Perttunen cpu@0 { 4727780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 4737780a034SMikko Perttunen device_type = "cpu"; 4747780a034SMikko Perttunen reg = <0x10000>; 4757780a034SMikko Perttunen enable-method = "psci"; 4767780a034SMikko Perttunen }; 4777780a034SMikko Perttunen 4787780a034SMikko Perttunen cpu@1 { 4797780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 4807780a034SMikko Perttunen device_type = "cpu"; 4817780a034SMikko Perttunen reg = <0x10001>; 4827780a034SMikko Perttunen enable-method = "psci"; 4837780a034SMikko Perttunen }; 4847780a034SMikko Perttunen 4857780a034SMikko Perttunen cpu@2 { 4867780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 4877780a034SMikko Perttunen device_type = "cpu"; 4887780a034SMikko Perttunen reg = <0x100>; 4897780a034SMikko Perttunen enable-method = "psci"; 4907780a034SMikko Perttunen }; 4917780a034SMikko Perttunen 4927780a034SMikko Perttunen cpu@3 { 4937780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 4947780a034SMikko Perttunen device_type = "cpu"; 4957780a034SMikko Perttunen reg = <0x101>; 4967780a034SMikko Perttunen enable-method = "psci"; 4977780a034SMikko Perttunen }; 4987780a034SMikko Perttunen 4997780a034SMikko Perttunen cpu@4 { 5007780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 5017780a034SMikko Perttunen device_type = "cpu"; 5027780a034SMikko Perttunen reg = <0x200>; 5037780a034SMikko Perttunen enable-method = "psci"; 5047780a034SMikko Perttunen }; 5057780a034SMikko Perttunen 5067780a034SMikko Perttunen cpu@5 { 5077780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 5087780a034SMikko Perttunen device_type = "cpu"; 5097780a034SMikko Perttunen reg = <0x201>; 5107780a034SMikko Perttunen enable-method = "psci"; 5117780a034SMikko Perttunen }; 5127780a034SMikko Perttunen 5137780a034SMikko Perttunen cpu@6 { 5147780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 5157780a034SMikko Perttunen device_type = "cpu"; 5167780a034SMikko Perttunen reg = <0x10300>; 5177780a034SMikko Perttunen enable-method = "psci"; 5187780a034SMikko Perttunen }; 5197780a034SMikko Perttunen 5207780a034SMikko Perttunen cpu@7 { 5217780a034SMikko Perttunen compatible = "nvidia,tegra194-carmel", "arm,armv8"; 5227780a034SMikko Perttunen device_type = "cpu"; 5237780a034SMikko Perttunen reg = <0x10301>; 5247780a034SMikko Perttunen enable-method = "psci"; 5257780a034SMikko Perttunen }; 5267780a034SMikko Perttunen }; 5277780a034SMikko Perttunen 5287780a034SMikko Perttunen psci { 5297780a034SMikko Perttunen compatible = "arm,psci-1.0"; 5307780a034SMikko Perttunen status = "okay"; 5317780a034SMikko Perttunen method = "smc"; 5327780a034SMikko Perttunen }; 5337780a034SMikko Perttunen 5345425fb15SMikko Perttunen timer { 5355425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 5365425fb15SMikko Perttunen interrupts = <GIC_PPI 13 5375425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5385425fb15SMikko Perttunen <GIC_PPI 14 5395425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5405425fb15SMikko Perttunen <GIC_PPI 11 5415425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5425425fb15SMikko Perttunen <GIC_PPI 10 5435425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 5445425fb15SMikko Perttunen interrupt-parent = <&gic>; 5455425fb15SMikko Perttunen }; 5465425fb15SMikko Perttunen}; 547