15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 65425fb15SMikko Perttunen#include <dt-bindings/reset/tegra194-reset.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 95425fb15SMikko Perttunen 105425fb15SMikko Perttunen/ { 115425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 125425fb15SMikko Perttunen interrupt-parent = <&gic>; 135425fb15SMikko Perttunen #address-cells = <2>; 145425fb15SMikko Perttunen #size-cells = <2>; 155425fb15SMikko Perttunen 165425fb15SMikko Perttunen /* control backbone */ 175425fb15SMikko Perttunen cbb { 185425fb15SMikko Perttunen compatible = "simple-bus"; 195425fb15SMikko Perttunen #address-cells = <1>; 205425fb15SMikko Perttunen #size-cells = <1>; 215425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 225425fb15SMikko Perttunen 23f69ce393SMikko Perttunen gpio: gpio@2200000 { 24f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 25f69ce393SMikko Perttunen reg-names = "security", "gpio"; 26f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 27f69ce393SMikko Perttunen <0x2210000 0x10000>; 28f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34f69ce393SMikko Perttunen #interrupt-cells = <2>; 35f69ce393SMikko Perttunen interrupt-controller; 36f69ce393SMikko Perttunen #gpio-cells = <2>; 37f69ce393SMikko Perttunen gpio-controller; 38f69ce393SMikko Perttunen }; 39f69ce393SMikko Perttunen 40f89b58ceSMikko Perttunen ethernet@2490000 { 41f89b58ceSMikko Perttunen compatible = "nvidia,tegra186-eqos", 42f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 43f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 44f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 47f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 48f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 49f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 52f89b58ceSMikko Perttunen reset-names = "eqos"; 53f89b58ceSMikko Perttunen status = "disabled"; 54f89b58ceSMikko Perttunen 55f89b58ceSMikko Perttunen snps,write-requests = <1>; 56f89b58ceSMikko Perttunen snps,read-requests = <3>; 57f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 58f89b58ceSMikko Perttunen snps,txpbl = <16>; 59f89b58ceSMikko Perttunen snps,rxpbl = <8>; 60f89b58ceSMikko Perttunen }; 61f89b58ceSMikko Perttunen 625d2249ddSSameer Pujar aconnect { 635d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 645d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 655d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 665d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 675d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 685d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 695d2249ddSSameer Pujar #address-cells = <1>; 705d2249ddSSameer Pujar #size-cells = <1>; 715d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 725d2249ddSSameer Pujar status = "disabled"; 735d2249ddSSameer Pujar 745d2249ddSSameer Pujar dma-controller@2930000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 765d2249ddSSameer Pujar "nvidia,tegra186-adma"; 775d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 785d2249ddSSameer Pujar interrupt-parent = <&agic>; 795d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 805d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 815d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 825d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 835d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 845d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 855d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 865d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 875d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 885d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 895d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1115d2249ddSSameer Pujar #dma-cells = <1>; 1125d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1135d2249ddSSameer Pujar clock-names = "d_audio"; 1145d2249ddSSameer Pujar status = "disabled"; 1155d2249ddSSameer Pujar }; 1165d2249ddSSameer Pujar 1175d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1185d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1195d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1205d2249ddSSameer Pujar #interrupt-cells = <3>; 1215d2249ddSSameer Pujar interrupt-controller; 1225d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1235d2249ddSSameer Pujar <0x02a42000 0x2000>; 1245d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1255d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1265d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1275d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1285d2249ddSSameer Pujar clock-names = "clk"; 1295d2249ddSSameer Pujar status = "disabled"; 1305d2249ddSSameer Pujar }; 1315d2249ddSSameer Pujar }; 1325d2249ddSSameer Pujar 1335425fb15SMikko Perttunen uarta: serial@3100000 { 1345425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1355425fb15SMikko Perttunen reg = <0x03100000 0x40>; 1365425fb15SMikko Perttunen reg-shift = <2>; 1375425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 1395425fb15SMikko Perttunen clock-names = "serial"; 1405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 1415425fb15SMikko Perttunen reset-names = "serial"; 1425425fb15SMikko Perttunen status = "disabled"; 1435425fb15SMikko Perttunen }; 1445425fb15SMikko Perttunen 1455425fb15SMikko Perttunen uartb: serial@3110000 { 1465425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1475425fb15SMikko Perttunen reg = <0x03110000 0x40>; 1485425fb15SMikko Perttunen reg-shift = <2>; 1495425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1505425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 1515425fb15SMikko Perttunen clock-names = "serial"; 1525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 1535425fb15SMikko Perttunen reset-names = "serial"; 1545425fb15SMikko Perttunen status = "disabled"; 1555425fb15SMikko Perttunen }; 1565425fb15SMikko Perttunen 1575425fb15SMikko Perttunen uartd: serial@3130000 { 1585425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1595425fb15SMikko Perttunen reg = <0x03130000 0x40>; 1605425fb15SMikko Perttunen reg-shift = <2>; 1615425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 1635425fb15SMikko Perttunen clock-names = "serial"; 1645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 1655425fb15SMikko Perttunen reset-names = "serial"; 1665425fb15SMikko Perttunen status = "disabled"; 1675425fb15SMikko Perttunen }; 1685425fb15SMikko Perttunen 1695425fb15SMikko Perttunen uarte: serial@3140000 { 1705425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1715425fb15SMikko Perttunen reg = <0x03140000 0x40>; 1725425fb15SMikko Perttunen reg-shift = <2>; 1735425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1745425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 1755425fb15SMikko Perttunen clock-names = "serial"; 1765425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 1775425fb15SMikko Perttunen reset-names = "serial"; 1785425fb15SMikko Perttunen status = "disabled"; 1795425fb15SMikko Perttunen }; 1805425fb15SMikko Perttunen 1815425fb15SMikko Perttunen uartf: serial@3150000 { 1825425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1835425fb15SMikko Perttunen reg = <0x03150000 0x40>; 1845425fb15SMikko Perttunen reg-shift = <2>; 1855425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1865425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 1875425fb15SMikko Perttunen clock-names = "serial"; 1885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 1895425fb15SMikko Perttunen reset-names = "serial"; 1905425fb15SMikko Perttunen status = "disabled"; 1915425fb15SMikko Perttunen }; 1925425fb15SMikko Perttunen 1935425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 194d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1955425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 1965425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1975425fb15SMikko Perttunen #address-cells = <1>; 1985425fb15SMikko Perttunen #size-cells = <0>; 1995425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2005425fb15SMikko Perttunen clock-names = "div-clk"; 2015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2025425fb15SMikko Perttunen reset-names = "i2c"; 2035425fb15SMikko Perttunen status = "disabled"; 2045425fb15SMikko Perttunen }; 2055425fb15SMikko Perttunen 2065425fb15SMikko Perttunen uarth: serial@3170000 { 2075425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2085425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2095425fb15SMikko Perttunen reg-shift = <2>; 2105425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 2125425fb15SMikko Perttunen clock-names = "serial"; 2135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 2145425fb15SMikko Perttunen reset-names = "serial"; 2155425fb15SMikko Perttunen status = "disabled"; 2165425fb15SMikko Perttunen }; 2175425fb15SMikko Perttunen 2185425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 219d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2205425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 2215425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2225425fb15SMikko Perttunen #address-cells = <1>; 2235425fb15SMikko Perttunen #size-cells = <0>; 2245425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 2255425fb15SMikko Perttunen clock-names = "div-clk"; 2265425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 2275425fb15SMikko Perttunen reset-names = "i2c"; 2285425fb15SMikko Perttunen status = "disabled"; 2295425fb15SMikko Perttunen }; 2305425fb15SMikko Perttunen 2315425fb15SMikko Perttunen /* shares pads with dpaux1 */ 2325425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 233d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2345425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 2355425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2365425fb15SMikko Perttunen #address-cells = <1>; 2375425fb15SMikko Perttunen #size-cells = <0>; 2385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 2395425fb15SMikko Perttunen clock-names = "div-clk"; 2405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 2415425fb15SMikko Perttunen reset-names = "i2c"; 2425425fb15SMikko Perttunen status = "disabled"; 2435425fb15SMikko Perttunen }; 2445425fb15SMikko Perttunen 2455425fb15SMikko Perttunen /* shares pads with dpaux0 */ 2465425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 247d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2485425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 2495425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2505425fb15SMikko Perttunen #address-cells = <1>; 2515425fb15SMikko Perttunen #size-cells = <0>; 2525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 2535425fb15SMikko Perttunen clock-names = "div-clk"; 2545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 2555425fb15SMikko Perttunen reset-names = "i2c"; 2565425fb15SMikko Perttunen status = "disabled"; 2575425fb15SMikko Perttunen }; 2585425fb15SMikko Perttunen 2595425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 260d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2615425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 2625425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2635425fb15SMikko Perttunen #address-cells = <1>; 2645425fb15SMikko Perttunen #size-cells = <0>; 2655425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 2665425fb15SMikko Perttunen clock-names = "div-clk"; 2675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 2685425fb15SMikko Perttunen reset-names = "i2c"; 2695425fb15SMikko Perttunen status = "disabled"; 2705425fb15SMikko Perttunen }; 2715425fb15SMikko Perttunen 2725425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 273d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2745425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 2755425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2765425fb15SMikko Perttunen #address-cells = <1>; 2775425fb15SMikko Perttunen #size-cells = <0>; 2785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 2795425fb15SMikko Perttunen clock-names = "div-clk"; 2805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 2815425fb15SMikko Perttunen reset-names = "i2c"; 2825425fb15SMikko Perttunen status = "disabled"; 2835425fb15SMikko Perttunen }; 2845425fb15SMikko Perttunen 2856a574ec7SThierry Reding pwm1: pwm@3280000 { 2866a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2876a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2886a574ec7SThierry Reding reg = <0x3280000 0x10000>; 2896a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 2906a574ec7SThierry Reding clock-names = "pwm"; 2916a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 2926a574ec7SThierry Reding reset-names = "pwm"; 2936a574ec7SThierry Reding status = "disabled"; 2946a574ec7SThierry Reding #pwm-cells = <2>; 2956a574ec7SThierry Reding }; 2966a574ec7SThierry Reding 2976a574ec7SThierry Reding pwm2: pwm@3290000 { 2986a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2996a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3006a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3016a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3026a574ec7SThierry Reding clock-names = "pwm"; 3036a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3046a574ec7SThierry Reding reset-names = "pwm"; 3056a574ec7SThierry Reding status = "disabled"; 3066a574ec7SThierry Reding #pwm-cells = <2>; 3076a574ec7SThierry Reding }; 3086a574ec7SThierry Reding 3096a574ec7SThierry Reding pwm3: pwm@32a0000 { 3106a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3116a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3126a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 3136a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 3146a574ec7SThierry Reding clock-names = "pwm"; 3156a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 3166a574ec7SThierry Reding reset-names = "pwm"; 3176a574ec7SThierry Reding status = "disabled"; 3186a574ec7SThierry Reding #pwm-cells = <2>; 3196a574ec7SThierry Reding }; 3206a574ec7SThierry Reding 3216a574ec7SThierry Reding pwm5: pwm@32c0000 { 3226a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3236a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3246a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 3256a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 3266a574ec7SThierry Reding clock-names = "pwm"; 3276a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 3286a574ec7SThierry Reding reset-names = "pwm"; 3296a574ec7SThierry Reding status = "disabled"; 3306a574ec7SThierry Reding #pwm-cells = <2>; 3316a574ec7SThierry Reding }; 3326a574ec7SThierry Reding 3336a574ec7SThierry Reding pwm6: pwm@32d0000 { 3346a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3356a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3366a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 3376a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 3386a574ec7SThierry Reding clock-names = "pwm"; 3396a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 3406a574ec7SThierry Reding reset-names = "pwm"; 3416a574ec7SThierry Reding status = "disabled"; 3426a574ec7SThierry Reding #pwm-cells = <2>; 3436a574ec7SThierry Reding }; 3446a574ec7SThierry Reding 3456a574ec7SThierry Reding pwm7: pwm@32e0000 { 3466a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3476a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3486a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 3496a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 3506a574ec7SThierry Reding clock-names = "pwm"; 3516a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 3526a574ec7SThierry Reding reset-names = "pwm"; 3536a574ec7SThierry Reding status = "disabled"; 3546a574ec7SThierry Reding #pwm-cells = <2>; 3556a574ec7SThierry Reding }; 3566a574ec7SThierry Reding 3576a574ec7SThierry Reding pwm8: pwm@32f0000 { 3586a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3596a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3606a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 3616a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 3626a574ec7SThierry Reding clock-names = "pwm"; 3636a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 3646a574ec7SThierry Reding reset-names = "pwm"; 3656a574ec7SThierry Reding status = "disabled"; 3666a574ec7SThierry Reding #pwm-cells = <2>; 3676a574ec7SThierry Reding }; 3686a574ec7SThierry Reding 3695425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 3705425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3715425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 3725425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3735425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 3745425fb15SMikko Perttunen clock-names = "sdhci"; 3755425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 3765425fb15SMikko Perttunen reset-names = "sdhci"; 3774e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 3784e0f1229SSowjanya Komatineni <0x07>; 3794e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 3804e0f1229SSowjanya Komatineni <0x07>; 3814e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 3834e0f1229SSowjanya Komatineni <0x07>; 3844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3864e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 3874e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 3885425fb15SMikko Perttunen status = "disabled"; 3895425fb15SMikko Perttunen }; 3905425fb15SMikko Perttunen 3915425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 3925425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3935425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 3945425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 3955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 3965425fb15SMikko Perttunen clock-names = "sdhci"; 3975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 3985425fb15SMikko Perttunen reset-names = "sdhci"; 3994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 4024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4034e0f1229SSowjanya Komatineni <0x07>; 4044e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4064e0f1229SSowjanya Komatineni <0x07>; 4074e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4094e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4104e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4115425fb15SMikko Perttunen status = "disabled"; 4125425fb15SMikko Perttunen }; 4135425fb15SMikko Perttunen 4145425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 4155425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4165425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 4175425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 4185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 4195425fb15SMikko Perttunen clock-names = "sdhci"; 420351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 421351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 422351648d0SSowjanya Komatineni assigned-clock-parents = 423351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 4245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 4255425fb15SMikko Perttunen reset-names = "sdhci"; 4264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 4274e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 4284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 4294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4304e0f1229SSowjanya Komatineni <0x0a>; 4314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 4324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4334e0f1229SSowjanya Komatineni <0x0a>; 4344e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 4354e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 4364e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 437dfd3cb6fSSowjanya Komatineni supports-cqe; 4385425fb15SMikko Perttunen status = "disabled"; 4395425fb15SMikko Perttunen }; 4405425fb15SMikko Perttunen 4414878cc0cSSameer Pujar hda@3510000 { 4424878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 4434878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 4444878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4454878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 4464878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 4474878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 4484878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 4494878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 4504878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 4514878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 4524878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 4534878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 4544878cc0cSSameer Pujar status = "disabled"; 4554878cc0cSSameer Pujar }; 4564878cc0cSSameer Pujar 4575425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 4585425fb15SMikko Perttunen compatible = "arm,gic-400"; 4595425fb15SMikko Perttunen #interrupt-cells = <3>; 4605425fb15SMikko Perttunen interrupt-controller; 4615425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 4625425fb15SMikko Perttunen <0x03882000 0x2000>, 4635425fb15SMikko Perttunen <0x03884000 0x2000>, 4645425fb15SMikko Perttunen <0x03886000 0x2000>; 4655425fb15SMikko Perttunen interrupts = <GIC_PPI 9 4665425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4675425fb15SMikko Perttunen interrupt-parent = <&gic>; 4685425fb15SMikko Perttunen }; 4695425fb15SMikko Perttunen 470badb80beSThierry Reding cec@3960000 { 471badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 472badb80beSThierry Reding reg = <0x03960000 0x10000>; 473badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 474badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 475badb80beSThierry Reding clock-names = "cec"; 476badb80beSThierry Reding status = "disabled"; 477badb80beSThierry Reding }; 478badb80beSThierry Reding 4795425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 480a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 4815425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 482a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 483a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 484a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 485a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 486a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 487a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 488a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 489a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 490a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 491a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 492a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 493a38570c2SMikko Perttunen "shared7"; 494a38570c2SMikko Perttunen #mbox-cells = <2>; 495a38570c2SMikko Perttunen }; 496a38570c2SMikko Perttunen 497a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 498a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 499a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 500a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 501a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 502a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 503a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 504a38570c2SMikko Perttunen /* 505a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 506a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 507a38570c2SMikko Perttunen */ 508a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 5095425fb15SMikko Perttunen #mbox-cells = <2>; 5105425fb15SMikko Perttunen }; 5115425fb15SMikko Perttunen 5125425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 513d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5145425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 5155425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 5165425fb15SMikko Perttunen #address-cells = <1>; 5175425fb15SMikko Perttunen #size-cells = <0>; 5185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 5195425fb15SMikko Perttunen clock-names = "div-clk"; 5205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 5215425fb15SMikko Perttunen reset-names = "i2c"; 5225425fb15SMikko Perttunen status = "disabled"; 5235425fb15SMikko Perttunen }; 5245425fb15SMikko Perttunen 5255425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 526d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5275425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 5285425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5295425fb15SMikko Perttunen #address-cells = <1>; 5305425fb15SMikko Perttunen #size-cells = <0>; 5315425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 5325425fb15SMikko Perttunen clock-names = "div-clk"; 5335425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 5345425fb15SMikko Perttunen reset-names = "i2c"; 5355425fb15SMikko Perttunen status = "disabled"; 5365425fb15SMikko Perttunen }; 5375425fb15SMikko Perttunen 5385425fb15SMikko Perttunen uartc: serial@c280000 { 5395425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5405425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 5415425fb15SMikko Perttunen reg-shift = <2>; 5425425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 5435425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 5445425fb15SMikko Perttunen clock-names = "serial"; 5455425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 5465425fb15SMikko Perttunen reset-names = "serial"; 5475425fb15SMikko Perttunen status = "disabled"; 5485425fb15SMikko Perttunen }; 5495425fb15SMikko Perttunen 5505425fb15SMikko Perttunen uartg: serial@c290000 { 5515425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5525425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 5535425fb15SMikko Perttunen reg-shift = <2>; 5545425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 5555425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 5565425fb15SMikko Perttunen clock-names = "serial"; 5575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 5585425fb15SMikko Perttunen reset-names = "serial"; 5595425fb15SMikko Perttunen status = "disabled"; 5605425fb15SMikko Perttunen }; 5615425fb15SMikko Perttunen 56237e5a31dSThierry Reding rtc: rtc@c2a0000 { 56337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 56437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 56537e5a31dSThierry Reding interrupt-parent = <&pmc>; 56637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 56737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 56837e5a31dSThierry Reding clock-names = "rtc"; 56937e5a31dSThierry Reding status = "disabled"; 57037e5a31dSThierry Reding }; 57137e5a31dSThierry Reding 5724d286331SThierry Reding gpio_aon: gpio@c2f0000 { 5734d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 5744d286331SThierry Reding reg-names = "security", "gpio"; 5754d286331SThierry Reding reg = <0xc2f0000 0x1000>, 5764d286331SThierry Reding <0xc2f1000 0x1000>; 5774d286331SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 5784d286331SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 5794d286331SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 5804d286331SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 5814d286331SThierry Reding gpio-controller; 5824d286331SThierry Reding #gpio-cells = <2>; 5834d286331SThierry Reding interrupt-controller; 5844d286331SThierry Reding #interrupt-cells = <2>; 5854d286331SThierry Reding }; 5864d286331SThierry Reding 5876a574ec7SThierry Reding pwm4: pwm@c340000 { 5886a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 5896a574ec7SThierry Reding "nvidia,tegra186-pwm"; 5906a574ec7SThierry Reding reg = <0xc340000 0x10000>; 5916a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 5926a574ec7SThierry Reding clock-names = "pwm"; 5936a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 5946a574ec7SThierry Reding reset-names = "pwm"; 5956a574ec7SThierry Reding status = "disabled"; 5966a574ec7SThierry Reding #pwm-cells = <2>; 5976a574ec7SThierry Reding }; 5986a574ec7SThierry Reding 59938ecf1e5SThierry Reding pmc: pmc@c360000 { 6005425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 6015425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 6025425fb15SMikko Perttunen <0x0c370000 0x10000>, 6035425fb15SMikko Perttunen <0x0c380000 0x10000>, 6045425fb15SMikko Perttunen <0x0c390000 0x10000>, 6055425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 6065425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 60738ecf1e5SThierry Reding 60838ecf1e5SThierry Reding #interrupt-cells = <2>; 60938ecf1e5SThierry Reding interrupt-controller; 6105425fb15SMikko Perttunen }; 6113db6d3baSThierry Reding 6123db6d3baSThierry Reding host1x@13e00000 { 6133db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 6143db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 6153db6d3baSThierry Reding <0x13e10000 0x10000>; 6163db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 6173db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 6183db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 6193db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 6203db6d3baSThierry Reding clock-names = "host1x"; 6213db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 6223db6d3baSThierry Reding reset-names = "host1x"; 6233db6d3baSThierry Reding 6243db6d3baSThierry Reding #address-cells = <1>; 6253db6d3baSThierry Reding #size-cells = <1>; 6263db6d3baSThierry Reding 6273db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 6283db6d3baSThierry Reding 6293db6d3baSThierry Reding display-hub@15200000 { 6303db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 631611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 6323db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 6333db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 6343db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 6353db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 6363db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 6373db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 6383db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 6393db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 6403db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 6413db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 6423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 6433db6d3baSThierry Reding clock-names = "disp", "hub"; 6443db6d3baSThierry Reding status = "disabled"; 6453db6d3baSThierry Reding 6463db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 6473db6d3baSThierry Reding 6483db6d3baSThierry Reding #address-cells = <1>; 6493db6d3baSThierry Reding #size-cells = <1>; 6503db6d3baSThierry Reding 6513db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 6523db6d3baSThierry Reding 6533db6d3baSThierry Reding display@15200000 { 6543db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 6553db6d3baSThierry Reding reg = <0x15200000 0x10000>; 6563db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 6573db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 6583db6d3baSThierry Reding clock-names = "dc"; 6593db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 6603db6d3baSThierry Reding reset-names = "dc"; 6613db6d3baSThierry Reding 6623db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 6633db6d3baSThierry Reding 6643db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 6653db6d3baSThierry Reding nvidia,head = <0>; 6663db6d3baSThierry Reding }; 6673db6d3baSThierry Reding 6683db6d3baSThierry Reding display@15210000 { 6693db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 6703db6d3baSThierry Reding reg = <0x15210000 0x10000>; 6713db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 6723db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 6733db6d3baSThierry Reding clock-names = "dc"; 6743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 6753db6d3baSThierry Reding reset-names = "dc"; 6763db6d3baSThierry Reding 6773db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 6783db6d3baSThierry Reding 6793db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 6803db6d3baSThierry Reding nvidia,head = <1>; 6813db6d3baSThierry Reding }; 6823db6d3baSThierry Reding 6833db6d3baSThierry Reding display@15220000 { 6843db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 6853db6d3baSThierry Reding reg = <0x15220000 0x10000>; 6863db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 6873db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 6883db6d3baSThierry Reding clock-names = "dc"; 6893db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 6903db6d3baSThierry Reding reset-names = "dc"; 6913db6d3baSThierry Reding 6923db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 6933db6d3baSThierry Reding 6943db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 6953db6d3baSThierry Reding nvidia,head = <2>; 6963db6d3baSThierry Reding }; 6973db6d3baSThierry Reding 6983db6d3baSThierry Reding display@15230000 { 6993db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 7003db6d3baSThierry Reding reg = <0x15230000 0x10000>; 7013db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 7023db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 7033db6d3baSThierry Reding clock-names = "dc"; 7043db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 7053db6d3baSThierry Reding reset-names = "dc"; 7063db6d3baSThierry Reding 7073db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 7083db6d3baSThierry Reding 7093db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 7103db6d3baSThierry Reding nvidia,head = <3>; 7113db6d3baSThierry Reding }; 7123db6d3baSThierry Reding }; 7133db6d3baSThierry Reding 7148d424ec2SThierry Reding vic@15340000 { 7158d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 7168d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 7178d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 7188d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 7198d424ec2SThierry Reding clock-names = "vic"; 7208d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 7218d424ec2SThierry Reding reset-names = "vic"; 7228d424ec2SThierry Reding 7238d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 7248d424ec2SThierry Reding }; 7258d424ec2SThierry Reding 7263db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 7273db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 7283db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 7293db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 7303db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 7313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 7323db6d3baSThierry Reding clock-names = "dpaux", "parent"; 7333db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 7343db6d3baSThierry Reding reset-names = "dpaux"; 7353db6d3baSThierry Reding status = "disabled"; 7363db6d3baSThierry Reding 7373db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 7383db6d3baSThierry Reding 7393db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 7403db6d3baSThierry Reding groups = "dpaux-io"; 7413db6d3baSThierry Reding function = "aux"; 7423db6d3baSThierry Reding }; 7433db6d3baSThierry Reding 7443db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 7453db6d3baSThierry Reding groups = "dpaux-io"; 7463db6d3baSThierry Reding function = "i2c"; 7473db6d3baSThierry Reding }; 7483db6d3baSThierry Reding 7493db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 7503db6d3baSThierry Reding groups = "dpaux-io"; 7513db6d3baSThierry Reding function = "off"; 7523db6d3baSThierry Reding }; 7533db6d3baSThierry Reding 7543db6d3baSThierry Reding i2c-bus { 7553db6d3baSThierry Reding #address-cells = <1>; 7563db6d3baSThierry Reding #size-cells = <0>; 7573db6d3baSThierry Reding }; 7583db6d3baSThierry Reding }; 7593db6d3baSThierry Reding 7603db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 7613db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 7623db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 7633db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 7643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 7653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 7663db6d3baSThierry Reding clock-names = "dpaux", "parent"; 7673db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 7683db6d3baSThierry Reding reset-names = "dpaux"; 7693db6d3baSThierry Reding status = "disabled"; 7703db6d3baSThierry Reding 7713db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 7723db6d3baSThierry Reding 7733db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 7743db6d3baSThierry Reding groups = "dpaux-io"; 7753db6d3baSThierry Reding function = "aux"; 7763db6d3baSThierry Reding }; 7773db6d3baSThierry Reding 7783db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 7793db6d3baSThierry Reding groups = "dpaux-io"; 7803db6d3baSThierry Reding function = "i2c"; 7813db6d3baSThierry Reding }; 7823db6d3baSThierry Reding 7833db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 7843db6d3baSThierry Reding groups = "dpaux-io"; 7853db6d3baSThierry Reding function = "off"; 7863db6d3baSThierry Reding }; 7873db6d3baSThierry Reding 7883db6d3baSThierry Reding i2c-bus { 7893db6d3baSThierry Reding #address-cells = <1>; 7903db6d3baSThierry Reding #size-cells = <0>; 7913db6d3baSThierry Reding }; 7923db6d3baSThierry Reding }; 7933db6d3baSThierry Reding 7943db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 7953db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 7963db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 7973db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 7983db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 7993db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 8003db6d3baSThierry Reding clock-names = "dpaux", "parent"; 8013db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 8023db6d3baSThierry Reding reset-names = "dpaux"; 8033db6d3baSThierry Reding status = "disabled"; 8043db6d3baSThierry Reding 8053db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8063db6d3baSThierry Reding 8073db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 8083db6d3baSThierry Reding groups = "dpaux-io"; 8093db6d3baSThierry Reding function = "aux"; 8103db6d3baSThierry Reding }; 8113db6d3baSThierry Reding 8123db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 8133db6d3baSThierry Reding groups = "dpaux-io"; 8143db6d3baSThierry Reding function = "i2c"; 8153db6d3baSThierry Reding }; 8163db6d3baSThierry Reding 8173db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 8183db6d3baSThierry Reding groups = "dpaux-io"; 8193db6d3baSThierry Reding function = "off"; 8203db6d3baSThierry Reding }; 8213db6d3baSThierry Reding 8223db6d3baSThierry Reding i2c-bus { 8233db6d3baSThierry Reding #address-cells = <1>; 8243db6d3baSThierry Reding #size-cells = <0>; 8253db6d3baSThierry Reding }; 8263db6d3baSThierry Reding }; 8273db6d3baSThierry Reding 8283db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 8293db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 8303db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 8313db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 8323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 8333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 8343db6d3baSThierry Reding clock-names = "dpaux", "parent"; 8353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 8363db6d3baSThierry Reding reset-names = "dpaux"; 8373db6d3baSThierry Reding status = "disabled"; 8383db6d3baSThierry Reding 8393db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8403db6d3baSThierry Reding 8413db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 8423db6d3baSThierry Reding groups = "dpaux-io"; 8433db6d3baSThierry Reding function = "aux"; 8443db6d3baSThierry Reding }; 8453db6d3baSThierry Reding 8463db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 8473db6d3baSThierry Reding groups = "dpaux-io"; 8483db6d3baSThierry Reding function = "i2c"; 8493db6d3baSThierry Reding }; 8503db6d3baSThierry Reding 8513db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 8523db6d3baSThierry Reding groups = "dpaux-io"; 8533db6d3baSThierry Reding function = "off"; 8543db6d3baSThierry Reding }; 8553db6d3baSThierry Reding 8563db6d3baSThierry Reding i2c-bus { 8573db6d3baSThierry Reding #address-cells = <1>; 8583db6d3baSThierry Reding #size-cells = <0>; 8593db6d3baSThierry Reding }; 8603db6d3baSThierry Reding }; 8613db6d3baSThierry Reding 8623db6d3baSThierry Reding sor0: sor@15b00000 { 8633db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 8643db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 8653db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 8663db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 8673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 8683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 8693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 8703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 8713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 8723db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 8733db6d3baSThierry Reding "pad"; 8743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 8753db6d3baSThierry Reding reset-names = "sor"; 8763db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 8773db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 8783db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 8793db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 8803db6d3baSThierry Reding status = "disabled"; 8813db6d3baSThierry Reding 8823db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8833db6d3baSThierry Reding nvidia,interface = <0>; 8843db6d3baSThierry Reding }; 8853db6d3baSThierry Reding 8863db6d3baSThierry Reding sor1: sor@15b40000 { 8873db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 8883db6d3baSThierry Reding reg = <0x155c0000 0x40000>; 8893db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 8903db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 8913db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 8923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 8933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 8943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 8953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 8963db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 8973db6d3baSThierry Reding "pad"; 8983db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 8993db6d3baSThierry Reding reset-names = "sor"; 9003db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 9013db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 9023db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 9033db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 9043db6d3baSThierry Reding status = "disabled"; 9053db6d3baSThierry Reding 9063db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9073db6d3baSThierry Reding nvidia,interface = <1>; 9083db6d3baSThierry Reding }; 9093db6d3baSThierry Reding 9103db6d3baSThierry Reding sor2: sor@15b80000 { 9113db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 9123db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 9133db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 9143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 9153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 9163db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 9173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 9183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 9193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 9203db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 9213db6d3baSThierry Reding "pad"; 9223db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 9233db6d3baSThierry Reding reset-names = "sor"; 9243db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 9253db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 9263db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 9273db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 9283db6d3baSThierry Reding status = "disabled"; 9293db6d3baSThierry Reding 9303db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9313db6d3baSThierry Reding nvidia,interface = <2>; 9323db6d3baSThierry Reding }; 9333db6d3baSThierry Reding 9343db6d3baSThierry Reding sor3: sor@15bc0000 { 9353db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 9363db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 9373db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 9383db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 9393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 9403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 9413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 9423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 9433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 9443db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 9453db6d3baSThierry Reding "pad"; 9463db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 9473db6d3baSThierry Reding reset-names = "sor"; 9483db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 9493db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 9503db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 9513db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 9523db6d3baSThierry Reding status = "disabled"; 9533db6d3baSThierry Reding 9543db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9553db6d3baSThierry Reding nvidia,interface = <3>; 9563db6d3baSThierry Reding }; 9573db6d3baSThierry Reding }; 9585425fb15SMikko Perttunen }; 9595425fb15SMikko Perttunen 9605425fb15SMikko Perttunen sysram@40000000 { 9615425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 9625425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 9635425fb15SMikko Perttunen #address-cells = <1>; 9645425fb15SMikko Perttunen #size-cells = <1>; 9655425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 9665425fb15SMikko Perttunen 9675425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 9685425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 9695425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 9705425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 9715425fb15SMikko Perttunen pool; 9725425fb15SMikko Perttunen }; 9735425fb15SMikko Perttunen 9745425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 9755425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 9765425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 9775425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 9785425fb15SMikko Perttunen pool; 9795425fb15SMikko Perttunen }; 9805425fb15SMikko Perttunen }; 9815425fb15SMikko Perttunen 9825425fb15SMikko Perttunen bpmp: bpmp { 9835425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 9845425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 9855425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 9865425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 9875425fb15SMikko Perttunen #clock-cells = <1>; 9885425fb15SMikko Perttunen #reset-cells = <1>; 9895425fb15SMikko Perttunen #power-domain-cells = <1>; 9905425fb15SMikko Perttunen 9915425fb15SMikko Perttunen bpmp_i2c: i2c { 9925425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 9935425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 9945425fb15SMikko Perttunen #address-cells = <1>; 9955425fb15SMikko Perttunen #size-cells = <0>; 9965425fb15SMikko Perttunen }; 9975425fb15SMikko Perttunen 9985425fb15SMikko Perttunen bpmp_thermal: thermal { 9995425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 10005425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 10015425fb15SMikko Perttunen }; 10025425fb15SMikko Perttunen }; 10035425fb15SMikko Perttunen 10047780a034SMikko Perttunen cpus { 10057780a034SMikko Perttunen #address-cells = <1>; 10067780a034SMikko Perttunen #size-cells = <0>; 10077780a034SMikko Perttunen 10087780a034SMikko Perttunen cpu@0 { 100931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10107780a034SMikko Perttunen device_type = "cpu"; 10117780a034SMikko Perttunen reg = <0x10000>; 10127780a034SMikko Perttunen enable-method = "psci"; 10137780a034SMikko Perttunen }; 10147780a034SMikko Perttunen 10157780a034SMikko Perttunen cpu@1 { 101631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10177780a034SMikko Perttunen device_type = "cpu"; 10187780a034SMikko Perttunen reg = <0x10001>; 10197780a034SMikko Perttunen enable-method = "psci"; 10207780a034SMikko Perttunen }; 10217780a034SMikko Perttunen 10227780a034SMikko Perttunen cpu@2 { 102331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10247780a034SMikko Perttunen device_type = "cpu"; 10257780a034SMikko Perttunen reg = <0x100>; 10267780a034SMikko Perttunen enable-method = "psci"; 10277780a034SMikko Perttunen }; 10287780a034SMikko Perttunen 10297780a034SMikko Perttunen cpu@3 { 103031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10317780a034SMikko Perttunen device_type = "cpu"; 10327780a034SMikko Perttunen reg = <0x101>; 10337780a034SMikko Perttunen enable-method = "psci"; 10347780a034SMikko Perttunen }; 10357780a034SMikko Perttunen 10367780a034SMikko Perttunen cpu@4 { 103731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10387780a034SMikko Perttunen device_type = "cpu"; 10397780a034SMikko Perttunen reg = <0x200>; 10407780a034SMikko Perttunen enable-method = "psci"; 10417780a034SMikko Perttunen }; 10427780a034SMikko Perttunen 10437780a034SMikko Perttunen cpu@5 { 104431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10457780a034SMikko Perttunen device_type = "cpu"; 10467780a034SMikko Perttunen reg = <0x201>; 10477780a034SMikko Perttunen enable-method = "psci"; 10487780a034SMikko Perttunen }; 10497780a034SMikko Perttunen 10507780a034SMikko Perttunen cpu@6 { 105131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10527780a034SMikko Perttunen device_type = "cpu"; 10537780a034SMikko Perttunen reg = <0x10300>; 10547780a034SMikko Perttunen enable-method = "psci"; 10557780a034SMikko Perttunen }; 10567780a034SMikko Perttunen 10577780a034SMikko Perttunen cpu@7 { 105831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 10597780a034SMikko Perttunen device_type = "cpu"; 10607780a034SMikko Perttunen reg = <0x10301>; 10617780a034SMikko Perttunen enable-method = "psci"; 10627780a034SMikko Perttunen }; 10637780a034SMikko Perttunen }; 10647780a034SMikko Perttunen 10657780a034SMikko Perttunen psci { 10667780a034SMikko Perttunen compatible = "arm,psci-1.0"; 10677780a034SMikko Perttunen status = "okay"; 10687780a034SMikko Perttunen method = "smc"; 10697780a034SMikko Perttunen }; 10707780a034SMikko Perttunen 1071a38570c2SMikko Perttunen tcu: tcu { 1072a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 1073a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1074a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1075a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 1076a38570c2SMikko Perttunen }; 1077a38570c2SMikko Perttunen 1078686ba009SThierry Reding thermal-zones { 1079686ba009SThierry Reding cpu { 1080686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1081686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1082686ba009SThierry Reding status = "disabled"; 1083686ba009SThierry Reding }; 1084686ba009SThierry Reding 1085686ba009SThierry Reding gpu { 1086686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1087686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1088686ba009SThierry Reding status = "disabled"; 1089686ba009SThierry Reding }; 1090686ba009SThierry Reding 1091686ba009SThierry Reding aux { 1092686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1093686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1094686ba009SThierry Reding status = "disabled"; 1095686ba009SThierry Reding }; 1096686ba009SThierry Reding 1097686ba009SThierry Reding pllx { 1098686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1099686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1100686ba009SThierry Reding status = "disabled"; 1101686ba009SThierry Reding }; 1102686ba009SThierry Reding 1103686ba009SThierry Reding ao { 1104686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1105686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 1106686ba009SThierry Reding status = "disabled"; 1107686ba009SThierry Reding }; 1108686ba009SThierry Reding 1109686ba009SThierry Reding tj { 1110686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1111686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1112686ba009SThierry Reding status = "disabled"; 1113686ba009SThierry Reding }; 1114686ba009SThierry Reding }; 1115686ba009SThierry Reding 11165425fb15SMikko Perttunen timer { 11175425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 11185425fb15SMikko Perttunen interrupts = <GIC_PPI 13 11195425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 11205425fb15SMikko Perttunen <GIC_PPI 14 11215425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 11225425fb15SMikko Perttunen <GIC_PPI 11 11235425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 11245425fb15SMikko Perttunen <GIC_PPI 10 11255425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 11265425fb15SMikko Perttunen interrupt-parent = <&gic>; 1127b30be673SThierry Reding always-on; 11285425fb15SMikko Perttunen }; 11295425fb15SMikko Perttunen}; 1130