15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 65f89b58ceSMikko Perttunen status = "disabled"; 66f89b58ceSMikko Perttunen 67f89b58ceSMikko Perttunen snps,write-requests = <1>; 68f89b58ceSMikko Perttunen snps,read-requests = <3>; 69f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 70f89b58ceSMikko Perttunen snps,txpbl = <16>; 71f89b58ceSMikko Perttunen snps,rxpbl = <8>; 72f89b58ceSMikko Perttunen }; 73f89b58ceSMikko Perttunen 741aaa7698SThierry Reding aconnect@2900000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 765d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 775d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 785d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 795d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 805d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 815d2249ddSSameer Pujar #address-cells = <1>; 825d2249ddSSameer Pujar #size-cells = <1>; 835d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 845d2249ddSSameer Pujar status = "disabled"; 855d2249ddSSameer Pujar 86177208f7SSameer Pujar adma: dma-controller@2930000 { 875d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 885d2249ddSSameer Pujar "nvidia,tegra186-adma"; 895d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 905d2249ddSSameer Pujar interrupt-parent = <&agic>; 915d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1235d2249ddSSameer Pujar #dma-cells = <1>; 1245d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1255d2249ddSSameer Pujar clock-names = "d_audio"; 1265d2249ddSSameer Pujar status = "disabled"; 1275d2249ddSSameer Pujar }; 1285d2249ddSSameer Pujar 1295d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1315d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1325d2249ddSSameer Pujar #interrupt-cells = <3>; 1335d2249ddSSameer Pujar interrupt-controller; 1345d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1355d2249ddSSameer Pujar <0x02a42000 0x2000>; 1365d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1375d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1385d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 146177208f7SSameer Pujar "nvidia,tegra186-ahub"; 147177208f7SSameer Pujar reg = <0x02900800 0x800>; 148177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 149177208f7SSameer Pujar clock-names = "ahub"; 150177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152177208f7SSameer Pujar #address-cells = <1>; 153177208f7SSameer Pujar #size-cells = <1>; 154177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 155177208f7SSameer Pujar status = "disabled"; 156177208f7SSameer Pujar 157177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 158177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 159177208f7SSameer Pujar "nvidia,tegra186-admaif"; 160177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 161177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 162177208f7SSameer Pujar <&adma 2>, <&adma 2>, 163177208f7SSameer Pujar <&adma 3>, <&adma 3>, 164177208f7SSameer Pujar <&adma 4>, <&adma 4>, 165177208f7SSameer Pujar <&adma 5>, <&adma 5>, 166177208f7SSameer Pujar <&adma 6>, <&adma 6>, 167177208f7SSameer Pujar <&adma 7>, <&adma 7>, 168177208f7SSameer Pujar <&adma 8>, <&adma 8>, 169177208f7SSameer Pujar <&adma 9>, <&adma 9>, 170177208f7SSameer Pujar <&adma 10>, <&adma 10>, 171177208f7SSameer Pujar <&adma 11>, <&adma 11>, 172177208f7SSameer Pujar <&adma 12>, <&adma 12>, 173177208f7SSameer Pujar <&adma 13>, <&adma 13>, 174177208f7SSameer Pujar <&adma 14>, <&adma 14>, 175177208f7SSameer Pujar <&adma 15>, <&adma 15>, 176177208f7SSameer Pujar <&adma 16>, <&adma 16>, 177177208f7SSameer Pujar <&adma 17>, <&adma 17>, 178177208f7SSameer Pujar <&adma 18>, <&adma 18>, 179177208f7SSameer Pujar <&adma 19>, <&adma 19>, 180177208f7SSameer Pujar <&adma 20>, <&adma 20>; 181177208f7SSameer Pujar dma-names = "rx1", "tx1", 182177208f7SSameer Pujar "rx2", "tx2", 183177208f7SSameer Pujar "rx3", "tx3", 184177208f7SSameer Pujar "rx4", "tx4", 185177208f7SSameer Pujar "rx5", "tx5", 186177208f7SSameer Pujar "rx6", "tx6", 187177208f7SSameer Pujar "rx7", "tx7", 188177208f7SSameer Pujar "rx8", "tx8", 189177208f7SSameer Pujar "rx9", "tx9", 190177208f7SSameer Pujar "rx10", "tx10", 191177208f7SSameer Pujar "rx11", "tx11", 192177208f7SSameer Pujar "rx12", "tx12", 193177208f7SSameer Pujar "rx13", "tx13", 194177208f7SSameer Pujar "rx14", "tx14", 195177208f7SSameer Pujar "rx15", "tx15", 196177208f7SSameer Pujar "rx16", "tx16", 197177208f7SSameer Pujar "rx17", "tx17", 198177208f7SSameer Pujar "rx18", "tx18", 199177208f7SSameer Pujar "rx19", "tx19", 200177208f7SSameer Pujar "rx20", "tx20"; 201177208f7SSameer Pujar status = "disabled"; 202177208f7SSameer Pujar }; 203177208f7SSameer Pujar 204177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 205177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 206177208f7SSameer Pujar "nvidia,tegra210-i2s"; 207177208f7SSameer Pujar reg = <0x2901000 0x100>; 208177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 209177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 211177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213177208f7SSameer Pujar assigned-clock-rates = <1536000>; 214177208f7SSameer Pujar sound-name-prefix = "I2S1"; 215177208f7SSameer Pujar status = "disabled"; 216177208f7SSameer Pujar }; 217177208f7SSameer Pujar 218177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 219177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 220177208f7SSameer Pujar "nvidia,tegra210-i2s"; 221177208f7SSameer Pujar reg = <0x2901100 0x100>; 222177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 223177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 225177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227177208f7SSameer Pujar assigned-clock-rates = <1536000>; 228177208f7SSameer Pujar sound-name-prefix = "I2S2"; 229177208f7SSameer Pujar status = "disabled"; 230177208f7SSameer Pujar }; 231177208f7SSameer Pujar 232177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 233177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 234177208f7SSameer Pujar "nvidia,tegra210-i2s"; 235177208f7SSameer Pujar reg = <0x2901200 0x100>; 236177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 237177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 239177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241177208f7SSameer Pujar assigned-clock-rates = <1536000>; 242177208f7SSameer Pujar sound-name-prefix = "I2S3"; 243177208f7SSameer Pujar status = "disabled"; 244177208f7SSameer Pujar }; 245177208f7SSameer Pujar 246177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 247177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 248177208f7SSameer Pujar "nvidia,tegra210-i2s"; 249177208f7SSameer Pujar reg = <0x2901300 0x100>; 250177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 251177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 253177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255177208f7SSameer Pujar assigned-clock-rates = <1536000>; 256177208f7SSameer Pujar sound-name-prefix = "I2S4"; 257177208f7SSameer Pujar status = "disabled"; 258177208f7SSameer Pujar }; 259177208f7SSameer Pujar 260177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 261177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 262177208f7SSameer Pujar "nvidia,tegra210-i2s"; 263177208f7SSameer Pujar reg = <0x2901400 0x100>; 264177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 265177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 267177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269177208f7SSameer Pujar assigned-clock-rates = <1536000>; 270177208f7SSameer Pujar sound-name-prefix = "I2S5"; 271177208f7SSameer Pujar status = "disabled"; 272177208f7SSameer Pujar }; 273177208f7SSameer Pujar 274177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 275177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 276177208f7SSameer Pujar "nvidia,tegra210-i2s"; 277177208f7SSameer Pujar reg = <0x2901500 0x100>; 278177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 279177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 281177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283177208f7SSameer Pujar assigned-clock-rates = <1536000>; 284177208f7SSameer Pujar sound-name-prefix = "I2S6"; 285177208f7SSameer Pujar status = "disabled"; 286177208f7SSameer Pujar }; 287177208f7SSameer Pujar 288177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 289177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 290177208f7SSameer Pujar "nvidia,tegra210-dmic"; 291177208f7SSameer Pujar reg = <0x2904000 0x100>; 292177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293177208f7SSameer Pujar clock-names = "dmic"; 294177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296177208f7SSameer Pujar assigned-clock-rates = <3072000>; 297177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 298177208f7SSameer Pujar status = "disabled"; 299177208f7SSameer Pujar }; 300177208f7SSameer Pujar 301177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 302177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 303177208f7SSameer Pujar "nvidia,tegra210-dmic"; 304177208f7SSameer Pujar reg = <0x2904100 0x100>; 305177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306177208f7SSameer Pujar clock-names = "dmic"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <3072000>; 310177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 315177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 316177208f7SSameer Pujar "nvidia,tegra210-dmic"; 317177208f7SSameer Pujar reg = <0x2904200 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319177208f7SSameer Pujar clock-names = "dmic"; 320177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322177208f7SSameer Pujar assigned-clock-rates = <3072000>; 323177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 324177208f7SSameer Pujar status = "disabled"; 325177208f7SSameer Pujar }; 326177208f7SSameer Pujar 327177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 328177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 329177208f7SSameer Pujar "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904300 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 341177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 342177208f7SSameer Pujar "nvidia,tegra186-dspk"; 343177208f7SSameer Pujar reg = <0x2905000 0x100>; 344177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345177208f7SSameer Pujar clock-names = "dspk"; 346177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348177208f7SSameer Pujar assigned-clock-rates = <12288000>; 349177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 350177208f7SSameer Pujar status = "disabled"; 351177208f7SSameer Pujar }; 352177208f7SSameer Pujar 353177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 354177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 355177208f7SSameer Pujar "nvidia,tegra186-dspk"; 356177208f7SSameer Pujar reg = <0x2905100 0x100>; 357177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358177208f7SSameer Pujar clock-names = "dspk"; 359177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361177208f7SSameer Pujar assigned-clock-rates = <12288000>; 362177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 363177208f7SSameer Pujar status = "disabled"; 364177208f7SSameer Pujar }; 365177208f7SSameer Pujar }; 3665d2249ddSSameer Pujar }; 3675d2249ddSSameer Pujar 368dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 369dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 370644c569dSThierry Reding reg = <0x2430000 0x17000>, 371644c569dSThierry Reding <0xc300000 0x4000>; 372dbb72e2cSVidya Sagar 373dbb72e2cSVidya Sagar status = "okay"; 374dbb72e2cSVidya Sagar 375dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 376dbb72e2cSVidya Sagar pex_rst { 377dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 378dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3816b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 382dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 383dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384dbb72e2cSVidya Sagar }; 385dbb72e2cSVidya Sagar }; 386dbb72e2cSVidya Sagar 387dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388dbb72e2cSVidya Sagar clkreq { 389dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3936b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 394dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 395dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396dbb72e2cSVidya Sagar }; 397dbb72e2cSVidya Sagar }; 398dbb72e2cSVidya Sagar }; 399dbb72e2cSVidya Sagar 400be9b887fSThierry Reding mc: memory-controller@2c00000 { 401be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 402be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 403be9b887fSThierry Reding <0x02b80000 0x040000>, 404be9b887fSThierry Reding <0x01700000 0x100000>; 4058613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406d5237c7cSThierry Reding #interconnect-cells = <1>; 407be9b887fSThierry Reding status = "disabled"; 408be9b887fSThierry Reding 409be9b887fSThierry Reding #address-cells = <2>; 410be9b887fSThierry Reding #size-cells = <2>; 411be9b887fSThierry Reding 412be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415be9b887fSThierry Reding 416be9b887fSThierry Reding /* 417be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 418be9b887fSThierry Reding * controller selects the XBAR format used when memory 419be9b887fSThierry Reding * is accessed. This is used to transparently access 420be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 421be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 422be9b887fSThierry Reding * 423be9b887fSThierry Reding * As a consequence, the operating system must ensure 424be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 425be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 426be9b887fSThierry Reding * devices require access to the XBAR switch, their 427be9b887fSThierry Reding * drivers must set this bit explicitly. 428be9b887fSThierry Reding * 429be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 430be9b887fSThierry Reding */ 431be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432be9b887fSThierry Reding 433be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 434be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 435be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 436be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 437be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 438be9b887fSThierry Reding clock-names = "emc"; 439be9b887fSThierry Reding 440d5237c7cSThierry Reding #interconnect-cells = <0>; 441d5237c7cSThierry Reding 442be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 443be9b887fSThierry Reding }; 444be9b887fSThierry Reding }; 445be9b887fSThierry Reding 4465425fb15SMikko Perttunen uarta: serial@3100000 { 4475425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4485425fb15SMikko Perttunen reg = <0x03100000 0x40>; 4495425fb15SMikko Perttunen reg-shift = <2>; 4505425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 4525425fb15SMikko Perttunen clock-names = "serial"; 4535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 4545425fb15SMikko Perttunen reset-names = "serial"; 4555425fb15SMikko Perttunen status = "disabled"; 4565425fb15SMikko Perttunen }; 4575425fb15SMikko Perttunen 4585425fb15SMikko Perttunen uartb: serial@3110000 { 4595425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4605425fb15SMikko Perttunen reg = <0x03110000 0x40>; 4615425fb15SMikko Perttunen reg-shift = <2>; 4625425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4635425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 4645425fb15SMikko Perttunen clock-names = "serial"; 4655425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 4665425fb15SMikko Perttunen reset-names = "serial"; 4675425fb15SMikko Perttunen status = "disabled"; 4685425fb15SMikko Perttunen }; 4695425fb15SMikko Perttunen 4705425fb15SMikko Perttunen uartd: serial@3130000 { 4715425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4725425fb15SMikko Perttunen reg = <0x03130000 0x40>; 4735425fb15SMikko Perttunen reg-shift = <2>; 4745425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 4755425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 4765425fb15SMikko Perttunen clock-names = "serial"; 4775425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 4785425fb15SMikko Perttunen reset-names = "serial"; 4795425fb15SMikko Perttunen status = "disabled"; 4805425fb15SMikko Perttunen }; 4815425fb15SMikko Perttunen 4825425fb15SMikko Perttunen uarte: serial@3140000 { 4835425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4845425fb15SMikko Perttunen reg = <0x03140000 0x40>; 4855425fb15SMikko Perttunen reg-shift = <2>; 4865425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 4875425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 4885425fb15SMikko Perttunen clock-names = "serial"; 4895425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 4905425fb15SMikko Perttunen reset-names = "serial"; 4915425fb15SMikko Perttunen status = "disabled"; 4925425fb15SMikko Perttunen }; 4935425fb15SMikko Perttunen 4945425fb15SMikko Perttunen uartf: serial@3150000 { 4955425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4965425fb15SMikko Perttunen reg = <0x03150000 0x40>; 4975425fb15SMikko Perttunen reg-shift = <2>; 4985425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 4995425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 5005425fb15SMikko Perttunen clock-names = "serial"; 5015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 5025425fb15SMikko Perttunen reset-names = "serial"; 5035425fb15SMikko Perttunen status = "disabled"; 5045425fb15SMikko Perttunen }; 5055425fb15SMikko Perttunen 5065425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 507d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5085425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 5095425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 5105425fb15SMikko Perttunen #address-cells = <1>; 5115425fb15SMikko Perttunen #size-cells = <0>; 5125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 5135425fb15SMikko Perttunen clock-names = "div-clk"; 5145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 5155425fb15SMikko Perttunen reset-names = "i2c"; 5165425fb15SMikko Perttunen status = "disabled"; 5175425fb15SMikko Perttunen }; 5185425fb15SMikko Perttunen 5195425fb15SMikko Perttunen uarth: serial@3170000 { 5205425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5215425fb15SMikko Perttunen reg = <0x03170000 0x40>; 5225425fb15SMikko Perttunen reg-shift = <2>; 5235425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 5245425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 5255425fb15SMikko Perttunen clock-names = "serial"; 5265425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 5275425fb15SMikko Perttunen reset-names = "serial"; 5285425fb15SMikko Perttunen status = "disabled"; 5295425fb15SMikko Perttunen }; 5305425fb15SMikko Perttunen 5315425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 532d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5335425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 5345425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5355425fb15SMikko Perttunen #address-cells = <1>; 5365425fb15SMikko Perttunen #size-cells = <0>; 5375425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 5385425fb15SMikko Perttunen clock-names = "div-clk"; 5395425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 5405425fb15SMikko Perttunen reset-names = "i2c"; 5415425fb15SMikko Perttunen status = "disabled"; 5425425fb15SMikko Perttunen }; 5435425fb15SMikko Perttunen 5445425fb15SMikko Perttunen /* shares pads with dpaux1 */ 5455425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 546d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5475425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 5485425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 5495425fb15SMikko Perttunen #address-cells = <1>; 5505425fb15SMikko Perttunen #size-cells = <0>; 5515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 5525425fb15SMikko Perttunen clock-names = "div-clk"; 5535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 5545425fb15SMikko Perttunen reset-names = "i2c"; 555a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 556a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 557a4131561SThierry Reding pinctrl-names = "default", "idle"; 5585425fb15SMikko Perttunen status = "disabled"; 5595425fb15SMikko Perttunen }; 5605425fb15SMikko Perttunen 5615425fb15SMikko Perttunen /* shares pads with dpaux0 */ 5625425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 563d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5645425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 5655425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 5665425fb15SMikko Perttunen #address-cells = <1>; 5675425fb15SMikko Perttunen #size-cells = <0>; 5685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 5695425fb15SMikko Perttunen clock-names = "div-clk"; 5705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 5715425fb15SMikko Perttunen reset-names = "i2c"; 572a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 573a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 574a4131561SThierry Reding pinctrl-names = "default", "idle"; 5755425fb15SMikko Perttunen status = "disabled"; 5765425fb15SMikko Perttunen }; 5775425fb15SMikko Perttunen 578a4131561SThierry Reding /* shares pads with dpaux2 */ 579a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 580d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5815425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 5825425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 5835425fb15SMikko Perttunen #address-cells = <1>; 5845425fb15SMikko Perttunen #size-cells = <0>; 5855425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 5865425fb15SMikko Perttunen clock-names = "div-clk"; 5875425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 5885425fb15SMikko Perttunen reset-names = "i2c"; 589a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 590a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 591a4131561SThierry Reding pinctrl-names = "default", "idle"; 5925425fb15SMikko Perttunen status = "disabled"; 5935425fb15SMikko Perttunen }; 5945425fb15SMikko Perttunen 595a4131561SThierry Reding /* shares pads with dpaux3 */ 596a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 597d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5985425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 5995425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 6005425fb15SMikko Perttunen #address-cells = <1>; 6015425fb15SMikko Perttunen #size-cells = <0>; 6025425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 6035425fb15SMikko Perttunen clock-names = "div-clk"; 6045425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 6055425fb15SMikko Perttunen reset-names = "i2c"; 606a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 607a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 608a4131561SThierry Reding pinctrl-names = "default", "idle"; 6095425fb15SMikko Perttunen status = "disabled"; 6105425fb15SMikko Perttunen }; 6115425fb15SMikko Perttunen 61296ded827SSowjanya Komatineni spi@3270000 { 61396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 61496ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 61596ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 61696ded827SSowjanya Komatineni #address-cells = <1>; 61796ded827SSowjanya Komatineni #size-cells = <0>; 61896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 61996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 62096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 62196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 62296ded827SSowjanya Komatineni reset-names = "qspi"; 62396ded827SSowjanya Komatineni status = "disabled"; 62496ded827SSowjanya Komatineni }; 62596ded827SSowjanya Komatineni 62696ded827SSowjanya Komatineni spi@3300000 { 62796ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 62896ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 62996ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 63096ded827SSowjanya Komatineni #address-cells = <1>; 63196ded827SSowjanya Komatineni #size-cells = <0>; 63296ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 63396ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 63496ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 63596ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 63696ded827SSowjanya Komatineni reset-names = "qspi"; 63796ded827SSowjanya Komatineni status = "disabled"; 63896ded827SSowjanya Komatineni }; 63996ded827SSowjanya Komatineni 6406a574ec7SThierry Reding pwm1: pwm@3280000 { 6416a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6426a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6436a574ec7SThierry Reding reg = <0x3280000 0x10000>; 6446a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 6456a574ec7SThierry Reding clock-names = "pwm"; 6466a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 6476a574ec7SThierry Reding reset-names = "pwm"; 6486a574ec7SThierry Reding status = "disabled"; 6496a574ec7SThierry Reding #pwm-cells = <2>; 6506a574ec7SThierry Reding }; 6516a574ec7SThierry Reding 6526a574ec7SThierry Reding pwm2: pwm@3290000 { 6536a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6546a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6556a574ec7SThierry Reding reg = <0x3290000 0x10000>; 6566a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 6576a574ec7SThierry Reding clock-names = "pwm"; 6586a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 6596a574ec7SThierry Reding reset-names = "pwm"; 6606a574ec7SThierry Reding status = "disabled"; 6616a574ec7SThierry Reding #pwm-cells = <2>; 6626a574ec7SThierry Reding }; 6636a574ec7SThierry Reding 6646a574ec7SThierry Reding pwm3: pwm@32a0000 { 6656a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6666a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6676a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 6686a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 6696a574ec7SThierry Reding clock-names = "pwm"; 6706a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 6716a574ec7SThierry Reding reset-names = "pwm"; 6726a574ec7SThierry Reding status = "disabled"; 6736a574ec7SThierry Reding #pwm-cells = <2>; 6746a574ec7SThierry Reding }; 6756a574ec7SThierry Reding 6766a574ec7SThierry Reding pwm5: pwm@32c0000 { 6776a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6786a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6796a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 6806a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 6816a574ec7SThierry Reding clock-names = "pwm"; 6826a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 6836a574ec7SThierry Reding reset-names = "pwm"; 6846a574ec7SThierry Reding status = "disabled"; 6856a574ec7SThierry Reding #pwm-cells = <2>; 6866a574ec7SThierry Reding }; 6876a574ec7SThierry Reding 6886a574ec7SThierry Reding pwm6: pwm@32d0000 { 6896a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6906a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6916a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 6926a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 6936a574ec7SThierry Reding clock-names = "pwm"; 6946a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 6956a574ec7SThierry Reding reset-names = "pwm"; 6966a574ec7SThierry Reding status = "disabled"; 6976a574ec7SThierry Reding #pwm-cells = <2>; 6986a574ec7SThierry Reding }; 6996a574ec7SThierry Reding 7006a574ec7SThierry Reding pwm7: pwm@32e0000 { 7016a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7026a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7036a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 7046a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 7056a574ec7SThierry Reding clock-names = "pwm"; 7066a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 7076a574ec7SThierry Reding reset-names = "pwm"; 7086a574ec7SThierry Reding status = "disabled"; 7096a574ec7SThierry Reding #pwm-cells = <2>; 7106a574ec7SThierry Reding }; 7116a574ec7SThierry Reding 7126a574ec7SThierry Reding pwm8: pwm@32f0000 { 7136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7156a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 7166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 7176a574ec7SThierry Reding clock-names = "pwm"; 7186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 7196a574ec7SThierry Reding reset-names = "pwm"; 7206a574ec7SThierry Reding status = "disabled"; 7216a574ec7SThierry Reding #pwm-cells = <2>; 7226a574ec7SThierry Reding }; 7236a574ec7SThierry Reding 72467bb17f6SThierry Reding sdmmc1: mmc@3400000 { 7252c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7265425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 7275425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 728c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 729c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 730c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7315425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 7325425fb15SMikko Perttunen reset-names = "sdhci"; 733d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 734d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 735d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 7374e0f1229SSowjanya Komatineni <0x07>; 7384e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7394e0f1229SSowjanya Komatineni <0x07>; 7404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7424e0f1229SSowjanya Komatineni <0x07>; 7434e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7454e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7464e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7475425fb15SMikko Perttunen status = "disabled"; 7485425fb15SMikko Perttunen }; 7495425fb15SMikko Perttunen 75067bb17f6SThierry Reding sdmmc3: mmc@3440000 { 7512c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7525425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 7535425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 754c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 755c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 756c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 7585425fb15SMikko Perttunen reset-names = "sdhci"; 759d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 760d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 761d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 7634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 7644e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 7654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7664e0f1229SSowjanya Komatineni <0x07>; 7674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7694e0f1229SSowjanya Komatineni <0x07>; 7704e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7724e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7734e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7745425fb15SMikko Perttunen status = "disabled"; 7755425fb15SMikko Perttunen }; 7765425fb15SMikko Perttunen 77767bb17f6SThierry Reding sdmmc4: mmc@3460000 { 7782c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7795425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 7805425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 781c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 782c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 783c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 784351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 785351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 786351648d0SSowjanya Komatineni assigned-clock-parents = 787351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 7885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 7895425fb15SMikko Perttunen reset-names = "sdhci"; 790d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 791d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 792d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7934e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 7944e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 7954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 7964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7974e0f1229SSowjanya Komatineni <0x0a>; 7984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 7994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 8004e0f1229SSowjanya Komatineni <0x0a>; 8014e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 8024e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 8034e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 804dfd3cb6fSSowjanya Komatineni supports-cqe; 8055425fb15SMikko Perttunen status = "disabled"; 8065425fb15SMikko Perttunen }; 8075425fb15SMikko Perttunen 8084878cc0cSSameer Pujar hda@3510000 { 8094878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 8104878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 8114878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 8124878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 81348f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 81448f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 81548f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 8164878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 81748f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 81848f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 81948f6e195SSameer Pujar reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 8204878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 821d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 822d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 823d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 8244878cc0cSSameer Pujar status = "disabled"; 8254878cc0cSSameer Pujar }; 8264878cc0cSSameer Pujar 827fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 828fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 829fab7a039SJC Kuo reg = <0x03520000 0x1000>, 830fab7a039SJC Kuo <0x03540000 0x1000>; 831fab7a039SJC Kuo reg-names = "padctl", "ao"; 8326450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 833fab7a039SJC Kuo 834fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 835fab7a039SJC Kuo reset-names = "padctl"; 836fab7a039SJC Kuo 837fab7a039SJC Kuo status = "disabled"; 838fab7a039SJC Kuo 839fab7a039SJC Kuo pads { 840fab7a039SJC Kuo usb2 { 841fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 842fab7a039SJC Kuo clock-names = "trk"; 843fab7a039SJC Kuo 844fab7a039SJC Kuo lanes { 845fab7a039SJC Kuo usb2-0 { 846fab7a039SJC Kuo nvidia,function = "xusb"; 847fab7a039SJC Kuo status = "disabled"; 848fab7a039SJC Kuo #phy-cells = <0>; 849fab7a039SJC Kuo }; 850fab7a039SJC Kuo 851fab7a039SJC Kuo usb2-1 { 852fab7a039SJC Kuo nvidia,function = "xusb"; 853fab7a039SJC Kuo status = "disabled"; 854fab7a039SJC Kuo #phy-cells = <0>; 855fab7a039SJC Kuo }; 856fab7a039SJC Kuo 857fab7a039SJC Kuo usb2-2 { 858fab7a039SJC Kuo nvidia,function = "xusb"; 859fab7a039SJC Kuo status = "disabled"; 860fab7a039SJC Kuo #phy-cells = <0>; 861fab7a039SJC Kuo }; 862fab7a039SJC Kuo 863fab7a039SJC Kuo usb2-3 { 864fab7a039SJC Kuo nvidia,function = "xusb"; 865fab7a039SJC Kuo status = "disabled"; 866fab7a039SJC Kuo #phy-cells = <0>; 867fab7a039SJC Kuo }; 868fab7a039SJC Kuo }; 869fab7a039SJC Kuo }; 870fab7a039SJC Kuo 871fab7a039SJC Kuo usb3 { 872fab7a039SJC Kuo lanes { 873fab7a039SJC Kuo usb3-0 { 874fab7a039SJC Kuo nvidia,function = "xusb"; 875fab7a039SJC Kuo status = "disabled"; 876fab7a039SJC Kuo #phy-cells = <0>; 877fab7a039SJC Kuo }; 878fab7a039SJC Kuo 879fab7a039SJC Kuo usb3-1 { 880fab7a039SJC Kuo nvidia,function = "xusb"; 881fab7a039SJC Kuo status = "disabled"; 882fab7a039SJC Kuo #phy-cells = <0>; 883fab7a039SJC Kuo }; 884fab7a039SJC Kuo 885fab7a039SJC Kuo usb3-2 { 886fab7a039SJC Kuo nvidia,function = "xusb"; 887fab7a039SJC Kuo status = "disabled"; 888fab7a039SJC Kuo #phy-cells = <0>; 889fab7a039SJC Kuo }; 890fab7a039SJC Kuo 891fab7a039SJC Kuo usb3-3 { 892fab7a039SJC Kuo nvidia,function = "xusb"; 893fab7a039SJC Kuo status = "disabled"; 894fab7a039SJC Kuo #phy-cells = <0>; 895fab7a039SJC Kuo }; 896fab7a039SJC Kuo }; 897fab7a039SJC Kuo }; 898fab7a039SJC Kuo }; 899fab7a039SJC Kuo 900fab7a039SJC Kuo ports { 901fab7a039SJC Kuo usb2-0 { 902fab7a039SJC Kuo status = "disabled"; 903fab7a039SJC Kuo }; 904fab7a039SJC Kuo 905fab7a039SJC Kuo usb2-1 { 906fab7a039SJC Kuo status = "disabled"; 907fab7a039SJC Kuo }; 908fab7a039SJC Kuo 909fab7a039SJC Kuo usb2-2 { 910fab7a039SJC Kuo status = "disabled"; 911fab7a039SJC Kuo }; 912fab7a039SJC Kuo 913fab7a039SJC Kuo usb2-3 { 914fab7a039SJC Kuo status = "disabled"; 915fab7a039SJC Kuo }; 916fab7a039SJC Kuo 917fab7a039SJC Kuo usb3-0 { 918fab7a039SJC Kuo status = "disabled"; 919fab7a039SJC Kuo }; 920fab7a039SJC Kuo 921fab7a039SJC Kuo usb3-1 { 922fab7a039SJC Kuo status = "disabled"; 923fab7a039SJC Kuo }; 924fab7a039SJC Kuo 925fab7a039SJC Kuo usb3-2 { 926fab7a039SJC Kuo status = "disabled"; 927fab7a039SJC Kuo }; 928fab7a039SJC Kuo 929fab7a039SJC Kuo usb3-3 { 930fab7a039SJC Kuo status = "disabled"; 931fab7a039SJC Kuo }; 932fab7a039SJC Kuo }; 933fab7a039SJC Kuo }; 934fab7a039SJC Kuo 935bc8788b2SNagarjuna Kristam usb@3550000 { 936bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 937bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 938bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 939bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 940bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 941bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 942bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 943bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 944bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 945bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 946bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 947bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 948bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 949bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 950bc8788b2SNagarjuna Kristam status = "disabled"; 951bc8788b2SNagarjuna Kristam }; 952bc8788b2SNagarjuna Kristam 953fab7a039SJC Kuo usb@3610000 { 954fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 955fab7a039SJC Kuo reg = <0x03610000 0x40000>, 956fab7a039SJC Kuo <0x03600000 0x10000>; 957fab7a039SJC Kuo reg-names = "hcd", "fpci"; 958fab7a039SJC Kuo 959fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 960a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 961fab7a039SJC Kuo 962fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 963fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 964fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 965fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 966fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 967fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 968fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 969fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 970fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 971fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 972fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 973fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 974fab7a039SJC Kuo "pll_e"; 975fab7a039SJC Kuo 976fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 977fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 978fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 979fab7a039SJC Kuo 980fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 981fab7a039SJC Kuo status = "disabled"; 982fab7a039SJC Kuo }; 983fab7a039SJC Kuo 98409903c5eSJC Kuo fuse@3820000 { 98509903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 98609903c5eSJC Kuo reg = <0x03820000 0x10000>; 98709903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 98809903c5eSJC Kuo clock-names = "fuse"; 98909903c5eSJC Kuo }; 99009903c5eSJC Kuo 9915425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 9925425fb15SMikko Perttunen compatible = "arm,gic-400"; 9935425fb15SMikko Perttunen #interrupt-cells = <3>; 9945425fb15SMikko Perttunen interrupt-controller; 9955425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 9965425fb15SMikko Perttunen <0x03882000 0x2000>, 9975425fb15SMikko Perttunen <0x03884000 0x2000>, 9985425fb15SMikko Perttunen <0x03886000 0x2000>; 9995425fb15SMikko Perttunen interrupts = <GIC_PPI 9 10005425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10015425fb15SMikko Perttunen interrupt-parent = <&gic>; 10025425fb15SMikko Perttunen }; 10035425fb15SMikko Perttunen 1004badb80beSThierry Reding cec@3960000 { 1005badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1006badb80beSThierry Reding reg = <0x03960000 0x10000>; 1007badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1008badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1009badb80beSThierry Reding clock-names = "cec"; 1010badb80beSThierry Reding status = "disabled"; 1011badb80beSThierry Reding }; 1012badb80beSThierry Reding 10135425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1014a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 10155425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1016a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1017a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1018a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1019a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1020a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1021a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1022a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1023a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1024a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1025a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1026a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1027a38570c2SMikko Perttunen "shared7"; 1028a38570c2SMikko Perttunen #mbox-cells = <2>; 1029a38570c2SMikko Perttunen }; 1030a38570c2SMikko Perttunen 10312602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 10322602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10332602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 10342602c32fSVidya Sagar reg-names = "ctl"; 10352602c32fSVidya Sagar 10362602c32fSVidya Sagar #phy-cells = <0>; 10372602c32fSVidya Sagar }; 10382602c32fSVidya Sagar 10392602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 10402602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10412602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 10422602c32fSVidya Sagar reg-names = "ctl"; 10432602c32fSVidya Sagar 10442602c32fSVidya Sagar #phy-cells = <0>; 10452602c32fSVidya Sagar }; 10462602c32fSVidya Sagar 10472602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 10482602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10492602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 10502602c32fSVidya Sagar reg-names = "ctl"; 10512602c32fSVidya Sagar 10522602c32fSVidya Sagar #phy-cells = <0>; 10532602c32fSVidya Sagar }; 10542602c32fSVidya Sagar 10552602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 10562602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10572602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 10582602c32fSVidya Sagar reg-names = "ctl"; 10592602c32fSVidya Sagar 10602602c32fSVidya Sagar #phy-cells = <0>; 10612602c32fSVidya Sagar }; 10622602c32fSVidya Sagar 10632602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 10642602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10652602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 10662602c32fSVidya Sagar reg-names = "ctl"; 10672602c32fSVidya Sagar 10682602c32fSVidya Sagar #phy-cells = <0>; 10692602c32fSVidya Sagar }; 10702602c32fSVidya Sagar 10712602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 10722602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10732602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 10742602c32fSVidya Sagar reg-names = "ctl"; 10752602c32fSVidya Sagar 10762602c32fSVidya Sagar #phy-cells = <0>; 10772602c32fSVidya Sagar }; 10782602c32fSVidya Sagar 10792602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 10802602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10812602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 10822602c32fSVidya Sagar reg-names = "ctl"; 10832602c32fSVidya Sagar 10842602c32fSVidya Sagar #phy-cells = <0>; 10852602c32fSVidya Sagar }; 10862602c32fSVidya Sagar 10872602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 10882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10892602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 10902602c32fSVidya Sagar reg-names = "ctl"; 10912602c32fSVidya Sagar 10922602c32fSVidya Sagar #phy-cells = <0>; 10932602c32fSVidya Sagar }; 10942602c32fSVidya Sagar 10952602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 10962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10972602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 10982602c32fSVidya Sagar reg-names = "ctl"; 10992602c32fSVidya Sagar 11002602c32fSVidya Sagar #phy-cells = <0>; 11012602c32fSVidya Sagar }; 11022602c32fSVidya Sagar 11032602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 11042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11052602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 11062602c32fSVidya Sagar reg-names = "ctl"; 11072602c32fSVidya Sagar 11082602c32fSVidya Sagar #phy-cells = <0>; 11092602c32fSVidya Sagar }; 11102602c32fSVidya Sagar 11112602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 11122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11132602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 11142602c32fSVidya Sagar reg-names = "ctl"; 11152602c32fSVidya Sagar 11162602c32fSVidya Sagar #phy-cells = <0>; 11172602c32fSVidya Sagar }; 11182602c32fSVidya Sagar 11192602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 11202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11212602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 11222602c32fSVidya Sagar reg-names = "ctl"; 11232602c32fSVidya Sagar 11242602c32fSVidya Sagar #phy-cells = <0>; 11252602c32fSVidya Sagar }; 11262602c32fSVidya Sagar 11272602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 11282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11292602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 11302602c32fSVidya Sagar reg-names = "ctl"; 11312602c32fSVidya Sagar 11322602c32fSVidya Sagar #phy-cells = <0>; 11332602c32fSVidya Sagar }; 11342602c32fSVidya Sagar 11352602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 11362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11372602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 11382602c32fSVidya Sagar reg-names = "ctl"; 11392602c32fSVidya Sagar 11402602c32fSVidya Sagar #phy-cells = <0>; 11412602c32fSVidya Sagar }; 11422602c32fSVidya Sagar 11432602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 11442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11452602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 11462602c32fSVidya Sagar reg-names = "ctl"; 11472602c32fSVidya Sagar 11482602c32fSVidya Sagar #phy-cells = <0>; 11492602c32fSVidya Sagar }; 11502602c32fSVidya Sagar 11512602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 11522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11532602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 11542602c32fSVidya Sagar reg-names = "ctl"; 11552602c32fSVidya Sagar 11562602c32fSVidya Sagar #phy-cells = <0>; 11572602c32fSVidya Sagar }; 11582602c32fSVidya Sagar 11592602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 11602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11612602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 11622602c32fSVidya Sagar reg-names = "ctl"; 11632602c32fSVidya Sagar 11642602c32fSVidya Sagar #phy-cells = <0>; 11652602c32fSVidya Sagar }; 11662602c32fSVidya Sagar 11672602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 11682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11692602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 11702602c32fSVidya Sagar reg-names = "ctl"; 11712602c32fSVidya Sagar 11722602c32fSVidya Sagar #phy-cells = <0>; 11732602c32fSVidya Sagar }; 11742602c32fSVidya Sagar 11752602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 11762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11772602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 11782602c32fSVidya Sagar reg-names = "ctl"; 11792602c32fSVidya Sagar 11802602c32fSVidya Sagar #phy-cells = <0>; 11812602c32fSVidya Sagar }; 11822602c32fSVidya Sagar 11832602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 11842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11852602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 11862602c32fSVidya Sagar reg-names = "ctl"; 11872602c32fSVidya Sagar 11882602c32fSVidya Sagar #phy-cells = <0>; 11892602c32fSVidya Sagar }; 11902602c32fSVidya Sagar 1191a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1192a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 11931741e187SDipen Patel reg = <0x0c150000 0x90000>; 1194a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1195a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1196a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1197a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1198a38570c2SMikko Perttunen /* 1199a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1200a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1201a38570c2SMikko Perttunen */ 1202a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 12035425fb15SMikko Perttunen #mbox-cells = <2>; 12045425fb15SMikko Perttunen }; 12055425fb15SMikko Perttunen 12065425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1207d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12085425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 12095425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 12105425fb15SMikko Perttunen #address-cells = <1>; 12115425fb15SMikko Perttunen #size-cells = <0>; 12125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 12135425fb15SMikko Perttunen clock-names = "div-clk"; 12145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 12155425fb15SMikko Perttunen reset-names = "i2c"; 12165425fb15SMikko Perttunen status = "disabled"; 12175425fb15SMikko Perttunen }; 12185425fb15SMikko Perttunen 12195425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1220d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12215425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 12225425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 12235425fb15SMikko Perttunen #address-cells = <1>; 12245425fb15SMikko Perttunen #size-cells = <0>; 12255425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 12265425fb15SMikko Perttunen clock-names = "div-clk"; 12275425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 12285425fb15SMikko Perttunen reset-names = "i2c"; 12295425fb15SMikko Perttunen status = "disabled"; 12305425fb15SMikko Perttunen }; 12315425fb15SMikko Perttunen 12325425fb15SMikko Perttunen uartc: serial@c280000 { 12335425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12345425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 12355425fb15SMikko Perttunen reg-shift = <2>; 12365425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 12375425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 12385425fb15SMikko Perttunen clock-names = "serial"; 12395425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 12405425fb15SMikko Perttunen reset-names = "serial"; 12415425fb15SMikko Perttunen status = "disabled"; 12425425fb15SMikko Perttunen }; 12435425fb15SMikko Perttunen 12445425fb15SMikko Perttunen uartg: serial@c290000 { 12455425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12465425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 12475425fb15SMikko Perttunen reg-shift = <2>; 12485425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 12495425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 12505425fb15SMikko Perttunen clock-names = "serial"; 12515425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 12525425fb15SMikko Perttunen reset-names = "serial"; 12535425fb15SMikko Perttunen status = "disabled"; 12545425fb15SMikko Perttunen }; 12555425fb15SMikko Perttunen 125637e5a31dSThierry Reding rtc: rtc@c2a0000 { 125737e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 125837e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 125937e5a31dSThierry Reding interrupt-parent = <&pmc>; 126037e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 126137e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 126237e5a31dSThierry Reding clock-names = "rtc"; 126337e5a31dSThierry Reding status = "disabled"; 126437e5a31dSThierry Reding }; 126537e5a31dSThierry Reding 12664d286331SThierry Reding gpio_aon: gpio@c2f0000 { 12674d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 12684d286331SThierry Reding reg-names = "security", "gpio"; 12694d286331SThierry Reding reg = <0xc2f0000 0x1000>, 12704d286331SThierry Reding <0xc2f1000 0x1000>; 127175b5608aSThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 12724d286331SThierry Reding gpio-controller; 12734d286331SThierry Reding #gpio-cells = <2>; 12744d286331SThierry Reding interrupt-controller; 12754d286331SThierry Reding #interrupt-cells = <2>; 12764d286331SThierry Reding }; 12774d286331SThierry Reding 12786a574ec7SThierry Reding pwm4: pwm@c340000 { 12796a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 12806a574ec7SThierry Reding "nvidia,tegra186-pwm"; 12816a574ec7SThierry Reding reg = <0xc340000 0x10000>; 12826a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 12836a574ec7SThierry Reding clock-names = "pwm"; 12846a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 12856a574ec7SThierry Reding reset-names = "pwm"; 12866a574ec7SThierry Reding status = "disabled"; 12876a574ec7SThierry Reding #pwm-cells = <2>; 12886a574ec7SThierry Reding }; 12896a574ec7SThierry Reding 129038ecf1e5SThierry Reding pmc: pmc@c360000 { 12915425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 12925425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 12935425fb15SMikko Perttunen <0x0c370000 0x10000>, 12945425fb15SMikko Perttunen <0x0c380000 0x10000>, 12955425fb15SMikko Perttunen <0x0c390000 0x10000>, 12965425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 12975425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 129838ecf1e5SThierry Reding 129938ecf1e5SThierry Reding #interrupt-cells = <2>; 130038ecf1e5SThierry Reding interrupt-controller; 13015425fb15SMikko Perttunen }; 13023db6d3baSThierry Reding 13033db6d3baSThierry Reding host1x@13e00000 { 1304ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 13053db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 13063db6d3baSThierry Reding <0x13e10000 0x10000>; 13073db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 13083db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 13093db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1310052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 13113db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 13123db6d3baSThierry Reding clock-names = "host1x"; 13133db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 13143db6d3baSThierry Reding reset-names = "host1x"; 13153db6d3baSThierry Reding 13163db6d3baSThierry Reding #address-cells = <1>; 13173db6d3baSThierry Reding #size-cells = <1>; 13183db6d3baSThierry Reding 13193db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1320d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1321d5237c7cSThierry Reding interconnect-names = "dma-mem"; 13223db6d3baSThierry Reding 13233db6d3baSThierry Reding display-hub@15200000 { 1324aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1325611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 13263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 13273db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 13283db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 13293db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 13303db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 13313db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 13323db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 13333db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 13343db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 13353db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 13363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 13373db6d3baSThierry Reding clock-names = "disp", "hub"; 13383db6d3baSThierry Reding status = "disabled"; 13393db6d3baSThierry Reding 13403db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13413db6d3baSThierry Reding 13423db6d3baSThierry Reding #address-cells = <1>; 13433db6d3baSThierry Reding #size-cells = <1>; 13443db6d3baSThierry Reding 13453db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 13463db6d3baSThierry Reding 13473db6d3baSThierry Reding display@15200000 { 13483db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13493db6d3baSThierry Reding reg = <0x15200000 0x10000>; 13503db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 13513db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 13523db6d3baSThierry Reding clock-names = "dc"; 13533db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 13543db6d3baSThierry Reding reset-names = "dc"; 13553db6d3baSThierry Reding 13563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1357d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1358d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1359d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13603db6d3baSThierry Reding 13613db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13623db6d3baSThierry Reding nvidia,head = <0>; 13633db6d3baSThierry Reding }; 13643db6d3baSThierry Reding 13653db6d3baSThierry Reding display@15210000 { 13663db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13673db6d3baSThierry Reding reg = <0x15210000 0x10000>; 13683db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 13693db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 13703db6d3baSThierry Reding clock-names = "dc"; 13713db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 13723db6d3baSThierry Reding reset-names = "dc"; 13733db6d3baSThierry Reding 13743db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1375d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1376d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1377d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13783db6d3baSThierry Reding 13793db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13803db6d3baSThierry Reding nvidia,head = <1>; 13813db6d3baSThierry Reding }; 13823db6d3baSThierry Reding 13833db6d3baSThierry Reding display@15220000 { 13843db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13853db6d3baSThierry Reding reg = <0x15220000 0x10000>; 13863db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 13873db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 13883db6d3baSThierry Reding clock-names = "dc"; 13893db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 13903db6d3baSThierry Reding reset-names = "dc"; 13913db6d3baSThierry Reding 13923db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1393d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1394d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1395d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13963db6d3baSThierry Reding 13973db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13983db6d3baSThierry Reding nvidia,head = <2>; 13993db6d3baSThierry Reding }; 14003db6d3baSThierry Reding 14013db6d3baSThierry Reding display@15230000 { 14023db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14033db6d3baSThierry Reding reg = <0x15230000 0x10000>; 14043db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 14053db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 14063db6d3baSThierry Reding clock-names = "dc"; 14073db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 14083db6d3baSThierry Reding reset-names = "dc"; 14093db6d3baSThierry Reding 14103db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1411d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1412d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1413d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 14143db6d3baSThierry Reding 14153db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 14163db6d3baSThierry Reding nvidia,head = <3>; 14173db6d3baSThierry Reding }; 14183db6d3baSThierry Reding }; 14193db6d3baSThierry Reding 14208d424ec2SThierry Reding vic@15340000 { 14218d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 14228d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 14238d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 14248d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 14258d424ec2SThierry Reding clock-names = "vic"; 14268d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 14278d424ec2SThierry Reding reset-names = "vic"; 14288d424ec2SThierry Reding 14298d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1430d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1431d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1432d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 14338d424ec2SThierry Reding }; 14348d424ec2SThierry Reding 14353db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 14363db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 14373db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 14383db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 14393db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 14403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 14413db6d3baSThierry Reding clock-names = "dpaux", "parent"; 14423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 14433db6d3baSThierry Reding reset-names = "dpaux"; 14443db6d3baSThierry Reding status = "disabled"; 14453db6d3baSThierry Reding 14463db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14473db6d3baSThierry Reding 14483db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 14493db6d3baSThierry Reding groups = "dpaux-io"; 14503db6d3baSThierry Reding function = "aux"; 14513db6d3baSThierry Reding }; 14523db6d3baSThierry Reding 14533db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 14543db6d3baSThierry Reding groups = "dpaux-io"; 14553db6d3baSThierry Reding function = "i2c"; 14563db6d3baSThierry Reding }; 14573db6d3baSThierry Reding 14583db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 14593db6d3baSThierry Reding groups = "dpaux-io"; 14603db6d3baSThierry Reding function = "off"; 14613db6d3baSThierry Reding }; 14623db6d3baSThierry Reding 14633db6d3baSThierry Reding i2c-bus { 14643db6d3baSThierry Reding #address-cells = <1>; 14653db6d3baSThierry Reding #size-cells = <0>; 14663db6d3baSThierry Reding }; 14673db6d3baSThierry Reding }; 14683db6d3baSThierry Reding 14693db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 14703db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 14713db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 14723db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 14733db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 14743db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 14753db6d3baSThierry Reding clock-names = "dpaux", "parent"; 14763db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 14773db6d3baSThierry Reding reset-names = "dpaux"; 14783db6d3baSThierry Reding status = "disabled"; 14793db6d3baSThierry Reding 14803db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14813db6d3baSThierry Reding 14823db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 14833db6d3baSThierry Reding groups = "dpaux-io"; 14843db6d3baSThierry Reding function = "aux"; 14853db6d3baSThierry Reding }; 14863db6d3baSThierry Reding 14873db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 14883db6d3baSThierry Reding groups = "dpaux-io"; 14893db6d3baSThierry Reding function = "i2c"; 14903db6d3baSThierry Reding }; 14913db6d3baSThierry Reding 14923db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 14933db6d3baSThierry Reding groups = "dpaux-io"; 14943db6d3baSThierry Reding function = "off"; 14953db6d3baSThierry Reding }; 14963db6d3baSThierry Reding 14973db6d3baSThierry Reding i2c-bus { 14983db6d3baSThierry Reding #address-cells = <1>; 14993db6d3baSThierry Reding #size-cells = <0>; 15003db6d3baSThierry Reding }; 15013db6d3baSThierry Reding }; 15023db6d3baSThierry Reding 15033db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 15043db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15053db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 15063db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 15073db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 15083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15093db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15103db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 15113db6d3baSThierry Reding reset-names = "dpaux"; 15123db6d3baSThierry Reding status = "disabled"; 15133db6d3baSThierry Reding 15143db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15153db6d3baSThierry Reding 15163db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 15173db6d3baSThierry Reding groups = "dpaux-io"; 15183db6d3baSThierry Reding function = "aux"; 15193db6d3baSThierry Reding }; 15203db6d3baSThierry Reding 15213db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 15223db6d3baSThierry Reding groups = "dpaux-io"; 15233db6d3baSThierry Reding function = "i2c"; 15243db6d3baSThierry Reding }; 15253db6d3baSThierry Reding 15263db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 15273db6d3baSThierry Reding groups = "dpaux-io"; 15283db6d3baSThierry Reding function = "off"; 15293db6d3baSThierry Reding }; 15303db6d3baSThierry Reding 15313db6d3baSThierry Reding i2c-bus { 15323db6d3baSThierry Reding #address-cells = <1>; 15333db6d3baSThierry Reding #size-cells = <0>; 15343db6d3baSThierry Reding }; 15353db6d3baSThierry Reding }; 15363db6d3baSThierry Reding 15373db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 15383db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15393db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 15403db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 15413db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 15423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15433db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 15453db6d3baSThierry Reding reset-names = "dpaux"; 15463db6d3baSThierry Reding status = "disabled"; 15473db6d3baSThierry Reding 15483db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15493db6d3baSThierry Reding 15503db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 15513db6d3baSThierry Reding groups = "dpaux-io"; 15523db6d3baSThierry Reding function = "aux"; 15533db6d3baSThierry Reding }; 15543db6d3baSThierry Reding 15553db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 15563db6d3baSThierry Reding groups = "dpaux-io"; 15573db6d3baSThierry Reding function = "i2c"; 15583db6d3baSThierry Reding }; 15593db6d3baSThierry Reding 15603db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 15613db6d3baSThierry Reding groups = "dpaux-io"; 15623db6d3baSThierry Reding function = "off"; 15633db6d3baSThierry Reding }; 15643db6d3baSThierry Reding 15653db6d3baSThierry Reding i2c-bus { 15663db6d3baSThierry Reding #address-cells = <1>; 15673db6d3baSThierry Reding #size-cells = <0>; 15683db6d3baSThierry Reding }; 15693db6d3baSThierry Reding }; 15703db6d3baSThierry Reding 15713db6d3baSThierry Reding sor0: sor@15b00000 { 15723db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 15733db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 15743db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 15753db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 15763db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 15773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 15783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 15793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 15803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 15813db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 15823db6d3baSThierry Reding "pad"; 15833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 15843db6d3baSThierry Reding reset-names = "sor"; 15853db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 15863db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 15873db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 15883db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 15893db6d3baSThierry Reding status = "disabled"; 15903db6d3baSThierry Reding 15913db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15923db6d3baSThierry Reding nvidia,interface = <0>; 15933db6d3baSThierry Reding }; 15943db6d3baSThierry Reding 15953db6d3baSThierry Reding sor1: sor@15b40000 { 15963db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1597939e7430SThierry Reding reg = <0x15b40000 0x40000>; 15983db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 15993db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 16003db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 16013db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 16023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16043db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 16053db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16063db6d3baSThierry Reding "pad"; 16073db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 16083db6d3baSThierry Reding reset-names = "sor"; 16093db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 16103db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 16113db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 16123db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16133db6d3baSThierry Reding status = "disabled"; 16143db6d3baSThierry Reding 16153db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16163db6d3baSThierry Reding nvidia,interface = <1>; 16173db6d3baSThierry Reding }; 16183db6d3baSThierry Reding 16193db6d3baSThierry Reding sor2: sor@15b80000 { 16203db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 16213db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 16223db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 16233db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 16243db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 16253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 16263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 16293db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16303db6d3baSThierry Reding "pad"; 16313db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 16323db6d3baSThierry Reding reset-names = "sor"; 16333db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 16343db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 16353db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 16363db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16373db6d3baSThierry Reding status = "disabled"; 16383db6d3baSThierry Reding 16393db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16403db6d3baSThierry Reding nvidia,interface = <2>; 16413db6d3baSThierry Reding }; 16423db6d3baSThierry Reding 16433db6d3baSThierry Reding sor3: sor@15bc0000 { 16443db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 16453db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 16463db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 16473db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 16483db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 16493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 16503db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 16533db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16543db6d3baSThierry Reding "pad"; 16553db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 16563db6d3baSThierry Reding reset-names = "sor"; 16573db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 16583db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 16593db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 16603db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16613db6d3baSThierry Reding status = "disabled"; 16623db6d3baSThierry Reding 16633db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16643db6d3baSThierry Reding nvidia,interface = <3>; 16653db6d3baSThierry Reding }; 16663db6d3baSThierry Reding }; 16670f134e39SThierry Reding 16680f134e39SThierry Reding gpu@17000000 { 16690f134e39SThierry Reding compatible = "nvidia,gv11b"; 1670818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1671818ae79aSThierry Reding <0x18000000 0x1000000>; 16720f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 16730f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 16740f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 16750f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 16760f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 16770f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 16780f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 16790f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 16800f134e39SThierry Reding reset-names = "gpu"; 16810f134e39SThierry Reding dma-coherent; 16820f134e39SThierry Reding 16830f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 16840f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 16850f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 16860f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 16870f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 16880f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 16890f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 16900f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 16910f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 16920f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 16930f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 16940f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 16950f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 16960f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 16970f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 16980f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 16990f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 17000f134e39SThierry Reding }; 17015425fb15SMikko Perttunen }; 17025425fb15SMikko Perttunen 17032602c32fSVidya Sagar pcie@14100000 { 1704f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17052602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1706644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1707644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1708644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1709644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 17102602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 17112602c32fSVidya Sagar 17122602c32fSVidya Sagar status = "disabled"; 17132602c32fSVidya Sagar 17142602c32fSVidya Sagar #address-cells = <3>; 17152602c32fSVidya Sagar #size-cells = <2>; 17162602c32fSVidya Sagar device_type = "pci"; 17172602c32fSVidya Sagar num-lanes = <1>; 17182602c32fSVidya Sagar num-viewport = <8>; 17192602c32fSVidya Sagar linux,pci-domain = <1>; 17202602c32fSVidya Sagar 17212602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 17222602c32fSVidya Sagar clock-names = "core"; 17232602c32fSVidya Sagar 17242602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 17252602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 17262602c32fSVidya Sagar reset-names = "apb", "core"; 17272602c32fSVidya Sagar 17282602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17292602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17302602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17312602c32fSVidya Sagar 17322602c32fSVidya Sagar #interrupt-cells = <1>; 17332602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17342602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 17352602c32fSVidya Sagar 17362602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 17372602c32fSVidya Sagar 17382602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17392602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17402602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17412602c32fSVidya Sagar 17422602c32fSVidya Sagar bus-range = <0x0 0xff>; 1743d5237c7cSThierry Reding 17448a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 17458a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 17468a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1747d5237c7cSThierry Reding 1748d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1749d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1750d5237c7cSThierry Reding interconnect-names = "read", "write"; 17512602c32fSVidya Sagar }; 17522602c32fSVidya Sagar 17532602c32fSVidya Sagar pcie@14120000 { 1754f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17552602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1756644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1757644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1758644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1759644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 17602602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 17612602c32fSVidya Sagar 17622602c32fSVidya Sagar status = "disabled"; 17632602c32fSVidya Sagar 17642602c32fSVidya Sagar #address-cells = <3>; 17652602c32fSVidya Sagar #size-cells = <2>; 17662602c32fSVidya Sagar device_type = "pci"; 17672602c32fSVidya Sagar num-lanes = <1>; 17682602c32fSVidya Sagar num-viewport = <8>; 17692602c32fSVidya Sagar linux,pci-domain = <2>; 17702602c32fSVidya Sagar 17712602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 17722602c32fSVidya Sagar clock-names = "core"; 17732602c32fSVidya Sagar 17742602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 17752602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 17762602c32fSVidya Sagar reset-names = "apb", "core"; 17772602c32fSVidya Sagar 17782602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17792602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17802602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17812602c32fSVidya Sagar 17822602c32fSVidya Sagar #interrupt-cells = <1>; 17832602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17842602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 17852602c32fSVidya Sagar 17862602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 17872602c32fSVidya Sagar 17882602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17892602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17902602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17912602c32fSVidya Sagar 17922602c32fSVidya Sagar bus-range = <0x0 0xff>; 1793d5237c7cSThierry Reding 17948a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 17958a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 17968a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1797d5237c7cSThierry Reding 1798d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1799d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1800d5237c7cSThierry Reding interconnect-names = "read", "write"; 18012602c32fSVidya Sagar }; 18022602c32fSVidya Sagar 18032602c32fSVidya Sagar pcie@14140000 { 1804f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18052602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1806644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1807644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1808644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1809644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18102602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18112602c32fSVidya Sagar 18122602c32fSVidya Sagar status = "disabled"; 18132602c32fSVidya Sagar 18142602c32fSVidya Sagar #address-cells = <3>; 18152602c32fSVidya Sagar #size-cells = <2>; 18162602c32fSVidya Sagar device_type = "pci"; 18172602c32fSVidya Sagar num-lanes = <1>; 18182602c32fSVidya Sagar num-viewport = <8>; 18192602c32fSVidya Sagar linux,pci-domain = <3>; 18202602c32fSVidya Sagar 18212602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 18222602c32fSVidya Sagar clock-names = "core"; 18232602c32fSVidya Sagar 18242602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 18252602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 18262602c32fSVidya Sagar reset-names = "apb", "core"; 18272602c32fSVidya Sagar 18282602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18292602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18302602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18312602c32fSVidya Sagar 18322602c32fSVidya Sagar #interrupt-cells = <1>; 18332602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18342602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 18352602c32fSVidya Sagar 18362602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 18372602c32fSVidya Sagar 18382602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18392602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18402602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18412602c32fSVidya Sagar 18422602c32fSVidya Sagar bus-range = <0x0 0xff>; 1843d5237c7cSThierry Reding 18448a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 18458a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 18468a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1847d5237c7cSThierry Reding 1848d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1849d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1850d5237c7cSThierry Reding interconnect-names = "read", "write"; 18512602c32fSVidya Sagar }; 18522602c32fSVidya Sagar 18532602c32fSVidya Sagar pcie@14160000 { 1854f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18552602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1856644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1857644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1858644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1859644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18602602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18612602c32fSVidya Sagar 18622602c32fSVidya Sagar status = "disabled"; 18632602c32fSVidya Sagar 18642602c32fSVidya Sagar #address-cells = <3>; 18652602c32fSVidya Sagar #size-cells = <2>; 18662602c32fSVidya Sagar device_type = "pci"; 18672602c32fSVidya Sagar num-lanes = <4>; 18682602c32fSVidya Sagar num-viewport = <8>; 18692602c32fSVidya Sagar linux,pci-domain = <4>; 18702602c32fSVidya Sagar 18712602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 18722602c32fSVidya Sagar clock-names = "core"; 18732602c32fSVidya Sagar 18742602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 18752602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 18762602c32fSVidya Sagar reset-names = "apb", "core"; 18772602c32fSVidya Sagar 18782602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18792602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18802602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18812602c32fSVidya Sagar 18822602c32fSVidya Sagar #interrupt-cells = <1>; 18832602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18842602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 18852602c32fSVidya Sagar 18862602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 18872602c32fSVidya Sagar 18882602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18892602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18902602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18912602c32fSVidya Sagar 18922602c32fSVidya Sagar bus-range = <0x0 0xff>; 1893d5237c7cSThierry Reding 18948a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 18958a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 18968a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1897d5237c7cSThierry Reding 1898d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1899d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1900d5237c7cSThierry Reding interconnect-names = "read", "write"; 19012602c32fSVidya Sagar }; 19022602c32fSVidya Sagar 19032602c32fSVidya Sagar pcie@14180000 { 1904f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19052602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1906644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1907644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1908644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1909644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19102602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19112602c32fSVidya Sagar 19122602c32fSVidya Sagar status = "disabled"; 19132602c32fSVidya Sagar 19142602c32fSVidya Sagar #address-cells = <3>; 19152602c32fSVidya Sagar #size-cells = <2>; 19162602c32fSVidya Sagar device_type = "pci"; 19172602c32fSVidya Sagar num-lanes = <8>; 19182602c32fSVidya Sagar num-viewport = <8>; 19192602c32fSVidya Sagar linux,pci-domain = <0>; 19202602c32fSVidya Sagar 19212602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 19222602c32fSVidya Sagar clock-names = "core"; 19232602c32fSVidya Sagar 19242602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 19252602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 19262602c32fSVidya Sagar reset-names = "apb", "core"; 19272602c32fSVidya Sagar 19282602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19292602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19302602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19312602c32fSVidya Sagar 19322602c32fSVidya Sagar #interrupt-cells = <1>; 19332602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19342602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 19352602c32fSVidya Sagar 19362602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 19372602c32fSVidya Sagar 19382602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19392602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19402602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19412602c32fSVidya Sagar 19422602c32fSVidya Sagar bus-range = <0x0 0xff>; 1943d5237c7cSThierry Reding 19448a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 19458a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 19468a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1947d5237c7cSThierry Reding 1948d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1949d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1950d5237c7cSThierry Reding interconnect-names = "read", "write"; 19512602c32fSVidya Sagar }; 19522602c32fSVidya Sagar 19532602c32fSVidya Sagar pcie@141a0000 { 1954f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19552602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1956644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1957644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1958644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1959644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19602602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19612602c32fSVidya Sagar 19622602c32fSVidya Sagar status = "disabled"; 19632602c32fSVidya Sagar 19642602c32fSVidya Sagar #address-cells = <3>; 19652602c32fSVidya Sagar #size-cells = <2>; 19662602c32fSVidya Sagar device_type = "pci"; 19672602c32fSVidya Sagar num-lanes = <8>; 19682602c32fSVidya Sagar num-viewport = <8>; 19692602c32fSVidya Sagar linux,pci-domain = <5>; 19702602c32fSVidya Sagar 1971dbb72e2cSVidya Sagar pinctrl-names = "default"; 1972dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1973dbb72e2cSVidya Sagar 19742602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 19752602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 19762602c32fSVidya Sagar clock-names = "core", "core_m"; 19772602c32fSVidya Sagar 19782602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 19792602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 19802602c32fSVidya Sagar reset-names = "apb", "core"; 19812602c32fSVidya Sagar 19822602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19832602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19842602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19852602c32fSVidya Sagar 19862602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 19872602c32fSVidya Sagar 19882602c32fSVidya Sagar #interrupt-cells = <1>; 19892602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19902602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 19912602c32fSVidya Sagar 19922602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19932602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19942602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19952602c32fSVidya Sagar 19962602c32fSVidya Sagar bus-range = <0x0 0xff>; 1997d5237c7cSThierry Reding 19988a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 19998a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 20008a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2001d5237c7cSThierry Reding 2002d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2003d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2004d5237c7cSThierry Reding interconnect-names = "read", "write"; 20052602c32fSVidya Sagar }; 20062602c32fSVidya Sagar 20070c988b73SVidya Sagar pcie_ep@14160000 { 20080c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 20090c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2010644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2011644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2012644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2013644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 20140c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 20150c988b73SVidya Sagar 20160c988b73SVidya Sagar status = "disabled"; 20170c988b73SVidya Sagar 20180c988b73SVidya Sagar num-lanes = <4>; 20190c988b73SVidya Sagar num-ib-windows = <2>; 20200c988b73SVidya Sagar num-ob-windows = <8>; 20210c988b73SVidya Sagar 20220c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 20230c988b73SVidya Sagar clock-names = "core"; 20240c988b73SVidya Sagar 20250c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 20260c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 20270c988b73SVidya Sagar reset-names = "apb", "core"; 20280c988b73SVidya Sagar 20290c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20300c988b73SVidya Sagar interrupt-names = "intr"; 20310c988b73SVidya Sagar 20320c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 20330c988b73SVidya Sagar 20340c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 20350c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20360c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20370c988b73SVidya Sagar }; 20380c988b73SVidya Sagar 20390c988b73SVidya Sagar pcie_ep@14180000 { 20400c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 20410c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2042644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2043644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2044644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2045644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 20460c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 20470c988b73SVidya Sagar 20480c988b73SVidya Sagar status = "disabled"; 20490c988b73SVidya Sagar 20500c988b73SVidya Sagar num-lanes = <8>; 20510c988b73SVidya Sagar num-ib-windows = <2>; 20520c988b73SVidya Sagar num-ob-windows = <8>; 20530c988b73SVidya Sagar 20540c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 20550c988b73SVidya Sagar clock-names = "core"; 20560c988b73SVidya Sagar 20570c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 20580c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 20590c988b73SVidya Sagar reset-names = "apb", "core"; 20600c988b73SVidya Sagar 20610c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20620c988b73SVidya Sagar interrupt-names = "intr"; 20630c988b73SVidya Sagar 20640c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 20650c988b73SVidya Sagar 20660c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 20670c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20680c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20690c988b73SVidya Sagar }; 20700c988b73SVidya Sagar 20710c988b73SVidya Sagar pcie_ep@141a0000 { 20720c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 20730c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2074644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2075644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2076644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2077644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 20780c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 20790c988b73SVidya Sagar 20800c988b73SVidya Sagar status = "disabled"; 20810c988b73SVidya Sagar 20820c988b73SVidya Sagar num-lanes = <8>; 20830c988b73SVidya Sagar num-ib-windows = <2>; 20840c988b73SVidya Sagar num-ob-windows = <8>; 20850c988b73SVidya Sagar 20860c988b73SVidya Sagar pinctrl-names = "default"; 20870c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 20880c988b73SVidya Sagar 20890c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 20900c988b73SVidya Sagar clock-names = "core"; 20910c988b73SVidya Sagar 20920c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 20930c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 20940c988b73SVidya Sagar reset-names = "apb", "core"; 20950c988b73SVidya Sagar 20960c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20970c988b73SVidya Sagar interrupt-names = "intr"; 20980c988b73SVidya Sagar 20990c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 21000c988b73SVidya Sagar 21010c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 21020c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21030c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21040c988b73SVidya Sagar }; 21050c988b73SVidya Sagar 2106e867fe41SThierry Reding sram@40000000 { 21075425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 21085425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 21095425fb15SMikko Perttunen #address-cells = <1>; 21105425fb15SMikko Perttunen #size-cells = <1>; 21115425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 21125425fb15SMikko Perttunen 2113e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 21145425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 21155425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 21165425fb15SMikko Perttunen pool; 21175425fb15SMikko Perttunen }; 21185425fb15SMikko Perttunen 2119e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 21205425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 21215425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 21225425fb15SMikko Perttunen pool; 21235425fb15SMikko Perttunen }; 21245425fb15SMikko Perttunen }; 21255425fb15SMikko Perttunen 21265425fb15SMikko Perttunen bpmp: bpmp { 21275425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 21285425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 21295425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 21305425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 21315425fb15SMikko Perttunen #clock-cells = <1>; 21325425fb15SMikko Perttunen #reset-cells = <1>; 21335425fb15SMikko Perttunen #power-domain-cells = <1>; 2134d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2135d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2136d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2137d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2138d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 21395425fb15SMikko Perttunen 21405425fb15SMikko Perttunen bpmp_i2c: i2c { 21415425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 21425425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 21435425fb15SMikko Perttunen #address-cells = <1>; 21445425fb15SMikko Perttunen #size-cells = <0>; 21455425fb15SMikko Perttunen }; 21465425fb15SMikko Perttunen 21475425fb15SMikko Perttunen bpmp_thermal: thermal { 21485425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 21495425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 21505425fb15SMikko Perttunen }; 21515425fb15SMikko Perttunen }; 21525425fb15SMikko Perttunen 21537780a034SMikko Perttunen cpus { 2154d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2155d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 21567780a034SMikko Perttunen #address-cells = <1>; 21577780a034SMikko Perttunen #size-cells = <0>; 21587780a034SMikko Perttunen 2159b45d322cSThierry Reding cpu0_0: cpu@0 { 216031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21617780a034SMikko Perttunen device_type = "cpu"; 2162b45d322cSThierry Reding reg = <0x000>; 21637780a034SMikko Perttunen enable-method = "psci"; 2164b45d322cSThierry Reding i-cache-size = <131072>; 2165b45d322cSThierry Reding i-cache-line-size = <64>; 2166b45d322cSThierry Reding i-cache-sets = <512>; 2167b45d322cSThierry Reding d-cache-size = <65536>; 2168b45d322cSThierry Reding d-cache-line-size = <64>; 2169b45d322cSThierry Reding d-cache-sets = <256>; 2170b45d322cSThierry Reding next-level-cache = <&l2c_0>; 21717780a034SMikko Perttunen }; 21727780a034SMikko Perttunen 2173b45d322cSThierry Reding cpu0_1: cpu@1 { 217431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21757780a034SMikko Perttunen device_type = "cpu"; 2176b45d322cSThierry Reding reg = <0x001>; 21777780a034SMikko Perttunen enable-method = "psci"; 2178b45d322cSThierry Reding i-cache-size = <131072>; 2179b45d322cSThierry Reding i-cache-line-size = <64>; 2180b45d322cSThierry Reding i-cache-sets = <512>; 2181b45d322cSThierry Reding d-cache-size = <65536>; 2182b45d322cSThierry Reding d-cache-line-size = <64>; 2183b45d322cSThierry Reding d-cache-sets = <256>; 2184b45d322cSThierry Reding next-level-cache = <&l2c_0>; 21857780a034SMikko Perttunen }; 21867780a034SMikko Perttunen 2187b45d322cSThierry Reding cpu1_0: cpu@100 { 218831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21897780a034SMikko Perttunen device_type = "cpu"; 21907780a034SMikko Perttunen reg = <0x100>; 21917780a034SMikko Perttunen enable-method = "psci"; 2192b45d322cSThierry Reding i-cache-size = <131072>; 2193b45d322cSThierry Reding i-cache-line-size = <64>; 2194b45d322cSThierry Reding i-cache-sets = <512>; 2195b45d322cSThierry Reding d-cache-size = <65536>; 2196b45d322cSThierry Reding d-cache-line-size = <64>; 2197b45d322cSThierry Reding d-cache-sets = <256>; 2198b45d322cSThierry Reding next-level-cache = <&l2c_1>; 21997780a034SMikko Perttunen }; 22007780a034SMikko Perttunen 2201b45d322cSThierry Reding cpu1_1: cpu@101 { 220231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22037780a034SMikko Perttunen device_type = "cpu"; 22047780a034SMikko Perttunen reg = <0x101>; 22057780a034SMikko Perttunen enable-method = "psci"; 2206b45d322cSThierry Reding i-cache-size = <131072>; 2207b45d322cSThierry Reding i-cache-line-size = <64>; 2208b45d322cSThierry Reding i-cache-sets = <512>; 2209b45d322cSThierry Reding d-cache-size = <65536>; 2210b45d322cSThierry Reding d-cache-line-size = <64>; 2211b45d322cSThierry Reding d-cache-sets = <256>; 2212b45d322cSThierry Reding next-level-cache = <&l2c_1>; 22137780a034SMikko Perttunen }; 22147780a034SMikko Perttunen 2215b45d322cSThierry Reding cpu2_0: cpu@200 { 221631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22177780a034SMikko Perttunen device_type = "cpu"; 22187780a034SMikko Perttunen reg = <0x200>; 22197780a034SMikko Perttunen enable-method = "psci"; 2220b45d322cSThierry Reding i-cache-size = <131072>; 2221b45d322cSThierry Reding i-cache-line-size = <64>; 2222b45d322cSThierry Reding i-cache-sets = <512>; 2223b45d322cSThierry Reding d-cache-size = <65536>; 2224b45d322cSThierry Reding d-cache-line-size = <64>; 2225b45d322cSThierry Reding d-cache-sets = <256>; 2226b45d322cSThierry Reding next-level-cache = <&l2c_2>; 22277780a034SMikko Perttunen }; 22287780a034SMikko Perttunen 2229b45d322cSThierry Reding cpu2_1: cpu@201 { 223031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22317780a034SMikko Perttunen device_type = "cpu"; 22327780a034SMikko Perttunen reg = <0x201>; 22337780a034SMikko Perttunen enable-method = "psci"; 2234b45d322cSThierry Reding i-cache-size = <131072>; 2235b45d322cSThierry Reding i-cache-line-size = <64>; 2236b45d322cSThierry Reding i-cache-sets = <512>; 2237b45d322cSThierry Reding d-cache-size = <65536>; 2238b45d322cSThierry Reding d-cache-line-size = <64>; 2239b45d322cSThierry Reding d-cache-sets = <256>; 2240b45d322cSThierry Reding next-level-cache = <&l2c_2>; 22417780a034SMikko Perttunen }; 22427780a034SMikko Perttunen 2243b45d322cSThierry Reding cpu3_0: cpu@300 { 224431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22457780a034SMikko Perttunen device_type = "cpu"; 2246b45d322cSThierry Reding reg = <0x300>; 22477780a034SMikko Perttunen enable-method = "psci"; 2248b45d322cSThierry Reding i-cache-size = <131072>; 2249b45d322cSThierry Reding i-cache-line-size = <64>; 2250b45d322cSThierry Reding i-cache-sets = <512>; 2251b45d322cSThierry Reding d-cache-size = <65536>; 2252b45d322cSThierry Reding d-cache-line-size = <64>; 2253b45d322cSThierry Reding d-cache-sets = <256>; 2254b45d322cSThierry Reding next-level-cache = <&l2c_3>; 22557780a034SMikko Perttunen }; 22567780a034SMikko Perttunen 2257b45d322cSThierry Reding cpu3_1: cpu@301 { 225831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22597780a034SMikko Perttunen device_type = "cpu"; 2260b45d322cSThierry Reding reg = <0x301>; 22617780a034SMikko Perttunen enable-method = "psci"; 2262b45d322cSThierry Reding i-cache-size = <131072>; 2263b45d322cSThierry Reding i-cache-line-size = <64>; 2264b45d322cSThierry Reding i-cache-sets = <512>; 2265b45d322cSThierry Reding d-cache-size = <65536>; 2266b45d322cSThierry Reding d-cache-line-size = <64>; 2267b45d322cSThierry Reding d-cache-sets = <256>; 2268b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2269b45d322cSThierry Reding }; 2270b45d322cSThierry Reding 2271b45d322cSThierry Reding cpu-map { 2272b45d322cSThierry Reding cluster0 { 2273b45d322cSThierry Reding core0 { 2274b45d322cSThierry Reding cpu = <&cpu0_0>; 2275b45d322cSThierry Reding }; 2276b45d322cSThierry Reding 2277b45d322cSThierry Reding core1 { 2278b45d322cSThierry Reding cpu = <&cpu0_1>; 2279b45d322cSThierry Reding }; 2280b45d322cSThierry Reding }; 2281b45d322cSThierry Reding 2282b45d322cSThierry Reding cluster1 { 2283b45d322cSThierry Reding core0 { 2284b45d322cSThierry Reding cpu = <&cpu1_0>; 2285b45d322cSThierry Reding }; 2286b45d322cSThierry Reding 2287b45d322cSThierry Reding core1 { 2288b45d322cSThierry Reding cpu = <&cpu1_1>; 2289b45d322cSThierry Reding }; 2290b45d322cSThierry Reding }; 2291b45d322cSThierry Reding 2292b45d322cSThierry Reding cluster2 { 2293b45d322cSThierry Reding core0 { 2294b45d322cSThierry Reding cpu = <&cpu2_0>; 2295b45d322cSThierry Reding }; 2296b45d322cSThierry Reding 2297b45d322cSThierry Reding core1 { 2298b45d322cSThierry Reding cpu = <&cpu2_1>; 2299b45d322cSThierry Reding }; 2300b45d322cSThierry Reding }; 2301b45d322cSThierry Reding 2302b45d322cSThierry Reding cluster3 { 2303b45d322cSThierry Reding core0 { 2304b45d322cSThierry Reding cpu = <&cpu3_0>; 2305b45d322cSThierry Reding }; 2306b45d322cSThierry Reding 2307b45d322cSThierry Reding core1 { 2308b45d322cSThierry Reding cpu = <&cpu3_1>; 2309b45d322cSThierry Reding }; 2310b45d322cSThierry Reding }; 2311b45d322cSThierry Reding }; 2312b45d322cSThierry Reding 2313b45d322cSThierry Reding l2c_0: l2-cache0 { 2314b45d322cSThierry Reding cache-size = <2097152>; 2315b45d322cSThierry Reding cache-line-size = <64>; 2316b45d322cSThierry Reding cache-sets = <2048>; 2317b45d322cSThierry Reding next-level-cache = <&l3c>; 2318b45d322cSThierry Reding }; 2319b45d322cSThierry Reding 2320b45d322cSThierry Reding l2c_1: l2-cache1 { 2321b45d322cSThierry Reding cache-size = <2097152>; 2322b45d322cSThierry Reding cache-line-size = <64>; 2323b45d322cSThierry Reding cache-sets = <2048>; 2324b45d322cSThierry Reding next-level-cache = <&l3c>; 2325b45d322cSThierry Reding }; 2326b45d322cSThierry Reding 2327b45d322cSThierry Reding l2c_2: l2-cache2 { 2328b45d322cSThierry Reding cache-size = <2097152>; 2329b45d322cSThierry Reding cache-line-size = <64>; 2330b45d322cSThierry Reding cache-sets = <2048>; 2331b45d322cSThierry Reding next-level-cache = <&l3c>; 2332b45d322cSThierry Reding }; 2333b45d322cSThierry Reding 2334b45d322cSThierry Reding l2c_3: l2-cache3 { 2335b45d322cSThierry Reding cache-size = <2097152>; 2336b45d322cSThierry Reding cache-line-size = <64>; 2337b45d322cSThierry Reding cache-sets = <2048>; 2338b45d322cSThierry Reding next-level-cache = <&l3c>; 2339b45d322cSThierry Reding }; 2340b45d322cSThierry Reding 2341b45d322cSThierry Reding l3c: l3-cache { 2342b45d322cSThierry Reding cache-size = <4194304>; 2343b45d322cSThierry Reding cache-line-size = <64>; 2344b45d322cSThierry Reding cache-sets = <4096>; 23457780a034SMikko Perttunen }; 23467780a034SMikko Perttunen }; 23477780a034SMikko Perttunen 23487780a034SMikko Perttunen psci { 23497780a034SMikko Perttunen compatible = "arm,psci-1.0"; 23507780a034SMikko Perttunen status = "okay"; 23517780a034SMikko Perttunen method = "smc"; 23527780a034SMikko Perttunen }; 23537780a034SMikko Perttunen 2354*5b4f6323SSameer Pujar sound { 2355*5b4f6323SSameer Pujar status = "disabled"; 2356*5b4f6323SSameer Pujar 2357*5b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 2358*5b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2359*5b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 2360*5b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2361*5b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2362*5b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 2363*5b4f6323SSameer Pujar assigned-clock-parents = <0>, 2364*5b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 2365*5b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2366*5b4f6323SSameer Pujar /* 2367*5b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2368*5b4f6323SSameer Pujar * for this to work and oscillate between base rates required 2369*5b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 2370*5b4f6323SSameer Pujar */ 2371*5b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 2372*5b4f6323SSameer Pujar }; 2373*5b4f6323SSameer Pujar 2374a38570c2SMikko Perttunen tcu: tcu { 2375a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2376a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2377a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2378a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2379a38570c2SMikko Perttunen }; 2380a38570c2SMikko Perttunen 2381686ba009SThierry Reding thermal-zones { 2382686ba009SThierry Reding cpu { 2383686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2384686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2385686ba009SThierry Reding status = "disabled"; 2386686ba009SThierry Reding }; 2387686ba009SThierry Reding 2388686ba009SThierry Reding gpu { 2389686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2390686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2391686ba009SThierry Reding status = "disabled"; 2392686ba009SThierry Reding }; 2393686ba009SThierry Reding 2394686ba009SThierry Reding aux { 2395686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2396686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2397686ba009SThierry Reding status = "disabled"; 2398686ba009SThierry Reding }; 2399686ba009SThierry Reding 2400686ba009SThierry Reding pllx { 2401686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2402686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2403686ba009SThierry Reding status = "disabled"; 2404686ba009SThierry Reding }; 2405686ba009SThierry Reding 2406686ba009SThierry Reding ao { 2407686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2408686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2409686ba009SThierry Reding status = "disabled"; 2410686ba009SThierry Reding }; 2411686ba009SThierry Reding 2412686ba009SThierry Reding tj { 2413686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2414686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2415686ba009SThierry Reding status = "disabled"; 2416686ba009SThierry Reding }; 2417686ba009SThierry Reding }; 2418686ba009SThierry Reding 24195425fb15SMikko Perttunen timer { 24205425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 24215425fb15SMikko Perttunen interrupts = <GIC_PPI 13 24225425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 24235425fb15SMikko Perttunen <GIC_PPI 14 24245425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 24255425fb15SMikko Perttunen <GIC_PPI 11 24265425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 24275425fb15SMikko Perttunen <GIC_PPI 10 24285425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 24295425fb15SMikko Perttunen interrupt-parent = <&gic>; 2430b30be673SThierry Reding always-on; 24315425fb15SMikko Perttunen }; 24325425fb15SMikko Perttunen}; 2433