15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 222838cfddSThierry Reding 232838cfddSThierry Reding #address-cells = <2>; 242838cfddSThierry Reding #size-cells = <2>; 25*4bb54c2cSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 265425fb15SMikko Perttunen 27a47e173eSSumit Gupta apbmisc: misc@100000 { 2809903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 292838cfddSThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 302838cfddSThierry Reding <0x0 0x0010f000 0x0 0x1000>; 3109903c5eSJC Kuo }; 3209903c5eSJC Kuo 33f69ce393SMikko Perttunen gpio: gpio@2200000 { 34f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 35f69ce393SMikko Perttunen reg-names = "security", "gpio"; 362838cfddSThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 372838cfddSThierry Reding <0x0 0x2210000 0x0 0x10000>; 38f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 450a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 530a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 610a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 690a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 850a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86f69ce393SMikko Perttunen #interrupt-cells = <2>; 87f69ce393SMikko Perttunen interrupt-controller; 88f69ce393SMikko Perttunen #gpio-cells = <2>; 89f69ce393SMikko Perttunen gpio-controller; 906f380a4eSThierry Reding gpio-ranges = <&pinmux 0 0 169>; 91f69ce393SMikko Perttunen }; 92f69ce393SMikko Perttunen 93a47e173eSSumit Gupta cbb-noc@2300000 { 94a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 952838cfddSThierry Reding reg = <0x0 0x02300000 0x0 0x1000>; 96a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 99a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 100a47e173eSSumit Gupta status = "okay"; 101a47e173eSSumit Gupta }; 102a47e173eSSumit Gupta 103a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 104a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 1052838cfddSThierry Reding reg = <0x0 0x2390000 0x0 0x1000>, 1062838cfddSThierry Reding <0x0 0x23a0000 0x0 0x1000>, 1072838cfddSThierry Reding <0x0 0x23b0000 0x0 0x1000>, 1082838cfddSThierry Reding <0x0 0x23c0000 0x0 0x1000>, 1092838cfddSThierry Reding <0x0 0x23d0000 0x0 0x1000>, 1102838cfddSThierry Reding <0x0 0x23e0000 0x0 0x1000>; 111a47e173eSSumit Gupta status = "okay"; 112a47e173eSSumit Gupta }; 113a47e173eSSumit Gupta 11479ed18d9SThierry Reding pinmux: pinmux@2430000 { 11579ed18d9SThierry Reding compatible = "nvidia,tegra194-pinmux"; 11679ed18d9SThierry Reding reg = <0x0 0x2430000 0x0 0x17000>; 11779ed18d9SThierry Reding status = "okay"; 11879ed18d9SThierry Reding 11979ed18d9SThierry Reding pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 12079ed18d9SThierry Reding clkreq { 12179ed18d9SThierry Reding nvidia,pins = "pex_l5_clkreq_n_pgg0"; 12279ed18d9SThierry Reding nvidia,schmitt = <TEGRA_PIN_DISABLE>; 12379ed18d9SThierry Reding nvidia,enable-input = <TEGRA_PIN_ENABLE>; 12479ed18d9SThierry Reding nvidia,io-hv = <TEGRA_PIN_ENABLE>; 12579ed18d9SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 12679ed18d9SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 12779ed18d9SThierry Reding }; 12879ed18d9SThierry Reding }; 12979ed18d9SThierry Reding 13079ed18d9SThierry Reding pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 13179ed18d9SThierry Reding pex_rst { 13279ed18d9SThierry Reding nvidia,pins = "pex_l5_rst_n_pgg1"; 13379ed18d9SThierry Reding nvidia,schmitt = <TEGRA_PIN_DISABLE>; 13479ed18d9SThierry Reding nvidia,enable-input = <TEGRA_PIN_DISABLE>; 13579ed18d9SThierry Reding nvidia,io-hv = <TEGRA_PIN_ENABLE>; 13679ed18d9SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 13779ed18d9SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 13879ed18d9SThierry Reding }; 13979ed18d9SThierry Reding }; 14079ed18d9SThierry Reding }; 14179ed18d9SThierry Reding 142f89b58ceSMikko Perttunen ethernet@2490000 { 14319dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 14419dc772aSThierry Reding "nvidia,tegra186-eqos", 145f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 1462838cfddSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 147f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 150f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 151f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 152f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 155f89b58ceSMikko Perttunen reset-names = "eqos"; 156d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 159c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 160f89b58ceSMikko Perttunen status = "disabled"; 161f89b58ceSMikko Perttunen 162f89b58ceSMikko Perttunen snps,write-requests = <1>; 163f89b58ceSMikko Perttunen snps,read-requests = <3>; 164f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 165f89b58ceSMikko Perttunen snps,txpbl = <16>; 166f89b58ceSMikko Perttunen snps,rxpbl = <8>; 167f89b58ceSMikko Perttunen }; 168f89b58ceSMikko Perttunen 169835553b3SAkhil R gpcdma: dma-controller@2600000 { 170835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 171835553b3SAkhil R "nvidia,tegra186-gpcdma"; 1722838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 173835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174835553b3SAkhil R reset-names = "gpcdma"; 175dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207835553b3SAkhil R #dma-cells = <1>; 208835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209835553b3SAkhil R dma-coherent; 210dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 211835553b3SAkhil R status = "okay"; 212835553b3SAkhil R }; 213835553b3SAkhil R 2141aaa7698SThierry Reding aconnect@2900000 { 2155d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 2165d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 2175d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 2185d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 2195d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 2205d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 2215d2249ddSSameer Pujar status = "disabled"; 2225d2249ddSSameer Pujar 2232838cfddSThierry Reding #address-cells = <2>; 2242838cfddSThierry Reding #size-cells = <2>; 2252838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 2262838cfddSThierry Reding 227177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 228177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 229177208f7SSameer Pujar "nvidia,tegra186-ahub"; 2302838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 231177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 232177208f7SSameer Pujar clock-names = "ahub"; 233177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 235177208f7SSameer Pujar status = "disabled"; 236177208f7SSameer Pujar 2372838cfddSThierry Reding #address-cells = <2>; 2382838cfddSThierry Reding #size-cells = <2>; 2392838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 2402838cfddSThierry Reding 241177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 242177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 243177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2442838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 245177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 246177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 247177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 248177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 249177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 250177208f7SSameer Pujar assigned-clock-rates = <1536000>; 251177208f7SSameer Pujar sound-name-prefix = "I2S1"; 252177208f7SSameer Pujar status = "disabled"; 253177208f7SSameer Pujar }; 254177208f7SSameer Pujar 255177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 256177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 257177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2582838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 259177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 260177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 261177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 262177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 263177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 264177208f7SSameer Pujar assigned-clock-rates = <1536000>; 265177208f7SSameer Pujar sound-name-prefix = "I2S2"; 266177208f7SSameer Pujar status = "disabled"; 267177208f7SSameer Pujar }; 268177208f7SSameer Pujar 269177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 270177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 271177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2722838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 273177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 274177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 275177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 276177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 277177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 278177208f7SSameer Pujar assigned-clock-rates = <1536000>; 279177208f7SSameer Pujar sound-name-prefix = "I2S3"; 280177208f7SSameer Pujar status = "disabled"; 281177208f7SSameer Pujar }; 282177208f7SSameer Pujar 283177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 284177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 285177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2862838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 287177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 288177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 289177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 290177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 291177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 292177208f7SSameer Pujar assigned-clock-rates = <1536000>; 293177208f7SSameer Pujar sound-name-prefix = "I2S4"; 294177208f7SSameer Pujar status = "disabled"; 295177208f7SSameer Pujar }; 296177208f7SSameer Pujar 297177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 298177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 299177208f7SSameer Pujar "nvidia,tegra210-i2s"; 3002838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 301177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 302177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 303177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 304177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 305177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 306177208f7SSameer Pujar assigned-clock-rates = <1536000>; 307177208f7SSameer Pujar sound-name-prefix = "I2S5"; 308177208f7SSameer Pujar status = "disabled"; 309177208f7SSameer Pujar }; 310177208f7SSameer Pujar 311177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 312177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 313177208f7SSameer Pujar "nvidia,tegra210-i2s"; 3142838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 315177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 316177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 317177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 318177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 319177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 320177208f7SSameer Pujar assigned-clock-rates = <1536000>; 321177208f7SSameer Pujar sound-name-prefix = "I2S6"; 322177208f7SSameer Pujar status = "disabled"; 323177208f7SSameer Pujar }; 324177208f7SSameer Pujar 32579ed18d9SThierry Reding tegra_sfc1: sfc@2902000 { 32679ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 32779ed18d9SThierry Reding "nvidia,tegra210-sfc"; 32879ed18d9SThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 32979ed18d9SThierry Reding sound-name-prefix = "SFC1"; 33079ed18d9SThierry Reding status = "disabled"; 33179ed18d9SThierry Reding }; 33279ed18d9SThierry Reding 33379ed18d9SThierry Reding tegra_sfc2: sfc@2902200 { 33479ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 33579ed18d9SThierry Reding "nvidia,tegra210-sfc"; 33679ed18d9SThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 33779ed18d9SThierry Reding sound-name-prefix = "SFC2"; 33879ed18d9SThierry Reding status = "disabled"; 33979ed18d9SThierry Reding }; 34079ed18d9SThierry Reding 34179ed18d9SThierry Reding tegra_sfc3: sfc@2902400 { 34279ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 34379ed18d9SThierry Reding "nvidia,tegra210-sfc"; 34479ed18d9SThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 34579ed18d9SThierry Reding sound-name-prefix = "SFC3"; 34679ed18d9SThierry Reding status = "disabled"; 34779ed18d9SThierry Reding }; 34879ed18d9SThierry Reding 34979ed18d9SThierry Reding tegra_sfc4: sfc@2902600 { 35079ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 35179ed18d9SThierry Reding "nvidia,tegra210-sfc"; 35279ed18d9SThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 35379ed18d9SThierry Reding sound-name-prefix = "SFC4"; 35479ed18d9SThierry Reding status = "disabled"; 35579ed18d9SThierry Reding }; 35679ed18d9SThierry Reding 35779ed18d9SThierry Reding tegra_amx1: amx@2903000 { 35879ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 35979ed18d9SThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 36079ed18d9SThierry Reding sound-name-prefix = "AMX1"; 36179ed18d9SThierry Reding status = "disabled"; 36279ed18d9SThierry Reding }; 36379ed18d9SThierry Reding 36479ed18d9SThierry Reding tegra_amx2: amx@2903100 { 36579ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 36679ed18d9SThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 36779ed18d9SThierry Reding sound-name-prefix = "AMX2"; 36879ed18d9SThierry Reding status = "disabled"; 36979ed18d9SThierry Reding }; 37079ed18d9SThierry Reding 37179ed18d9SThierry Reding tegra_amx3: amx@2903200 { 37279ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 37379ed18d9SThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 37479ed18d9SThierry Reding sound-name-prefix = "AMX3"; 37579ed18d9SThierry Reding status = "disabled"; 37679ed18d9SThierry Reding }; 37779ed18d9SThierry Reding 37879ed18d9SThierry Reding tegra_amx4: amx@2903300 { 37979ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 38079ed18d9SThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 38179ed18d9SThierry Reding sound-name-prefix = "AMX4"; 38279ed18d9SThierry Reding status = "disabled"; 38379ed18d9SThierry Reding }; 38479ed18d9SThierry Reding 38579ed18d9SThierry Reding tegra_adx1: adx@2903800 { 38679ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 38779ed18d9SThierry Reding "nvidia,tegra210-adx"; 38879ed18d9SThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 38979ed18d9SThierry Reding sound-name-prefix = "ADX1"; 39079ed18d9SThierry Reding status = "disabled"; 39179ed18d9SThierry Reding }; 39279ed18d9SThierry Reding 39379ed18d9SThierry Reding tegra_adx2: adx@2903900 { 39479ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 39579ed18d9SThierry Reding "nvidia,tegra210-adx"; 39679ed18d9SThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 39779ed18d9SThierry Reding sound-name-prefix = "ADX2"; 39879ed18d9SThierry Reding status = "disabled"; 39979ed18d9SThierry Reding }; 40079ed18d9SThierry Reding 40179ed18d9SThierry Reding tegra_adx3: adx@2903a00 { 40279ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 40379ed18d9SThierry Reding "nvidia,tegra210-adx"; 40479ed18d9SThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 40579ed18d9SThierry Reding sound-name-prefix = "ADX3"; 40679ed18d9SThierry Reding status = "disabled"; 40779ed18d9SThierry Reding }; 40879ed18d9SThierry Reding 40979ed18d9SThierry Reding tegra_adx4: adx@2903b00 { 41079ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 41179ed18d9SThierry Reding "nvidia,tegra210-adx"; 41279ed18d9SThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 41379ed18d9SThierry Reding sound-name-prefix = "ADX4"; 41479ed18d9SThierry Reding status = "disabled"; 41579ed18d9SThierry Reding }; 41679ed18d9SThierry Reding 417177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 418177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 419177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4202838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 421177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 422177208f7SSameer Pujar clock-names = "dmic"; 423177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 424177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 425177208f7SSameer Pujar assigned-clock-rates = <3072000>; 426177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 427177208f7SSameer Pujar status = "disabled"; 428177208f7SSameer Pujar }; 429177208f7SSameer Pujar 430177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 431177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 432177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4332838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 434177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 435177208f7SSameer Pujar clock-names = "dmic"; 436177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 437177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 438177208f7SSameer Pujar assigned-clock-rates = <3072000>; 439177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 440177208f7SSameer Pujar status = "disabled"; 441177208f7SSameer Pujar }; 442177208f7SSameer Pujar 443177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 444177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 445177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4462838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 447177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 448177208f7SSameer Pujar clock-names = "dmic"; 449177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 450177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 451177208f7SSameer Pujar assigned-clock-rates = <3072000>; 452177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 453177208f7SSameer Pujar status = "disabled"; 454177208f7SSameer Pujar }; 455177208f7SSameer Pujar 456177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 457177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 458177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4592838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 460177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 461177208f7SSameer Pujar clock-names = "dmic"; 462177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 463177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 464177208f7SSameer Pujar assigned-clock-rates = <3072000>; 465177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 466177208f7SSameer Pujar status = "disabled"; 467177208f7SSameer Pujar }; 468177208f7SSameer Pujar 469177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 470177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 471177208f7SSameer Pujar "nvidia,tegra186-dspk"; 4722838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 473177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 474177208f7SSameer Pujar clock-names = "dspk"; 475177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 476177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 477177208f7SSameer Pujar assigned-clock-rates = <12288000>; 478177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 479177208f7SSameer Pujar status = "disabled"; 480177208f7SSameer Pujar }; 481177208f7SSameer Pujar 482177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 483177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 484177208f7SSameer Pujar "nvidia,tegra186-dspk"; 4852838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 486177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 487177208f7SSameer Pujar clock-names = "dspk"; 488177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 489177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 490177208f7SSameer Pujar assigned-clock-rates = <12288000>; 491177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 492177208f7SSameer Pujar status = "disabled"; 493177208f7SSameer Pujar }; 494848f3290SSameer Pujar 4954b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4964b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 4974b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4982838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 4994b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5004b6a1b7cSSameer Pujar status = "disabled"; 5014b6a1b7cSSameer Pujar 5022838cfddSThierry Reding #address-cells = <2>; 5032838cfddSThierry Reding #size-cells = <2>; 5042838cfddSThierry Reding ranges; 5052838cfddSThierry Reding 5064b6a1b7cSSameer Pujar equalizer@2908100 { 5074b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 5084b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5092838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 5104b6a1b7cSSameer Pujar }; 5114b6a1b7cSSameer Pujar 5124b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 5134b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 5144b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 5152838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 5164b6a1b7cSSameer Pujar }; 5174b6a1b7cSSameer Pujar }; 5184b6a1b7cSSameer Pujar 51979ed18d9SThierry Reding tegra_mvc1: mvc@290a000 { 52079ed18d9SThierry Reding compatible = "nvidia,tegra194-mvc", 52179ed18d9SThierry Reding "nvidia,tegra210-mvc"; 52279ed18d9SThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 52379ed18d9SThierry Reding sound-name-prefix = "MVC1"; 52479ed18d9SThierry Reding status = "disabled"; 52579ed18d9SThierry Reding }; 52679ed18d9SThierry Reding 52779ed18d9SThierry Reding tegra_mvc2: mvc@290a200 { 52879ed18d9SThierry Reding compatible = "nvidia,tegra194-mvc", 52979ed18d9SThierry Reding "nvidia,tegra210-mvc"; 53079ed18d9SThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 53179ed18d9SThierry Reding sound-name-prefix = "MVC2"; 53279ed18d9SThierry Reding status = "disabled"; 53379ed18d9SThierry Reding }; 53479ed18d9SThierry Reding 535848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 536848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 537848f3290SSameer Pujar "nvidia,tegra210-amixer"; 5382838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 539848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 540848f3290SSameer Pujar status = "disabled"; 541848f3290SSameer Pujar }; 54247a08153SSameer Pujar 54379ed18d9SThierry Reding tegra_admaif: admaif@290f000 { 54479ed18d9SThierry Reding compatible = "nvidia,tegra194-admaif", 54579ed18d9SThierry Reding "nvidia,tegra186-admaif"; 54679ed18d9SThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 54779ed18d9SThierry Reding dmas = <&adma 1>, <&adma 1>, 54879ed18d9SThierry Reding <&adma 2>, <&adma 2>, 54979ed18d9SThierry Reding <&adma 3>, <&adma 3>, 55079ed18d9SThierry Reding <&adma 4>, <&adma 4>, 55179ed18d9SThierry Reding <&adma 5>, <&adma 5>, 55279ed18d9SThierry Reding <&adma 6>, <&adma 6>, 55379ed18d9SThierry Reding <&adma 7>, <&adma 7>, 55479ed18d9SThierry Reding <&adma 8>, <&adma 8>, 55579ed18d9SThierry Reding <&adma 9>, <&adma 9>, 55679ed18d9SThierry Reding <&adma 10>, <&adma 10>, 55779ed18d9SThierry Reding <&adma 11>, <&adma 11>, 55879ed18d9SThierry Reding <&adma 12>, <&adma 12>, 55979ed18d9SThierry Reding <&adma 13>, <&adma 13>, 56079ed18d9SThierry Reding <&adma 14>, <&adma 14>, 56179ed18d9SThierry Reding <&adma 15>, <&adma 15>, 56279ed18d9SThierry Reding <&adma 16>, <&adma 16>, 56379ed18d9SThierry Reding <&adma 17>, <&adma 17>, 56479ed18d9SThierry Reding <&adma 18>, <&adma 18>, 56579ed18d9SThierry Reding <&adma 19>, <&adma 19>, 56679ed18d9SThierry Reding <&adma 20>, <&adma 20>; 56779ed18d9SThierry Reding dma-names = "rx1", "tx1", 56879ed18d9SThierry Reding "rx2", "tx2", 56979ed18d9SThierry Reding "rx3", "tx3", 57079ed18d9SThierry Reding "rx4", "tx4", 57179ed18d9SThierry Reding "rx5", "tx5", 57279ed18d9SThierry Reding "rx6", "tx6", 57379ed18d9SThierry Reding "rx7", "tx7", 57479ed18d9SThierry Reding "rx8", "tx8", 57579ed18d9SThierry Reding "rx9", "tx9", 57679ed18d9SThierry Reding "rx10", "tx10", 57779ed18d9SThierry Reding "rx11", "tx11", 57879ed18d9SThierry Reding "rx12", "tx12", 57979ed18d9SThierry Reding "rx13", "tx13", 58079ed18d9SThierry Reding "rx14", "tx14", 58179ed18d9SThierry Reding "rx15", "tx15", 58279ed18d9SThierry Reding "rx16", "tx16", 58379ed18d9SThierry Reding "rx17", "tx17", 58479ed18d9SThierry Reding "rx18", "tx18", 58579ed18d9SThierry Reding "rx19", "tx19", 58679ed18d9SThierry Reding "rx20", "tx20"; 58779ed18d9SThierry Reding status = "disabled"; 58879ed18d9SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 58979ed18d9SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 59079ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 59179ed18d9SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 59279ed18d9SThierry Reding }; 59379ed18d9SThierry Reding 59447a08153SSameer Pujar tegra_asrc: asrc@2910000 { 59547a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 59647a08153SSameer Pujar "nvidia,tegra186-asrc"; 5972838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 59847a08153SSameer Pujar sound-name-prefix = "ASRC1"; 59947a08153SSameer Pujar status = "disabled"; 60047a08153SSameer Pujar }; 601177208f7SSameer Pujar }; 60279ed18d9SThierry Reding 60379ed18d9SThierry Reding adma: dma-controller@2930000 { 60479ed18d9SThierry Reding compatible = "nvidia,tegra194-adma", 60579ed18d9SThierry Reding "nvidia,tegra186-adma"; 60679ed18d9SThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 60779ed18d9SThierry Reding interrupt-parent = <&agic>; 60879ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 60979ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 61079ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 61179ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 61279ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 61379ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 61479ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 61579ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 61679ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 61779ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 61879ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 61979ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 62079ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 62179ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 62279ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 62379ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 62479ed18d9SThierry Reding <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 62579ed18d9SThierry Reding <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 62679ed18d9SThierry Reding <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 62779ed18d9SThierry Reding <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 62879ed18d9SThierry Reding <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 62979ed18d9SThierry Reding <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 63079ed18d9SThierry Reding <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 63179ed18d9SThierry Reding <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 63279ed18d9SThierry Reding <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 63379ed18d9SThierry Reding <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 63479ed18d9SThierry Reding <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 63579ed18d9SThierry Reding <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 63679ed18d9SThierry Reding <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 63779ed18d9SThierry Reding <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 63879ed18d9SThierry Reding <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 63979ed18d9SThierry Reding <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 64079ed18d9SThierry Reding #dma-cells = <1>; 64179ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_AHUB>; 64279ed18d9SThierry Reding clock-names = "d_audio"; 64379ed18d9SThierry Reding status = "disabled"; 6445d2249ddSSameer Pujar }; 6455d2249ddSSameer Pujar 64679ed18d9SThierry Reding agic: interrupt-controller@2a40000 { 64779ed18d9SThierry Reding compatible = "nvidia,tegra194-agic", 64879ed18d9SThierry Reding "nvidia,tegra210-agic"; 64979ed18d9SThierry Reding #interrupt-cells = <3>; 65079ed18d9SThierry Reding interrupt-controller; 65179ed18d9SThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 65279ed18d9SThierry Reding <0x0 0x02a42000 0x0 0x2000>; 65379ed18d9SThierry Reding interrupts = <GIC_SPI 145 65479ed18d9SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | 65579ed18d9SThierry Reding IRQ_TYPE_LEVEL_HIGH)>; 65679ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_APE>; 65779ed18d9SThierry Reding clock-names = "clk"; 65879ed18d9SThierry Reding status = "disabled"; 659dbb72e2cSVidya Sagar }; 660dbb72e2cSVidya Sagar }; 661dbb72e2cSVidya Sagar 662be9b887fSThierry Reding mc: memory-controller@2c00000 { 663be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 6642838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6652838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6662838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6672838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6682838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6692838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6702838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6712838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6722838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6732838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6742838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6752838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6762838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6772838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6782838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6792838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6802838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6812838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6858613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686d5237c7cSThierry Reding #interconnect-cells = <1>; 687be9b887fSThierry Reding status = "disabled"; 688be9b887fSThierry Reding 689be9b887fSThierry Reding #address-cells = <2>; 690be9b887fSThierry Reding #size-cells = <2>; 6912838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6922838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6932838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694be9b887fSThierry Reding 695be9b887fSThierry Reding /* 696be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 697be9b887fSThierry Reding * controller selects the XBAR format used when memory 698be9b887fSThierry Reding * is accessed. This is used to transparently access 699be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 700be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 701be9b887fSThierry Reding * 702be9b887fSThierry Reding * As a consequence, the operating system must ensure 703be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 704be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 705be9b887fSThierry Reding * devices require access to the XBAR switch, their 706be9b887fSThierry Reding * drivers must set this bit explicitly. 707be9b887fSThierry Reding * 708be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 709be9b887fSThierry Reding */ 7102838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711be9b887fSThierry Reding 712be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 713be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 714be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 715be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 716cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 718be9b887fSThierry Reding clock-names = "emc"; 719be9b887fSThierry Reding 720d5237c7cSThierry Reding #interconnect-cells = <0>; 721d5237c7cSThierry Reding 722be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 723be9b887fSThierry Reding }; 724be9b887fSThierry Reding }; 725be9b887fSThierry Reding 7265aa9083eSThierry Reding timer@3010000 { 7275aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 7282838cfddSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 7295aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7305aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7345aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7355aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7365aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7375aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7385aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7395aa9083eSThierry Reding status = "okay"; 7405aa9083eSThierry Reding }; 7415aa9083eSThierry Reding 7425425fb15SMikko Perttunen uarta: serial@3100000 { 7435425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7442838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x40>; 7455425fb15SMikko Perttunen reg-shift = <2>; 7465425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7475425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7485425fb15SMikko Perttunen clock-names = "serial"; 7495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7505425fb15SMikko Perttunen reset-names = "serial"; 7515425fb15SMikko Perttunen status = "disabled"; 7525425fb15SMikko Perttunen }; 7535425fb15SMikko Perttunen 7545425fb15SMikko Perttunen uartb: serial@3110000 { 7555425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7562838cfddSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 7575425fb15SMikko Perttunen reg-shift = <2>; 7585425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7595425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7605425fb15SMikko Perttunen clock-names = "serial"; 7615425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7625425fb15SMikko Perttunen reset-names = "serial"; 7635425fb15SMikko Perttunen status = "disabled"; 7645425fb15SMikko Perttunen }; 7655425fb15SMikko Perttunen 7665425fb15SMikko Perttunen uartd: serial@3130000 { 7675425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7682838cfddSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 7695425fb15SMikko Perttunen reg-shift = <2>; 7705425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7725425fb15SMikko Perttunen clock-names = "serial"; 7735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7745425fb15SMikko Perttunen reset-names = "serial"; 7755425fb15SMikko Perttunen status = "disabled"; 7765425fb15SMikko Perttunen }; 7775425fb15SMikko Perttunen 7785425fb15SMikko Perttunen uarte: serial@3140000 { 7795425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7802838cfddSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 7815425fb15SMikko Perttunen reg-shift = <2>; 7825425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7845425fb15SMikko Perttunen clock-names = "serial"; 7855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7865425fb15SMikko Perttunen reset-names = "serial"; 7875425fb15SMikko Perttunen status = "disabled"; 7885425fb15SMikko Perttunen }; 7895425fb15SMikko Perttunen 7905425fb15SMikko Perttunen uartf: serial@3150000 { 7915425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7922838cfddSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 7935425fb15SMikko Perttunen reg-shift = <2>; 7945425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7965425fb15SMikko Perttunen clock-names = "serial"; 7975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7985425fb15SMikko Perttunen reset-names = "serial"; 7995425fb15SMikko Perttunen status = "disabled"; 8005425fb15SMikko Perttunen }; 8015425fb15SMikko Perttunen 8025425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 803d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8042838cfddSThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 8055425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8065425fb15SMikko Perttunen #address-cells = <1>; 8075425fb15SMikko Perttunen #size-cells = <0>; 8085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8095425fb15SMikko Perttunen clock-names = "div-clk"; 8105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8115425fb15SMikko Perttunen reset-names = "i2c"; 8128e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8138e442805SAkhil R dma-names = "rx", "tx"; 8145425fb15SMikko Perttunen status = "disabled"; 8155425fb15SMikko Perttunen }; 8165425fb15SMikko Perttunen 8175425fb15SMikko Perttunen uarth: serial@3170000 { 8185425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8192838cfddSThierry Reding reg = <0x0 0x03170000 0x0 0x40>; 8205425fb15SMikko Perttunen reg-shift = <2>; 8215425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8225425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8235425fb15SMikko Perttunen clock-names = "serial"; 8245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8255425fb15SMikko Perttunen reset-names = "serial"; 8265425fb15SMikko Perttunen status = "disabled"; 8275425fb15SMikko Perttunen }; 8285425fb15SMikko Perttunen 8295425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 830d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8312838cfddSThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 8325425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8335425fb15SMikko Perttunen #address-cells = <1>; 8345425fb15SMikko Perttunen #size-cells = <0>; 8355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8365425fb15SMikko Perttunen clock-names = "div-clk"; 8375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8385425fb15SMikko Perttunen reset-names = "i2c"; 8398e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8408e442805SAkhil R dma-names = "rx", "tx"; 8415425fb15SMikko Perttunen status = "disabled"; 8425425fb15SMikko Perttunen }; 8435425fb15SMikko Perttunen 8445425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8455425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 846d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8472838cfddSThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 8485425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8495425fb15SMikko Perttunen #address-cells = <1>; 8505425fb15SMikko Perttunen #size-cells = <0>; 8515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8525425fb15SMikko Perttunen clock-names = "div-clk"; 8535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8545425fb15SMikko Perttunen reset-names = "i2c"; 855a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 856a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 857a4131561SThierry Reding pinctrl-names = "default", "idle"; 8588e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8598e442805SAkhil R dma-names = "rx", "tx"; 8605425fb15SMikko Perttunen status = "disabled"; 8615425fb15SMikko Perttunen }; 8625425fb15SMikko Perttunen 8635425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8645425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 865d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8662838cfddSThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 8675425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8685425fb15SMikko Perttunen #address-cells = <1>; 8695425fb15SMikko Perttunen #size-cells = <0>; 8705425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8715425fb15SMikko Perttunen clock-names = "div-clk"; 8725425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8735425fb15SMikko Perttunen reset-names = "i2c"; 874a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 875a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 876a4131561SThierry Reding pinctrl-names = "default", "idle"; 8778e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8788e442805SAkhil R dma-names = "rx", "tx"; 8795425fb15SMikko Perttunen status = "disabled"; 8805425fb15SMikko Perttunen }; 8815425fb15SMikko Perttunen 882a4131561SThierry Reding /* shares pads with dpaux2 */ 883a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 884d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8852838cfddSThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 8865425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8875425fb15SMikko Perttunen #address-cells = <1>; 8885425fb15SMikko Perttunen #size-cells = <0>; 8895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8905425fb15SMikko Perttunen clock-names = "div-clk"; 8915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8925425fb15SMikko Perttunen reset-names = "i2c"; 893a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 894a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 895a4131561SThierry Reding pinctrl-names = "default", "idle"; 8968e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 8978e442805SAkhil R dma-names = "rx", "tx"; 8985425fb15SMikko Perttunen status = "disabled"; 8995425fb15SMikko Perttunen }; 9005425fb15SMikko Perttunen 901a4131561SThierry Reding /* shares pads with dpaux3 */ 902a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 903d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9042838cfddSThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 9055425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9065425fb15SMikko Perttunen #address-cells = <1>; 9075425fb15SMikko Perttunen #size-cells = <0>; 9085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9095425fb15SMikko Perttunen clock-names = "div-clk"; 9105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9115425fb15SMikko Perttunen reset-names = "i2c"; 912a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 913a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 914a4131561SThierry Reding pinctrl-names = "default", "idle"; 9158e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9168e442805SAkhil R dma-names = "rx", "tx"; 9175425fb15SMikko Perttunen status = "disabled"; 9185425fb15SMikko Perttunen }; 9195425fb15SMikko Perttunen 92096ded827SSowjanya Komatineni spi@3270000 { 92196ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 9222838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 92396ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 92496ded827SSowjanya Komatineni #address-cells = <1>; 92596ded827SSowjanya Komatineni #size-cells = <0>; 92696ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 92796ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 92896ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 92996ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 93096ded827SSowjanya Komatineni status = "disabled"; 93196ded827SSowjanya Komatineni }; 93296ded827SSowjanya Komatineni 9336a574ec7SThierry Reding pwm1: pwm@3280000 { 9346a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9356a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9362838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 9376a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9386a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9396a574ec7SThierry Reding reset-names = "pwm"; 9406a574ec7SThierry Reding status = "disabled"; 9416a574ec7SThierry Reding #pwm-cells = <2>; 9426a574ec7SThierry Reding }; 9436a574ec7SThierry Reding 9446a574ec7SThierry Reding pwm2: pwm@3290000 { 9456a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9466a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9472838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 9486a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9496a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9506a574ec7SThierry Reding reset-names = "pwm"; 9516a574ec7SThierry Reding status = "disabled"; 9526a574ec7SThierry Reding #pwm-cells = <2>; 9536a574ec7SThierry Reding }; 9546a574ec7SThierry Reding 9556a574ec7SThierry Reding pwm3: pwm@32a0000 { 9566a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9576a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9582838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 9596a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9606a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9616a574ec7SThierry Reding reset-names = "pwm"; 9626a574ec7SThierry Reding status = "disabled"; 9636a574ec7SThierry Reding #pwm-cells = <2>; 9646a574ec7SThierry Reding }; 9656a574ec7SThierry Reding 9666a574ec7SThierry Reding pwm5: pwm@32c0000 { 9676a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9686a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9692838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 9706a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9716a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9726a574ec7SThierry Reding reset-names = "pwm"; 9736a574ec7SThierry Reding status = "disabled"; 9746a574ec7SThierry Reding #pwm-cells = <2>; 9756a574ec7SThierry Reding }; 9766a574ec7SThierry Reding 9776a574ec7SThierry Reding pwm6: pwm@32d0000 { 9786a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9796a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9802838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 9816a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 9826a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 9836a574ec7SThierry Reding reset-names = "pwm"; 9846a574ec7SThierry Reding status = "disabled"; 9856a574ec7SThierry Reding #pwm-cells = <2>; 9866a574ec7SThierry Reding }; 9876a574ec7SThierry Reding 9886a574ec7SThierry Reding pwm7: pwm@32e0000 { 9896a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9906a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9912838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 9926a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 9936a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 9946a574ec7SThierry Reding reset-names = "pwm"; 9956a574ec7SThierry Reding status = "disabled"; 9966a574ec7SThierry Reding #pwm-cells = <2>; 9976a574ec7SThierry Reding }; 9986a574ec7SThierry Reding 9996a574ec7SThierry Reding pwm8: pwm@32f0000 { 10006a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10016a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10022838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 10036a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10046a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10056a574ec7SThierry Reding reset-names = "pwm"; 10066a574ec7SThierry Reding status = "disabled"; 10076a574ec7SThierry Reding #pwm-cells = <2>; 10086a574ec7SThierry Reding }; 10096a574ec7SThierry Reding 101079ed18d9SThierry Reding spi@3300000 { 101179ed18d9SThierry Reding compatible = "nvidia,tegra194-qspi"; 101279ed18d9SThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 101379ed18d9SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 101479ed18d9SThierry Reding #address-cells = <1>; 101579ed18d9SThierry Reding #size-cells = <0>; 101679ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_QSPI1>, 101779ed18d9SThierry Reding <&bpmp TEGRA194_CLK_QSPI1_PM>; 101879ed18d9SThierry Reding clock-names = "qspi", "qspi_out"; 101979ed18d9SThierry Reding resets = <&bpmp TEGRA194_RESET_QSPI1>; 102079ed18d9SThierry Reding status = "disabled"; 102179ed18d9SThierry Reding }; 102279ed18d9SThierry Reding 102367bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10242c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10252838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 10265425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1027c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1028c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1029c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10307ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10317ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10327ac853baSAniruddha Rao assigned-clock-parents = 10337ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10347ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10365425fb15SMikko Perttunen reset-names = "sdhci"; 1037d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1038d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1039d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1040c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1041ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1042ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1043ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10454e0f1229SSowjanya Komatineni <0x07>; 10464e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10474e0f1229SSowjanya Komatineni <0x07>; 10484e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10494e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10504e0f1229SSowjanya Komatineni <0x07>; 10514e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10524e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10534e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10544e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1055ff21087eSPrathamesh Shete sd-uhs-sdr25; 1056ff21087eSPrathamesh Shete sd-uhs-sdr50; 1057ff21087eSPrathamesh Shete sd-uhs-ddr50; 1058ff21087eSPrathamesh Shete sd-uhs-sdr104; 10595425fb15SMikko Perttunen status = "disabled"; 10605425fb15SMikko Perttunen }; 10615425fb15SMikko Perttunen 106267bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10632c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10642838cfddSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 10655425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1066c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1067c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1068c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10697ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10707ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10717ac853baSAniruddha Rao assigned-clock-parents = 10727ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10737ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10755425fb15SMikko Perttunen reset-names = "sdhci"; 1076d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1077d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1078d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1079c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1080ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1081ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1082ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10834e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10864e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10874e0f1229SSowjanya Komatineni <0x07>; 10884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10894e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10904e0f1229SSowjanya Komatineni <0x07>; 10914e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10924e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10934e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10944e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1095ff21087eSPrathamesh Shete sd-uhs-sdr25; 1096ff21087eSPrathamesh Shete sd-uhs-sdr50; 1097ff21087eSPrathamesh Shete sd-uhs-ddr50; 1098ff21087eSPrathamesh Shete sd-uhs-sdr104; 10995425fb15SMikko Perttunen status = "disabled"; 11005425fb15SMikko Perttunen }; 11015425fb15SMikko Perttunen 110267bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11032c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 11042838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 11055425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1106c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1107c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1108c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1109351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1110351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1111351648d0SSowjanya Komatineni assigned-clock-parents = 1112351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11145425fb15SMikko Perttunen reset-names = "sdhci"; 1115d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1116d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1117d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1118c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11194e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11204e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11214e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11224e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11234e0f1229SSowjanya Komatineni <0x0a>; 11244e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11254e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11264e0f1229SSowjanya Komatineni <0x0a>; 11274e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11284e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11294e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1130c2fee443SPrathamesh Shete cap-mmc-highspeed; 1131c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1132c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1133c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1134c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1135dfd3cb6fSSowjanya Komatineni supports-cqe; 11365425fb15SMikko Perttunen status = "disabled"; 11375425fb15SMikko Perttunen }; 11385425fb15SMikko Perttunen 11394878cc0cSSameer Pujar hda@3510000 { 11407f0ea5acSThierry Reding compatible = "nvidia,tegra194-hda"; 11412838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 11424878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11434878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 114448f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 114548f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 114648f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11474878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1148146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1149146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11504878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1151d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1152d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1153d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1154c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11554878cc0cSSameer Pujar status = "disabled"; 11564878cc0cSSameer Pujar }; 11574878cc0cSSameer Pujar 1158fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1159fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 11602838cfddSThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 11612838cfddSThierry Reding <0x0 0x03540000 0x0 0x1000>; 1162fab7a039SJC Kuo reg-names = "padctl", "ao"; 11636450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1164fab7a039SJC Kuo 1165fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1166fab7a039SJC Kuo reset-names = "padctl"; 1167fab7a039SJC Kuo 1168fab7a039SJC Kuo status = "disabled"; 1169fab7a039SJC Kuo 1170fab7a039SJC Kuo pads { 1171fab7a039SJC Kuo usb2 { 1172fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1173fab7a039SJC Kuo clock-names = "trk"; 1174fab7a039SJC Kuo 1175fab7a039SJC Kuo lanes { 1176fab7a039SJC Kuo usb2-0 { 1177fab7a039SJC Kuo nvidia,function = "xusb"; 1178fab7a039SJC Kuo status = "disabled"; 1179fab7a039SJC Kuo #phy-cells = <0>; 1180fab7a039SJC Kuo }; 1181fab7a039SJC Kuo 1182fab7a039SJC Kuo usb2-1 { 1183fab7a039SJC Kuo nvidia,function = "xusb"; 1184fab7a039SJC Kuo status = "disabled"; 1185fab7a039SJC Kuo #phy-cells = <0>; 1186fab7a039SJC Kuo }; 1187fab7a039SJC Kuo 1188fab7a039SJC Kuo usb2-2 { 1189fab7a039SJC Kuo nvidia,function = "xusb"; 1190fab7a039SJC Kuo status = "disabled"; 1191fab7a039SJC Kuo #phy-cells = <0>; 1192fab7a039SJC Kuo }; 1193fab7a039SJC Kuo 1194fab7a039SJC Kuo usb2-3 { 1195fab7a039SJC Kuo nvidia,function = "xusb"; 1196fab7a039SJC Kuo status = "disabled"; 1197fab7a039SJC Kuo #phy-cells = <0>; 1198fab7a039SJC Kuo }; 1199fab7a039SJC Kuo }; 1200fab7a039SJC Kuo }; 1201fab7a039SJC Kuo 1202fab7a039SJC Kuo usb3 { 1203fab7a039SJC Kuo lanes { 1204fab7a039SJC Kuo usb3-0 { 1205fab7a039SJC Kuo nvidia,function = "xusb"; 1206fab7a039SJC Kuo status = "disabled"; 1207fab7a039SJC Kuo #phy-cells = <0>; 1208fab7a039SJC Kuo }; 1209fab7a039SJC Kuo 1210fab7a039SJC Kuo usb3-1 { 1211fab7a039SJC Kuo nvidia,function = "xusb"; 1212fab7a039SJC Kuo status = "disabled"; 1213fab7a039SJC Kuo #phy-cells = <0>; 1214fab7a039SJC Kuo }; 1215fab7a039SJC Kuo 1216fab7a039SJC Kuo usb3-2 { 1217fab7a039SJC Kuo nvidia,function = "xusb"; 1218fab7a039SJC Kuo status = "disabled"; 1219fab7a039SJC Kuo #phy-cells = <0>; 1220fab7a039SJC Kuo }; 1221fab7a039SJC Kuo 1222fab7a039SJC Kuo usb3-3 { 1223fab7a039SJC Kuo nvidia,function = "xusb"; 1224fab7a039SJC Kuo status = "disabled"; 1225fab7a039SJC Kuo #phy-cells = <0>; 1226fab7a039SJC Kuo }; 1227fab7a039SJC Kuo }; 1228fab7a039SJC Kuo }; 1229fab7a039SJC Kuo }; 1230fab7a039SJC Kuo 1231fab7a039SJC Kuo ports { 1232fab7a039SJC Kuo usb2-0 { 1233fab7a039SJC Kuo status = "disabled"; 1234fab7a039SJC Kuo }; 1235fab7a039SJC Kuo 1236fab7a039SJC Kuo usb2-1 { 1237fab7a039SJC Kuo status = "disabled"; 1238fab7a039SJC Kuo }; 1239fab7a039SJC Kuo 1240fab7a039SJC Kuo usb2-2 { 1241fab7a039SJC Kuo status = "disabled"; 1242fab7a039SJC Kuo }; 1243fab7a039SJC Kuo 1244fab7a039SJC Kuo usb2-3 { 1245fab7a039SJC Kuo status = "disabled"; 1246fab7a039SJC Kuo }; 1247fab7a039SJC Kuo 1248fab7a039SJC Kuo usb3-0 { 1249fab7a039SJC Kuo status = "disabled"; 1250fab7a039SJC Kuo }; 1251fab7a039SJC Kuo 1252fab7a039SJC Kuo usb3-1 { 1253fab7a039SJC Kuo status = "disabled"; 1254fab7a039SJC Kuo }; 1255fab7a039SJC Kuo 1256fab7a039SJC Kuo usb3-2 { 1257fab7a039SJC Kuo status = "disabled"; 1258fab7a039SJC Kuo }; 1259fab7a039SJC Kuo 1260fab7a039SJC Kuo usb3-3 { 1261fab7a039SJC Kuo status = "disabled"; 1262fab7a039SJC Kuo }; 1263fab7a039SJC Kuo }; 1264fab7a039SJC Kuo }; 1265fab7a039SJC Kuo 1266bc8788b2SNagarjuna Kristam usb@3550000 { 1267bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 12682838cfddSThierry Reding reg = <0x0 0x03550000 0x0 0x8000>, 12692838cfddSThierry Reding <0x0 0x03558000 0x0 0x1000>; 1270bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1271bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1272bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1273bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1274bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1275bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1276bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1277c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1278c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1279c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1280c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1281bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1282bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1283bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1284bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1285f19bb95dSJon Hunter dma-coherent; 1286bc8788b2SNagarjuna Kristam status = "disabled"; 1287bc8788b2SNagarjuna Kristam }; 1288bc8788b2SNagarjuna Kristam 1289fab7a039SJC Kuo usb@3610000 { 1290fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 12912838cfddSThierry Reding reg = <0x0 0x03610000 0x0 0x40000>, 12922838cfddSThierry Reding <0x0 0x03600000 0x0 0x10000>; 1293fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1294fab7a039SJC Kuo 1295fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1296a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1297fab7a039SJC Kuo 1298fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1299fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1300fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1301fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1302fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1303fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1304fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1305fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1306fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1307fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1308fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1309fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1310fab7a039SJC Kuo "pll_e"; 1311c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1312c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1313c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1314c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1315fab7a039SJC Kuo 1316fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1317fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1318fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1319fab7a039SJC Kuo 1320fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1321fab7a039SJC Kuo status = "disabled"; 1322fab7a039SJC Kuo }; 1323fab7a039SJC Kuo 132409903c5eSJC Kuo fuse@3820000 { 132509903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 13262838cfddSThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 132709903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 132809903c5eSJC Kuo clock-names = "fuse"; 132909903c5eSJC Kuo }; 133009903c5eSJC Kuo 13315425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13325425fb15SMikko Perttunen compatible = "arm,gic-400"; 13335425fb15SMikko Perttunen #interrupt-cells = <3>; 13345425fb15SMikko Perttunen interrupt-controller; 13352838cfddSThierry Reding reg = <0x0 0x03881000 0x0 0x1000>, 13362838cfddSThierry Reding <0x0 0x03882000 0x0 0x2000>, 13372838cfddSThierry Reding <0x0 0x03884000 0x0 0x2000>, 13382838cfddSThierry Reding <0x0 0x03886000 0x0 0x2000>; 13395425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13405425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13415425fb15SMikko Perttunen interrupt-parent = <&gic>; 13425425fb15SMikko Perttunen }; 13435425fb15SMikko Perttunen 1344badb80beSThierry Reding cec@3960000 { 1345badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 13462838cfddSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 1347badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1348badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1349badb80beSThierry Reding clock-names = "cec"; 1350badb80beSThierry Reding status = "disabled"; 1351badb80beSThierry Reding }; 1352badb80beSThierry Reding 13538fbd2d11SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 13548fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 13552838cfddSThierry Reding reg = <0x0 0x3aa0000 0x0 0x10000>; 13568fbd2d11SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 13578fbd2d11SDipen Patel nvidia,int-threshold = <1>; 13588fbd2d11SDipen Patel nvidia,slices = <11>; 13598fbd2d11SDipen Patel #timestamp-cells = <1>; 13608fbd2d11SDipen Patel status = "okay"; 13618fbd2d11SDipen Patel }; 13628fbd2d11SDipen Patel 13635425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1364cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13652838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 1366a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1367a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1368a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1369a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1370a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1371a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1372a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1373a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1374a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1375a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1376a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1377a38570c2SMikko Perttunen "shared7"; 1378a38570c2SMikko Perttunen #mbox-cells = <2>; 1379a38570c2SMikko Perttunen }; 1380a38570c2SMikko Perttunen 13812602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13822602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13832838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 13842602c32fSVidya Sagar reg-names = "ctl"; 13852602c32fSVidya Sagar 13862602c32fSVidya Sagar #phy-cells = <0>; 13872602c32fSVidya Sagar }; 13882602c32fSVidya Sagar 13892602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 13902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13912838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 13922602c32fSVidya Sagar reg-names = "ctl"; 13932602c32fSVidya Sagar 13942602c32fSVidya Sagar #phy-cells = <0>; 13952602c32fSVidya Sagar }; 13962602c32fSVidya Sagar 13972602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 13982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13992838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 14002602c32fSVidya Sagar reg-names = "ctl"; 14012602c32fSVidya Sagar 14022602c32fSVidya Sagar #phy-cells = <0>; 14032602c32fSVidya Sagar }; 14042602c32fSVidya Sagar 14052602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14072838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 14082602c32fSVidya Sagar reg-names = "ctl"; 14092602c32fSVidya Sagar 14102602c32fSVidya Sagar #phy-cells = <0>; 14112602c32fSVidya Sagar }; 14122602c32fSVidya Sagar 14132602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14152838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 14162602c32fSVidya Sagar reg-names = "ctl"; 14172602c32fSVidya Sagar 14182602c32fSVidya Sagar #phy-cells = <0>; 14192602c32fSVidya Sagar }; 14202602c32fSVidya Sagar 14212602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14232838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 14242602c32fSVidya Sagar reg-names = "ctl"; 14252602c32fSVidya Sagar 14262602c32fSVidya Sagar #phy-cells = <0>; 14272602c32fSVidya Sagar }; 14282602c32fSVidya Sagar 14292602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14312838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 14322602c32fSVidya Sagar reg-names = "ctl"; 14332602c32fSVidya Sagar 14342602c32fSVidya Sagar #phy-cells = <0>; 14352602c32fSVidya Sagar }; 14362602c32fSVidya Sagar 14372602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14392838cfddSThierry Reding reg = <0x0 0x03e80000 0x0 0x10000>; 14402602c32fSVidya Sagar reg-names = "ctl"; 14412602c32fSVidya Sagar 14422602c32fSVidya Sagar #phy-cells = <0>; 14432602c32fSVidya Sagar }; 14442602c32fSVidya Sagar 14452602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14472838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 14482602c32fSVidya Sagar reg-names = "ctl"; 14492602c32fSVidya Sagar 14502602c32fSVidya Sagar #phy-cells = <0>; 14512602c32fSVidya Sagar }; 14522602c32fSVidya Sagar 14532602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14552838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 14562602c32fSVidya Sagar reg-names = "ctl"; 14572602c32fSVidya Sagar 14582602c32fSVidya Sagar #phy-cells = <0>; 14592602c32fSVidya Sagar }; 14602602c32fSVidya Sagar 14612602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14622602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14632838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 14642602c32fSVidya Sagar reg-names = "ctl"; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar #phy-cells = <0>; 14672602c32fSVidya Sagar }; 14682602c32fSVidya Sagar 14692602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14702602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14712838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 14722602c32fSVidya Sagar reg-names = "ctl"; 14732602c32fSVidya Sagar 14742602c32fSVidya Sagar #phy-cells = <0>; 14752602c32fSVidya Sagar }; 14762602c32fSVidya Sagar 14772602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14782602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14792838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 14802602c32fSVidya Sagar reg-names = "ctl"; 14812602c32fSVidya Sagar 14822602c32fSVidya Sagar #phy-cells = <0>; 14832602c32fSVidya Sagar }; 14842602c32fSVidya Sagar 14852602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14862602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14872838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 14882602c32fSVidya Sagar reg-names = "ctl"; 14892602c32fSVidya Sagar 14902602c32fSVidya Sagar #phy-cells = <0>; 14912602c32fSVidya Sagar }; 14922602c32fSVidya Sagar 14932602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 14942602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14952838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 14962602c32fSVidya Sagar reg-names = "ctl"; 14972602c32fSVidya Sagar 14982602c32fSVidya Sagar #phy-cells = <0>; 14992602c32fSVidya Sagar }; 15002602c32fSVidya Sagar 15012602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 15022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15032838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 15042602c32fSVidya Sagar reg-names = "ctl"; 15052602c32fSVidya Sagar 15062602c32fSVidya Sagar #phy-cells = <0>; 15072602c32fSVidya Sagar }; 15082602c32fSVidya Sagar 15092602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15112838cfddSThierry Reding reg = <0x0 0x03f10000 0x0 0x10000>; 15122602c32fSVidya Sagar reg-names = "ctl"; 15132602c32fSVidya Sagar 15142602c32fSVidya Sagar #phy-cells = <0>; 15152602c32fSVidya Sagar }; 15162602c32fSVidya Sagar 15172602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15192838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 15202602c32fSVidya Sagar reg-names = "ctl"; 15212602c32fSVidya Sagar 15222602c32fSVidya Sagar #phy-cells = <0>; 15232602c32fSVidya Sagar }; 15242602c32fSVidya Sagar 15252602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15272838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 15282602c32fSVidya Sagar reg-names = "ctl"; 15292602c32fSVidya Sagar 15302602c32fSVidya Sagar #phy-cells = <0>; 15312602c32fSVidya Sagar }; 15322602c32fSVidya Sagar 15332602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15352838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 15362602c32fSVidya Sagar reg-names = "ctl"; 15372602c32fSVidya Sagar 15382602c32fSVidya Sagar #phy-cells = <0>; 15392602c32fSVidya Sagar }; 15402602c32fSVidya Sagar 1541a47e173eSSumit Gupta sce-noc@b600000 { 1542a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 15432838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x1000>; 1544a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1545a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1546a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1547a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1548a47e173eSSumit Gupta status = "okay"; 1549a47e173eSSumit Gupta }; 1550a47e173eSSumit Gupta 1551a47e173eSSumit Gupta rce-noc@be00000 { 1552a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 15532838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x1000>; 1554a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1555a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1556a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1557a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1558a47e173eSSumit Gupta status = "okay"; 1559a47e173eSSumit Gupta }; 1560a47e173eSSumit Gupta 1561a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1562cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15632838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 1564a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1565a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1566a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1567a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1568a38570c2SMikko Perttunen /* 1569a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1570a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1571a38570c2SMikko Perttunen */ 1572a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15735425fb15SMikko Perttunen #mbox-cells = <2>; 15745425fb15SMikko Perttunen }; 15755425fb15SMikko Perttunen 15768fbd2d11SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 15778fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 15782838cfddSThierry Reding reg = <0x0 0xc1e0000 0x0 0x10000>; 15798fbd2d11SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 15808fbd2d11SDipen Patel nvidia,int-threshold = <1>; 15818fbd2d11SDipen Patel nvidia,slices = <3>; 15828fbd2d11SDipen Patel #timestamp-cells = <1>; 15838fbd2d11SDipen Patel status = "okay"; 15848fbd2d11SDipen Patel }; 15858fbd2d11SDipen Patel 15865425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1587d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15882838cfddSThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 15895425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 15905425fb15SMikko Perttunen #address-cells = <1>; 15915425fb15SMikko Perttunen #size-cells = <0>; 15925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 15935425fb15SMikko Perttunen clock-names = "div-clk"; 15945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 15955425fb15SMikko Perttunen reset-names = "i2c"; 15968e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 15978e442805SAkhil R dma-names = "rx", "tx"; 15985425fb15SMikko Perttunen status = "disabled"; 15995425fb15SMikko Perttunen }; 16005425fb15SMikko Perttunen 16015425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1602d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 16032838cfddSThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 16045425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16055425fb15SMikko Perttunen #address-cells = <1>; 16065425fb15SMikko Perttunen #size-cells = <0>; 16075425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16085425fb15SMikko Perttunen clock-names = "div-clk"; 16095425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16105425fb15SMikko Perttunen reset-names = "i2c"; 16118e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16128e442805SAkhil R dma-names = "rx", "tx"; 16135425fb15SMikko Perttunen status = "disabled"; 16145425fb15SMikko Perttunen }; 16155425fb15SMikko Perttunen 16165425fb15SMikko Perttunen uartc: serial@c280000 { 16175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16182838cfddSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 16195425fb15SMikko Perttunen reg-shift = <2>; 16205425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16225425fb15SMikko Perttunen clock-names = "serial"; 16235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16245425fb15SMikko Perttunen reset-names = "serial"; 16255425fb15SMikko Perttunen status = "disabled"; 16265425fb15SMikko Perttunen }; 16275425fb15SMikko Perttunen 16285425fb15SMikko Perttunen uartg: serial@c290000 { 16295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16302838cfddSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 16315425fb15SMikko Perttunen reg-shift = <2>; 16325425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16345425fb15SMikko Perttunen clock-names = "serial"; 16355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16365425fb15SMikko Perttunen reset-names = "serial"; 16375425fb15SMikko Perttunen status = "disabled"; 16385425fb15SMikko Perttunen }; 16395425fb15SMikko Perttunen 164037e5a31dSThierry Reding rtc: rtc@c2a0000 { 164137e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 16422838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 164337e5a31dSThierry Reding interrupt-parent = <&pmc>; 164437e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 164537e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 164637e5a31dSThierry Reding clock-names = "rtc"; 164737e5a31dSThierry Reding status = "disabled"; 164837e5a31dSThierry Reding }; 164937e5a31dSThierry Reding 16504d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16514d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16524d286331SThierry Reding reg-names = "security", "gpio"; 16532838cfddSThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 16542838cfddSThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 16550a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16560a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16570a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16580a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16594d286331SThierry Reding gpio-controller; 16604d286331SThierry Reding #gpio-cells = <2>; 16614d286331SThierry Reding interrupt-controller; 16624d286331SThierry Reding #interrupt-cells = <2>; 1663979ac5efSThierry Reding gpio-ranges = <&pinmux_aon 0 0 30>; 16646f380a4eSThierry Reding }; 16656f380a4eSThierry Reding 16666f380a4eSThierry Reding pinmux_aon: pinmux@c300000 { 16676f380a4eSThierry Reding compatible = "nvidia,tegra194-pinmux-aon"; 16682838cfddSThierry Reding reg = <0x0 0xc300000 0x0 0x4000>; 16696f380a4eSThierry Reding 16706f380a4eSThierry Reding status = "okay"; 16714d286331SThierry Reding }; 16724d286331SThierry Reding 16736a574ec7SThierry Reding pwm4: pwm@c340000 { 16746a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16756a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16762838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 16776a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16786a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16796a574ec7SThierry Reding reset-names = "pwm"; 16806a574ec7SThierry Reding status = "disabled"; 16816a574ec7SThierry Reding #pwm-cells = <2>; 16826a574ec7SThierry Reding }; 16836a574ec7SThierry Reding 168438ecf1e5SThierry Reding pmc: pmc@c360000 { 16855425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 16862838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 16872838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 16882838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 16892838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 16902838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 16915425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 169238ecf1e5SThierry Reding 169338ecf1e5SThierry Reding #interrupt-cells = <2>; 169438ecf1e5SThierry Reding interrupt-controller; 1695ff21087eSPrathamesh Shete 1696ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1697ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1698ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1699ff21087eSPrathamesh Shete }; 170079ed18d9SThierry Reding 170179ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 170279ed18d9SThierry Reding pins = "sdmmc1-hv"; 1703ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1704ff21087eSPrathamesh Shete }; 1705ff21087eSPrathamesh Shete 1706ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1707ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1708ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1709ff21087eSPrathamesh Shete }; 1710ff21087eSPrathamesh Shete 171179ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 171279ed18d9SThierry Reding pins = "sdmmc3-hv"; 171379ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 171479ed18d9SThierry Reding }; 17155425fb15SMikko Perttunen }; 17163db6d3baSThierry Reding 1717a47e173eSSumit Gupta aon-noc@c600000 { 1718a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 17192838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x1000>; 1720a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1721a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1722a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1723a47e173eSSumit Gupta status = "okay"; 1724a47e173eSSumit Gupta }; 1725a47e173eSSumit Gupta 1726a47e173eSSumit Gupta bpmp-noc@d600000 { 1727a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 17282838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x1000>; 1729a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1730a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1731a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1732a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1733a47e173eSSumit Gupta status = "okay"; 1734a47e173eSSumit Gupta }; 1735a47e173eSSumit Gupta 1736e762232fSJon Hunter iommu@10000000 { 1737e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 17382838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x800000>; 1739e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1804e762232fSJon Hunter stream-match-mask = <0x7f80>; 1805e762232fSJon Hunter #global-interrupts = <1>; 1806e762232fSJon Hunter #iommu-cells = <1>; 1807e762232fSJon Hunter 1808e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1809ebea268eSJon Hunter status = "disabled"; 1810e762232fSJon Hunter }; 1811e762232fSJon Hunter 1812c7289b1cSThierry Reding smmu: iommu@12000000 { 1813c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 18142838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x800000>, 18152838cfddSThierry Reding <0x0 0x11000000 0x0 0x800000>; 1816c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1818c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1882c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1883c7289b1cSThierry Reding #global-interrupts = <2>; 1884c7289b1cSThierry Reding #iommu-cells = <1>; 1885c7289b1cSThierry Reding 1886c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1887c7289b1cSThierry Reding status = "okay"; 1888c7289b1cSThierry Reding }; 1889c7289b1cSThierry Reding 18903db6d3baSThierry Reding host1x@13e00000 { 1891ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 18922838cfddSThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 18932838cfddSThierry Reding <0x0 0x13e10000 0x0 0x10000>; 18943db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 18953db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 18963db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1897052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 18983db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 18993db6d3baSThierry Reding clock-names = "host1x"; 19003db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 19013db6d3baSThierry Reding reset-names = "host1x"; 19023db6d3baSThierry Reding 19032838cfddSThierry Reding #address-cells = <2>; 19042838cfddSThierry Reding #size-cells = <2>; 19052838cfddSThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 19063db6d3baSThierry Reding 1907d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1908d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1909c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 1910361238cdSMikko Perttunen dma-coherent; 19113db6d3baSThierry Reding 1912e30cf101SMikko Perttunen /* Context isolation domains */ 1913b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1914b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1915b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1916b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1917b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1918b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1919b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1920b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1921e30cf101SMikko Perttunen 192278a05873SMikko Perttunen nvdec@15140000 { 192378a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 19242838cfddSThierry Reding reg = <0x0 0x15140000 0x0 0x00040000>; 192578a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 192678a05873SMikko Perttunen clock-names = "nvdec"; 192778a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 192878a05873SMikko Perttunen reset-names = "nvdec"; 192978a05873SMikko Perttunen 193078a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 193178a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 193278a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 193378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 193478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 193578a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 193678a05873SMikko Perttunen dma-coherent; 193778a05873SMikko Perttunen 193878a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 193978a05873SMikko Perttunen }; 194078a05873SMikko Perttunen 19413db6d3baSThierry Reding display-hub@15200000 { 1942aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 19432838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x00040000>; 19443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19453db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19463db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19473db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19483db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19493db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19503db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19513db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19523db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19533db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19553db6d3baSThierry Reding clock-names = "disp", "hub"; 19563db6d3baSThierry Reding status = "disabled"; 19573db6d3baSThierry Reding 19583db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19593db6d3baSThierry Reding 19602838cfddSThierry Reding #address-cells = <2>; 19612838cfddSThierry Reding #size-cells = <2>; 19622838cfddSThierry Reding ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 19633db6d3baSThierry Reding 19643db6d3baSThierry Reding display@15200000 { 19653db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19662838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x10000>; 19673db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19683db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19693db6d3baSThierry Reding clock-names = "dc"; 19703db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19713db6d3baSThierry Reding reset-names = "dc"; 19723db6d3baSThierry Reding 19733db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1974d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1975d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1976d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19773db6d3baSThierry Reding 19783db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19793db6d3baSThierry Reding nvidia,head = <0>; 19803db6d3baSThierry Reding }; 19813db6d3baSThierry Reding 19823db6d3baSThierry Reding display@15210000 { 19833db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19842838cfddSThierry Reding reg = <0x0 0x15210000 0x0 0x10000>; 19853db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19863db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 19873db6d3baSThierry Reding clock-names = "dc"; 19883db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 19893db6d3baSThierry Reding reset-names = "dc"; 19903db6d3baSThierry Reding 19913db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1992d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1993d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1994d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19953db6d3baSThierry Reding 19963db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19973db6d3baSThierry Reding nvidia,head = <1>; 19983db6d3baSThierry Reding }; 19993db6d3baSThierry Reding 20003db6d3baSThierry Reding display@15220000 { 20013db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20022838cfddSThierry Reding reg = <0x0 0x15220000 0x0 0x10000>; 20033db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 20043db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 20053db6d3baSThierry Reding clock-names = "dc"; 20063db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 20073db6d3baSThierry Reding reset-names = "dc"; 20083db6d3baSThierry Reding 20093db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2010d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2011d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2012d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20133db6d3baSThierry Reding 20143db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20153db6d3baSThierry Reding nvidia,head = <2>; 20163db6d3baSThierry Reding }; 20173db6d3baSThierry Reding 20183db6d3baSThierry Reding display@15230000 { 20193db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20202838cfddSThierry Reding reg = <0x0 0x15230000 0x0 0x10000>; 20213db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20223db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20233db6d3baSThierry Reding clock-names = "dc"; 20243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20253db6d3baSThierry Reding reset-names = "dc"; 20263db6d3baSThierry Reding 20273db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2028d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2029d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2030d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20313db6d3baSThierry Reding 20323db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20333db6d3baSThierry Reding nvidia,head = <3>; 20343db6d3baSThierry Reding }; 20353db6d3baSThierry Reding }; 20363db6d3baSThierry Reding 20378d424ec2SThierry Reding vic@15340000 { 20388d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 20392838cfddSThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 20408d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20418d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20428d424ec2SThierry Reding clock-names = "vic"; 20438d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20448d424ec2SThierry Reding reset-names = "vic"; 20458d424ec2SThierry Reding 20468d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2047d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2048d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2049d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2050c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2051a52280c8SJon Hunter dma-coherent; 20528d424ec2SThierry Reding }; 20538d424ec2SThierry Reding 2054f7eb2785SJon Hunter nvjpg@15380000 { 2055f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 20562838cfddSThierry Reding reg = <0x0 0x15380000 0x0 0x40000>; 2057f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2058f7eb2785SJon Hunter clock-names = "nvjpg"; 2059f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2060f7eb2785SJon Hunter reset-names = "nvjpg"; 2061f7eb2785SJon Hunter 2062f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2063f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2064f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2065f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2066f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2067f7eb2785SJon Hunter dma-coherent; 2068f7eb2785SJon Hunter }; 2069f7eb2785SJon Hunter 207078a05873SMikko Perttunen nvdec@15480000 { 207178a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 20722838cfddSThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 207378a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 207478a05873SMikko Perttunen clock-names = "nvdec"; 207578a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 207678a05873SMikko Perttunen reset-names = "nvdec"; 207778a05873SMikko Perttunen 207878a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 207978a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 208078a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 208178a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 208278a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 208378a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 208478a05873SMikko Perttunen dma-coherent; 208578a05873SMikko Perttunen 208678a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 208778a05873SMikko Perttunen }; 208878a05873SMikko Perttunen 2089f7eb2785SJon Hunter nvenc@154c0000 { 2090f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 20912838cfddSThierry Reding reg = <0x0 0x154c0000 0x0 0x40000>; 2092f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2093f7eb2785SJon Hunter clock-names = "nvenc"; 2094f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2095f7eb2785SJon Hunter reset-names = "nvenc"; 2096f7eb2785SJon Hunter 2097f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2098f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2099f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2100f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2101f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2102f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2103f7eb2785SJon Hunter dma-coherent; 2104f7eb2785SJon Hunter 2105f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2106f7eb2785SJon Hunter }; 2107f7eb2785SJon Hunter 21083db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21093db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21102838cfddSThierry Reding reg = <0x0 0x155c0000 0x0 0x10000>; 21113db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21123db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21133db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21143db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21153db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21163db6d3baSThierry Reding reset-names = "dpaux"; 21173db6d3baSThierry Reding status = "disabled"; 21183db6d3baSThierry Reding 21193db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21203db6d3baSThierry Reding 21213db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21223db6d3baSThierry Reding groups = "dpaux-io"; 21233db6d3baSThierry Reding function = "aux"; 21243db6d3baSThierry Reding }; 21253db6d3baSThierry Reding 21263db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21273db6d3baSThierry Reding groups = "dpaux-io"; 21283db6d3baSThierry Reding function = "i2c"; 21293db6d3baSThierry Reding }; 21303db6d3baSThierry Reding 21313db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21323db6d3baSThierry Reding groups = "dpaux-io"; 21333db6d3baSThierry Reding function = "off"; 21343db6d3baSThierry Reding }; 21353db6d3baSThierry Reding 21363db6d3baSThierry Reding i2c-bus { 21373db6d3baSThierry Reding #address-cells = <1>; 21383db6d3baSThierry Reding #size-cells = <0>; 21393db6d3baSThierry Reding }; 21403db6d3baSThierry Reding }; 21413db6d3baSThierry Reding 21423db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21433db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21442838cfddSThierry Reding reg = <0x0 0x155d0000 0x0 0x10000>; 21453db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21463db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21473db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21483db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21493db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21503db6d3baSThierry Reding reset-names = "dpaux"; 21513db6d3baSThierry Reding status = "disabled"; 21523db6d3baSThierry Reding 21533db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21543db6d3baSThierry Reding 21553db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21563db6d3baSThierry Reding groups = "dpaux-io"; 21573db6d3baSThierry Reding function = "aux"; 21583db6d3baSThierry Reding }; 21593db6d3baSThierry Reding 21603db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21613db6d3baSThierry Reding groups = "dpaux-io"; 21623db6d3baSThierry Reding function = "i2c"; 21633db6d3baSThierry Reding }; 21643db6d3baSThierry Reding 21653db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21663db6d3baSThierry Reding groups = "dpaux-io"; 21673db6d3baSThierry Reding function = "off"; 21683db6d3baSThierry Reding }; 21693db6d3baSThierry Reding 21703db6d3baSThierry Reding i2c-bus { 21713db6d3baSThierry Reding #address-cells = <1>; 21723db6d3baSThierry Reding #size-cells = <0>; 21733db6d3baSThierry Reding }; 21743db6d3baSThierry Reding }; 21753db6d3baSThierry Reding 21763db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21773db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21782838cfddSThierry Reding reg = <0x0 0x155e0000 0x0 0x10000>; 21793db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21823db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21843db6d3baSThierry Reding reset-names = "dpaux"; 21853db6d3baSThierry Reding status = "disabled"; 21863db6d3baSThierry Reding 21873db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21883db6d3baSThierry Reding 21893db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 21903db6d3baSThierry Reding groups = "dpaux-io"; 21913db6d3baSThierry Reding function = "aux"; 21923db6d3baSThierry Reding }; 21933db6d3baSThierry Reding 21943db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 21953db6d3baSThierry Reding groups = "dpaux-io"; 21963db6d3baSThierry Reding function = "i2c"; 21973db6d3baSThierry Reding }; 21983db6d3baSThierry Reding 21993db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 22003db6d3baSThierry Reding groups = "dpaux-io"; 22013db6d3baSThierry Reding function = "off"; 22023db6d3baSThierry Reding }; 22033db6d3baSThierry Reding 22043db6d3baSThierry Reding i2c-bus { 22053db6d3baSThierry Reding #address-cells = <1>; 22063db6d3baSThierry Reding #size-cells = <0>; 22073db6d3baSThierry Reding }; 22083db6d3baSThierry Reding }; 22093db6d3baSThierry Reding 22103db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22113db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 22122838cfddSThierry Reding reg = <0x0 0x155f0000 0x0 0x10000>; 22133db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22163db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22183db6d3baSThierry Reding reset-names = "dpaux"; 22193db6d3baSThierry Reding status = "disabled"; 22203db6d3baSThierry Reding 22213db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22223db6d3baSThierry Reding 22233db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22243db6d3baSThierry Reding groups = "dpaux-io"; 22253db6d3baSThierry Reding function = "aux"; 22263db6d3baSThierry Reding }; 22273db6d3baSThierry Reding 22283db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22293db6d3baSThierry Reding groups = "dpaux-io"; 22303db6d3baSThierry Reding function = "i2c"; 22313db6d3baSThierry Reding }; 22323db6d3baSThierry Reding 22333db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22343db6d3baSThierry Reding groups = "dpaux-io"; 22353db6d3baSThierry Reding function = "off"; 22363db6d3baSThierry Reding }; 22373db6d3baSThierry Reding 22383db6d3baSThierry Reding i2c-bus { 22393db6d3baSThierry Reding #address-cells = <1>; 22403db6d3baSThierry Reding #size-cells = <0>; 22413db6d3baSThierry Reding }; 22423db6d3baSThierry Reding }; 22433db6d3baSThierry Reding 2244f7eb2785SJon Hunter nvenc@15a80000 { 2245f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 22462838cfddSThierry Reding reg = <0x0 0x15a80000 0x0 0x00040000>; 2247f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2248f7eb2785SJon Hunter clock-names = "nvenc"; 2249f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2250f7eb2785SJon Hunter reset-names = "nvenc"; 2251f7eb2785SJon Hunter 2252f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2253f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2254f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2255f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2256f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2257f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2258f7eb2785SJon Hunter dma-coherent; 2259f7eb2785SJon Hunter 2260f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2261f7eb2785SJon Hunter }; 2262f7eb2785SJon Hunter 22633db6d3baSThierry Reding sor0: sor@15b00000 { 22643db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22652838cfddSThierry Reding reg = <0x0 0x15b00000 0x0 0x40000>; 22663db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22673db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22733db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22743db6d3baSThierry Reding "pad"; 22753db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22763db6d3baSThierry Reding reset-names = "sor"; 22773db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22783db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22793db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22803db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22813db6d3baSThierry Reding status = "disabled"; 22823db6d3baSThierry Reding 22833db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22843db6d3baSThierry Reding nvidia,interface = <0>; 22853db6d3baSThierry Reding }; 22863db6d3baSThierry Reding 22873db6d3baSThierry Reding sor1: sor@15b40000 { 22883db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22892838cfddSThierry Reding reg = <0x0 0x15b40000 0x0 0x40000>; 22903db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 22913db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 22923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 22933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 22943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22963db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 22973db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22983db6d3baSThierry Reding "pad"; 22993db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 23003db6d3baSThierry Reding reset-names = "sor"; 23013db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 23023db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 23033db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 23043db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23053db6d3baSThierry Reding status = "disabled"; 23063db6d3baSThierry Reding 23073db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23083db6d3baSThierry Reding nvidia,interface = <1>; 23093db6d3baSThierry Reding }; 23103db6d3baSThierry Reding 23113db6d3baSThierry Reding sor2: sor@15b80000 { 23123db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23132838cfddSThierry Reding reg = <0x0 0x15b80000 0x0 0x40000>; 23143db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23153db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23163db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23203db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23213db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23223db6d3baSThierry Reding "pad"; 23233db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23243db6d3baSThierry Reding reset-names = "sor"; 23253db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23263db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23273db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23283db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23293db6d3baSThierry Reding status = "disabled"; 23303db6d3baSThierry Reding 23313db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23323db6d3baSThierry Reding nvidia,interface = <2>; 23333db6d3baSThierry Reding }; 23343db6d3baSThierry Reding 23353db6d3baSThierry Reding sor3: sor@15bc0000 { 23363db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23372838cfddSThierry Reding reg = <0x0 0x15bc0000 0x0 0x40000>; 23383db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23393db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23443db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23453db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23463db6d3baSThierry Reding "pad"; 23473db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23483db6d3baSThierry Reding reset-names = "sor"; 23493db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23503db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23513db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23523db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23533db6d3baSThierry Reding status = "disabled"; 23543db6d3baSThierry Reding 23553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23563db6d3baSThierry Reding nvidia,interface = <3>; 23573db6d3baSThierry Reding }; 23583db6d3baSThierry Reding }; 23590f134e39SThierry Reding 23602602c32fSVidya Sagar pcie@14100000 { 2361f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23622602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 236379ed18d9SThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 236479ed18d9SThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 236579ed18d9SThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 236679ed18d9SThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23672602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23682602c32fSVidya Sagar 23692602c32fSVidya Sagar status = "disabled"; 23702602c32fSVidya Sagar 23712602c32fSVidya Sagar #address-cells = <3>; 23722602c32fSVidya Sagar #size-cells = <2>; 23732602c32fSVidya Sagar device_type = "pci"; 23742602c32fSVidya Sagar num-lanes = <1>; 23752602c32fSVidya Sagar linux,pci-domain = <1>; 23762602c32fSVidya Sagar 23772602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 23782602c32fSVidya Sagar clock-names = "core"; 23792602c32fSVidya Sagar 23802602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 23812602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 23822602c32fSVidya Sagar reset-names = "apb", "core"; 23832602c32fSVidya Sagar 23842602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23852602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23862602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23872602c32fSVidya Sagar 23882602c32fSVidya Sagar #interrupt-cells = <1>; 23892602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23902602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 23912602c32fSVidya Sagar 23922602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 23932602c32fSVidya Sagar 23942602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23952602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23962602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23972602c32fSVidya Sagar 23982602c32fSVidya Sagar bus-range = <0x0 0xff>; 2399d5237c7cSThierry Reding 24008a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24018a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24028a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2403d5237c7cSThierry Reding 2404d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2405d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2406ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2407ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2408ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2409ba02920cSVidya Sagar dma-coherent; 24102602c32fSVidya Sagar }; 24112602c32fSVidya Sagar 24122602c32fSVidya Sagar pcie@14120000 { 2413f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24142602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2415644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2416644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2417644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2418644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24192602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24202602c32fSVidya Sagar 24212602c32fSVidya Sagar status = "disabled"; 24222602c32fSVidya Sagar 24232602c32fSVidya Sagar #address-cells = <3>; 24242602c32fSVidya Sagar #size-cells = <2>; 24252602c32fSVidya Sagar device_type = "pci"; 24262602c32fSVidya Sagar num-lanes = <1>; 24272602c32fSVidya Sagar linux,pci-domain = <2>; 24282602c32fSVidya Sagar 24292602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24302602c32fSVidya Sagar clock-names = "core"; 24312602c32fSVidya Sagar 24322602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24332602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24342602c32fSVidya Sagar reset-names = "apb", "core"; 24352602c32fSVidya Sagar 24362602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24372602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24382602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24392602c32fSVidya Sagar 24402602c32fSVidya Sagar #interrupt-cells = <1>; 24412602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24422602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24432602c32fSVidya Sagar 24442602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24452602c32fSVidya Sagar 24462602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24472602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24482602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24492602c32fSVidya Sagar 24502602c32fSVidya Sagar bus-range = <0x0 0xff>; 2451d5237c7cSThierry Reding 24528a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24538a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24548a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2455d5237c7cSThierry Reding 2456d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2457d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2458ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2459ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2460ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2461ba02920cSVidya Sagar dma-coherent; 24622602c32fSVidya Sagar }; 24632602c32fSVidya Sagar 24642602c32fSVidya Sagar pcie@14140000 { 2465f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24662602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2467644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2468644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2469644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2470644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24712602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24722602c32fSVidya Sagar 24732602c32fSVidya Sagar status = "disabled"; 24742602c32fSVidya Sagar 24752602c32fSVidya Sagar #address-cells = <3>; 24762602c32fSVidya Sagar #size-cells = <2>; 24772602c32fSVidya Sagar device_type = "pci"; 24782602c32fSVidya Sagar num-lanes = <1>; 24792602c32fSVidya Sagar linux,pci-domain = <3>; 24802602c32fSVidya Sagar 24812602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 24822602c32fSVidya Sagar clock-names = "core"; 24832602c32fSVidya Sagar 24842602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 24852602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 24862602c32fSVidya Sagar reset-names = "apb", "core"; 24872602c32fSVidya Sagar 24882602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24892602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24902602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24912602c32fSVidya Sagar 24922602c32fSVidya Sagar #interrupt-cells = <1>; 24932602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24942602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 24952602c32fSVidya Sagar 24962602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 24972602c32fSVidya Sagar 24982602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24992602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25002602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25012602c32fSVidya Sagar 25022602c32fSVidya Sagar bus-range = <0x0 0xff>; 2503d5237c7cSThierry Reding 25048a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25058a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25068a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2507d5237c7cSThierry Reding 2508d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2509d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2510ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2511ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2512ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2513ba02920cSVidya Sagar dma-coherent; 25142602c32fSVidya Sagar }; 25152602c32fSVidya Sagar 25162602c32fSVidya Sagar pcie@14160000 { 2517f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25182602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2519644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2520644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2521644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2522644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25232602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25242602c32fSVidya Sagar 25252602c32fSVidya Sagar status = "disabled"; 25262602c32fSVidya Sagar 25272602c32fSVidya Sagar #address-cells = <3>; 25282602c32fSVidya Sagar #size-cells = <2>; 25292602c32fSVidya Sagar device_type = "pci"; 25302602c32fSVidya Sagar num-lanes = <4>; 25312602c32fSVidya Sagar linux,pci-domain = <4>; 25322602c32fSVidya Sagar 25332602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25342602c32fSVidya Sagar clock-names = "core"; 25352602c32fSVidya Sagar 25362602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25372602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25382602c32fSVidya Sagar reset-names = "apb", "core"; 25392602c32fSVidya Sagar 25402602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25412602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25422602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25432602c32fSVidya Sagar 25442602c32fSVidya Sagar #interrupt-cells = <1>; 25452602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25462602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25472602c32fSVidya Sagar 25482602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25492602c32fSVidya Sagar 25502602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25512602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25522602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25532602c32fSVidya Sagar 25542602c32fSVidya Sagar bus-range = <0x0 0xff>; 2555d5237c7cSThierry Reding 25568a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25578a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25588a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2559d5237c7cSThierry Reding 2560d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2561d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2562ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2563ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2564ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2565ba02920cSVidya Sagar dma-coherent; 25662602c32fSVidya Sagar }; 25672602c32fSVidya Sagar 25682838cfddSThierry Reding pcie-ep@14160000 { 25692838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 25702838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 25712838cfddSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 25722838cfddSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 25732838cfddSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 25742838cfddSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25752838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25762838cfddSThierry Reding 25772838cfddSThierry Reding status = "disabled"; 25782838cfddSThierry Reding 25792838cfddSThierry Reding num-lanes = <4>; 25802838cfddSThierry Reding num-ib-windows = <2>; 25812838cfddSThierry Reding num-ob-windows = <8>; 25822838cfddSThierry Reding 25832838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25842838cfddSThierry Reding clock-names = "core"; 25852838cfddSThierry Reding 25862838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25872838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25882838cfddSThierry Reding reset-names = "apb", "core"; 25892838cfddSThierry Reding 25902838cfddSThierry Reding interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25912838cfddSThierry Reding interrupt-names = "intr"; 25922838cfddSThierry Reding 25932838cfddSThierry Reding nvidia,bpmp = <&bpmp 4>; 25942838cfddSThierry Reding 25952838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 25962838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 25972838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 25982838cfddSThierry Reding 25992838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 26002838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 26012838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 26022838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 26032838cfddSThierry Reding iommu-map-mask = <0x0>; 26042838cfddSThierry Reding dma-coherent; 26052838cfddSThierry Reding }; 26062838cfddSThierry Reding 26072602c32fSVidya Sagar pcie@14180000 { 2608f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26092602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2610644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2611644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2612644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2613644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26142602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26152602c32fSVidya Sagar 26162602c32fSVidya Sagar status = "disabled"; 26172602c32fSVidya Sagar 26182602c32fSVidya Sagar #address-cells = <3>; 26192602c32fSVidya Sagar #size-cells = <2>; 26202602c32fSVidya Sagar device_type = "pci"; 26212602c32fSVidya Sagar num-lanes = <8>; 26222602c32fSVidya Sagar linux,pci-domain = <0>; 26232602c32fSVidya Sagar 26242602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26252602c32fSVidya Sagar clock-names = "core"; 26262602c32fSVidya Sagar 26272602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26282602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26292602c32fSVidya Sagar reset-names = "apb", "core"; 26302602c32fSVidya Sagar 26312602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26322602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26332602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26342602c32fSVidya Sagar 26352602c32fSVidya Sagar #interrupt-cells = <1>; 26362602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26372602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26382602c32fSVidya Sagar 26392602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26402602c32fSVidya Sagar 26412602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26422602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26432602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26442602c32fSVidya Sagar 26452602c32fSVidya Sagar bus-range = <0x0 0xff>; 2646d5237c7cSThierry Reding 26478a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26488a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26498a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2650d5237c7cSThierry Reding 2651d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2652d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2653ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2654ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2655ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2656ba02920cSVidya Sagar dma-coherent; 26572602c32fSVidya Sagar }; 26582602c32fSVidya Sagar 26592838cfddSThierry Reding pcie-ep@14180000 { 26602838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 26612838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 26622838cfddSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 26632838cfddSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 26642838cfddSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 26652838cfddSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26662838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26672838cfddSThierry Reding 26682838cfddSThierry Reding status = "disabled"; 26692838cfddSThierry Reding 26702838cfddSThierry Reding num-lanes = <8>; 26712838cfddSThierry Reding num-ib-windows = <2>; 26722838cfddSThierry Reding num-ob-windows = <8>; 26732838cfddSThierry Reding 26742838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26752838cfddSThierry Reding clock-names = "core"; 26762838cfddSThierry Reding 26772838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26782838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26792838cfddSThierry Reding reset-names = "apb", "core"; 26802838cfddSThierry Reding 26812838cfddSThierry Reding interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26822838cfddSThierry Reding interrupt-names = "intr"; 26832838cfddSThierry Reding 26842838cfddSThierry Reding nvidia,bpmp = <&bpmp 0>; 26852838cfddSThierry Reding 26862838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 26872838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 26882838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 26892838cfddSThierry Reding 26902838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 26912838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 26922838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 26932838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 26942838cfddSThierry Reding iommu-map-mask = <0x0>; 26952838cfddSThierry Reding dma-coherent; 26962838cfddSThierry Reding }; 26972838cfddSThierry Reding 26982602c32fSVidya Sagar pcie@141a0000 { 2699f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 27002602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2701644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2702644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2703644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2704644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 27052602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 27062602c32fSVidya Sagar 27072602c32fSVidya Sagar status = "disabled"; 27082602c32fSVidya Sagar 27092602c32fSVidya Sagar #address-cells = <3>; 27102602c32fSVidya Sagar #size-cells = <2>; 27112602c32fSVidya Sagar device_type = "pci"; 27122602c32fSVidya Sagar num-lanes = <8>; 27132602c32fSVidya Sagar linux,pci-domain = <5>; 27142602c32fSVidya Sagar 2715dbb72e2cSVidya Sagar pinctrl-names = "default"; 271679ed18d9SThierry Reding pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2717dbb72e2cSVidya Sagar 2718c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2719c453cc9eSThierry Reding clock-names = "core"; 27202602c32fSVidya Sagar 27212602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27222602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27232602c32fSVidya Sagar reset-names = "apb", "core"; 27242602c32fSVidya Sagar 27252602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27262602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27272602c32fSVidya Sagar interrupt-names = "intr", "msi"; 27282602c32fSVidya Sagar 27292602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 27302602c32fSVidya Sagar 27312602c32fSVidya Sagar #interrupt-cells = <1>; 27322602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 27332602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 27342602c32fSVidya Sagar 27352602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 27362602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27372602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 27382602c32fSVidya Sagar 27392602c32fSVidya Sagar bus-range = <0x0 0xff>; 2740d5237c7cSThierry Reding 27418a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 27428a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 27438a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2744d5237c7cSThierry Reding 2745d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2746d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2747ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2748ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2749ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2750ba02920cSVidya Sagar dma-coherent; 27512602c32fSVidya Sagar }; 27522602c32fSVidya Sagar 2753b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2754bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27550c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2756644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2757644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2758644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2759644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27600c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27610c988b73SVidya Sagar 27620c988b73SVidya Sagar status = "disabled"; 27630c988b73SVidya Sagar 27640c988b73SVidya Sagar num-lanes = <8>; 27650c988b73SVidya Sagar num-ib-windows = <2>; 27660c988b73SVidya Sagar num-ob-windows = <8>; 27670c988b73SVidya Sagar 27680c988b73SVidya Sagar pinctrl-names = "default"; 276979ed18d9SThierry Reding pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 27700c988b73SVidya Sagar 27710c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 27720c988b73SVidya Sagar clock-names = "core"; 27730c988b73SVidya Sagar 27740c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27750c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27760c988b73SVidya Sagar reset-names = "apb", "core"; 27770c988b73SVidya Sagar 27780c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27790c988b73SVidya Sagar interrupt-names = "intr"; 27800c988b73SVidya Sagar 27810c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 27820c988b73SVidya Sagar 27830c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27840c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27850c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2786ba02920cSVidya Sagar 2787ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2788ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2789ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2790ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2791ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2792ba02920cSVidya Sagar dma-coherent; 27930c988b73SVidya Sagar }; 27940c988b73SVidya Sagar 27952838cfddSThierry Reding gpu@17000000 { 27962838cfddSThierry Reding compatible = "nvidia,gv11b"; 27972838cfddSThierry Reding reg = <0x0 0x17000000 0x0 0x1000000>, 27982838cfddSThierry Reding <0x0 0x18000000 0x0 0x1000000>; 27992838cfddSThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 28002838cfddSThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 28012838cfddSThierry Reding interrupt-names = "stall", "nonstall"; 28022838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 28032838cfddSThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 28042838cfddSThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 28052838cfddSThierry Reding clock-names = "gpu", "pwr", "fuse"; 28062838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 28072838cfddSThierry Reding reset-names = "gpu"; 28082838cfddSThierry Reding dma-coherent; 28092838cfddSThierry Reding 28102838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 28112838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 28122838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 28132838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 28142838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 28152838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 28162838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 28172838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 28182838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 28192838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 28202838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 28212838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 28222838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 28232838cfddSThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 28242838cfddSThierry Reding "read-1", "read-1-hp", "write-1", 28252838cfddSThierry Reding "read-2", "read-2-hp", "write-2", 28262838cfddSThierry Reding "read-3", "read-3-hp", "write-3"; 28272838cfddSThierry Reding }; 28282838cfddSThierry Reding }; 28292838cfddSThierry Reding 2830e867fe41SThierry Reding sram@40000000 { 28315425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28325425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 28332838cfddSThierry Reding 28345425fb15SMikko Perttunen #address-cells = <1>; 28355425fb15SMikko Perttunen #size-cells = <1>; 28365425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 28372838cfddSThierry Reding 283861192a9dSMikko Perttunen no-memory-wc; 28395425fb15SMikko Perttunen 2840e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28415425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28425425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28435425fb15SMikko Perttunen pool; 28445425fb15SMikko Perttunen }; 28455425fb15SMikko Perttunen 2846e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28475425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28485425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28495425fb15SMikko Perttunen pool; 28505425fb15SMikko Perttunen }; 28515425fb15SMikko Perttunen }; 28525425fb15SMikko Perttunen 28535425fb15SMikko Perttunen bpmp: bpmp { 28545425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28555425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28565425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28577fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28585425fb15SMikko Perttunen #clock-cells = <1>; 28595425fb15SMikko Perttunen #reset-cells = <1>; 28605425fb15SMikko Perttunen #power-domain-cells = <1>; 2861d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2862d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2863d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2864d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2865d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2866c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28675425fb15SMikko Perttunen 28685425fb15SMikko Perttunen bpmp_i2c: i2c { 28695425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28705425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28715425fb15SMikko Perttunen #address-cells = <1>; 28725425fb15SMikko Perttunen #size-cells = <0>; 28735425fb15SMikko Perttunen }; 28745425fb15SMikko Perttunen 28755425fb15SMikko Perttunen bpmp_thermal: thermal { 28765425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28775425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28785425fb15SMikko Perttunen }; 28795425fb15SMikko Perttunen }; 28805425fb15SMikko Perttunen 28817780a034SMikko Perttunen cpus { 2882d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2883d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28847780a034SMikko Perttunen #address-cells = <1>; 28857780a034SMikko Perttunen #size-cells = <0>; 28867780a034SMikko Perttunen 2887b45d322cSThierry Reding cpu0_0: cpu@0 { 288831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28897780a034SMikko Perttunen device_type = "cpu"; 2890b45d322cSThierry Reding reg = <0x000>; 28917780a034SMikko Perttunen enable-method = "psci"; 2892b45d322cSThierry Reding i-cache-size = <131072>; 2893b45d322cSThierry Reding i-cache-line-size = <64>; 2894b45d322cSThierry Reding i-cache-sets = <512>; 2895b45d322cSThierry Reding d-cache-size = <65536>; 2896b45d322cSThierry Reding d-cache-line-size = <64>; 2897b45d322cSThierry Reding d-cache-sets = <256>; 2898b45d322cSThierry Reding next-level-cache = <&l2c_0>; 28997780a034SMikko Perttunen }; 29007780a034SMikko Perttunen 2901b45d322cSThierry Reding cpu0_1: cpu@1 { 290231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29037780a034SMikko Perttunen device_type = "cpu"; 2904b45d322cSThierry Reding reg = <0x001>; 29057780a034SMikko Perttunen enable-method = "psci"; 2906b45d322cSThierry Reding i-cache-size = <131072>; 2907b45d322cSThierry Reding i-cache-line-size = <64>; 2908b45d322cSThierry Reding i-cache-sets = <512>; 2909b45d322cSThierry Reding d-cache-size = <65536>; 2910b45d322cSThierry Reding d-cache-line-size = <64>; 2911b45d322cSThierry Reding d-cache-sets = <256>; 2912b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29137780a034SMikko Perttunen }; 29147780a034SMikko Perttunen 2915b45d322cSThierry Reding cpu1_0: cpu@100 { 291631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29177780a034SMikko Perttunen device_type = "cpu"; 29187780a034SMikko Perttunen reg = <0x100>; 29197780a034SMikko Perttunen enable-method = "psci"; 2920b45d322cSThierry Reding i-cache-size = <131072>; 2921b45d322cSThierry Reding i-cache-line-size = <64>; 2922b45d322cSThierry Reding i-cache-sets = <512>; 2923b45d322cSThierry Reding d-cache-size = <65536>; 2924b45d322cSThierry Reding d-cache-line-size = <64>; 2925b45d322cSThierry Reding d-cache-sets = <256>; 2926b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29277780a034SMikko Perttunen }; 29287780a034SMikko Perttunen 2929b45d322cSThierry Reding cpu1_1: cpu@101 { 293031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29317780a034SMikko Perttunen device_type = "cpu"; 29327780a034SMikko Perttunen reg = <0x101>; 29337780a034SMikko Perttunen enable-method = "psci"; 2934b45d322cSThierry Reding i-cache-size = <131072>; 2935b45d322cSThierry Reding i-cache-line-size = <64>; 2936b45d322cSThierry Reding i-cache-sets = <512>; 2937b45d322cSThierry Reding d-cache-size = <65536>; 2938b45d322cSThierry Reding d-cache-line-size = <64>; 2939b45d322cSThierry Reding d-cache-sets = <256>; 2940b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29417780a034SMikko Perttunen }; 29427780a034SMikko Perttunen 2943b45d322cSThierry Reding cpu2_0: cpu@200 { 294431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29457780a034SMikko Perttunen device_type = "cpu"; 29467780a034SMikko Perttunen reg = <0x200>; 29477780a034SMikko Perttunen enable-method = "psci"; 2948b45d322cSThierry Reding i-cache-size = <131072>; 2949b45d322cSThierry Reding i-cache-line-size = <64>; 2950b45d322cSThierry Reding i-cache-sets = <512>; 2951b45d322cSThierry Reding d-cache-size = <65536>; 2952b45d322cSThierry Reding d-cache-line-size = <64>; 2953b45d322cSThierry Reding d-cache-sets = <256>; 2954b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29557780a034SMikko Perttunen }; 29567780a034SMikko Perttunen 2957b45d322cSThierry Reding cpu2_1: cpu@201 { 295831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29597780a034SMikko Perttunen device_type = "cpu"; 29607780a034SMikko Perttunen reg = <0x201>; 29617780a034SMikko Perttunen enable-method = "psci"; 2962b45d322cSThierry Reding i-cache-size = <131072>; 2963b45d322cSThierry Reding i-cache-line-size = <64>; 2964b45d322cSThierry Reding i-cache-sets = <512>; 2965b45d322cSThierry Reding d-cache-size = <65536>; 2966b45d322cSThierry Reding d-cache-line-size = <64>; 2967b45d322cSThierry Reding d-cache-sets = <256>; 2968b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29697780a034SMikko Perttunen }; 29707780a034SMikko Perttunen 2971b45d322cSThierry Reding cpu3_0: cpu@300 { 297231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29737780a034SMikko Perttunen device_type = "cpu"; 2974b45d322cSThierry Reding reg = <0x300>; 29757780a034SMikko Perttunen enable-method = "psci"; 2976b45d322cSThierry Reding i-cache-size = <131072>; 2977b45d322cSThierry Reding i-cache-line-size = <64>; 2978b45d322cSThierry Reding i-cache-sets = <512>; 2979b45d322cSThierry Reding d-cache-size = <65536>; 2980b45d322cSThierry Reding d-cache-line-size = <64>; 2981b45d322cSThierry Reding d-cache-sets = <256>; 2982b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29837780a034SMikko Perttunen }; 29847780a034SMikko Perttunen 2985b45d322cSThierry Reding cpu3_1: cpu@301 { 298631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29877780a034SMikko Perttunen device_type = "cpu"; 2988b45d322cSThierry Reding reg = <0x301>; 29897780a034SMikko Perttunen enable-method = "psci"; 2990b45d322cSThierry Reding i-cache-size = <131072>; 2991b45d322cSThierry Reding i-cache-line-size = <64>; 2992b45d322cSThierry Reding i-cache-sets = <512>; 2993b45d322cSThierry Reding d-cache-size = <65536>; 2994b45d322cSThierry Reding d-cache-line-size = <64>; 2995b45d322cSThierry Reding d-cache-sets = <256>; 2996b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2997b45d322cSThierry Reding }; 2998b45d322cSThierry Reding 2999b45d322cSThierry Reding cpu-map { 3000b45d322cSThierry Reding cluster0 { 3001b45d322cSThierry Reding core0 { 3002b45d322cSThierry Reding cpu = <&cpu0_0>; 3003b45d322cSThierry Reding }; 3004b45d322cSThierry Reding 3005b45d322cSThierry Reding core1 { 3006b45d322cSThierry Reding cpu = <&cpu0_1>; 3007b45d322cSThierry Reding }; 3008b45d322cSThierry Reding }; 3009b45d322cSThierry Reding 3010b45d322cSThierry Reding cluster1 { 3011b45d322cSThierry Reding core0 { 3012b45d322cSThierry Reding cpu = <&cpu1_0>; 3013b45d322cSThierry Reding }; 3014b45d322cSThierry Reding 3015b45d322cSThierry Reding core1 { 3016b45d322cSThierry Reding cpu = <&cpu1_1>; 3017b45d322cSThierry Reding }; 3018b45d322cSThierry Reding }; 3019b45d322cSThierry Reding 3020b45d322cSThierry Reding cluster2 { 3021b45d322cSThierry Reding core0 { 3022b45d322cSThierry Reding cpu = <&cpu2_0>; 3023b45d322cSThierry Reding }; 3024b45d322cSThierry Reding 3025b45d322cSThierry Reding core1 { 3026b45d322cSThierry Reding cpu = <&cpu2_1>; 3027b45d322cSThierry Reding }; 3028b45d322cSThierry Reding }; 3029b45d322cSThierry Reding 3030b45d322cSThierry Reding cluster3 { 3031b45d322cSThierry Reding core0 { 3032b45d322cSThierry Reding cpu = <&cpu3_0>; 3033b45d322cSThierry Reding }; 3034b45d322cSThierry Reding 3035b45d322cSThierry Reding core1 { 3036b45d322cSThierry Reding cpu = <&cpu3_1>; 3037b45d322cSThierry Reding }; 3038b45d322cSThierry Reding }; 3039b45d322cSThierry Reding }; 3040b45d322cSThierry Reding 3041b45d322cSThierry Reding l2c_0: l2-cache0 { 304227f1568bSPierre Gondois compatible = "cache"; 304327f1568bSPierre Gondois cache-unified; 3044b45d322cSThierry Reding cache-size = <2097152>; 3045b45d322cSThierry Reding cache-line-size = <64>; 3046b45d322cSThierry Reding cache-sets = <2048>; 304727f1568bSPierre Gondois cache-level = <2>; 3048b45d322cSThierry Reding next-level-cache = <&l3c>; 3049b45d322cSThierry Reding }; 3050b45d322cSThierry Reding 3051b45d322cSThierry Reding l2c_1: l2-cache1 { 305227f1568bSPierre Gondois compatible = "cache"; 305327f1568bSPierre Gondois cache-unified; 3054b45d322cSThierry Reding cache-size = <2097152>; 3055b45d322cSThierry Reding cache-line-size = <64>; 3056b45d322cSThierry Reding cache-sets = <2048>; 305727f1568bSPierre Gondois cache-level = <2>; 3058b45d322cSThierry Reding next-level-cache = <&l3c>; 3059b45d322cSThierry Reding }; 3060b45d322cSThierry Reding 3061b45d322cSThierry Reding l2c_2: l2-cache2 { 306227f1568bSPierre Gondois compatible = "cache"; 306327f1568bSPierre Gondois cache-unified; 3064b45d322cSThierry Reding cache-size = <2097152>; 3065b45d322cSThierry Reding cache-line-size = <64>; 3066b45d322cSThierry Reding cache-sets = <2048>; 306727f1568bSPierre Gondois cache-level = <2>; 3068b45d322cSThierry Reding next-level-cache = <&l3c>; 3069b45d322cSThierry Reding }; 3070b45d322cSThierry Reding 3071b45d322cSThierry Reding l2c_3: l2-cache3 { 307227f1568bSPierre Gondois compatible = "cache"; 307327f1568bSPierre Gondois cache-unified; 3074b45d322cSThierry Reding cache-size = <2097152>; 3075b45d322cSThierry Reding cache-line-size = <64>; 3076b45d322cSThierry Reding cache-sets = <2048>; 307727f1568bSPierre Gondois cache-level = <2>; 3078b45d322cSThierry Reding next-level-cache = <&l3c>; 3079b45d322cSThierry Reding }; 3080b45d322cSThierry Reding 3081b45d322cSThierry Reding l3c: l3-cache { 308227f1568bSPierre Gondois compatible = "cache"; 308327f1568bSPierre Gondois cache-unified; 3084b45d322cSThierry Reding cache-size = <4194304>; 3085b45d322cSThierry Reding cache-line-size = <64>; 308627f1568bSPierre Gondois cache-level = <3>; 3087b45d322cSThierry Reding cache-sets = <4096>; 30887780a034SMikko Perttunen }; 30897780a034SMikko Perttunen }; 30907780a034SMikko Perttunen 30919e79e58fSJon Hunter pmu { 3092f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 30939e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 30949e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 30959e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 30969e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 30979e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 30989e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 30999e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 31009e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 31019e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 31029e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 31039e79e58fSJon Hunter }; 31049e79e58fSJon Hunter 31057780a034SMikko Perttunen psci { 31067780a034SMikko Perttunen compatible = "arm,psci-1.0"; 31077780a034SMikko Perttunen status = "okay"; 31087780a034SMikko Perttunen method = "smc"; 31097780a034SMikko Perttunen }; 31107780a034SMikko Perttunen 311179ed18d9SThierry Reding tcu: serial { 311279ed18d9SThierry Reding compatible = "nvidia,tegra194-tcu"; 311379ed18d9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 311479ed18d9SThierry Reding <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 311579ed18d9SThierry Reding mbox-names = "rx", "tx"; 311679ed18d9SThierry Reding }; 311779ed18d9SThierry Reding 31185b4f6323SSameer Pujar sound { 31195b4f6323SSameer Pujar status = "disabled"; 31205b4f6323SSameer Pujar 31215b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 31225b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31235b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 31245b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 31255b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 31265b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 31275b4f6323SSameer Pujar assigned-clock-parents = <0>, 31285b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 31295b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31305b4f6323SSameer Pujar /* 31315b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31325b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31335b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31345b4f6323SSameer Pujar */ 31355b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31365b4f6323SSameer Pujar }; 31375b4f6323SSameer Pujar 3138686ba009SThierry Reding thermal-zones { 3139fe57ff53SThierry Reding cpu-thermal { 3140fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3141686ba009SThierry Reding status = "disabled"; 3142686ba009SThierry Reding }; 3143686ba009SThierry Reding 3144fe57ff53SThierry Reding gpu-thermal { 3145fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3146686ba009SThierry Reding status = "disabled"; 3147686ba009SThierry Reding }; 3148686ba009SThierry Reding 3149fe57ff53SThierry Reding aux-thermal { 3150fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3151686ba009SThierry Reding status = "disabled"; 3152686ba009SThierry Reding }; 3153686ba009SThierry Reding 3154fe57ff53SThierry Reding pllx-thermal { 3155fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3156686ba009SThierry Reding status = "disabled"; 3157686ba009SThierry Reding }; 3158686ba009SThierry Reding 3159fe57ff53SThierry Reding ao-thermal { 3160fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3161686ba009SThierry Reding status = "disabled"; 3162686ba009SThierry Reding }; 3163686ba009SThierry Reding 3164fe57ff53SThierry Reding tj-thermal { 3165fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3166686ba009SThierry Reding status = "disabled"; 3167686ba009SThierry Reding }; 3168686ba009SThierry Reding }; 3169686ba009SThierry Reding 31705425fb15SMikko Perttunen timer { 31715425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31725425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31735425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31745425fb15SMikko Perttunen <GIC_PPI 14 31755425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31765425fb15SMikko Perttunen <GIC_PPI 11 31775425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31785425fb15SMikko Perttunen <GIC_PPI 10 31795425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31805425fb15SMikko Perttunen interrupt-parent = <&gic>; 3181b30be673SThierry Reding always-on; 31825425fb15SMikko Perttunen }; 31835425fb15SMikko Perttunen}; 3184