15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 19eef97c2aSThierry Reding cbb@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62f89b58ceSMikko Perttunen status = "disabled"; 63f89b58ceSMikko Perttunen 64f89b58ceSMikko Perttunen snps,write-requests = <1>; 65f89b58ceSMikko Perttunen snps,read-requests = <3>; 66f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 67f89b58ceSMikko Perttunen snps,txpbl = <16>; 68f89b58ceSMikko Perttunen snps,rxpbl = <8>; 69f89b58ceSMikko Perttunen }; 70f89b58ceSMikko Perttunen 711aaa7698SThierry Reding aconnect@2900000 { 725d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 735d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 745d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 755d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 765d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 775d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 785d2249ddSSameer Pujar #address-cells = <1>; 795d2249ddSSameer Pujar #size-cells = <1>; 805d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 815d2249ddSSameer Pujar status = "disabled"; 825d2249ddSSameer Pujar 835d2249ddSSameer Pujar dma-controller@2930000 { 845d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 855d2249ddSSameer Pujar "nvidia,tegra186-adma"; 865d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 875d2249ddSSameer Pujar interrupt-parent = <&agic>; 885d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 895d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1205d2249ddSSameer Pujar #dma-cells = <1>; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1225d2249ddSSameer Pujar clock-names = "d_audio"; 1235d2249ddSSameer Pujar status = "disabled"; 1245d2249ddSSameer Pujar }; 1255d2249ddSSameer Pujar 1265d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1275d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1285d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1295d2249ddSSameer Pujar #interrupt-cells = <3>; 1305d2249ddSSameer Pujar interrupt-controller; 1315d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1325d2249ddSSameer Pujar <0x02a42000 0x2000>; 1335d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1345d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1355d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1365d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1375d2249ddSSameer Pujar clock-names = "clk"; 1385d2249ddSSameer Pujar status = "disabled"; 1395d2249ddSSameer Pujar }; 1405d2249ddSSameer Pujar }; 1415d2249ddSSameer Pujar 142dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 143dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 144dbb72e2cSVidya Sagar reg = <0x2430000 0x17000 145dbb72e2cSVidya Sagar 0xc300000 0x4000>; 146dbb72e2cSVidya Sagar 147dbb72e2cSVidya Sagar status = "okay"; 148dbb72e2cSVidya Sagar 149dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 150dbb72e2cSVidya Sagar pex_rst { 151dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 152dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 153dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 154dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 155dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 156dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 157dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158dbb72e2cSVidya Sagar }; 159dbb72e2cSVidya Sagar }; 160dbb72e2cSVidya Sagar 161dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 162dbb72e2cSVidya Sagar clkreq { 163dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 164dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 165dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 166dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 168dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 169dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 170dbb72e2cSVidya Sagar }; 171dbb72e2cSVidya Sagar }; 172dbb72e2cSVidya Sagar }; 173dbb72e2cSVidya Sagar 174be9b887fSThierry Reding mc: memory-controller@2c00000 { 175be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 176be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 177be9b887fSThierry Reding <0x02b80000 0x040000>, 178be9b887fSThierry Reding <0x01700000 0x100000>; 179be9b887fSThierry Reding status = "disabled"; 180be9b887fSThierry Reding 181be9b887fSThierry Reding #address-cells = <2>; 182be9b887fSThierry Reding #size-cells = <2>; 183be9b887fSThierry Reding 184be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 185be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 186be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 187be9b887fSThierry Reding 188be9b887fSThierry Reding /* 189be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 190be9b887fSThierry Reding * controller selects the XBAR format used when memory 191be9b887fSThierry Reding * is accessed. This is used to transparently access 192be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 193be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 194be9b887fSThierry Reding * 195be9b887fSThierry Reding * As a consequence, the operating system must ensure 196be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 197be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 198be9b887fSThierry Reding * devices require access to the XBAR switch, their 199be9b887fSThierry Reding * drivers must set this bit explicitly. 200be9b887fSThierry Reding * 201be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 202be9b887fSThierry Reding */ 203be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 204be9b887fSThierry Reding 205be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 206be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 207be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 208be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 209be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 210be9b887fSThierry Reding clock-names = "emc"; 211be9b887fSThierry Reding 212be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 213be9b887fSThierry Reding }; 214be9b887fSThierry Reding }; 215be9b887fSThierry Reding 2165425fb15SMikko Perttunen uarta: serial@3100000 { 2175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2185425fb15SMikko Perttunen reg = <0x03100000 0x40>; 2195425fb15SMikko Perttunen reg-shift = <2>; 2205425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 2225425fb15SMikko Perttunen clock-names = "serial"; 2235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 2245425fb15SMikko Perttunen reset-names = "serial"; 2255425fb15SMikko Perttunen status = "disabled"; 2265425fb15SMikko Perttunen }; 2275425fb15SMikko Perttunen 2285425fb15SMikko Perttunen uartb: serial@3110000 { 2295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2305425fb15SMikko Perttunen reg = <0x03110000 0x40>; 2315425fb15SMikko Perttunen reg-shift = <2>; 2325425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 2345425fb15SMikko Perttunen clock-names = "serial"; 2355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 2365425fb15SMikko Perttunen reset-names = "serial"; 2375425fb15SMikko Perttunen status = "disabled"; 2385425fb15SMikko Perttunen }; 2395425fb15SMikko Perttunen 2405425fb15SMikko Perttunen uartd: serial@3130000 { 2415425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2425425fb15SMikko Perttunen reg = <0x03130000 0x40>; 2435425fb15SMikko Perttunen reg-shift = <2>; 2445425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 2465425fb15SMikko Perttunen clock-names = "serial"; 2475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 2485425fb15SMikko Perttunen reset-names = "serial"; 2495425fb15SMikko Perttunen status = "disabled"; 2505425fb15SMikko Perttunen }; 2515425fb15SMikko Perttunen 2525425fb15SMikko Perttunen uarte: serial@3140000 { 2535425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2545425fb15SMikko Perttunen reg = <0x03140000 0x40>; 2555425fb15SMikko Perttunen reg-shift = <2>; 2565425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 2585425fb15SMikko Perttunen clock-names = "serial"; 2595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 2605425fb15SMikko Perttunen reset-names = "serial"; 2615425fb15SMikko Perttunen status = "disabled"; 2625425fb15SMikko Perttunen }; 2635425fb15SMikko Perttunen 2645425fb15SMikko Perttunen uartf: serial@3150000 { 2655425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2665425fb15SMikko Perttunen reg = <0x03150000 0x40>; 2675425fb15SMikko Perttunen reg-shift = <2>; 2685425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 2705425fb15SMikko Perttunen clock-names = "serial"; 2715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 2725425fb15SMikko Perttunen reset-names = "serial"; 2735425fb15SMikko Perttunen status = "disabled"; 2745425fb15SMikko Perttunen }; 2755425fb15SMikko Perttunen 2765425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 277d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2785425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 2795425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2805425fb15SMikko Perttunen #address-cells = <1>; 2815425fb15SMikko Perttunen #size-cells = <0>; 2825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2835425fb15SMikko Perttunen clock-names = "div-clk"; 2845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2855425fb15SMikko Perttunen reset-names = "i2c"; 2865425fb15SMikko Perttunen status = "disabled"; 2875425fb15SMikko Perttunen }; 2885425fb15SMikko Perttunen 2895425fb15SMikko Perttunen uarth: serial@3170000 { 2905425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2915425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2925425fb15SMikko Perttunen reg-shift = <2>; 2935425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 2955425fb15SMikko Perttunen clock-names = "serial"; 2965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 2975425fb15SMikko Perttunen reset-names = "serial"; 2985425fb15SMikko Perttunen status = "disabled"; 2995425fb15SMikko Perttunen }; 3005425fb15SMikko Perttunen 3015425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 302d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3035425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 3045425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 3055425fb15SMikko Perttunen #address-cells = <1>; 3065425fb15SMikko Perttunen #size-cells = <0>; 3075425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 3085425fb15SMikko Perttunen clock-names = "div-clk"; 3095425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 3105425fb15SMikko Perttunen reset-names = "i2c"; 3115425fb15SMikko Perttunen status = "disabled"; 3125425fb15SMikko Perttunen }; 3135425fb15SMikko Perttunen 3145425fb15SMikko Perttunen /* shares pads with dpaux1 */ 3155425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 316d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3175425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 3185425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 3195425fb15SMikko Perttunen #address-cells = <1>; 3205425fb15SMikko Perttunen #size-cells = <0>; 3215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 3225425fb15SMikko Perttunen clock-names = "div-clk"; 3235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 3245425fb15SMikko Perttunen reset-names = "i2c"; 3255425fb15SMikko Perttunen status = "disabled"; 3265425fb15SMikko Perttunen }; 3275425fb15SMikko Perttunen 3285425fb15SMikko Perttunen /* shares pads with dpaux0 */ 3295425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 330d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3315425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 3325425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3335425fb15SMikko Perttunen #address-cells = <1>; 3345425fb15SMikko Perttunen #size-cells = <0>; 3355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 3365425fb15SMikko Perttunen clock-names = "div-clk"; 3375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 3385425fb15SMikko Perttunen reset-names = "i2c"; 3395425fb15SMikko Perttunen status = "disabled"; 3405425fb15SMikko Perttunen }; 3415425fb15SMikko Perttunen 3425425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 343d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3445425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 3455425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 3465425fb15SMikko Perttunen #address-cells = <1>; 3475425fb15SMikko Perttunen #size-cells = <0>; 3485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 3495425fb15SMikko Perttunen clock-names = "div-clk"; 3505425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 3515425fb15SMikko Perttunen reset-names = "i2c"; 3525425fb15SMikko Perttunen status = "disabled"; 3535425fb15SMikko Perttunen }; 3545425fb15SMikko Perttunen 3555425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 356d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3575425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 3585425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3595425fb15SMikko Perttunen #address-cells = <1>; 3605425fb15SMikko Perttunen #size-cells = <0>; 3615425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 3625425fb15SMikko Perttunen clock-names = "div-clk"; 3635425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 3645425fb15SMikko Perttunen reset-names = "i2c"; 3655425fb15SMikko Perttunen status = "disabled"; 3665425fb15SMikko Perttunen }; 3675425fb15SMikko Perttunen 3686a574ec7SThierry Reding pwm1: pwm@3280000 { 3696a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3706a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3716a574ec7SThierry Reding reg = <0x3280000 0x10000>; 3726a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 3736a574ec7SThierry Reding clock-names = "pwm"; 3746a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 3756a574ec7SThierry Reding reset-names = "pwm"; 3766a574ec7SThierry Reding status = "disabled"; 3776a574ec7SThierry Reding #pwm-cells = <2>; 3786a574ec7SThierry Reding }; 3796a574ec7SThierry Reding 3806a574ec7SThierry Reding pwm2: pwm@3290000 { 3816a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3826a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3836a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3846a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3856a574ec7SThierry Reding clock-names = "pwm"; 3866a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3876a574ec7SThierry Reding reset-names = "pwm"; 3886a574ec7SThierry Reding status = "disabled"; 3896a574ec7SThierry Reding #pwm-cells = <2>; 3906a574ec7SThierry Reding }; 3916a574ec7SThierry Reding 3926a574ec7SThierry Reding pwm3: pwm@32a0000 { 3936a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3946a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3956a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 3966a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 3976a574ec7SThierry Reding clock-names = "pwm"; 3986a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 3996a574ec7SThierry Reding reset-names = "pwm"; 4006a574ec7SThierry Reding status = "disabled"; 4016a574ec7SThierry Reding #pwm-cells = <2>; 4026a574ec7SThierry Reding }; 4036a574ec7SThierry Reding 4046a574ec7SThierry Reding pwm5: pwm@32c0000 { 4056a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4066a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4076a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 4086a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 4096a574ec7SThierry Reding clock-names = "pwm"; 4106a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 4116a574ec7SThierry Reding reset-names = "pwm"; 4126a574ec7SThierry Reding status = "disabled"; 4136a574ec7SThierry Reding #pwm-cells = <2>; 4146a574ec7SThierry Reding }; 4156a574ec7SThierry Reding 4166a574ec7SThierry Reding pwm6: pwm@32d0000 { 4176a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4186a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4196a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 4206a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 4216a574ec7SThierry Reding clock-names = "pwm"; 4226a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 4236a574ec7SThierry Reding reset-names = "pwm"; 4246a574ec7SThierry Reding status = "disabled"; 4256a574ec7SThierry Reding #pwm-cells = <2>; 4266a574ec7SThierry Reding }; 4276a574ec7SThierry Reding 4286a574ec7SThierry Reding pwm7: pwm@32e0000 { 4296a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4306a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4316a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 4326a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 4336a574ec7SThierry Reding clock-names = "pwm"; 4346a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 4356a574ec7SThierry Reding reset-names = "pwm"; 4366a574ec7SThierry Reding status = "disabled"; 4376a574ec7SThierry Reding #pwm-cells = <2>; 4386a574ec7SThierry Reding }; 4396a574ec7SThierry Reding 4406a574ec7SThierry Reding pwm8: pwm@32f0000 { 4416a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4426a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4436a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 4446a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 4456a574ec7SThierry Reding clock-names = "pwm"; 4466a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 4476a574ec7SThierry Reding reset-names = "pwm"; 4486a574ec7SThierry Reding status = "disabled"; 4496a574ec7SThierry Reding #pwm-cells = <2>; 4506a574ec7SThierry Reding }; 4516a574ec7SThierry Reding 4525425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 4535425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4545425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 4555425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 4565425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 4575425fb15SMikko Perttunen clock-names = "sdhci"; 4585425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 4595425fb15SMikko Perttunen reset-names = "sdhci"; 4604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 4614e0f1229SSowjanya Komatineni <0x07>; 4624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4634e0f1229SSowjanya Komatineni <0x07>; 4644e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4664e0f1229SSowjanya Komatineni <0x07>; 4674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4694e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4704e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4715425fb15SMikko Perttunen status = "disabled"; 4725425fb15SMikko Perttunen }; 4735425fb15SMikko Perttunen 4745425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 4755425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4765425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 4775425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 4785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 4795425fb15SMikko Perttunen clock-names = "sdhci"; 4805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 4815425fb15SMikko Perttunen reset-names = "sdhci"; 4824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4834e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 4854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4864e0f1229SSowjanya Komatineni <0x07>; 4874e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4894e0f1229SSowjanya Komatineni <0x07>; 4904e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4914e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4924e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4934e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4945425fb15SMikko Perttunen status = "disabled"; 4955425fb15SMikko Perttunen }; 4965425fb15SMikko Perttunen 4975425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 4985425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4995425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 5005425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 5015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 5025425fb15SMikko Perttunen clock-names = "sdhci"; 503351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 504351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 505351648d0SSowjanya Komatineni assigned-clock-parents = 506351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 5075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 5085425fb15SMikko Perttunen reset-names = "sdhci"; 5094e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 5104e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 5114e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 5124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5134e0f1229SSowjanya Komatineni <0x0a>; 5144e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 5154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5164e0f1229SSowjanya Komatineni <0x0a>; 5174e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 5184e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 5194e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 520dfd3cb6fSSowjanya Komatineni supports-cqe; 5215425fb15SMikko Perttunen status = "disabled"; 5225425fb15SMikko Perttunen }; 5235425fb15SMikko Perttunen 5244878cc0cSSameer Pujar hda@3510000 { 5254878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 5264878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 5274878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 5284878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 5294878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 5304878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 5314878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 5324878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 5334878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 5344878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 5354878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 5364878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 5374878cc0cSSameer Pujar status = "disabled"; 5384878cc0cSSameer Pujar }; 5394878cc0cSSameer Pujar 540fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 541fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 542fab7a039SJC Kuo reg = <0x03520000 0x1000>, 543fab7a039SJC Kuo <0x03540000 0x1000>; 544fab7a039SJC Kuo reg-names = "padctl", "ao"; 545fab7a039SJC Kuo 546fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 547fab7a039SJC Kuo reset-names = "padctl"; 548fab7a039SJC Kuo 549fab7a039SJC Kuo status = "disabled"; 550fab7a039SJC Kuo 551fab7a039SJC Kuo pads { 552fab7a039SJC Kuo usb2 { 553fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 554fab7a039SJC Kuo clock-names = "trk"; 555fab7a039SJC Kuo 556fab7a039SJC Kuo lanes { 557fab7a039SJC Kuo usb2-0 { 558fab7a039SJC Kuo nvidia,function = "xusb"; 559fab7a039SJC Kuo status = "disabled"; 560fab7a039SJC Kuo #phy-cells = <0>; 561fab7a039SJC Kuo }; 562fab7a039SJC Kuo 563fab7a039SJC Kuo usb2-1 { 564fab7a039SJC Kuo nvidia,function = "xusb"; 565fab7a039SJC Kuo status = "disabled"; 566fab7a039SJC Kuo #phy-cells = <0>; 567fab7a039SJC Kuo }; 568fab7a039SJC Kuo 569fab7a039SJC Kuo usb2-2 { 570fab7a039SJC Kuo nvidia,function = "xusb"; 571fab7a039SJC Kuo status = "disabled"; 572fab7a039SJC Kuo #phy-cells = <0>; 573fab7a039SJC Kuo }; 574fab7a039SJC Kuo 575fab7a039SJC Kuo usb2-3 { 576fab7a039SJC Kuo nvidia,function = "xusb"; 577fab7a039SJC Kuo status = "disabled"; 578fab7a039SJC Kuo #phy-cells = <0>; 579fab7a039SJC Kuo }; 580fab7a039SJC Kuo }; 581fab7a039SJC Kuo }; 582fab7a039SJC Kuo 583fab7a039SJC Kuo usb3 { 584fab7a039SJC Kuo lanes { 585fab7a039SJC Kuo usb3-0 { 586fab7a039SJC Kuo nvidia,function = "xusb"; 587fab7a039SJC Kuo status = "disabled"; 588fab7a039SJC Kuo #phy-cells = <0>; 589fab7a039SJC Kuo }; 590fab7a039SJC Kuo 591fab7a039SJC Kuo usb3-1 { 592fab7a039SJC Kuo nvidia,function = "xusb"; 593fab7a039SJC Kuo status = "disabled"; 594fab7a039SJC Kuo #phy-cells = <0>; 595fab7a039SJC Kuo }; 596fab7a039SJC Kuo 597fab7a039SJC Kuo usb3-2 { 598fab7a039SJC Kuo nvidia,function = "xusb"; 599fab7a039SJC Kuo status = "disabled"; 600fab7a039SJC Kuo #phy-cells = <0>; 601fab7a039SJC Kuo }; 602fab7a039SJC Kuo 603fab7a039SJC Kuo usb3-3 { 604fab7a039SJC Kuo nvidia,function = "xusb"; 605fab7a039SJC Kuo status = "disabled"; 606fab7a039SJC Kuo #phy-cells = <0>; 607fab7a039SJC Kuo }; 608fab7a039SJC Kuo }; 609fab7a039SJC Kuo }; 610fab7a039SJC Kuo }; 611fab7a039SJC Kuo 612fab7a039SJC Kuo ports { 613fab7a039SJC Kuo usb2-0 { 614fab7a039SJC Kuo status = "disabled"; 615fab7a039SJC Kuo }; 616fab7a039SJC Kuo 617fab7a039SJC Kuo usb2-1 { 618fab7a039SJC Kuo status = "disabled"; 619fab7a039SJC Kuo }; 620fab7a039SJC Kuo 621fab7a039SJC Kuo usb2-2 { 622fab7a039SJC Kuo status = "disabled"; 623fab7a039SJC Kuo }; 624fab7a039SJC Kuo 625fab7a039SJC Kuo usb2-3 { 626fab7a039SJC Kuo status = "disabled"; 627fab7a039SJC Kuo }; 628fab7a039SJC Kuo 629fab7a039SJC Kuo usb3-0 { 630fab7a039SJC Kuo status = "disabled"; 631fab7a039SJC Kuo }; 632fab7a039SJC Kuo 633fab7a039SJC Kuo usb3-1 { 634fab7a039SJC Kuo status = "disabled"; 635fab7a039SJC Kuo }; 636fab7a039SJC Kuo 637fab7a039SJC Kuo usb3-2 { 638fab7a039SJC Kuo status = "disabled"; 639fab7a039SJC Kuo }; 640fab7a039SJC Kuo 641fab7a039SJC Kuo usb3-3 { 642fab7a039SJC Kuo status = "disabled"; 643fab7a039SJC Kuo }; 644fab7a039SJC Kuo }; 645fab7a039SJC Kuo }; 646fab7a039SJC Kuo 647bc8788b2SNagarjuna Kristam usb@3550000 { 648bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 649bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 650bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 651bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 652bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 653bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 654bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 655bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 656bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 657bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 658bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 659bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 660bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 661bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 662bc8788b2SNagarjuna Kristam status = "disabled"; 663bc8788b2SNagarjuna Kristam }; 664bc8788b2SNagarjuna Kristam 665fab7a039SJC Kuo usb@3610000 { 666fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 667fab7a039SJC Kuo reg = <0x03610000 0x40000>, 668fab7a039SJC Kuo <0x03600000 0x10000>; 669fab7a039SJC Kuo reg-names = "hcd", "fpci"; 670fab7a039SJC Kuo 671fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 672fab7a039SJC Kuo <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 673fab7a039SJC Kuo <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 674fab7a039SJC Kuo 675fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 676fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 677fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 678fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 679fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 680fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 681fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 682fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 683fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 684fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 685fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 686fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 687fab7a039SJC Kuo "pll_e"; 688fab7a039SJC Kuo 689fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 690fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 691fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 692fab7a039SJC Kuo 693fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 694fab7a039SJC Kuo status = "disabled"; 695fab7a039SJC Kuo }; 696fab7a039SJC Kuo 69709903c5eSJC Kuo fuse@3820000 { 69809903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 69909903c5eSJC Kuo reg = <0x03820000 0x10000>; 70009903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 70109903c5eSJC Kuo clock-names = "fuse"; 70209903c5eSJC Kuo }; 70309903c5eSJC Kuo 7045425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 7055425fb15SMikko Perttunen compatible = "arm,gic-400"; 7065425fb15SMikko Perttunen #interrupt-cells = <3>; 7075425fb15SMikko Perttunen interrupt-controller; 7085425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 7095425fb15SMikko Perttunen <0x03882000 0x2000>, 7105425fb15SMikko Perttunen <0x03884000 0x2000>, 7115425fb15SMikko Perttunen <0x03886000 0x2000>; 7125425fb15SMikko Perttunen interrupts = <GIC_PPI 9 7135425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 7145425fb15SMikko Perttunen interrupt-parent = <&gic>; 7155425fb15SMikko Perttunen }; 7165425fb15SMikko Perttunen 717badb80beSThierry Reding cec@3960000 { 718badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 719badb80beSThierry Reding reg = <0x03960000 0x10000>; 720badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 721badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 722badb80beSThierry Reding clock-names = "cec"; 723badb80beSThierry Reding status = "disabled"; 724badb80beSThierry Reding }; 725badb80beSThierry Reding 7265425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 727a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 7285425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 729a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 730a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 731a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 732a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 733a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 734a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 735a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 736a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 737a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 738a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 739a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 740a38570c2SMikko Perttunen "shared7"; 741a38570c2SMikko Perttunen #mbox-cells = <2>; 742a38570c2SMikko Perttunen }; 743a38570c2SMikko Perttunen 7442602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 7452602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7462602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 7472602c32fSVidya Sagar reg-names = "ctl"; 7482602c32fSVidya Sagar 7492602c32fSVidya Sagar #phy-cells = <0>; 7502602c32fSVidya Sagar }; 7512602c32fSVidya Sagar 7522602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 7532602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7542602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 7552602c32fSVidya Sagar reg-names = "ctl"; 7562602c32fSVidya Sagar 7572602c32fSVidya Sagar #phy-cells = <0>; 7582602c32fSVidya Sagar }; 7592602c32fSVidya Sagar 7602602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 7612602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7622602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 7632602c32fSVidya Sagar reg-names = "ctl"; 7642602c32fSVidya Sagar 7652602c32fSVidya Sagar #phy-cells = <0>; 7662602c32fSVidya Sagar }; 7672602c32fSVidya Sagar 7682602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 7692602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7702602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 7712602c32fSVidya Sagar reg-names = "ctl"; 7722602c32fSVidya Sagar 7732602c32fSVidya Sagar #phy-cells = <0>; 7742602c32fSVidya Sagar }; 7752602c32fSVidya Sagar 7762602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 7772602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7782602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 7792602c32fSVidya Sagar reg-names = "ctl"; 7802602c32fSVidya Sagar 7812602c32fSVidya Sagar #phy-cells = <0>; 7822602c32fSVidya Sagar }; 7832602c32fSVidya Sagar 7842602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 7852602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7862602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 7872602c32fSVidya Sagar reg-names = "ctl"; 7882602c32fSVidya Sagar 7892602c32fSVidya Sagar #phy-cells = <0>; 7902602c32fSVidya Sagar }; 7912602c32fSVidya Sagar 7922602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 7932602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7942602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 7952602c32fSVidya Sagar reg-names = "ctl"; 7962602c32fSVidya Sagar 7972602c32fSVidya Sagar #phy-cells = <0>; 7982602c32fSVidya Sagar }; 7992602c32fSVidya Sagar 8002602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 8012602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8022602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 8032602c32fSVidya Sagar reg-names = "ctl"; 8042602c32fSVidya Sagar 8052602c32fSVidya Sagar #phy-cells = <0>; 8062602c32fSVidya Sagar }; 8072602c32fSVidya Sagar 8082602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 8092602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8102602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 8112602c32fSVidya Sagar reg-names = "ctl"; 8122602c32fSVidya Sagar 8132602c32fSVidya Sagar #phy-cells = <0>; 8142602c32fSVidya Sagar }; 8152602c32fSVidya Sagar 8162602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 8172602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8182602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 8192602c32fSVidya Sagar reg-names = "ctl"; 8202602c32fSVidya Sagar 8212602c32fSVidya Sagar #phy-cells = <0>; 8222602c32fSVidya Sagar }; 8232602c32fSVidya Sagar 8242602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 8252602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8262602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 8272602c32fSVidya Sagar reg-names = "ctl"; 8282602c32fSVidya Sagar 8292602c32fSVidya Sagar #phy-cells = <0>; 8302602c32fSVidya Sagar }; 8312602c32fSVidya Sagar 8322602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 8332602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8342602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 8352602c32fSVidya Sagar reg-names = "ctl"; 8362602c32fSVidya Sagar 8372602c32fSVidya Sagar #phy-cells = <0>; 8382602c32fSVidya Sagar }; 8392602c32fSVidya Sagar 8402602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 8412602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8422602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 8432602c32fSVidya Sagar reg-names = "ctl"; 8442602c32fSVidya Sagar 8452602c32fSVidya Sagar #phy-cells = <0>; 8462602c32fSVidya Sagar }; 8472602c32fSVidya Sagar 8482602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 8492602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8502602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 8512602c32fSVidya Sagar reg-names = "ctl"; 8522602c32fSVidya Sagar 8532602c32fSVidya Sagar #phy-cells = <0>; 8542602c32fSVidya Sagar }; 8552602c32fSVidya Sagar 8562602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 8572602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8582602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 8592602c32fSVidya Sagar reg-names = "ctl"; 8602602c32fSVidya Sagar 8612602c32fSVidya Sagar #phy-cells = <0>; 8622602c32fSVidya Sagar }; 8632602c32fSVidya Sagar 8642602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 8652602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8662602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 8672602c32fSVidya Sagar reg-names = "ctl"; 8682602c32fSVidya Sagar 8692602c32fSVidya Sagar #phy-cells = <0>; 8702602c32fSVidya Sagar }; 8712602c32fSVidya Sagar 8722602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 8732602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8742602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 8752602c32fSVidya Sagar reg-names = "ctl"; 8762602c32fSVidya Sagar 8772602c32fSVidya Sagar #phy-cells = <0>; 8782602c32fSVidya Sagar }; 8792602c32fSVidya Sagar 8802602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 8812602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8822602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 8832602c32fSVidya Sagar reg-names = "ctl"; 8842602c32fSVidya Sagar 8852602c32fSVidya Sagar #phy-cells = <0>; 8862602c32fSVidya Sagar }; 8872602c32fSVidya Sagar 8882602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 8892602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8902602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 8912602c32fSVidya Sagar reg-names = "ctl"; 8922602c32fSVidya Sagar 8932602c32fSVidya Sagar #phy-cells = <0>; 8942602c32fSVidya Sagar }; 8952602c32fSVidya Sagar 8962602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 8972602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 8982602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 8992602c32fSVidya Sagar reg-names = "ctl"; 9002602c32fSVidya Sagar 9012602c32fSVidya Sagar #phy-cells = <0>; 9022602c32fSVidya Sagar }; 9032602c32fSVidya Sagar 904a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 905a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 906a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 907a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 908a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 909a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 910a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 911a38570c2SMikko Perttunen /* 912a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 913a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 914a38570c2SMikko Perttunen */ 915a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 9165425fb15SMikko Perttunen #mbox-cells = <2>; 9175425fb15SMikko Perttunen }; 9185425fb15SMikko Perttunen 9195425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 920d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9215425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 9225425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 9235425fb15SMikko Perttunen #address-cells = <1>; 9245425fb15SMikko Perttunen #size-cells = <0>; 9255425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 9265425fb15SMikko Perttunen clock-names = "div-clk"; 9275425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 9285425fb15SMikko Perttunen reset-names = "i2c"; 9295425fb15SMikko Perttunen status = "disabled"; 9305425fb15SMikko Perttunen }; 9315425fb15SMikko Perttunen 9325425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 933d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9345425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 9355425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 9365425fb15SMikko Perttunen #address-cells = <1>; 9375425fb15SMikko Perttunen #size-cells = <0>; 9385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 9395425fb15SMikko Perttunen clock-names = "div-clk"; 9405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 9415425fb15SMikko Perttunen reset-names = "i2c"; 9425425fb15SMikko Perttunen status = "disabled"; 9435425fb15SMikko Perttunen }; 9445425fb15SMikko Perttunen 9455425fb15SMikko Perttunen uartc: serial@c280000 { 9465425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9475425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 9485425fb15SMikko Perttunen reg-shift = <2>; 9495425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 9505425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 9515425fb15SMikko Perttunen clock-names = "serial"; 9525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 9535425fb15SMikko Perttunen reset-names = "serial"; 9545425fb15SMikko Perttunen status = "disabled"; 9555425fb15SMikko Perttunen }; 9565425fb15SMikko Perttunen 9575425fb15SMikko Perttunen uartg: serial@c290000 { 9585425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 9595425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 9605425fb15SMikko Perttunen reg-shift = <2>; 9615425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 9625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 9635425fb15SMikko Perttunen clock-names = "serial"; 9645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 9655425fb15SMikko Perttunen reset-names = "serial"; 9665425fb15SMikko Perttunen status = "disabled"; 9675425fb15SMikko Perttunen }; 9685425fb15SMikko Perttunen 96937e5a31dSThierry Reding rtc: rtc@c2a0000 { 97037e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 97137e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 97237e5a31dSThierry Reding interrupt-parent = <&pmc>; 97337e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 97437e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 97537e5a31dSThierry Reding clock-names = "rtc"; 97637e5a31dSThierry Reding status = "disabled"; 97737e5a31dSThierry Reding }; 97837e5a31dSThierry Reding 9794d286331SThierry Reding gpio_aon: gpio@c2f0000 { 9804d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 9814d286331SThierry Reding reg-names = "security", "gpio"; 9824d286331SThierry Reding reg = <0xc2f0000 0x1000>, 9834d286331SThierry Reding <0xc2f1000 0x1000>; 9844d286331SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 9854d286331SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 9864d286331SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 9874d286331SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 9884d286331SThierry Reding gpio-controller; 9894d286331SThierry Reding #gpio-cells = <2>; 9904d286331SThierry Reding interrupt-controller; 9914d286331SThierry Reding #interrupt-cells = <2>; 9924d286331SThierry Reding }; 9934d286331SThierry Reding 9946a574ec7SThierry Reding pwm4: pwm@c340000 { 9956a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9966a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9976a574ec7SThierry Reding reg = <0xc340000 0x10000>; 9986a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 9996a574ec7SThierry Reding clock-names = "pwm"; 10006a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 10016a574ec7SThierry Reding reset-names = "pwm"; 10026a574ec7SThierry Reding status = "disabled"; 10036a574ec7SThierry Reding #pwm-cells = <2>; 10046a574ec7SThierry Reding }; 10056a574ec7SThierry Reding 100638ecf1e5SThierry Reding pmc: pmc@c360000 { 10075425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 10085425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 10095425fb15SMikko Perttunen <0x0c370000 0x10000>, 10105425fb15SMikko Perttunen <0x0c380000 0x10000>, 10115425fb15SMikko Perttunen <0x0c390000 0x10000>, 10125425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 10135425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 101438ecf1e5SThierry Reding 101538ecf1e5SThierry Reding #interrupt-cells = <2>; 101638ecf1e5SThierry Reding interrupt-controller; 10175425fb15SMikko Perttunen }; 10183db6d3baSThierry Reding 10193db6d3baSThierry Reding host1x@13e00000 { 10203db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 10213db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 10223db6d3baSThierry Reding <0x13e10000 0x10000>; 10233db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 10243db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 10253db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 10263db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 10273db6d3baSThierry Reding clock-names = "host1x"; 10283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 10293db6d3baSThierry Reding reset-names = "host1x"; 10303db6d3baSThierry Reding 10313db6d3baSThierry Reding #address-cells = <1>; 10323db6d3baSThierry Reding #size-cells = <1>; 10333db6d3baSThierry Reding 10343db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 10353db6d3baSThierry Reding 10363db6d3baSThierry Reding display-hub@15200000 { 10373db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 1038611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 10393db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 10403db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 10413db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 10423db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 10433db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 10443db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 10453db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 10463db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 10473db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 10483db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 10493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 10503db6d3baSThierry Reding clock-names = "disp", "hub"; 10513db6d3baSThierry Reding status = "disabled"; 10523db6d3baSThierry Reding 10533db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10543db6d3baSThierry Reding 10553db6d3baSThierry Reding #address-cells = <1>; 10563db6d3baSThierry Reding #size-cells = <1>; 10573db6d3baSThierry Reding 10583db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 10593db6d3baSThierry Reding 10603db6d3baSThierry Reding display@15200000 { 10613db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 10623db6d3baSThierry Reding reg = <0x15200000 0x10000>; 10633db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 10643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 10653db6d3baSThierry Reding clock-names = "dc"; 10663db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 10673db6d3baSThierry Reding reset-names = "dc"; 10683db6d3baSThierry Reding 10693db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10703db6d3baSThierry Reding 10713db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 10723db6d3baSThierry Reding nvidia,head = <0>; 10733db6d3baSThierry Reding }; 10743db6d3baSThierry Reding 10753db6d3baSThierry Reding display@15210000 { 10763db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 10773db6d3baSThierry Reding reg = <0x15210000 0x10000>; 10783db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 10793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 10803db6d3baSThierry Reding clock-names = "dc"; 10813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 10823db6d3baSThierry Reding reset-names = "dc"; 10833db6d3baSThierry Reding 10843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 10853db6d3baSThierry Reding 10863db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 10873db6d3baSThierry Reding nvidia,head = <1>; 10883db6d3baSThierry Reding }; 10893db6d3baSThierry Reding 10903db6d3baSThierry Reding display@15220000 { 10913db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 10923db6d3baSThierry Reding reg = <0x15220000 0x10000>; 10933db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 10943db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 10953db6d3baSThierry Reding clock-names = "dc"; 10963db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 10973db6d3baSThierry Reding reset-names = "dc"; 10983db6d3baSThierry Reding 10993db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 11003db6d3baSThierry Reding 11013db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11023db6d3baSThierry Reding nvidia,head = <2>; 11033db6d3baSThierry Reding }; 11043db6d3baSThierry Reding 11053db6d3baSThierry Reding display@15230000 { 11063db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 11073db6d3baSThierry Reding reg = <0x15230000 0x10000>; 11083db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 11093db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 11103db6d3baSThierry Reding clock-names = "dc"; 11113db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 11123db6d3baSThierry Reding reset-names = "dc"; 11133db6d3baSThierry Reding 11143db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 11153db6d3baSThierry Reding 11163db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 11173db6d3baSThierry Reding nvidia,head = <3>; 11183db6d3baSThierry Reding }; 11193db6d3baSThierry Reding }; 11203db6d3baSThierry Reding 11218d424ec2SThierry Reding vic@15340000 { 11228d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 11238d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 11248d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 11258d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 11268d424ec2SThierry Reding clock-names = "vic"; 11278d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 11288d424ec2SThierry Reding reset-names = "vic"; 11298d424ec2SThierry Reding 11308d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 11318d424ec2SThierry Reding }; 11328d424ec2SThierry Reding 11333db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 11343db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 11353db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 11363db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 11373db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 11383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 11393db6d3baSThierry Reding clock-names = "dpaux", "parent"; 11403db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 11413db6d3baSThierry Reding reset-names = "dpaux"; 11423db6d3baSThierry Reding status = "disabled"; 11433db6d3baSThierry Reding 11443db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11453db6d3baSThierry Reding 11463db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 11473db6d3baSThierry Reding groups = "dpaux-io"; 11483db6d3baSThierry Reding function = "aux"; 11493db6d3baSThierry Reding }; 11503db6d3baSThierry Reding 11513db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 11523db6d3baSThierry Reding groups = "dpaux-io"; 11533db6d3baSThierry Reding function = "i2c"; 11543db6d3baSThierry Reding }; 11553db6d3baSThierry Reding 11563db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 11573db6d3baSThierry Reding groups = "dpaux-io"; 11583db6d3baSThierry Reding function = "off"; 11593db6d3baSThierry Reding }; 11603db6d3baSThierry Reding 11613db6d3baSThierry Reding i2c-bus { 11623db6d3baSThierry Reding #address-cells = <1>; 11633db6d3baSThierry Reding #size-cells = <0>; 11643db6d3baSThierry Reding }; 11653db6d3baSThierry Reding }; 11663db6d3baSThierry Reding 11673db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 11683db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 11693db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 11703db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 11713db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 11723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 11733db6d3baSThierry Reding clock-names = "dpaux", "parent"; 11743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 11753db6d3baSThierry Reding reset-names = "dpaux"; 11763db6d3baSThierry Reding status = "disabled"; 11773db6d3baSThierry Reding 11783db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11793db6d3baSThierry Reding 11803db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 11813db6d3baSThierry Reding groups = "dpaux-io"; 11823db6d3baSThierry Reding function = "aux"; 11833db6d3baSThierry Reding }; 11843db6d3baSThierry Reding 11853db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 11863db6d3baSThierry Reding groups = "dpaux-io"; 11873db6d3baSThierry Reding function = "i2c"; 11883db6d3baSThierry Reding }; 11893db6d3baSThierry Reding 11903db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 11913db6d3baSThierry Reding groups = "dpaux-io"; 11923db6d3baSThierry Reding function = "off"; 11933db6d3baSThierry Reding }; 11943db6d3baSThierry Reding 11953db6d3baSThierry Reding i2c-bus { 11963db6d3baSThierry Reding #address-cells = <1>; 11973db6d3baSThierry Reding #size-cells = <0>; 11983db6d3baSThierry Reding }; 11993db6d3baSThierry Reding }; 12003db6d3baSThierry Reding 12013db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 12023db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12033db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 12043db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 12053db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 12063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12073db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12083db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 12093db6d3baSThierry Reding reset-names = "dpaux"; 12103db6d3baSThierry Reding status = "disabled"; 12113db6d3baSThierry Reding 12123db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12133db6d3baSThierry Reding 12143db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 12153db6d3baSThierry Reding groups = "dpaux-io"; 12163db6d3baSThierry Reding function = "aux"; 12173db6d3baSThierry Reding }; 12183db6d3baSThierry Reding 12193db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 12203db6d3baSThierry Reding groups = "dpaux-io"; 12213db6d3baSThierry Reding function = "i2c"; 12223db6d3baSThierry Reding }; 12233db6d3baSThierry Reding 12243db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 12253db6d3baSThierry Reding groups = "dpaux-io"; 12263db6d3baSThierry Reding function = "off"; 12273db6d3baSThierry Reding }; 12283db6d3baSThierry Reding 12293db6d3baSThierry Reding i2c-bus { 12303db6d3baSThierry Reding #address-cells = <1>; 12313db6d3baSThierry Reding #size-cells = <0>; 12323db6d3baSThierry Reding }; 12333db6d3baSThierry Reding }; 12343db6d3baSThierry Reding 12353db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 12363db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 12373db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 12383db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 12393db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 12403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 12413db6d3baSThierry Reding clock-names = "dpaux", "parent"; 12423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 12433db6d3baSThierry Reding reset-names = "dpaux"; 12443db6d3baSThierry Reding status = "disabled"; 12453db6d3baSThierry Reding 12463db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12473db6d3baSThierry Reding 12483db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 12493db6d3baSThierry Reding groups = "dpaux-io"; 12503db6d3baSThierry Reding function = "aux"; 12513db6d3baSThierry Reding }; 12523db6d3baSThierry Reding 12533db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 12543db6d3baSThierry Reding groups = "dpaux-io"; 12553db6d3baSThierry Reding function = "i2c"; 12563db6d3baSThierry Reding }; 12573db6d3baSThierry Reding 12583db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 12593db6d3baSThierry Reding groups = "dpaux-io"; 12603db6d3baSThierry Reding function = "off"; 12613db6d3baSThierry Reding }; 12623db6d3baSThierry Reding 12633db6d3baSThierry Reding i2c-bus { 12643db6d3baSThierry Reding #address-cells = <1>; 12653db6d3baSThierry Reding #size-cells = <0>; 12663db6d3baSThierry Reding }; 12673db6d3baSThierry Reding }; 12683db6d3baSThierry Reding 12693db6d3baSThierry Reding sor0: sor@15b00000 { 12703db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 12713db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 12723db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 12733db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 12743db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 12753db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 12763db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 12773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 12783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 12793db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 12803db6d3baSThierry Reding "pad"; 12813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 12823db6d3baSThierry Reding reset-names = "sor"; 12833db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 12843db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 12853db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 12863db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 12873db6d3baSThierry Reding status = "disabled"; 12883db6d3baSThierry Reding 12893db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12903db6d3baSThierry Reding nvidia,interface = <0>; 12913db6d3baSThierry Reding }; 12923db6d3baSThierry Reding 12933db6d3baSThierry Reding sor1: sor@15b40000 { 12943db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1295939e7430SThierry Reding reg = <0x15b40000 0x40000>; 12963db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 12973db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 12983db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 12993db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 13003db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13013db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 13033db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13043db6d3baSThierry Reding "pad"; 13053db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 13063db6d3baSThierry Reding reset-names = "sor"; 13073db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 13083db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 13093db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 13103db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13113db6d3baSThierry Reding status = "disabled"; 13123db6d3baSThierry Reding 13133db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13143db6d3baSThierry Reding nvidia,interface = <1>; 13153db6d3baSThierry Reding }; 13163db6d3baSThierry Reding 13173db6d3baSThierry Reding sor2: sor@15b80000 { 13183db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13193db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 13203db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 13213db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 13223db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 13233db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 13243db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 13273db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13283db6d3baSThierry Reding "pad"; 13293db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 13303db6d3baSThierry Reding reset-names = "sor"; 13313db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 13323db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 13333db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 13343db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13353db6d3baSThierry Reding status = "disabled"; 13363db6d3baSThierry Reding 13373db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13383db6d3baSThierry Reding nvidia,interface = <2>; 13393db6d3baSThierry Reding }; 13403db6d3baSThierry Reding 13413db6d3baSThierry Reding sor3: sor@15bc0000 { 13423db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 13433db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 13443db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 13453db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 13463db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 13473db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 13483db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 13493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 13503db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 13513db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 13523db6d3baSThierry Reding "pad"; 13533db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 13543db6d3baSThierry Reding reset-names = "sor"; 13553db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 13563db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 13573db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 13583db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 13593db6d3baSThierry Reding status = "disabled"; 13603db6d3baSThierry Reding 13613db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13623db6d3baSThierry Reding nvidia,interface = <3>; 13633db6d3baSThierry Reding }; 13643db6d3baSThierry Reding }; 13655425fb15SMikko Perttunen }; 13665425fb15SMikko Perttunen 13672602c32fSVidya Sagar pcie@14100000 { 1368f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 13692602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 13702602c32fSVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 13712602c32fSVidya Sagar 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 13722602c32fSVidya Sagar 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13732602c32fSVidya Sagar 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13742602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13752602c32fSVidya Sagar 13762602c32fSVidya Sagar status = "disabled"; 13772602c32fSVidya Sagar 13782602c32fSVidya Sagar #address-cells = <3>; 13792602c32fSVidya Sagar #size-cells = <2>; 13802602c32fSVidya Sagar device_type = "pci"; 13812602c32fSVidya Sagar num-lanes = <1>; 13822602c32fSVidya Sagar num-viewport = <8>; 13832602c32fSVidya Sagar linux,pci-domain = <1>; 13842602c32fSVidya Sagar 13852602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 13862602c32fSVidya Sagar clock-names = "core"; 13872602c32fSVidya Sagar 13882602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 13892602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 13902602c32fSVidya Sagar reset-names = "apb", "core"; 13912602c32fSVidya Sagar 13922602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13932602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13942602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13952602c32fSVidya Sagar 13962602c32fSVidya Sagar #interrupt-cells = <1>; 13972602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13982602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 13992602c32fSVidya Sagar 14002602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 14012602c32fSVidya Sagar 14022602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14032602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14042602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14052602c32fSVidya Sagar 14062602c32fSVidya Sagar bus-range = <0x0 0xff>; 14072602c32fSVidya Sagar ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14083482a7afSVidya Sagar 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 14092602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 14102602c32fSVidya Sagar }; 14112602c32fSVidya Sagar 14122602c32fSVidya Sagar pcie@14120000 { 1413f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 14142602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 14152602c32fSVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 14162602c32fSVidya Sagar 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 14172602c32fSVidya Sagar 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 14182602c32fSVidya Sagar 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14192602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14202602c32fSVidya Sagar 14212602c32fSVidya Sagar status = "disabled"; 14222602c32fSVidya Sagar 14232602c32fSVidya Sagar #address-cells = <3>; 14242602c32fSVidya Sagar #size-cells = <2>; 14252602c32fSVidya Sagar device_type = "pci"; 14262602c32fSVidya Sagar num-lanes = <1>; 14272602c32fSVidya Sagar num-viewport = <8>; 14282602c32fSVidya Sagar linux,pci-domain = <2>; 14292602c32fSVidya Sagar 14302602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 14312602c32fSVidya Sagar clock-names = "core"; 14322602c32fSVidya Sagar 14332602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 14342602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 14352602c32fSVidya Sagar reset-names = "apb", "core"; 14362602c32fSVidya Sagar 14372602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14382602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14392602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14402602c32fSVidya Sagar 14412602c32fSVidya Sagar #interrupt-cells = <1>; 14422602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14432602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 14442602c32fSVidya Sagar 14452602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 14462602c32fSVidya Sagar 14472602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14482602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14492602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14502602c32fSVidya Sagar 14512602c32fSVidya Sagar bus-range = <0x0 0xff>; 14522602c32fSVidya Sagar ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14533482a7afSVidya Sagar 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 14542602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 14552602c32fSVidya Sagar }; 14562602c32fSVidya Sagar 14572602c32fSVidya Sagar pcie@14140000 { 1458f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 14592602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 14602602c32fSVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 14612602c32fSVidya Sagar 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 14622602c32fSVidya Sagar 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 14632602c32fSVidya Sagar 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14642602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar status = "disabled"; 14672602c32fSVidya Sagar 14682602c32fSVidya Sagar #address-cells = <3>; 14692602c32fSVidya Sagar #size-cells = <2>; 14702602c32fSVidya Sagar device_type = "pci"; 14712602c32fSVidya Sagar num-lanes = <1>; 14722602c32fSVidya Sagar num-viewport = <8>; 14732602c32fSVidya Sagar linux,pci-domain = <3>; 14742602c32fSVidya Sagar 14752602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 14762602c32fSVidya Sagar clock-names = "core"; 14772602c32fSVidya Sagar 14782602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 14792602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 14802602c32fSVidya Sagar reset-names = "apb", "core"; 14812602c32fSVidya Sagar 14822602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14832602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14842602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14852602c32fSVidya Sagar 14862602c32fSVidya Sagar #interrupt-cells = <1>; 14872602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14882602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 14892602c32fSVidya Sagar 14902602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 14912602c32fSVidya Sagar 14922602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14932602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14942602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14952602c32fSVidya Sagar 14962602c32fSVidya Sagar bus-range = <0x0 0xff>; 14972602c32fSVidya Sagar ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14983482a7afSVidya Sagar 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 14992602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 15002602c32fSVidya Sagar }; 15012602c32fSVidya Sagar 15022602c32fSVidya Sagar pcie@14160000 { 1503f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15042602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 15052602c32fSVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 15062602c32fSVidya Sagar 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 15072602c32fSVidya Sagar 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 15082602c32fSVidya Sagar 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15092602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15102602c32fSVidya Sagar 15112602c32fSVidya Sagar status = "disabled"; 15122602c32fSVidya Sagar 15132602c32fSVidya Sagar #address-cells = <3>; 15142602c32fSVidya Sagar #size-cells = <2>; 15152602c32fSVidya Sagar device_type = "pci"; 15162602c32fSVidya Sagar num-lanes = <4>; 15172602c32fSVidya Sagar num-viewport = <8>; 15182602c32fSVidya Sagar linux,pci-domain = <4>; 15192602c32fSVidya Sagar 15202602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 15212602c32fSVidya Sagar clock-names = "core"; 15222602c32fSVidya Sagar 15232602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 15242602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 15252602c32fSVidya Sagar reset-names = "apb", "core"; 15262602c32fSVidya Sagar 15272602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15282602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15292602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15302602c32fSVidya Sagar 15312602c32fSVidya Sagar #interrupt-cells = <1>; 15322602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15332602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 15342602c32fSVidya Sagar 15352602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 15362602c32fSVidya Sagar 15372602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15382602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15392602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15402602c32fSVidya Sagar 15412602c32fSVidya Sagar bus-range = <0x0 0xff>; 15422602c32fSVidya Sagar ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 15433482a7afSVidya Sagar 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 15442602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 15452602c32fSVidya Sagar }; 15462602c32fSVidya Sagar 15472602c32fSVidya Sagar pcie@14180000 { 1548f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15492602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 15502602c32fSVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 15512602c32fSVidya Sagar 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 15522602c32fSVidya Sagar 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 15532602c32fSVidya Sagar 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15542602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 15552602c32fSVidya Sagar 15562602c32fSVidya Sagar status = "disabled"; 15572602c32fSVidya Sagar 15582602c32fSVidya Sagar #address-cells = <3>; 15592602c32fSVidya Sagar #size-cells = <2>; 15602602c32fSVidya Sagar device_type = "pci"; 15612602c32fSVidya Sagar num-lanes = <8>; 15622602c32fSVidya Sagar num-viewport = <8>; 15632602c32fSVidya Sagar linux,pci-domain = <0>; 15642602c32fSVidya Sagar 15652602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 15662602c32fSVidya Sagar clock-names = "core"; 15672602c32fSVidya Sagar 15682602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 15692602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 15702602c32fSVidya Sagar reset-names = "apb", "core"; 15712602c32fSVidya Sagar 15722602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 15732602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 15742602c32fSVidya Sagar interrupt-names = "intr", "msi"; 15752602c32fSVidya Sagar 15762602c32fSVidya Sagar #interrupt-cells = <1>; 15772602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 15782602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 15792602c32fSVidya Sagar 15802602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 15812602c32fSVidya Sagar 15822602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 15832602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 15842602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 15852602c32fSVidya Sagar 15862602c32fSVidya Sagar bus-range = <0x0 0xff>; 15872602c32fSVidya Sagar ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 15883482a7afSVidya Sagar 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 15892602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 15902602c32fSVidya Sagar }; 15912602c32fSVidya Sagar 15922602c32fSVidya Sagar pcie@141a0000 { 1593f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 15942602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 15952602c32fSVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 15962602c32fSVidya Sagar 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 15972602c32fSVidya Sagar 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 15982602c32fSVidya Sagar 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 15992602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16002602c32fSVidya Sagar 16012602c32fSVidya Sagar status = "disabled"; 16022602c32fSVidya Sagar 16032602c32fSVidya Sagar #address-cells = <3>; 16042602c32fSVidya Sagar #size-cells = <2>; 16052602c32fSVidya Sagar device_type = "pci"; 16062602c32fSVidya Sagar num-lanes = <8>; 16072602c32fSVidya Sagar num-viewport = <8>; 16082602c32fSVidya Sagar linux,pci-domain = <5>; 16092602c32fSVidya Sagar 1610dbb72e2cSVidya Sagar pinctrl-names = "default"; 1611dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1612dbb72e2cSVidya Sagar 16132602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 16142602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 16152602c32fSVidya Sagar clock-names = "core", "core_m"; 16162602c32fSVidya Sagar 16172602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 16182602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 16192602c32fSVidya Sagar reset-names = "apb", "core"; 16202602c32fSVidya Sagar 16212602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 16222602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 16232602c32fSVidya Sagar interrupt-names = "intr", "msi"; 16242602c32fSVidya Sagar 16252602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 16262602c32fSVidya Sagar 16272602c32fSVidya Sagar #interrupt-cells = <1>; 16282602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 16292602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 16302602c32fSVidya Sagar 16312602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 16322602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16332602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16342602c32fSVidya Sagar 16352602c32fSVidya Sagar bus-range = <0x0 0xff>; 16362602c32fSVidya Sagar ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 16373482a7afSVidya Sagar 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 16382602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 16392602c32fSVidya Sagar }; 16402602c32fSVidya Sagar 16410c988b73SVidya Sagar pcie_ep@14160000 { 16420c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 16430c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 16440c988b73SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 16450c988b73SVidya Sagar 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 16460c988b73SVidya Sagar 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */ 16470c988b73SVidya Sagar 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 16480c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 16490c988b73SVidya Sagar 16500c988b73SVidya Sagar status = "disabled"; 16510c988b73SVidya Sagar 16520c988b73SVidya Sagar num-lanes = <4>; 16530c988b73SVidya Sagar num-ib-windows = <2>; 16540c988b73SVidya Sagar num-ob-windows = <8>; 16550c988b73SVidya Sagar 16560c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 16570c988b73SVidya Sagar clock-names = "core"; 16580c988b73SVidya Sagar 16590c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 16600c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 16610c988b73SVidya Sagar reset-names = "apb", "core"; 16620c988b73SVidya Sagar 16630c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 16640c988b73SVidya Sagar interrupt-names = "intr"; 16650c988b73SVidya Sagar 16660c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 16670c988b73SVidya Sagar 16680c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 16690c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 16700c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 16710c988b73SVidya Sagar }; 16720c988b73SVidya Sagar 16730c988b73SVidya Sagar pcie_ep@14180000 { 16740c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 16750c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 16760c988b73SVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 16770c988b73SVidya Sagar 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 16780c988b73SVidya Sagar 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */ 16790c988b73SVidya Sagar 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 16800c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 16810c988b73SVidya Sagar 16820c988b73SVidya Sagar status = "disabled"; 16830c988b73SVidya Sagar 16840c988b73SVidya Sagar num-lanes = <8>; 16850c988b73SVidya Sagar num-ib-windows = <2>; 16860c988b73SVidya Sagar num-ob-windows = <8>; 16870c988b73SVidya Sagar 16880c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 16890c988b73SVidya Sagar clock-names = "core"; 16900c988b73SVidya Sagar 16910c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 16920c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 16930c988b73SVidya Sagar reset-names = "apb", "core"; 16940c988b73SVidya Sagar 16950c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 16960c988b73SVidya Sagar interrupt-names = "intr"; 16970c988b73SVidya Sagar 16980c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 16990c988b73SVidya Sagar 17000c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 17010c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17020c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17030c988b73SVidya Sagar }; 17040c988b73SVidya Sagar 17050c988b73SVidya Sagar pcie_ep@141a0000 { 17060c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 17070c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 17080c988b73SVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 17090c988b73SVidya Sagar 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 17100c988b73SVidya Sagar 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 17110c988b73SVidya Sagar 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 17120c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 17130c988b73SVidya Sagar 17140c988b73SVidya Sagar status = "disabled"; 17150c988b73SVidya Sagar 17160c988b73SVidya Sagar num-lanes = <8>; 17170c988b73SVidya Sagar num-ib-windows = <2>; 17180c988b73SVidya Sagar num-ob-windows = <8>; 17190c988b73SVidya Sagar 17200c988b73SVidya Sagar pinctrl-names = "default"; 17210c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 17220c988b73SVidya Sagar 17230c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 17240c988b73SVidya Sagar clock-names = "core"; 17250c988b73SVidya Sagar 17260c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 17270c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 17280c988b73SVidya Sagar reset-names = "apb", "core"; 17290c988b73SVidya Sagar 17300c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 17310c988b73SVidya Sagar interrupt-names = "intr"; 17320c988b73SVidya Sagar 17330c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 17340c988b73SVidya Sagar 17350c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 17360c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17370c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17380c988b73SVidya Sagar }; 17390c988b73SVidya Sagar 17405425fb15SMikko Perttunen sysram@40000000 { 17415425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 17425425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 17435425fb15SMikko Perttunen #address-cells = <1>; 17445425fb15SMikko Perttunen #size-cells = <1>; 17455425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 17465425fb15SMikko Perttunen 17475425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 17485425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 17495425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 17505425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 17515425fb15SMikko Perttunen pool; 17525425fb15SMikko Perttunen }; 17535425fb15SMikko Perttunen 17545425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 17555425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 17565425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 17575425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 17585425fb15SMikko Perttunen pool; 17595425fb15SMikko Perttunen }; 17605425fb15SMikko Perttunen }; 17615425fb15SMikko Perttunen 17625425fb15SMikko Perttunen bpmp: bpmp { 17635425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 17645425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 17655425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 17665425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 17675425fb15SMikko Perttunen #clock-cells = <1>; 17685425fb15SMikko Perttunen #reset-cells = <1>; 17695425fb15SMikko Perttunen #power-domain-cells = <1>; 17705425fb15SMikko Perttunen 17715425fb15SMikko Perttunen bpmp_i2c: i2c { 17725425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 17735425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 17745425fb15SMikko Perttunen #address-cells = <1>; 17755425fb15SMikko Perttunen #size-cells = <0>; 17765425fb15SMikko Perttunen }; 17775425fb15SMikko Perttunen 17785425fb15SMikko Perttunen bpmp_thermal: thermal { 17795425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 17805425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 17815425fb15SMikko Perttunen }; 17825425fb15SMikko Perttunen }; 17835425fb15SMikko Perttunen 17847780a034SMikko Perttunen cpus { 17857780a034SMikko Perttunen #address-cells = <1>; 17867780a034SMikko Perttunen #size-cells = <0>; 17877780a034SMikko Perttunen 1788b45d322cSThierry Reding cpu0_0: cpu@0 { 178931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 17907780a034SMikko Perttunen device_type = "cpu"; 1791b45d322cSThierry Reding reg = <0x000>; 17927780a034SMikko Perttunen enable-method = "psci"; 1793b45d322cSThierry Reding i-cache-size = <131072>; 1794b45d322cSThierry Reding i-cache-line-size = <64>; 1795b45d322cSThierry Reding i-cache-sets = <512>; 1796b45d322cSThierry Reding d-cache-size = <65536>; 1797b45d322cSThierry Reding d-cache-line-size = <64>; 1798b45d322cSThierry Reding d-cache-sets = <256>; 1799b45d322cSThierry Reding next-level-cache = <&l2c_0>; 18007780a034SMikko Perttunen }; 18017780a034SMikko Perttunen 1802b45d322cSThierry Reding cpu0_1: cpu@1 { 180331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18047780a034SMikko Perttunen device_type = "cpu"; 1805b45d322cSThierry Reding reg = <0x001>; 18067780a034SMikko Perttunen enable-method = "psci"; 1807b45d322cSThierry Reding i-cache-size = <131072>; 1808b45d322cSThierry Reding i-cache-line-size = <64>; 1809b45d322cSThierry Reding i-cache-sets = <512>; 1810b45d322cSThierry Reding d-cache-size = <65536>; 1811b45d322cSThierry Reding d-cache-line-size = <64>; 1812b45d322cSThierry Reding d-cache-sets = <256>; 1813b45d322cSThierry Reding next-level-cache = <&l2c_0>; 18147780a034SMikko Perttunen }; 18157780a034SMikko Perttunen 1816b45d322cSThierry Reding cpu1_0: cpu@100 { 181731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18187780a034SMikko Perttunen device_type = "cpu"; 18197780a034SMikko Perttunen reg = <0x100>; 18207780a034SMikko Perttunen enable-method = "psci"; 1821b45d322cSThierry Reding i-cache-size = <131072>; 1822b45d322cSThierry Reding i-cache-line-size = <64>; 1823b45d322cSThierry Reding i-cache-sets = <512>; 1824b45d322cSThierry Reding d-cache-size = <65536>; 1825b45d322cSThierry Reding d-cache-line-size = <64>; 1826b45d322cSThierry Reding d-cache-sets = <256>; 1827b45d322cSThierry Reding next-level-cache = <&l2c_1>; 18287780a034SMikko Perttunen }; 18297780a034SMikko Perttunen 1830b45d322cSThierry Reding cpu1_1: cpu@101 { 183131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18327780a034SMikko Perttunen device_type = "cpu"; 18337780a034SMikko Perttunen reg = <0x101>; 18347780a034SMikko Perttunen enable-method = "psci"; 1835b45d322cSThierry Reding i-cache-size = <131072>; 1836b45d322cSThierry Reding i-cache-line-size = <64>; 1837b45d322cSThierry Reding i-cache-sets = <512>; 1838b45d322cSThierry Reding d-cache-size = <65536>; 1839b45d322cSThierry Reding d-cache-line-size = <64>; 1840b45d322cSThierry Reding d-cache-sets = <256>; 1841b45d322cSThierry Reding next-level-cache = <&l2c_1>; 18427780a034SMikko Perttunen }; 18437780a034SMikko Perttunen 1844b45d322cSThierry Reding cpu2_0: cpu@200 { 184531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18467780a034SMikko Perttunen device_type = "cpu"; 18477780a034SMikko Perttunen reg = <0x200>; 18487780a034SMikko Perttunen enable-method = "psci"; 1849b45d322cSThierry Reding i-cache-size = <131072>; 1850b45d322cSThierry Reding i-cache-line-size = <64>; 1851b45d322cSThierry Reding i-cache-sets = <512>; 1852b45d322cSThierry Reding d-cache-size = <65536>; 1853b45d322cSThierry Reding d-cache-line-size = <64>; 1854b45d322cSThierry Reding d-cache-sets = <256>; 1855b45d322cSThierry Reding next-level-cache = <&l2c_2>; 18567780a034SMikko Perttunen }; 18577780a034SMikko Perttunen 1858b45d322cSThierry Reding cpu2_1: cpu@201 { 185931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18607780a034SMikko Perttunen device_type = "cpu"; 18617780a034SMikko Perttunen reg = <0x201>; 18627780a034SMikko Perttunen enable-method = "psci"; 1863b45d322cSThierry Reding i-cache-size = <131072>; 1864b45d322cSThierry Reding i-cache-line-size = <64>; 1865b45d322cSThierry Reding i-cache-sets = <512>; 1866b45d322cSThierry Reding d-cache-size = <65536>; 1867b45d322cSThierry Reding d-cache-line-size = <64>; 1868b45d322cSThierry Reding d-cache-sets = <256>; 1869b45d322cSThierry Reding next-level-cache = <&l2c_2>; 18707780a034SMikko Perttunen }; 18717780a034SMikko Perttunen 1872b45d322cSThierry Reding cpu3_0: cpu@300 { 187331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18747780a034SMikko Perttunen device_type = "cpu"; 1875b45d322cSThierry Reding reg = <0x300>; 18767780a034SMikko Perttunen enable-method = "psci"; 1877b45d322cSThierry Reding i-cache-size = <131072>; 1878b45d322cSThierry Reding i-cache-line-size = <64>; 1879b45d322cSThierry Reding i-cache-sets = <512>; 1880b45d322cSThierry Reding d-cache-size = <65536>; 1881b45d322cSThierry Reding d-cache-line-size = <64>; 1882b45d322cSThierry Reding d-cache-sets = <256>; 1883b45d322cSThierry Reding next-level-cache = <&l2c_3>; 18847780a034SMikko Perttunen }; 18857780a034SMikko Perttunen 1886b45d322cSThierry Reding cpu3_1: cpu@301 { 188731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 18887780a034SMikko Perttunen device_type = "cpu"; 1889b45d322cSThierry Reding reg = <0x301>; 18907780a034SMikko Perttunen enable-method = "psci"; 1891b45d322cSThierry Reding i-cache-size = <131072>; 1892b45d322cSThierry Reding i-cache-line-size = <64>; 1893b45d322cSThierry Reding i-cache-sets = <512>; 1894b45d322cSThierry Reding d-cache-size = <65536>; 1895b45d322cSThierry Reding d-cache-line-size = <64>; 1896b45d322cSThierry Reding d-cache-sets = <256>; 1897b45d322cSThierry Reding next-level-cache = <&l2c_3>; 1898b45d322cSThierry Reding }; 1899b45d322cSThierry Reding 1900b45d322cSThierry Reding cpu-map { 1901b45d322cSThierry Reding cluster0 { 1902b45d322cSThierry Reding core0 { 1903b45d322cSThierry Reding cpu = <&cpu0_0>; 1904b45d322cSThierry Reding }; 1905b45d322cSThierry Reding 1906b45d322cSThierry Reding core1 { 1907b45d322cSThierry Reding cpu = <&cpu0_1>; 1908b45d322cSThierry Reding }; 1909b45d322cSThierry Reding }; 1910b45d322cSThierry Reding 1911b45d322cSThierry Reding cluster1 { 1912b45d322cSThierry Reding core0 { 1913b45d322cSThierry Reding cpu = <&cpu1_0>; 1914b45d322cSThierry Reding }; 1915b45d322cSThierry Reding 1916b45d322cSThierry Reding core1 { 1917b45d322cSThierry Reding cpu = <&cpu1_1>; 1918b45d322cSThierry Reding }; 1919b45d322cSThierry Reding }; 1920b45d322cSThierry Reding 1921b45d322cSThierry Reding cluster2 { 1922b45d322cSThierry Reding core0 { 1923b45d322cSThierry Reding cpu = <&cpu2_0>; 1924b45d322cSThierry Reding }; 1925b45d322cSThierry Reding 1926b45d322cSThierry Reding core1 { 1927b45d322cSThierry Reding cpu = <&cpu2_1>; 1928b45d322cSThierry Reding }; 1929b45d322cSThierry Reding }; 1930b45d322cSThierry Reding 1931b45d322cSThierry Reding cluster3 { 1932b45d322cSThierry Reding core0 { 1933b45d322cSThierry Reding cpu = <&cpu3_0>; 1934b45d322cSThierry Reding }; 1935b45d322cSThierry Reding 1936b45d322cSThierry Reding core1 { 1937b45d322cSThierry Reding cpu = <&cpu3_1>; 1938b45d322cSThierry Reding }; 1939b45d322cSThierry Reding }; 1940b45d322cSThierry Reding }; 1941b45d322cSThierry Reding 1942b45d322cSThierry Reding l2c_0: l2-cache0 { 1943b45d322cSThierry Reding cache-size = <2097152>; 1944b45d322cSThierry Reding cache-line-size = <64>; 1945b45d322cSThierry Reding cache-sets = <2048>; 1946b45d322cSThierry Reding next-level-cache = <&l3c>; 1947b45d322cSThierry Reding }; 1948b45d322cSThierry Reding 1949b45d322cSThierry Reding l2c_1: l2-cache1 { 1950b45d322cSThierry Reding cache-size = <2097152>; 1951b45d322cSThierry Reding cache-line-size = <64>; 1952b45d322cSThierry Reding cache-sets = <2048>; 1953b45d322cSThierry Reding next-level-cache = <&l3c>; 1954b45d322cSThierry Reding }; 1955b45d322cSThierry Reding 1956b45d322cSThierry Reding l2c_2: l2-cache2 { 1957b45d322cSThierry Reding cache-size = <2097152>; 1958b45d322cSThierry Reding cache-line-size = <64>; 1959b45d322cSThierry Reding cache-sets = <2048>; 1960b45d322cSThierry Reding next-level-cache = <&l3c>; 1961b45d322cSThierry Reding }; 1962b45d322cSThierry Reding 1963b45d322cSThierry Reding l2c_3: l2-cache3 { 1964b45d322cSThierry Reding cache-size = <2097152>; 1965b45d322cSThierry Reding cache-line-size = <64>; 1966b45d322cSThierry Reding cache-sets = <2048>; 1967b45d322cSThierry Reding next-level-cache = <&l3c>; 1968b45d322cSThierry Reding }; 1969b45d322cSThierry Reding 1970b45d322cSThierry Reding l3c: l3-cache { 1971b45d322cSThierry Reding cache-size = <4194304>; 1972b45d322cSThierry Reding cache-line-size = <64>; 1973b45d322cSThierry Reding cache-sets = <4096>; 19747780a034SMikko Perttunen }; 19757780a034SMikko Perttunen }; 19767780a034SMikko Perttunen 19777780a034SMikko Perttunen psci { 19787780a034SMikko Perttunen compatible = "arm,psci-1.0"; 19797780a034SMikko Perttunen status = "okay"; 19807780a034SMikko Perttunen method = "smc"; 19817780a034SMikko Perttunen }; 19827780a034SMikko Perttunen 1983a38570c2SMikko Perttunen tcu: tcu { 1984a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 1985a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1986a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1987a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 1988a38570c2SMikko Perttunen }; 1989a38570c2SMikko Perttunen 1990686ba009SThierry Reding thermal-zones { 1991686ba009SThierry Reding cpu { 1992686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1993686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1994686ba009SThierry Reding status = "disabled"; 1995686ba009SThierry Reding }; 1996686ba009SThierry Reding 1997686ba009SThierry Reding gpu { 1998686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1999686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2000686ba009SThierry Reding status = "disabled"; 2001686ba009SThierry Reding }; 2002686ba009SThierry Reding 2003686ba009SThierry Reding aux { 2004686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2005686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2006686ba009SThierry Reding status = "disabled"; 2007686ba009SThierry Reding }; 2008686ba009SThierry Reding 2009686ba009SThierry Reding pllx { 2010686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2011686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2012686ba009SThierry Reding status = "disabled"; 2013686ba009SThierry Reding }; 2014686ba009SThierry Reding 2015686ba009SThierry Reding ao { 2016686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2017686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2018686ba009SThierry Reding status = "disabled"; 2019686ba009SThierry Reding }; 2020686ba009SThierry Reding 2021686ba009SThierry Reding tj { 2022686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2023686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2024686ba009SThierry Reding status = "disabled"; 2025686ba009SThierry Reding }; 2026686ba009SThierry Reding }; 2027686ba009SThierry Reding 20285425fb15SMikko Perttunen timer { 20295425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 20305425fb15SMikko Perttunen interrupts = <GIC_PPI 13 20315425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 20325425fb15SMikko Perttunen <GIC_PPI 14 20335425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 20345425fb15SMikko Perttunen <GIC_PPI 11 20355425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 20365425fb15SMikko Perttunen <GIC_PPI 10 20375425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 20385425fb15SMikko Perttunen interrupt-parent = <&gic>; 2039b30be673SThierry Reding always-on; 20405425fb15SMikko Perttunen }; 20415425fb15SMikko Perttunen}; 2042