15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 22*2838cfddSThierry Reding 23*2838cfddSThierry Reding #address-cells = <2>; 24*2838cfddSThierry Reding #size-cells = <2>; 25*2838cfddSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 265425fb15SMikko Perttunen 27a47e173eSSumit Gupta apbmisc: misc@100000 { 2809903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 29*2838cfddSThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 30*2838cfddSThierry Reding <0x0 0x0010f000 0x0 0x1000>; 3109903c5eSJC Kuo }; 3209903c5eSJC Kuo 33f69ce393SMikko Perttunen gpio: gpio@2200000 { 34f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 35f69ce393SMikko Perttunen reg-names = "security", "gpio"; 36*2838cfddSThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 37*2838cfddSThierry Reding <0x0 0x2210000 0x0 0x10000>; 38f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 450a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 530a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 610a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 690a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 850a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86f69ce393SMikko Perttunen #interrupt-cells = <2>; 87f69ce393SMikko Perttunen interrupt-controller; 88f69ce393SMikko Perttunen #gpio-cells = <2>; 89f69ce393SMikko Perttunen gpio-controller; 906f380a4eSThierry Reding gpio-ranges = <&pinmux 0 0 169>; 91f69ce393SMikko Perttunen }; 92f69ce393SMikko Perttunen 93a47e173eSSumit Gupta cbb-noc@2300000 { 94a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 95*2838cfddSThierry Reding reg = <0x0 0x02300000 0x0 0x1000>; 96a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 99a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 100a47e173eSSumit Gupta status = "okay"; 101a47e173eSSumit Gupta }; 102a47e173eSSumit Gupta 103a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 104a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 105*2838cfddSThierry Reding reg = <0x0 0x2390000 0x0 0x1000>, 106*2838cfddSThierry Reding <0x0 0x23a0000 0x0 0x1000>, 107*2838cfddSThierry Reding <0x0 0x23b0000 0x0 0x1000>, 108*2838cfddSThierry Reding <0x0 0x23c0000 0x0 0x1000>, 109*2838cfddSThierry Reding <0x0 0x23d0000 0x0 0x1000>, 110*2838cfddSThierry Reding <0x0 0x23e0000 0x0 0x1000>; 111a47e173eSSumit Gupta status = "okay"; 112a47e173eSSumit Gupta }; 113a47e173eSSumit Gupta 114f89b58ceSMikko Perttunen ethernet@2490000 { 11519dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 11619dc772aSThierry Reding "nvidia,tegra186-eqos", 117f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 118*2838cfddSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 119f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 120f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 121f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 122f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 123f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 124f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 125f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 126f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 127f89b58ceSMikko Perttunen reset-names = "eqos"; 128d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 129d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 130d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 131c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 132f89b58ceSMikko Perttunen status = "disabled"; 133f89b58ceSMikko Perttunen 134f89b58ceSMikko Perttunen snps,write-requests = <1>; 135f89b58ceSMikko Perttunen snps,read-requests = <3>; 136f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 137f89b58ceSMikko Perttunen snps,txpbl = <16>; 138f89b58ceSMikko Perttunen snps,rxpbl = <8>; 139f89b58ceSMikko Perttunen }; 140f89b58ceSMikko Perttunen 141835553b3SAkhil R gpcdma: dma-controller@2600000 { 142835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 143835553b3SAkhil R "nvidia,tegra186-gpcdma"; 144*2838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 145835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 146835553b3SAkhil R reset-names = "gpcdma"; 147dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 148dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 155835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 156835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 157835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 158835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 159835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 160835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 161835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 162835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 163835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 164835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 165835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 166835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 167835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 168835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 169835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 170835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 171835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 172835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 173835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 174835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 175835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 176835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 177835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 178835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 179835553b3SAkhil R #dma-cells = <1>; 180835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 181835553b3SAkhil R dma-coherent; 182dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 183835553b3SAkhil R status = "okay"; 184835553b3SAkhil R }; 185835553b3SAkhil R 1861aaa7698SThierry Reding aconnect@2900000 { 1875d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1885d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1895d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1905d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1915d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1925d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1935d2249ddSSameer Pujar status = "disabled"; 1945d2249ddSSameer Pujar 195*2838cfddSThierry Reding #address-cells = <2>; 196*2838cfddSThierry Reding #size-cells = <2>; 197*2838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 198*2838cfddSThierry Reding 199177208f7SSameer Pujar adma: dma-controller@2930000 { 2005d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 2015d2249ddSSameer Pujar "nvidia,tegra186-adma"; 202*2838cfddSThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 2035d2249ddSSameer Pujar interrupt-parent = <&agic>; 2045d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2105d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2115d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2125d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2135d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2145d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2155d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2165d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2175d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2185d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2195d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2205d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2215d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2225d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2235d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2245d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2255d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2265d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2275d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2285d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2295d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2305d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2315d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2325d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2335d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2345d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2355d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2365d2249ddSSameer Pujar #dma-cells = <1>; 2375d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2385d2249ddSSameer Pujar clock-names = "d_audio"; 2395d2249ddSSameer Pujar status = "disabled"; 2405d2249ddSSameer Pujar }; 2415d2249ddSSameer Pujar 2425d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2435d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2445d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2455d2249ddSSameer Pujar #interrupt-cells = <3>; 2465d2249ddSSameer Pujar interrupt-controller; 247*2838cfddSThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 248*2838cfddSThierry Reding <0x0 0x02a42000 0x0 0x2000>; 2495d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2505d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2515d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2525d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2535d2249ddSSameer Pujar clock-names = "clk"; 2545d2249ddSSameer Pujar status = "disabled"; 2555d2249ddSSameer Pujar }; 256177208f7SSameer Pujar 257177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 258177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 259177208f7SSameer Pujar "nvidia,tegra186-ahub"; 260*2838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 261177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 262177208f7SSameer Pujar clock-names = "ahub"; 263177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 264177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 265177208f7SSameer Pujar status = "disabled"; 266177208f7SSameer Pujar 267*2838cfddSThierry Reding #address-cells = <2>; 268*2838cfddSThierry Reding #size-cells = <2>; 269*2838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 270*2838cfddSThierry Reding 271177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 272177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 273177208f7SSameer Pujar "nvidia,tegra186-admaif"; 274*2838cfddSThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 275177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 276177208f7SSameer Pujar <&adma 2>, <&adma 2>, 277177208f7SSameer Pujar <&adma 3>, <&adma 3>, 278177208f7SSameer Pujar <&adma 4>, <&adma 4>, 279177208f7SSameer Pujar <&adma 5>, <&adma 5>, 280177208f7SSameer Pujar <&adma 6>, <&adma 6>, 281177208f7SSameer Pujar <&adma 7>, <&adma 7>, 282177208f7SSameer Pujar <&adma 8>, <&adma 8>, 283177208f7SSameer Pujar <&adma 9>, <&adma 9>, 284177208f7SSameer Pujar <&adma 10>, <&adma 10>, 285177208f7SSameer Pujar <&adma 11>, <&adma 11>, 286177208f7SSameer Pujar <&adma 12>, <&adma 12>, 287177208f7SSameer Pujar <&adma 13>, <&adma 13>, 288177208f7SSameer Pujar <&adma 14>, <&adma 14>, 289177208f7SSameer Pujar <&adma 15>, <&adma 15>, 290177208f7SSameer Pujar <&adma 16>, <&adma 16>, 291177208f7SSameer Pujar <&adma 17>, <&adma 17>, 292177208f7SSameer Pujar <&adma 18>, <&adma 18>, 293177208f7SSameer Pujar <&adma 19>, <&adma 19>, 294177208f7SSameer Pujar <&adma 20>, <&adma 20>; 295177208f7SSameer Pujar dma-names = "rx1", "tx1", 296177208f7SSameer Pujar "rx2", "tx2", 297177208f7SSameer Pujar "rx3", "tx3", 298177208f7SSameer Pujar "rx4", "tx4", 299177208f7SSameer Pujar "rx5", "tx5", 300177208f7SSameer Pujar "rx6", "tx6", 301177208f7SSameer Pujar "rx7", "tx7", 302177208f7SSameer Pujar "rx8", "tx8", 303177208f7SSameer Pujar "rx9", "tx9", 304177208f7SSameer Pujar "rx10", "tx10", 305177208f7SSameer Pujar "rx11", "tx11", 306177208f7SSameer Pujar "rx12", "tx12", 307177208f7SSameer Pujar "rx13", "tx13", 308177208f7SSameer Pujar "rx14", "tx14", 309177208f7SSameer Pujar "rx15", "tx15", 310177208f7SSameer Pujar "rx16", "tx16", 311177208f7SSameer Pujar "rx17", "tx17", 312177208f7SSameer Pujar "rx18", "tx18", 313177208f7SSameer Pujar "rx19", "tx19", 314177208f7SSameer Pujar "rx20", "tx20"; 315177208f7SSameer Pujar status = "disabled"; 316cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 317cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 318cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 319cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 320177208f7SSameer Pujar }; 321177208f7SSameer Pujar 322177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 323177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 324177208f7SSameer Pujar "nvidia,tegra210-i2s"; 325*2838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 326177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 327177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 328177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 329177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 330177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 331177208f7SSameer Pujar assigned-clock-rates = <1536000>; 332177208f7SSameer Pujar sound-name-prefix = "I2S1"; 333177208f7SSameer Pujar status = "disabled"; 334177208f7SSameer Pujar }; 335177208f7SSameer Pujar 336177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 337177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 338177208f7SSameer Pujar "nvidia,tegra210-i2s"; 339*2838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 340177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 341177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 342177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 343177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 344177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 345177208f7SSameer Pujar assigned-clock-rates = <1536000>; 346177208f7SSameer Pujar sound-name-prefix = "I2S2"; 347177208f7SSameer Pujar status = "disabled"; 348177208f7SSameer Pujar }; 349177208f7SSameer Pujar 350177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 351177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 352177208f7SSameer Pujar "nvidia,tegra210-i2s"; 353*2838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 354177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 355177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 356177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 357177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 358177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 359177208f7SSameer Pujar assigned-clock-rates = <1536000>; 360177208f7SSameer Pujar sound-name-prefix = "I2S3"; 361177208f7SSameer Pujar status = "disabled"; 362177208f7SSameer Pujar }; 363177208f7SSameer Pujar 364177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 365177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 366177208f7SSameer Pujar "nvidia,tegra210-i2s"; 367*2838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 368177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 369177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 370177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 371177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 372177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 373177208f7SSameer Pujar assigned-clock-rates = <1536000>; 374177208f7SSameer Pujar sound-name-prefix = "I2S4"; 375177208f7SSameer Pujar status = "disabled"; 376177208f7SSameer Pujar }; 377177208f7SSameer Pujar 378177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 379177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 380177208f7SSameer Pujar "nvidia,tegra210-i2s"; 381*2838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 382177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 383177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 384177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 385177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 386177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387177208f7SSameer Pujar assigned-clock-rates = <1536000>; 388177208f7SSameer Pujar sound-name-prefix = "I2S5"; 389177208f7SSameer Pujar status = "disabled"; 390177208f7SSameer Pujar }; 391177208f7SSameer Pujar 392177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 393177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 394177208f7SSameer Pujar "nvidia,tegra210-i2s"; 395*2838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 396177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 397177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 398177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 399177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 400177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 401177208f7SSameer Pujar assigned-clock-rates = <1536000>; 402177208f7SSameer Pujar sound-name-prefix = "I2S6"; 403177208f7SSameer Pujar status = "disabled"; 404177208f7SSameer Pujar }; 405177208f7SSameer Pujar 406177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 407177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 408177208f7SSameer Pujar "nvidia,tegra210-dmic"; 409*2838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 410177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 411177208f7SSameer Pujar clock-names = "dmic"; 412177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 413177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 414177208f7SSameer Pujar assigned-clock-rates = <3072000>; 415177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 416177208f7SSameer Pujar status = "disabled"; 417177208f7SSameer Pujar }; 418177208f7SSameer Pujar 419177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 420177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 421177208f7SSameer Pujar "nvidia,tegra210-dmic"; 422*2838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 423177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 424177208f7SSameer Pujar clock-names = "dmic"; 425177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 426177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 427177208f7SSameer Pujar assigned-clock-rates = <3072000>; 428177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 429177208f7SSameer Pujar status = "disabled"; 430177208f7SSameer Pujar }; 431177208f7SSameer Pujar 432177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 433177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 434177208f7SSameer Pujar "nvidia,tegra210-dmic"; 435*2838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 436177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 437177208f7SSameer Pujar clock-names = "dmic"; 438177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 439177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 440177208f7SSameer Pujar assigned-clock-rates = <3072000>; 441177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 442177208f7SSameer Pujar status = "disabled"; 443177208f7SSameer Pujar }; 444177208f7SSameer Pujar 445177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 446177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 447177208f7SSameer Pujar "nvidia,tegra210-dmic"; 448*2838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 449177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 450177208f7SSameer Pujar clock-names = "dmic"; 451177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 452177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 453177208f7SSameer Pujar assigned-clock-rates = <3072000>; 454177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 455177208f7SSameer Pujar status = "disabled"; 456177208f7SSameer Pujar }; 457177208f7SSameer Pujar 458177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 459177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 460177208f7SSameer Pujar "nvidia,tegra186-dspk"; 461*2838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 462177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 463177208f7SSameer Pujar clock-names = "dspk"; 464177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 465177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 466177208f7SSameer Pujar assigned-clock-rates = <12288000>; 467177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 468177208f7SSameer Pujar status = "disabled"; 469177208f7SSameer Pujar }; 470177208f7SSameer Pujar 471177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 472177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 473177208f7SSameer Pujar "nvidia,tegra186-dspk"; 474*2838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 475177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 476177208f7SSameer Pujar clock-names = "dspk"; 477177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 478177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 479177208f7SSameer Pujar assigned-clock-rates = <12288000>; 480177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 481177208f7SSameer Pujar status = "disabled"; 482177208f7SSameer Pujar }; 483848f3290SSameer Pujar 484848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 485848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 486848f3290SSameer Pujar "nvidia,tegra210-sfc"; 487*2838cfddSThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 488848f3290SSameer Pujar sound-name-prefix = "SFC1"; 489848f3290SSameer Pujar status = "disabled"; 490848f3290SSameer Pujar }; 491848f3290SSameer Pujar 492848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 493848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 494848f3290SSameer Pujar "nvidia,tegra210-sfc"; 495*2838cfddSThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 496848f3290SSameer Pujar sound-name-prefix = "SFC2"; 497848f3290SSameer Pujar status = "disabled"; 498848f3290SSameer Pujar }; 499848f3290SSameer Pujar 500848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 501848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 502848f3290SSameer Pujar "nvidia,tegra210-sfc"; 503*2838cfddSThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 504848f3290SSameer Pujar sound-name-prefix = "SFC3"; 505848f3290SSameer Pujar status = "disabled"; 506848f3290SSameer Pujar }; 507848f3290SSameer Pujar 508848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 509848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 510848f3290SSameer Pujar "nvidia,tegra210-sfc"; 511*2838cfddSThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 512848f3290SSameer Pujar sound-name-prefix = "SFC4"; 513848f3290SSameer Pujar status = "disabled"; 514848f3290SSameer Pujar }; 515848f3290SSameer Pujar 516848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 517848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 518848f3290SSameer Pujar "nvidia,tegra210-mvc"; 519*2838cfddSThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 520848f3290SSameer Pujar sound-name-prefix = "MVC1"; 521848f3290SSameer Pujar status = "disabled"; 522848f3290SSameer Pujar }; 523848f3290SSameer Pujar 524848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 525848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 526848f3290SSameer Pujar "nvidia,tegra210-mvc"; 527*2838cfddSThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 528848f3290SSameer Pujar sound-name-prefix = "MVC2"; 529848f3290SSameer Pujar status = "disabled"; 530848f3290SSameer Pujar }; 531848f3290SSameer Pujar 532848f3290SSameer Pujar tegra_amx1: amx@2903000 { 533848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 534*2838cfddSThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 535848f3290SSameer Pujar sound-name-prefix = "AMX1"; 536848f3290SSameer Pujar status = "disabled"; 537848f3290SSameer Pujar }; 538848f3290SSameer Pujar 539848f3290SSameer Pujar tegra_amx2: amx@2903100 { 540848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 541*2838cfddSThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 542848f3290SSameer Pujar sound-name-prefix = "AMX2"; 543848f3290SSameer Pujar status = "disabled"; 544848f3290SSameer Pujar }; 545848f3290SSameer Pujar 546848f3290SSameer Pujar tegra_amx3: amx@2903200 { 547848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 548*2838cfddSThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 549848f3290SSameer Pujar sound-name-prefix = "AMX3"; 550848f3290SSameer Pujar status = "disabled"; 551848f3290SSameer Pujar }; 552848f3290SSameer Pujar 553848f3290SSameer Pujar tegra_amx4: amx@2903300 { 554848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 555*2838cfddSThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 556848f3290SSameer Pujar sound-name-prefix = "AMX4"; 557848f3290SSameer Pujar status = "disabled"; 558848f3290SSameer Pujar }; 559848f3290SSameer Pujar 560848f3290SSameer Pujar tegra_adx1: adx@2903800 { 561848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 562848f3290SSameer Pujar "nvidia,tegra210-adx"; 563*2838cfddSThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 564848f3290SSameer Pujar sound-name-prefix = "ADX1"; 565848f3290SSameer Pujar status = "disabled"; 566848f3290SSameer Pujar }; 567848f3290SSameer Pujar 568848f3290SSameer Pujar tegra_adx2: adx@2903900 { 569848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 570848f3290SSameer Pujar "nvidia,tegra210-adx"; 571*2838cfddSThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 572848f3290SSameer Pujar sound-name-prefix = "ADX2"; 573848f3290SSameer Pujar status = "disabled"; 574848f3290SSameer Pujar }; 575848f3290SSameer Pujar 576848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 577848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 578848f3290SSameer Pujar "nvidia,tegra210-adx"; 579*2838cfddSThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 580848f3290SSameer Pujar sound-name-prefix = "ADX3"; 581848f3290SSameer Pujar status = "disabled"; 582848f3290SSameer Pujar }; 583848f3290SSameer Pujar 584848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 585848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 586848f3290SSameer Pujar "nvidia,tegra210-adx"; 587*2838cfddSThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 588848f3290SSameer Pujar sound-name-prefix = "ADX4"; 589848f3290SSameer Pujar status = "disabled"; 590848f3290SSameer Pujar }; 591848f3290SSameer Pujar 5924b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5934b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 5944b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 595*2838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 5964b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5974b6a1b7cSSameer Pujar status = "disabled"; 5984b6a1b7cSSameer Pujar 599*2838cfddSThierry Reding #address-cells = <2>; 600*2838cfddSThierry Reding #size-cells = <2>; 601*2838cfddSThierry Reding ranges; 602*2838cfddSThierry Reding 6034b6a1b7cSSameer Pujar equalizer@2908100 { 6044b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 6054b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 606*2838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 6074b6a1b7cSSameer Pujar }; 6084b6a1b7cSSameer Pujar 6094b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 6104b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 6114b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 612*2838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 6134b6a1b7cSSameer Pujar }; 6144b6a1b7cSSameer Pujar }; 6154b6a1b7cSSameer Pujar 616848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 617848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 618848f3290SSameer Pujar "nvidia,tegra210-amixer"; 619*2838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 620848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 621848f3290SSameer Pujar status = "disabled"; 622848f3290SSameer Pujar }; 62347a08153SSameer Pujar 62447a08153SSameer Pujar tegra_asrc: asrc@2910000 { 62547a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 62647a08153SSameer Pujar "nvidia,tegra186-asrc"; 627*2838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 62847a08153SSameer Pujar sound-name-prefix = "ASRC1"; 62947a08153SSameer Pujar status = "disabled"; 63047a08153SSameer Pujar }; 631177208f7SSameer Pujar }; 6325d2249ddSSameer Pujar }; 6335d2249ddSSameer Pujar 634dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 635dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 636*2838cfddSThierry Reding reg = <0x0 0x2430000 0x0 0x17000>; 637dbb72e2cSVidya Sagar status = "okay"; 638dbb72e2cSVidya Sagar 639efe499d8SThierry Reding pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 640dbb72e2cSVidya Sagar pex_rst { 641dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 642dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 643dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6446b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 645dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 646dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 647dbb72e2cSVidya Sagar }; 648dbb72e2cSVidya Sagar }; 649dbb72e2cSVidya Sagar 650efe499d8SThierry Reding clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { 651dbb72e2cSVidya Sagar clkreq { 652dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 653dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 654dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 6556b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 656dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 657dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 658dbb72e2cSVidya Sagar }; 659dbb72e2cSVidya Sagar }; 660dbb72e2cSVidya Sagar }; 661dbb72e2cSVidya Sagar 662be9b887fSThierry Reding mc: memory-controller@2c00000 { 663be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 664*2838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665*2838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666*2838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667*2838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668*2838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669*2838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670*2838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671*2838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672*2838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673*2838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674*2838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675*2838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676*2838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677*2838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678*2838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679*2838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680*2838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681*2838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6858613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686d5237c7cSThierry Reding #interconnect-cells = <1>; 687be9b887fSThierry Reding status = "disabled"; 688be9b887fSThierry Reding 689be9b887fSThierry Reding #address-cells = <2>; 690be9b887fSThierry Reding #size-cells = <2>; 691*2838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692*2838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693*2838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694be9b887fSThierry Reding 695be9b887fSThierry Reding /* 696be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 697be9b887fSThierry Reding * controller selects the XBAR format used when memory 698be9b887fSThierry Reding * is accessed. This is used to transparently access 699be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 700be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 701be9b887fSThierry Reding * 702be9b887fSThierry Reding * As a consequence, the operating system must ensure 703be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 704be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 705be9b887fSThierry Reding * devices require access to the XBAR switch, their 706be9b887fSThierry Reding * drivers must set this bit explicitly. 707be9b887fSThierry Reding * 708be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 709be9b887fSThierry Reding */ 710*2838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711be9b887fSThierry Reding 712be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 713be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 714be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 715be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 716cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 718be9b887fSThierry Reding clock-names = "emc"; 719be9b887fSThierry Reding 720d5237c7cSThierry Reding #interconnect-cells = <0>; 721d5237c7cSThierry Reding 722be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 723be9b887fSThierry Reding }; 724be9b887fSThierry Reding }; 725be9b887fSThierry Reding 7265aa9083eSThierry Reding timer@3010000 { 7275aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 728*2838cfddSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 7295aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7305aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7345aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7355aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7365aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7375aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7385aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7395aa9083eSThierry Reding status = "okay"; 7405aa9083eSThierry Reding }; 7415aa9083eSThierry Reding 7425425fb15SMikko Perttunen uarta: serial@3100000 { 7435425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744*2838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x40>; 7455425fb15SMikko Perttunen reg-shift = <2>; 7465425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7475425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7485425fb15SMikko Perttunen clock-names = "serial"; 7495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7505425fb15SMikko Perttunen reset-names = "serial"; 7515425fb15SMikko Perttunen status = "disabled"; 7525425fb15SMikko Perttunen }; 7535425fb15SMikko Perttunen 7545425fb15SMikko Perttunen uartb: serial@3110000 { 7555425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 756*2838cfddSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 7575425fb15SMikko Perttunen reg-shift = <2>; 7585425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7595425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7605425fb15SMikko Perttunen clock-names = "serial"; 7615425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7625425fb15SMikko Perttunen reset-names = "serial"; 7635425fb15SMikko Perttunen status = "disabled"; 7645425fb15SMikko Perttunen }; 7655425fb15SMikko Perttunen 7665425fb15SMikko Perttunen uartd: serial@3130000 { 7675425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 768*2838cfddSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 7695425fb15SMikko Perttunen reg-shift = <2>; 7705425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7725425fb15SMikko Perttunen clock-names = "serial"; 7735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7745425fb15SMikko Perttunen reset-names = "serial"; 7755425fb15SMikko Perttunen status = "disabled"; 7765425fb15SMikko Perttunen }; 7775425fb15SMikko Perttunen 7785425fb15SMikko Perttunen uarte: serial@3140000 { 7795425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 780*2838cfddSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 7815425fb15SMikko Perttunen reg-shift = <2>; 7825425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7845425fb15SMikko Perttunen clock-names = "serial"; 7855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7865425fb15SMikko Perttunen reset-names = "serial"; 7875425fb15SMikko Perttunen status = "disabled"; 7885425fb15SMikko Perttunen }; 7895425fb15SMikko Perttunen 7905425fb15SMikko Perttunen uartf: serial@3150000 { 7915425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 792*2838cfddSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 7935425fb15SMikko Perttunen reg-shift = <2>; 7945425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7965425fb15SMikko Perttunen clock-names = "serial"; 7975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7985425fb15SMikko Perttunen reset-names = "serial"; 7995425fb15SMikko Perttunen status = "disabled"; 8005425fb15SMikko Perttunen }; 8015425fb15SMikko Perttunen 8025425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 803d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 804*2838cfddSThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 8055425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8065425fb15SMikko Perttunen #address-cells = <1>; 8075425fb15SMikko Perttunen #size-cells = <0>; 8085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8095425fb15SMikko Perttunen clock-names = "div-clk"; 8105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8115425fb15SMikko Perttunen reset-names = "i2c"; 8128e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8138e442805SAkhil R dma-coherent; 8148e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8158e442805SAkhil R dma-names = "rx", "tx"; 8165425fb15SMikko Perttunen status = "disabled"; 8175425fb15SMikko Perttunen }; 8185425fb15SMikko Perttunen 8195425fb15SMikko Perttunen uarth: serial@3170000 { 8205425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 821*2838cfddSThierry Reding reg = <0x0 0x03170000 0x0 0x40>; 8225425fb15SMikko Perttunen reg-shift = <2>; 8235425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8245425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8255425fb15SMikko Perttunen clock-names = "serial"; 8265425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8275425fb15SMikko Perttunen reset-names = "serial"; 8285425fb15SMikko Perttunen status = "disabled"; 8295425fb15SMikko Perttunen }; 8305425fb15SMikko Perttunen 8315425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 832d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 833*2838cfddSThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 8345425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8355425fb15SMikko Perttunen #address-cells = <1>; 8365425fb15SMikko Perttunen #size-cells = <0>; 8375425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8385425fb15SMikko Perttunen clock-names = "div-clk"; 8395425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8405425fb15SMikko Perttunen reset-names = "i2c"; 8418e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8428e442805SAkhil R dma-coherent; 8438e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8448e442805SAkhil R dma-names = "rx", "tx"; 8455425fb15SMikko Perttunen status = "disabled"; 8465425fb15SMikko Perttunen }; 8475425fb15SMikko Perttunen 8485425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8495425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 850d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 851*2838cfddSThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 8525425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8535425fb15SMikko Perttunen #address-cells = <1>; 8545425fb15SMikko Perttunen #size-cells = <0>; 8555425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8565425fb15SMikko Perttunen clock-names = "div-clk"; 8575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8585425fb15SMikko Perttunen reset-names = "i2c"; 859a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 860a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 861a4131561SThierry Reding pinctrl-names = "default", "idle"; 8628e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8638e442805SAkhil R dma-coherent; 8648e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8658e442805SAkhil R dma-names = "rx", "tx"; 8665425fb15SMikko Perttunen status = "disabled"; 8675425fb15SMikko Perttunen }; 8685425fb15SMikko Perttunen 8695425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8705425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 871d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 872*2838cfddSThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 8735425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8745425fb15SMikko Perttunen #address-cells = <1>; 8755425fb15SMikko Perttunen #size-cells = <0>; 8765425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8775425fb15SMikko Perttunen clock-names = "div-clk"; 8785425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8795425fb15SMikko Perttunen reset-names = "i2c"; 880a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 881a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 882a4131561SThierry Reding pinctrl-names = "default", "idle"; 8838e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8848e442805SAkhil R dma-coherent; 8858e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8868e442805SAkhil R dma-names = "rx", "tx"; 8875425fb15SMikko Perttunen status = "disabled"; 8885425fb15SMikko Perttunen }; 8895425fb15SMikko Perttunen 890a4131561SThierry Reding /* shares pads with dpaux2 */ 891a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 892d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 893*2838cfddSThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 8945425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8955425fb15SMikko Perttunen #address-cells = <1>; 8965425fb15SMikko Perttunen #size-cells = <0>; 8975425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8985425fb15SMikko Perttunen clock-names = "div-clk"; 8995425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 9005425fb15SMikko Perttunen reset-names = "i2c"; 901a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 902a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 903a4131561SThierry Reding pinctrl-names = "default", "idle"; 9048e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9058e442805SAkhil R dma-coherent; 9068e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 9078e442805SAkhil R dma-names = "rx", "tx"; 9085425fb15SMikko Perttunen status = "disabled"; 9095425fb15SMikko Perttunen }; 9105425fb15SMikko Perttunen 911a4131561SThierry Reding /* shares pads with dpaux3 */ 912a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 913d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 914*2838cfddSThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 9155425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9165425fb15SMikko Perttunen #address-cells = <1>; 9175425fb15SMikko Perttunen #size-cells = <0>; 9185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9195425fb15SMikko Perttunen clock-names = "div-clk"; 9205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9215425fb15SMikko Perttunen reset-names = "i2c"; 922a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 923a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 924a4131561SThierry Reding pinctrl-names = "default", "idle"; 9258e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9268e442805SAkhil R dma-coherent; 9278e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9288e442805SAkhil R dma-names = "rx", "tx"; 9295425fb15SMikko Perttunen status = "disabled"; 9305425fb15SMikko Perttunen }; 9315425fb15SMikko Perttunen 93296ded827SSowjanya Komatineni spi@3270000 { 93396ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 934*2838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 93596ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 93696ded827SSowjanya Komatineni #address-cells = <1>; 93796ded827SSowjanya Komatineni #size-cells = <0>; 93896ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 93996ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 94096ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 94196ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 94296ded827SSowjanya Komatineni status = "disabled"; 94396ded827SSowjanya Komatineni }; 94496ded827SSowjanya Komatineni 94596ded827SSowjanya Komatineni spi@3300000 { 94696ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 947*2838cfddSThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 94896ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 94996ded827SSowjanya Komatineni #address-cells = <1>; 95096ded827SSowjanya Komatineni #size-cells = <0>; 95196ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 95296ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 95396ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 95496ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 95596ded827SSowjanya Komatineni status = "disabled"; 95696ded827SSowjanya Komatineni }; 95796ded827SSowjanya Komatineni 9586a574ec7SThierry Reding pwm1: pwm@3280000 { 9596a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9606a574ec7SThierry Reding "nvidia,tegra186-pwm"; 961*2838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 9626a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9636a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9646a574ec7SThierry Reding reset-names = "pwm"; 9656a574ec7SThierry Reding status = "disabled"; 9666a574ec7SThierry Reding #pwm-cells = <2>; 9676a574ec7SThierry Reding }; 9686a574ec7SThierry Reding 9696a574ec7SThierry Reding pwm2: pwm@3290000 { 9706a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9716a574ec7SThierry Reding "nvidia,tegra186-pwm"; 972*2838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 9736a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9746a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9756a574ec7SThierry Reding reset-names = "pwm"; 9766a574ec7SThierry Reding status = "disabled"; 9776a574ec7SThierry Reding #pwm-cells = <2>; 9786a574ec7SThierry Reding }; 9796a574ec7SThierry Reding 9806a574ec7SThierry Reding pwm3: pwm@32a0000 { 9816a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9826a574ec7SThierry Reding "nvidia,tegra186-pwm"; 983*2838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 9846a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9856a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9866a574ec7SThierry Reding reset-names = "pwm"; 9876a574ec7SThierry Reding status = "disabled"; 9886a574ec7SThierry Reding #pwm-cells = <2>; 9896a574ec7SThierry Reding }; 9906a574ec7SThierry Reding 9916a574ec7SThierry Reding pwm5: pwm@32c0000 { 9926a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9936a574ec7SThierry Reding "nvidia,tegra186-pwm"; 994*2838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 9956a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9966a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9976a574ec7SThierry Reding reset-names = "pwm"; 9986a574ec7SThierry Reding status = "disabled"; 9996a574ec7SThierry Reding #pwm-cells = <2>; 10006a574ec7SThierry Reding }; 10016a574ec7SThierry Reding 10026a574ec7SThierry Reding pwm6: pwm@32d0000 { 10036a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10046a574ec7SThierry Reding "nvidia,tegra186-pwm"; 1005*2838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 10066a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 10076a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 10086a574ec7SThierry Reding reset-names = "pwm"; 10096a574ec7SThierry Reding status = "disabled"; 10106a574ec7SThierry Reding #pwm-cells = <2>; 10116a574ec7SThierry Reding }; 10126a574ec7SThierry Reding 10136a574ec7SThierry Reding pwm7: pwm@32e0000 { 10146a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10156a574ec7SThierry Reding "nvidia,tegra186-pwm"; 1016*2838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 10176a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 10186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 10196a574ec7SThierry Reding reset-names = "pwm"; 10206a574ec7SThierry Reding status = "disabled"; 10216a574ec7SThierry Reding #pwm-cells = <2>; 10226a574ec7SThierry Reding }; 10236a574ec7SThierry Reding 10246a574ec7SThierry Reding pwm8: pwm@32f0000 { 10256a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10266a574ec7SThierry Reding "nvidia,tegra186-pwm"; 1027*2838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 10286a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10296a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10306a574ec7SThierry Reding reset-names = "pwm"; 10316a574ec7SThierry Reding status = "disabled"; 10326a574ec7SThierry Reding #pwm-cells = <2>; 10336a574ec7SThierry Reding }; 10346a574ec7SThierry Reding 103567bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10362c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 1037*2838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 10385425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1039c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1040c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1041c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10427ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10437ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10447ac853baSAniruddha Rao assigned-clock-parents = 10457ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10467ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10485425fb15SMikko Perttunen reset-names = "sdhci"; 1049d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1050d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1051d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1052c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1053ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1054ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1055ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10564e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10574e0f1229SSowjanya Komatineni <0x07>; 10584e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10594e0f1229SSowjanya Komatineni <0x07>; 10604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10624e0f1229SSowjanya Komatineni <0x07>; 10634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10644e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10654e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10664e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1067ff21087eSPrathamesh Shete sd-uhs-sdr25; 1068ff21087eSPrathamesh Shete sd-uhs-sdr50; 1069ff21087eSPrathamesh Shete sd-uhs-ddr50; 1070ff21087eSPrathamesh Shete sd-uhs-sdr104; 10715425fb15SMikko Perttunen status = "disabled"; 10725425fb15SMikko Perttunen }; 10735425fb15SMikko Perttunen 107467bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10752c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 1076*2838cfddSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 10775425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1078c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1079c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1080c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10817ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10827ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10837ac853baSAniruddha Rao assigned-clock-parents = 10847ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10857ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10865425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10875425fb15SMikko Perttunen reset-names = "sdhci"; 1088d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1089d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1090d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1091c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1092ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1093ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1094ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10994e0f1229SSowjanya Komatineni <0x07>; 11004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 11014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11024e0f1229SSowjanya Komatineni <0x07>; 11034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 11044e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 11054e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 11064e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1107ff21087eSPrathamesh Shete sd-uhs-sdr25; 1108ff21087eSPrathamesh Shete sd-uhs-sdr50; 1109ff21087eSPrathamesh Shete sd-uhs-ddr50; 1110ff21087eSPrathamesh Shete sd-uhs-sdr104; 11115425fb15SMikko Perttunen status = "disabled"; 11125425fb15SMikko Perttunen }; 11135425fb15SMikko Perttunen 111467bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11152c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 1116*2838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 11175425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1118c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1120c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1121351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1122351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1123351648d0SSowjanya Komatineni assigned-clock-parents = 1124351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11255425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11265425fb15SMikko Perttunen reset-names = "sdhci"; 1127d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1128d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1129d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1130c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11354e0f1229SSowjanya Komatineni <0x0a>; 11364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11374e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11384e0f1229SSowjanya Komatineni <0x0a>; 11394e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11404e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11414e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1142c2fee443SPrathamesh Shete cap-mmc-highspeed; 1143c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1144c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1145c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1146c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1147dfd3cb6fSSowjanya Komatineni supports-cqe; 11485425fb15SMikko Perttunen status = "disabled"; 11495425fb15SMikko Perttunen }; 11505425fb15SMikko Perttunen 11514878cc0cSSameer Pujar hda@3510000 { 11527f0ea5acSThierry Reding compatible = "nvidia,tegra194-hda"; 1153*2838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 11544878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11554878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 115648f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 115748f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 115848f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11594878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1160146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1161146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11624878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1163d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1164d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1165d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1166c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11674878cc0cSSameer Pujar status = "disabled"; 11684878cc0cSSameer Pujar }; 11694878cc0cSSameer Pujar 1170fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1171fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1172*2838cfddSThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 1173*2838cfddSThierry Reding <0x0 0x03540000 0x0 0x1000>; 1174fab7a039SJC Kuo reg-names = "padctl", "ao"; 11756450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1176fab7a039SJC Kuo 1177fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1178fab7a039SJC Kuo reset-names = "padctl"; 1179fab7a039SJC Kuo 1180fab7a039SJC Kuo status = "disabled"; 1181fab7a039SJC Kuo 1182fab7a039SJC Kuo pads { 1183fab7a039SJC Kuo usb2 { 1184fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1185fab7a039SJC Kuo clock-names = "trk"; 1186fab7a039SJC Kuo 1187fab7a039SJC Kuo lanes { 1188fab7a039SJC Kuo usb2-0 { 1189fab7a039SJC Kuo nvidia,function = "xusb"; 1190fab7a039SJC Kuo status = "disabled"; 1191fab7a039SJC Kuo #phy-cells = <0>; 1192fab7a039SJC Kuo }; 1193fab7a039SJC Kuo 1194fab7a039SJC Kuo usb2-1 { 1195fab7a039SJC Kuo nvidia,function = "xusb"; 1196fab7a039SJC Kuo status = "disabled"; 1197fab7a039SJC Kuo #phy-cells = <0>; 1198fab7a039SJC Kuo }; 1199fab7a039SJC Kuo 1200fab7a039SJC Kuo usb2-2 { 1201fab7a039SJC Kuo nvidia,function = "xusb"; 1202fab7a039SJC Kuo status = "disabled"; 1203fab7a039SJC Kuo #phy-cells = <0>; 1204fab7a039SJC Kuo }; 1205fab7a039SJC Kuo 1206fab7a039SJC Kuo usb2-3 { 1207fab7a039SJC Kuo nvidia,function = "xusb"; 1208fab7a039SJC Kuo status = "disabled"; 1209fab7a039SJC Kuo #phy-cells = <0>; 1210fab7a039SJC Kuo }; 1211fab7a039SJC Kuo }; 1212fab7a039SJC Kuo }; 1213fab7a039SJC Kuo 1214fab7a039SJC Kuo usb3 { 1215fab7a039SJC Kuo lanes { 1216fab7a039SJC Kuo usb3-0 { 1217fab7a039SJC Kuo nvidia,function = "xusb"; 1218fab7a039SJC Kuo status = "disabled"; 1219fab7a039SJC Kuo #phy-cells = <0>; 1220fab7a039SJC Kuo }; 1221fab7a039SJC Kuo 1222fab7a039SJC Kuo usb3-1 { 1223fab7a039SJC Kuo nvidia,function = "xusb"; 1224fab7a039SJC Kuo status = "disabled"; 1225fab7a039SJC Kuo #phy-cells = <0>; 1226fab7a039SJC Kuo }; 1227fab7a039SJC Kuo 1228fab7a039SJC Kuo usb3-2 { 1229fab7a039SJC Kuo nvidia,function = "xusb"; 1230fab7a039SJC Kuo status = "disabled"; 1231fab7a039SJC Kuo #phy-cells = <0>; 1232fab7a039SJC Kuo }; 1233fab7a039SJC Kuo 1234fab7a039SJC Kuo usb3-3 { 1235fab7a039SJC Kuo nvidia,function = "xusb"; 1236fab7a039SJC Kuo status = "disabled"; 1237fab7a039SJC Kuo #phy-cells = <0>; 1238fab7a039SJC Kuo }; 1239fab7a039SJC Kuo }; 1240fab7a039SJC Kuo }; 1241fab7a039SJC Kuo }; 1242fab7a039SJC Kuo 1243fab7a039SJC Kuo ports { 1244fab7a039SJC Kuo usb2-0 { 1245fab7a039SJC Kuo status = "disabled"; 1246fab7a039SJC Kuo }; 1247fab7a039SJC Kuo 1248fab7a039SJC Kuo usb2-1 { 1249fab7a039SJC Kuo status = "disabled"; 1250fab7a039SJC Kuo }; 1251fab7a039SJC Kuo 1252fab7a039SJC Kuo usb2-2 { 1253fab7a039SJC Kuo status = "disabled"; 1254fab7a039SJC Kuo }; 1255fab7a039SJC Kuo 1256fab7a039SJC Kuo usb2-3 { 1257fab7a039SJC Kuo status = "disabled"; 1258fab7a039SJC Kuo }; 1259fab7a039SJC Kuo 1260fab7a039SJC Kuo usb3-0 { 1261fab7a039SJC Kuo status = "disabled"; 1262fab7a039SJC Kuo }; 1263fab7a039SJC Kuo 1264fab7a039SJC Kuo usb3-1 { 1265fab7a039SJC Kuo status = "disabled"; 1266fab7a039SJC Kuo }; 1267fab7a039SJC Kuo 1268fab7a039SJC Kuo usb3-2 { 1269fab7a039SJC Kuo status = "disabled"; 1270fab7a039SJC Kuo }; 1271fab7a039SJC Kuo 1272fab7a039SJC Kuo usb3-3 { 1273fab7a039SJC Kuo status = "disabled"; 1274fab7a039SJC Kuo }; 1275fab7a039SJC Kuo }; 1276fab7a039SJC Kuo }; 1277fab7a039SJC Kuo 1278bc8788b2SNagarjuna Kristam usb@3550000 { 1279bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1280*2838cfddSThierry Reding reg = <0x0 0x03550000 0x0 0x8000>, 1281*2838cfddSThierry Reding <0x0 0x03558000 0x0 0x1000>; 1282bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1283bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1284bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1285bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1286bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1287bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1288bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1289c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1290c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1291c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1292c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1293bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1294bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1295bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1296bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1297bc8788b2SNagarjuna Kristam status = "disabled"; 1298bc8788b2SNagarjuna Kristam }; 1299bc8788b2SNagarjuna Kristam 1300fab7a039SJC Kuo usb@3610000 { 1301fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1302*2838cfddSThierry Reding reg = <0x0 0x03610000 0x0 0x40000>, 1303*2838cfddSThierry Reding <0x0 0x03600000 0x0 0x10000>; 1304fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1305fab7a039SJC Kuo 1306fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1307a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1308fab7a039SJC Kuo 1309fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1310fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1311fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1312fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1313fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1314fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1315fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1316fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1317fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1318fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1319fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1320fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1321fab7a039SJC Kuo "pll_e"; 1322c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1323c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1324c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1325c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1326fab7a039SJC Kuo 1327fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1328fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1329fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1330fab7a039SJC Kuo 1331fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1332fab7a039SJC Kuo status = "disabled"; 1333fab7a039SJC Kuo }; 1334fab7a039SJC Kuo 133509903c5eSJC Kuo fuse@3820000 { 133609903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 1337*2838cfddSThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 133809903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 133909903c5eSJC Kuo clock-names = "fuse"; 134009903c5eSJC Kuo }; 134109903c5eSJC Kuo 13425425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13435425fb15SMikko Perttunen compatible = "arm,gic-400"; 13445425fb15SMikko Perttunen #interrupt-cells = <3>; 13455425fb15SMikko Perttunen interrupt-controller; 1346*2838cfddSThierry Reding reg = <0x0 0x03881000 0x0 0x1000>, 1347*2838cfddSThierry Reding <0x0 0x03882000 0x0 0x2000>, 1348*2838cfddSThierry Reding <0x0 0x03884000 0x0 0x2000>, 1349*2838cfddSThierry Reding <0x0 0x03886000 0x0 0x2000>; 13505425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13515425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13525425fb15SMikko Perttunen interrupt-parent = <&gic>; 13535425fb15SMikko Perttunen }; 13545425fb15SMikko Perttunen 1355badb80beSThierry Reding cec@3960000 { 1356badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1357*2838cfddSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 1358badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1359badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1360badb80beSThierry Reding clock-names = "cec"; 1361badb80beSThierry Reding status = "disabled"; 1362badb80beSThierry Reding }; 1363badb80beSThierry Reding 13648fbd2d11SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 13658fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 1366*2838cfddSThierry Reding reg = <0x0 0x3aa0000 0x0 0x10000>; 13678fbd2d11SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 13688fbd2d11SDipen Patel nvidia,int-threshold = <1>; 13698fbd2d11SDipen Patel nvidia,slices = <11>; 13708fbd2d11SDipen Patel #timestamp-cells = <1>; 13718fbd2d11SDipen Patel status = "okay"; 13728fbd2d11SDipen Patel }; 13738fbd2d11SDipen Patel 13745425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1375cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 1376*2838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 1377a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1378a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1379a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1380a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1381a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1382a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1383a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1384a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1385a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1386a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1387a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1388a38570c2SMikko Perttunen "shared7"; 1389a38570c2SMikko Perttunen #mbox-cells = <2>; 1390a38570c2SMikko Perttunen }; 1391a38570c2SMikko Perttunen 13922602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13932602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1394*2838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 13952602c32fSVidya Sagar reg-names = "ctl"; 13962602c32fSVidya Sagar 13972602c32fSVidya Sagar #phy-cells = <0>; 13982602c32fSVidya Sagar }; 13992602c32fSVidya Sagar 14002602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 14012602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1402*2838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 14032602c32fSVidya Sagar reg-names = "ctl"; 14042602c32fSVidya Sagar 14052602c32fSVidya Sagar #phy-cells = <0>; 14062602c32fSVidya Sagar }; 14072602c32fSVidya Sagar 14082602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 14092602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1410*2838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 14112602c32fSVidya Sagar reg-names = "ctl"; 14122602c32fSVidya Sagar 14132602c32fSVidya Sagar #phy-cells = <0>; 14142602c32fSVidya Sagar }; 14152602c32fSVidya Sagar 14162602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14172602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1418*2838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 14192602c32fSVidya Sagar reg-names = "ctl"; 14202602c32fSVidya Sagar 14212602c32fSVidya Sagar #phy-cells = <0>; 14222602c32fSVidya Sagar }; 14232602c32fSVidya Sagar 14242602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14252602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1426*2838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 14272602c32fSVidya Sagar reg-names = "ctl"; 14282602c32fSVidya Sagar 14292602c32fSVidya Sagar #phy-cells = <0>; 14302602c32fSVidya Sagar }; 14312602c32fSVidya Sagar 14322602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14332602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1434*2838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 14352602c32fSVidya Sagar reg-names = "ctl"; 14362602c32fSVidya Sagar 14372602c32fSVidya Sagar #phy-cells = <0>; 14382602c32fSVidya Sagar }; 14392602c32fSVidya Sagar 14402602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14412602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1442*2838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 14432602c32fSVidya Sagar reg-names = "ctl"; 14442602c32fSVidya Sagar 14452602c32fSVidya Sagar #phy-cells = <0>; 14462602c32fSVidya Sagar }; 14472602c32fSVidya Sagar 14482602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14492602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1450*2838cfddSThierry Reding reg = <0x0 0x03e80000 0x0 0x10000>; 14512602c32fSVidya Sagar reg-names = "ctl"; 14522602c32fSVidya Sagar 14532602c32fSVidya Sagar #phy-cells = <0>; 14542602c32fSVidya Sagar }; 14552602c32fSVidya Sagar 14562602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14572602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1458*2838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 14592602c32fSVidya Sagar reg-names = "ctl"; 14602602c32fSVidya Sagar 14612602c32fSVidya Sagar #phy-cells = <0>; 14622602c32fSVidya Sagar }; 14632602c32fSVidya Sagar 14642602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14652602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1466*2838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 14672602c32fSVidya Sagar reg-names = "ctl"; 14682602c32fSVidya Sagar 14692602c32fSVidya Sagar #phy-cells = <0>; 14702602c32fSVidya Sagar }; 14712602c32fSVidya Sagar 14722602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14732602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1474*2838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 14752602c32fSVidya Sagar reg-names = "ctl"; 14762602c32fSVidya Sagar 14772602c32fSVidya Sagar #phy-cells = <0>; 14782602c32fSVidya Sagar }; 14792602c32fSVidya Sagar 14802602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14812602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1482*2838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 14832602c32fSVidya Sagar reg-names = "ctl"; 14842602c32fSVidya Sagar 14852602c32fSVidya Sagar #phy-cells = <0>; 14862602c32fSVidya Sagar }; 14872602c32fSVidya Sagar 14882602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14892602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1490*2838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 14912602c32fSVidya Sagar reg-names = "ctl"; 14922602c32fSVidya Sagar 14932602c32fSVidya Sagar #phy-cells = <0>; 14942602c32fSVidya Sagar }; 14952602c32fSVidya Sagar 14962602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14972602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1498*2838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 14992602c32fSVidya Sagar reg-names = "ctl"; 15002602c32fSVidya Sagar 15012602c32fSVidya Sagar #phy-cells = <0>; 15022602c32fSVidya Sagar }; 15032602c32fSVidya Sagar 15042602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 15052602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1506*2838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 15072602c32fSVidya Sagar reg-names = "ctl"; 15082602c32fSVidya Sagar 15092602c32fSVidya Sagar #phy-cells = <0>; 15102602c32fSVidya Sagar }; 15112602c32fSVidya Sagar 15122602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 15132602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1514*2838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 15152602c32fSVidya Sagar reg-names = "ctl"; 15162602c32fSVidya Sagar 15172602c32fSVidya Sagar #phy-cells = <0>; 15182602c32fSVidya Sagar }; 15192602c32fSVidya Sagar 15202602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15212602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1522*2838cfddSThierry Reding reg = <0x0 0x03f10000 0x0 0x10000>; 15232602c32fSVidya Sagar reg-names = "ctl"; 15242602c32fSVidya Sagar 15252602c32fSVidya Sagar #phy-cells = <0>; 15262602c32fSVidya Sagar }; 15272602c32fSVidya Sagar 15282602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15292602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1530*2838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 15312602c32fSVidya Sagar reg-names = "ctl"; 15322602c32fSVidya Sagar 15332602c32fSVidya Sagar #phy-cells = <0>; 15342602c32fSVidya Sagar }; 15352602c32fSVidya Sagar 15362602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15372602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1538*2838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 15392602c32fSVidya Sagar reg-names = "ctl"; 15402602c32fSVidya Sagar 15412602c32fSVidya Sagar #phy-cells = <0>; 15422602c32fSVidya Sagar }; 15432602c32fSVidya Sagar 15442602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15452602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 1546*2838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 15472602c32fSVidya Sagar reg-names = "ctl"; 15482602c32fSVidya Sagar 15492602c32fSVidya Sagar #phy-cells = <0>; 15502602c32fSVidya Sagar }; 15512602c32fSVidya Sagar 1552a47e173eSSumit Gupta sce-noc@b600000 { 1553a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 1554*2838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x1000>; 1555a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1556a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1557a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1558a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1559a47e173eSSumit Gupta status = "okay"; 1560a47e173eSSumit Gupta }; 1561a47e173eSSumit Gupta 1562a47e173eSSumit Gupta rce-noc@be00000 { 1563a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 1564*2838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x1000>; 1565a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1566a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1567a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1568a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1569a47e173eSSumit Gupta status = "okay"; 1570a47e173eSSumit Gupta }; 1571a47e173eSSumit Gupta 1572a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1573cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 1574*2838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 1575a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1576a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1577a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1578a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1579a38570c2SMikko Perttunen /* 1580a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1581a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1582a38570c2SMikko Perttunen */ 1583a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15845425fb15SMikko Perttunen #mbox-cells = <2>; 15855425fb15SMikko Perttunen }; 15865425fb15SMikko Perttunen 15878fbd2d11SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 15888fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 1589*2838cfddSThierry Reding reg = <0x0 0xc1e0000 0x0 0x10000>; 15908fbd2d11SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 15918fbd2d11SDipen Patel nvidia,int-threshold = <1>; 15928fbd2d11SDipen Patel nvidia,slices = <3>; 15938fbd2d11SDipen Patel #timestamp-cells = <1>; 15948fbd2d11SDipen Patel status = "okay"; 15958fbd2d11SDipen Patel }; 15968fbd2d11SDipen Patel 15975425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1598d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1599*2838cfddSThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 16005425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 16015425fb15SMikko Perttunen #address-cells = <1>; 16025425fb15SMikko Perttunen #size-cells = <0>; 16035425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 16045425fb15SMikko Perttunen clock-names = "div-clk"; 16055425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 16065425fb15SMikko Perttunen reset-names = "i2c"; 16078e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16088e442805SAkhil R dma-coherent; 16098e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 16108e442805SAkhil R dma-names = "rx", "tx"; 16115425fb15SMikko Perttunen status = "disabled"; 16125425fb15SMikko Perttunen }; 16135425fb15SMikko Perttunen 16145425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1615d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1616*2838cfddSThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 16175425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16185425fb15SMikko Perttunen #address-cells = <1>; 16195425fb15SMikko Perttunen #size-cells = <0>; 16205425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16215425fb15SMikko Perttunen clock-names = "div-clk"; 16225425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16235425fb15SMikko Perttunen reset-names = "i2c"; 16248e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16258e442805SAkhil R dma-coherent; 16268e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16278e442805SAkhil R dma-names = "rx", "tx"; 16285425fb15SMikko Perttunen status = "disabled"; 16295425fb15SMikko Perttunen }; 16305425fb15SMikko Perttunen 16315425fb15SMikko Perttunen uartc: serial@c280000 { 16325425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1633*2838cfddSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 16345425fb15SMikko Perttunen reg-shift = <2>; 16355425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16365425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16375425fb15SMikko Perttunen clock-names = "serial"; 16385425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16395425fb15SMikko Perttunen reset-names = "serial"; 16405425fb15SMikko Perttunen status = "disabled"; 16415425fb15SMikko Perttunen }; 16425425fb15SMikko Perttunen 16435425fb15SMikko Perttunen uartg: serial@c290000 { 16445425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1645*2838cfddSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 16465425fb15SMikko Perttunen reg-shift = <2>; 16475425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16495425fb15SMikko Perttunen clock-names = "serial"; 16505425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16515425fb15SMikko Perttunen reset-names = "serial"; 16525425fb15SMikko Perttunen status = "disabled"; 16535425fb15SMikko Perttunen }; 16545425fb15SMikko Perttunen 165537e5a31dSThierry Reding rtc: rtc@c2a0000 { 165637e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1657*2838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 165837e5a31dSThierry Reding interrupt-parent = <&pmc>; 165937e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 166037e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 166137e5a31dSThierry Reding clock-names = "rtc"; 166237e5a31dSThierry Reding status = "disabled"; 166337e5a31dSThierry Reding }; 166437e5a31dSThierry Reding 16654d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16664d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16674d286331SThierry Reding reg-names = "security", "gpio"; 1668*2838cfddSThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1669*2838cfddSThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 16700a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16710a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16720a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16730a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16744d286331SThierry Reding gpio-controller; 16754d286331SThierry Reding #gpio-cells = <2>; 16764d286331SThierry Reding interrupt-controller; 16774d286331SThierry Reding #interrupt-cells = <2>; 1678979ac5efSThierry Reding gpio-ranges = <&pinmux_aon 0 0 30>; 16796f380a4eSThierry Reding }; 16806f380a4eSThierry Reding 16816f380a4eSThierry Reding pinmux_aon: pinmux@c300000 { 16826f380a4eSThierry Reding compatible = "nvidia,tegra194-pinmux-aon"; 1683*2838cfddSThierry Reding reg = <0x0 0xc300000 0x0 0x4000>; 16846f380a4eSThierry Reding 16856f380a4eSThierry Reding status = "okay"; 16864d286331SThierry Reding }; 16874d286331SThierry Reding 16886a574ec7SThierry Reding pwm4: pwm@c340000 { 16896a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16906a574ec7SThierry Reding "nvidia,tegra186-pwm"; 1691*2838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 16926a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16936a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16946a574ec7SThierry Reding reset-names = "pwm"; 16956a574ec7SThierry Reding status = "disabled"; 16966a574ec7SThierry Reding #pwm-cells = <2>; 16976a574ec7SThierry Reding }; 16986a574ec7SThierry Reding 169938ecf1e5SThierry Reding pmc: pmc@c360000 { 17005425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 1701*2838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 1702*2838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 1703*2838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 1704*2838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 1705*2838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 17065425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 170738ecf1e5SThierry Reding 170838ecf1e5SThierry Reding #interrupt-cells = <2>; 170938ecf1e5SThierry Reding interrupt-controller; 1710ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1711ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1712ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1713ff21087eSPrathamesh Shete }; 1714ff21087eSPrathamesh Shete 1715ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1716ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1717ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1718ff21087eSPrathamesh Shete }; 1719ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1720ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1721ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1722ff21087eSPrathamesh Shete }; 1723ff21087eSPrathamesh Shete 1724ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1725ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1726ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1727ff21087eSPrathamesh Shete }; 1728ff21087eSPrathamesh Shete 17295425fb15SMikko Perttunen }; 17303db6d3baSThierry Reding 1731a47e173eSSumit Gupta aon-noc@c600000 { 1732a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 1733*2838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x1000>; 1734a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1735a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1736a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1737a47e173eSSumit Gupta status = "okay"; 1738a47e173eSSumit Gupta }; 1739a47e173eSSumit Gupta 1740a47e173eSSumit Gupta bpmp-noc@d600000 { 1741a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 1742*2838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x1000>; 1743a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1744a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1745a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1746a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1747a47e173eSSumit Gupta status = "okay"; 1748a47e173eSSumit Gupta }; 1749a47e173eSSumit Gupta 1750e762232fSJon Hunter iommu@10000000 { 1751e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1752*2838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x800000>; 1753e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1818e762232fSJon Hunter stream-match-mask = <0x7f80>; 1819e762232fSJon Hunter #global-interrupts = <1>; 1820e762232fSJon Hunter #iommu-cells = <1>; 1821e762232fSJon Hunter 1822e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1823ebea268eSJon Hunter status = "disabled"; 1824e762232fSJon Hunter }; 1825e762232fSJon Hunter 1826c7289b1cSThierry Reding smmu: iommu@12000000 { 1827c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1828*2838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x800000>, 1829*2838cfddSThierry Reding <0x0 0x11000000 0x0 0x800000>; 1830c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1896c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1897c7289b1cSThierry Reding #global-interrupts = <2>; 1898c7289b1cSThierry Reding #iommu-cells = <1>; 1899c7289b1cSThierry Reding 1900c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1901c7289b1cSThierry Reding status = "okay"; 1902c7289b1cSThierry Reding }; 1903c7289b1cSThierry Reding 19043db6d3baSThierry Reding host1x@13e00000 { 1905ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 1906*2838cfddSThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 1907*2838cfddSThierry Reding <0x0 0x13e10000 0x0 0x10000>; 19083db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 19093db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 19103db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1911052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 19123db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 19133db6d3baSThierry Reding clock-names = "host1x"; 19143db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 19153db6d3baSThierry Reding reset-names = "host1x"; 19163db6d3baSThierry Reding 1917*2838cfddSThierry Reding #address-cells = <2>; 1918*2838cfddSThierry Reding #size-cells = <2>; 1919*2838cfddSThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 19203db6d3baSThierry Reding 1921d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1922d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1923c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 19243db6d3baSThierry Reding 1925e30cf101SMikko Perttunen /* Context isolation domains */ 1926b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1927b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1928b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1929b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1930b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1931b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1932b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1933b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1934e30cf101SMikko Perttunen 193578a05873SMikko Perttunen nvdec@15140000 { 193678a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 1937*2838cfddSThierry Reding reg = <0x0 0x15140000 0x0 0x00040000>; 193878a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 193978a05873SMikko Perttunen clock-names = "nvdec"; 194078a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 194178a05873SMikko Perttunen reset-names = "nvdec"; 194278a05873SMikko Perttunen 194378a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 194478a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 194578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 194678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 194778a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 194878a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 194978a05873SMikko Perttunen dma-coherent; 195078a05873SMikko Perttunen 195178a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 195278a05873SMikko Perttunen }; 195378a05873SMikko Perttunen 19543db6d3baSThierry Reding display-hub@15200000 { 1955aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1956*2838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x00040000>; 19573db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19583db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19593db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19603db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19613db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19623db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19633db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19643db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19653db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19663db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19683db6d3baSThierry Reding clock-names = "disp", "hub"; 19693db6d3baSThierry Reding status = "disabled"; 19703db6d3baSThierry Reding 19713db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19723db6d3baSThierry Reding 1973*2838cfddSThierry Reding #address-cells = <2>; 1974*2838cfddSThierry Reding #size-cells = <2>; 1975*2838cfddSThierry Reding ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 19763db6d3baSThierry Reding 19773db6d3baSThierry Reding display@15200000 { 19783db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 1979*2838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x10000>; 19803db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19813db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19823db6d3baSThierry Reding clock-names = "dc"; 19833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19843db6d3baSThierry Reding reset-names = "dc"; 19853db6d3baSThierry Reding 19863db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1987d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1988d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1989d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19903db6d3baSThierry Reding 19913db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19923db6d3baSThierry Reding nvidia,head = <0>; 19933db6d3baSThierry Reding }; 19943db6d3baSThierry Reding 19953db6d3baSThierry Reding display@15210000 { 19963db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 1997*2838cfddSThierry Reding reg = <0x0 0x15210000 0x0 0x10000>; 19983db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19993db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 20003db6d3baSThierry Reding clock-names = "dc"; 20013db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 20023db6d3baSThierry Reding reset-names = "dc"; 20033db6d3baSThierry Reding 20043db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2005d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2006d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2007d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20083db6d3baSThierry Reding 20093db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20103db6d3baSThierry Reding nvidia,head = <1>; 20113db6d3baSThierry Reding }; 20123db6d3baSThierry Reding 20133db6d3baSThierry Reding display@15220000 { 20143db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 2015*2838cfddSThierry Reding reg = <0x0 0x15220000 0x0 0x10000>; 20163db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 20173db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 20183db6d3baSThierry Reding clock-names = "dc"; 20193db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 20203db6d3baSThierry Reding reset-names = "dc"; 20213db6d3baSThierry Reding 20223db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2023d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2024d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2025d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20263db6d3baSThierry Reding 20273db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20283db6d3baSThierry Reding nvidia,head = <2>; 20293db6d3baSThierry Reding }; 20303db6d3baSThierry Reding 20313db6d3baSThierry Reding display@15230000 { 20323db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 2033*2838cfddSThierry Reding reg = <0x0 0x15230000 0x0 0x10000>; 20343db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20353db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20363db6d3baSThierry Reding clock-names = "dc"; 20373db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20383db6d3baSThierry Reding reset-names = "dc"; 20393db6d3baSThierry Reding 20403db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2041d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2042d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2043d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20443db6d3baSThierry Reding 20453db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20463db6d3baSThierry Reding nvidia,head = <3>; 20473db6d3baSThierry Reding }; 20483db6d3baSThierry Reding }; 20493db6d3baSThierry Reding 20508d424ec2SThierry Reding vic@15340000 { 20518d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 2052*2838cfddSThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 20538d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20548d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20558d424ec2SThierry Reding clock-names = "vic"; 20568d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20578d424ec2SThierry Reding reset-names = "vic"; 20588d424ec2SThierry Reding 20598d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2060d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2061d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2062d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2063c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2064a52280c8SJon Hunter dma-coherent; 20658d424ec2SThierry Reding }; 20668d424ec2SThierry Reding 2067f7eb2785SJon Hunter nvjpg@15380000 { 2068f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 2069*2838cfddSThierry Reding reg = <0x0 0x15380000 0x0 0x40000>; 2070f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2071f7eb2785SJon Hunter clock-names = "nvjpg"; 2072f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2073f7eb2785SJon Hunter reset-names = "nvjpg"; 2074f7eb2785SJon Hunter 2075f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2076f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2077f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2078f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2079f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2080f7eb2785SJon Hunter dma-coherent; 2081f7eb2785SJon Hunter }; 2082f7eb2785SJon Hunter 208378a05873SMikko Perttunen nvdec@15480000 { 208478a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 2085*2838cfddSThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 208678a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 208778a05873SMikko Perttunen clock-names = "nvdec"; 208878a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 208978a05873SMikko Perttunen reset-names = "nvdec"; 209078a05873SMikko Perttunen 209178a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 209278a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 209378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 209478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 209578a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 209678a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 209778a05873SMikko Perttunen dma-coherent; 209878a05873SMikko Perttunen 209978a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 210078a05873SMikko Perttunen }; 210178a05873SMikko Perttunen 2102f7eb2785SJon Hunter nvenc@154c0000 { 2103f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2104*2838cfddSThierry Reding reg = <0x0 0x154c0000 0x0 0x40000>; 2105f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2106f7eb2785SJon Hunter clock-names = "nvenc"; 2107f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2108f7eb2785SJon Hunter reset-names = "nvenc"; 2109f7eb2785SJon Hunter 2110f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2111f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2112f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2113f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2114f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2115f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2116f7eb2785SJon Hunter dma-coherent; 2117f7eb2785SJon Hunter 2118f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2119f7eb2785SJon Hunter }; 2120f7eb2785SJon Hunter 21213db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21223db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 2123*2838cfddSThierry Reding reg = <0x0 0x155c0000 0x0 0x10000>; 21243db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21253db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21273db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21293db6d3baSThierry Reding reset-names = "dpaux"; 21303db6d3baSThierry Reding status = "disabled"; 21313db6d3baSThierry Reding 21323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21333db6d3baSThierry Reding 21343db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21353db6d3baSThierry Reding groups = "dpaux-io"; 21363db6d3baSThierry Reding function = "aux"; 21373db6d3baSThierry Reding }; 21383db6d3baSThierry Reding 21393db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21403db6d3baSThierry Reding groups = "dpaux-io"; 21413db6d3baSThierry Reding function = "i2c"; 21423db6d3baSThierry Reding }; 21433db6d3baSThierry Reding 21443db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21453db6d3baSThierry Reding groups = "dpaux-io"; 21463db6d3baSThierry Reding function = "off"; 21473db6d3baSThierry Reding }; 21483db6d3baSThierry Reding 21493db6d3baSThierry Reding i2c-bus { 21503db6d3baSThierry Reding #address-cells = <1>; 21513db6d3baSThierry Reding #size-cells = <0>; 21523db6d3baSThierry Reding }; 21533db6d3baSThierry Reding }; 21543db6d3baSThierry Reding 21553db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21563db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 2157*2838cfddSThierry Reding reg = <0x0 0x155d0000 0x0 0x10000>; 21583db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21593db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21613db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21623db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21633db6d3baSThierry Reding reset-names = "dpaux"; 21643db6d3baSThierry Reding status = "disabled"; 21653db6d3baSThierry Reding 21663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21673db6d3baSThierry Reding 21683db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21693db6d3baSThierry Reding groups = "dpaux-io"; 21703db6d3baSThierry Reding function = "aux"; 21713db6d3baSThierry Reding }; 21723db6d3baSThierry Reding 21733db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21743db6d3baSThierry Reding groups = "dpaux-io"; 21753db6d3baSThierry Reding function = "i2c"; 21763db6d3baSThierry Reding }; 21773db6d3baSThierry Reding 21783db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21793db6d3baSThierry Reding groups = "dpaux-io"; 21803db6d3baSThierry Reding function = "off"; 21813db6d3baSThierry Reding }; 21823db6d3baSThierry Reding 21833db6d3baSThierry Reding i2c-bus { 21843db6d3baSThierry Reding #address-cells = <1>; 21853db6d3baSThierry Reding #size-cells = <0>; 21863db6d3baSThierry Reding }; 21873db6d3baSThierry Reding }; 21883db6d3baSThierry Reding 21893db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21903db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 2191*2838cfddSThierry Reding reg = <0x0 0x155e0000 0x0 0x10000>; 21923db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21933db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21953db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21963db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21973db6d3baSThierry Reding reset-names = "dpaux"; 21983db6d3baSThierry Reding status = "disabled"; 21993db6d3baSThierry Reding 22003db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22013db6d3baSThierry Reding 22023db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 22033db6d3baSThierry Reding groups = "dpaux-io"; 22043db6d3baSThierry Reding function = "aux"; 22053db6d3baSThierry Reding }; 22063db6d3baSThierry Reding 22073db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 22083db6d3baSThierry Reding groups = "dpaux-io"; 22093db6d3baSThierry Reding function = "i2c"; 22103db6d3baSThierry Reding }; 22113db6d3baSThierry Reding 22123db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 22133db6d3baSThierry Reding groups = "dpaux-io"; 22143db6d3baSThierry Reding function = "off"; 22153db6d3baSThierry Reding }; 22163db6d3baSThierry Reding 22173db6d3baSThierry Reding i2c-bus { 22183db6d3baSThierry Reding #address-cells = <1>; 22193db6d3baSThierry Reding #size-cells = <0>; 22203db6d3baSThierry Reding }; 22213db6d3baSThierry Reding }; 22223db6d3baSThierry Reding 22233db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22243db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 2225*2838cfddSThierry Reding reg = <0x0 0x155f0000 0x0 0x10000>; 22263db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22273db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22293db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22303db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22313db6d3baSThierry Reding reset-names = "dpaux"; 22323db6d3baSThierry Reding status = "disabled"; 22333db6d3baSThierry Reding 22343db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22353db6d3baSThierry Reding 22363db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22373db6d3baSThierry Reding groups = "dpaux-io"; 22383db6d3baSThierry Reding function = "aux"; 22393db6d3baSThierry Reding }; 22403db6d3baSThierry Reding 22413db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22423db6d3baSThierry Reding groups = "dpaux-io"; 22433db6d3baSThierry Reding function = "i2c"; 22443db6d3baSThierry Reding }; 22453db6d3baSThierry Reding 22463db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22473db6d3baSThierry Reding groups = "dpaux-io"; 22483db6d3baSThierry Reding function = "off"; 22493db6d3baSThierry Reding }; 22503db6d3baSThierry Reding 22513db6d3baSThierry Reding i2c-bus { 22523db6d3baSThierry Reding #address-cells = <1>; 22533db6d3baSThierry Reding #size-cells = <0>; 22543db6d3baSThierry Reding }; 22553db6d3baSThierry Reding }; 22563db6d3baSThierry Reding 2257f7eb2785SJon Hunter nvenc@15a80000 { 2258f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2259*2838cfddSThierry Reding reg = <0x0 0x15a80000 0x0 0x00040000>; 2260f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2261f7eb2785SJon Hunter clock-names = "nvenc"; 2262f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2263f7eb2785SJon Hunter reset-names = "nvenc"; 2264f7eb2785SJon Hunter 2265f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2266f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2267f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2268f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2269f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2270f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2271f7eb2785SJon Hunter dma-coherent; 2272f7eb2785SJon Hunter 2273f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2274f7eb2785SJon Hunter }; 2275f7eb2785SJon Hunter 22763db6d3baSThierry Reding sor0: sor@15b00000 { 22773db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2278*2838cfddSThierry Reding reg = <0x0 0x15b00000 0x0 0x40000>; 22793db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22863db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22873db6d3baSThierry Reding "pad"; 22883db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22893db6d3baSThierry Reding reset-names = "sor"; 22903db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22913db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22923db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22933db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22943db6d3baSThierry Reding status = "disabled"; 22953db6d3baSThierry Reding 22963db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22973db6d3baSThierry Reding nvidia,interface = <0>; 22983db6d3baSThierry Reding }; 22993db6d3baSThierry Reding 23003db6d3baSThierry Reding sor1: sor@15b40000 { 23013db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2302*2838cfddSThierry Reding reg = <0x0 0x15b40000 0x0 0x40000>; 23033db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 23043db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 23053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 23063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 23073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 23103db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23113db6d3baSThierry Reding "pad"; 23123db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 23133db6d3baSThierry Reding reset-names = "sor"; 23143db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 23153db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 23163db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 23173db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23183db6d3baSThierry Reding status = "disabled"; 23193db6d3baSThierry Reding 23203db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23213db6d3baSThierry Reding nvidia,interface = <1>; 23223db6d3baSThierry Reding }; 23233db6d3baSThierry Reding 23243db6d3baSThierry Reding sor2: sor@15b80000 { 23253db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2326*2838cfddSThierry Reding reg = <0x0 0x15b80000 0x0 0x40000>; 23273db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23283db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23323db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23343db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23353db6d3baSThierry Reding "pad"; 23363db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23373db6d3baSThierry Reding reset-names = "sor"; 23383db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23393db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23403db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23413db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23423db6d3baSThierry Reding status = "disabled"; 23433db6d3baSThierry Reding 23443db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23453db6d3baSThierry Reding nvidia,interface = <2>; 23463db6d3baSThierry Reding }; 23473db6d3baSThierry Reding 23483db6d3baSThierry Reding sor3: sor@15bc0000 { 23493db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2350*2838cfddSThierry Reding reg = <0x0 0x15bc0000 0x0 0x40000>; 23513db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23523db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23553db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23563db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23573db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23583db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23593db6d3baSThierry Reding "pad"; 23603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23613db6d3baSThierry Reding reset-names = "sor"; 23623db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23633db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23643db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23653db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23663db6d3baSThierry Reding status = "disabled"; 23673db6d3baSThierry Reding 23683db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23693db6d3baSThierry Reding nvidia,interface = <3>; 23703db6d3baSThierry Reding }; 23713db6d3baSThierry Reding }; 23720f134e39SThierry Reding 23732602c32fSVidya Sagar pcie@14100000 { 2374f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23752602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2376*2838cfddSThierry Reding reg = <0x0 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2377*2838cfddSThierry Reding <0x0 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2378*2838cfddSThierry Reding <0x0 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2379*2838cfddSThierry Reding <0x0 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23802602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23812602c32fSVidya Sagar 23822602c32fSVidya Sagar status = "disabled"; 23832602c32fSVidya Sagar 23842602c32fSVidya Sagar #address-cells = <3>; 23852602c32fSVidya Sagar #size-cells = <2>; 23862602c32fSVidya Sagar device_type = "pci"; 23872602c32fSVidya Sagar num-lanes = <1>; 23882602c32fSVidya Sagar linux,pci-domain = <1>; 23892602c32fSVidya Sagar 23902602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 23912602c32fSVidya Sagar clock-names = "core"; 23922602c32fSVidya Sagar 23932602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 23942602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 23952602c32fSVidya Sagar reset-names = "apb", "core"; 23962602c32fSVidya Sagar 23972602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23982602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23992602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24002602c32fSVidya Sagar 24012602c32fSVidya Sagar #interrupt-cells = <1>; 24022602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24032602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24042602c32fSVidya Sagar 24052602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 24062602c32fSVidya Sagar 24072602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24082602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24092602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24102602c32fSVidya Sagar 24112602c32fSVidya Sagar bus-range = <0x0 0xff>; 2412d5237c7cSThierry Reding 24138a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24148a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24158a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2416d5237c7cSThierry Reding 2417d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2418d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2419ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2420ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2421ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2422ba02920cSVidya Sagar dma-coherent; 24232602c32fSVidya Sagar }; 24242602c32fSVidya Sagar 24252602c32fSVidya Sagar pcie@14120000 { 2426f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24272602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2428644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2429644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2430644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2431644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24322602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24332602c32fSVidya Sagar 24342602c32fSVidya Sagar status = "disabled"; 24352602c32fSVidya Sagar 24362602c32fSVidya Sagar #address-cells = <3>; 24372602c32fSVidya Sagar #size-cells = <2>; 24382602c32fSVidya Sagar device_type = "pci"; 24392602c32fSVidya Sagar num-lanes = <1>; 24402602c32fSVidya Sagar linux,pci-domain = <2>; 24412602c32fSVidya Sagar 24422602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24432602c32fSVidya Sagar clock-names = "core"; 24442602c32fSVidya Sagar 24452602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24462602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24472602c32fSVidya Sagar reset-names = "apb", "core"; 24482602c32fSVidya Sagar 24492602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24502602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24512602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24522602c32fSVidya Sagar 24532602c32fSVidya Sagar #interrupt-cells = <1>; 24542602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24552602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24562602c32fSVidya Sagar 24572602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24582602c32fSVidya Sagar 24592602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24602602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24612602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24622602c32fSVidya Sagar 24632602c32fSVidya Sagar bus-range = <0x0 0xff>; 2464d5237c7cSThierry Reding 24658a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24668a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24678a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2468d5237c7cSThierry Reding 2469d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2470d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2471ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2472ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2473ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2474ba02920cSVidya Sagar dma-coherent; 24752602c32fSVidya Sagar }; 24762602c32fSVidya Sagar 24772602c32fSVidya Sagar pcie@14140000 { 2478f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24792602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2480644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2481644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2482644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2483644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24842602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24852602c32fSVidya Sagar 24862602c32fSVidya Sagar status = "disabled"; 24872602c32fSVidya Sagar 24882602c32fSVidya Sagar #address-cells = <3>; 24892602c32fSVidya Sagar #size-cells = <2>; 24902602c32fSVidya Sagar device_type = "pci"; 24912602c32fSVidya Sagar num-lanes = <1>; 24922602c32fSVidya Sagar linux,pci-domain = <3>; 24932602c32fSVidya Sagar 24942602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 24952602c32fSVidya Sagar clock-names = "core"; 24962602c32fSVidya Sagar 24972602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 24982602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 24992602c32fSVidya Sagar reset-names = "apb", "core"; 25002602c32fSVidya Sagar 25012602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25022602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25032602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25042602c32fSVidya Sagar 25052602c32fSVidya Sagar #interrupt-cells = <1>; 25062602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25072602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 25082602c32fSVidya Sagar 25092602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 25102602c32fSVidya Sagar 25112602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25122602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25132602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25142602c32fSVidya Sagar 25152602c32fSVidya Sagar bus-range = <0x0 0xff>; 2516d5237c7cSThierry Reding 25178a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25188a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25198a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2520d5237c7cSThierry Reding 2521d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2522d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2523ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2524ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2525ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2526ba02920cSVidya Sagar dma-coherent; 25272602c32fSVidya Sagar }; 25282602c32fSVidya Sagar 25292602c32fSVidya Sagar pcie@14160000 { 2530f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25312602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2532644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2533644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2534644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2535644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25362602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25372602c32fSVidya Sagar 25382602c32fSVidya Sagar status = "disabled"; 25392602c32fSVidya Sagar 25402602c32fSVidya Sagar #address-cells = <3>; 25412602c32fSVidya Sagar #size-cells = <2>; 25422602c32fSVidya Sagar device_type = "pci"; 25432602c32fSVidya Sagar num-lanes = <4>; 25442602c32fSVidya Sagar linux,pci-domain = <4>; 25452602c32fSVidya Sagar 25462602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25472602c32fSVidya Sagar clock-names = "core"; 25482602c32fSVidya Sagar 25492602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25502602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25512602c32fSVidya Sagar reset-names = "apb", "core"; 25522602c32fSVidya Sagar 25532602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25542602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25552602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25562602c32fSVidya Sagar 25572602c32fSVidya Sagar #interrupt-cells = <1>; 25582602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25592602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25602602c32fSVidya Sagar 25612602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25622602c32fSVidya Sagar 25632602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25642602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25652602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25662602c32fSVidya Sagar 25672602c32fSVidya Sagar bus-range = <0x0 0xff>; 2568d5237c7cSThierry Reding 25698a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25708a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25718a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2572d5237c7cSThierry Reding 2573d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2574d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2575ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2576ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2577ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2578ba02920cSVidya Sagar dma-coherent; 25792602c32fSVidya Sagar }; 25802602c32fSVidya Sagar 2581*2838cfddSThierry Reding pcie-ep@14160000 { 2582*2838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 2583*2838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2584*2838cfddSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2585*2838cfddSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2586*2838cfddSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2587*2838cfddSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2588*2838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2589*2838cfddSThierry Reding 2590*2838cfddSThierry Reding status = "disabled"; 2591*2838cfddSThierry Reding 2592*2838cfddSThierry Reding num-lanes = <4>; 2593*2838cfddSThierry Reding num-ib-windows = <2>; 2594*2838cfddSThierry Reding num-ob-windows = <8>; 2595*2838cfddSThierry Reding 2596*2838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2597*2838cfddSThierry Reding clock-names = "core"; 2598*2838cfddSThierry Reding 2599*2838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2600*2838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2601*2838cfddSThierry Reding reset-names = "apb", "core"; 2602*2838cfddSThierry Reding 2603*2838cfddSThierry Reding interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2604*2838cfddSThierry Reding interrupt-names = "intr"; 2605*2838cfddSThierry Reding 2606*2838cfddSThierry Reding nvidia,bpmp = <&bpmp 4>; 2607*2838cfddSThierry Reding 2608*2838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 2609*2838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 2610*2838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 2611*2838cfddSThierry Reding 2612*2838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2613*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2614*2838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 2615*2838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2616*2838cfddSThierry Reding iommu-map-mask = <0x0>; 2617*2838cfddSThierry Reding dma-coherent; 2618*2838cfddSThierry Reding }; 2619*2838cfddSThierry Reding 26202602c32fSVidya Sagar pcie@14180000 { 2621f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26222602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2623644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2624644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2625644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2626644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26272602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26282602c32fSVidya Sagar 26292602c32fSVidya Sagar status = "disabled"; 26302602c32fSVidya Sagar 26312602c32fSVidya Sagar #address-cells = <3>; 26322602c32fSVidya Sagar #size-cells = <2>; 26332602c32fSVidya Sagar device_type = "pci"; 26342602c32fSVidya Sagar num-lanes = <8>; 26352602c32fSVidya Sagar linux,pci-domain = <0>; 26362602c32fSVidya Sagar 26372602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26382602c32fSVidya Sagar clock-names = "core"; 26392602c32fSVidya Sagar 26402602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26412602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26422602c32fSVidya Sagar reset-names = "apb", "core"; 26432602c32fSVidya Sagar 26442602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26452602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26462602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26472602c32fSVidya Sagar 26482602c32fSVidya Sagar #interrupt-cells = <1>; 26492602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26502602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26512602c32fSVidya Sagar 26522602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26532602c32fSVidya Sagar 26542602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26552602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26562602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26572602c32fSVidya Sagar 26582602c32fSVidya Sagar bus-range = <0x0 0xff>; 2659d5237c7cSThierry Reding 26608a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26618a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26628a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2663d5237c7cSThierry Reding 2664d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2665d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2666ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2667ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2668ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2669ba02920cSVidya Sagar dma-coherent; 26702602c32fSVidya Sagar }; 26712602c32fSVidya Sagar 2672*2838cfddSThierry Reding pcie-ep@14180000 { 2673*2838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 2674*2838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2675*2838cfddSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2676*2838cfddSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2677*2838cfddSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2678*2838cfddSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2679*2838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2680*2838cfddSThierry Reding 2681*2838cfddSThierry Reding status = "disabled"; 2682*2838cfddSThierry Reding 2683*2838cfddSThierry Reding num-lanes = <8>; 2684*2838cfddSThierry Reding num-ib-windows = <2>; 2685*2838cfddSThierry Reding num-ob-windows = <8>; 2686*2838cfddSThierry Reding 2687*2838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2688*2838cfddSThierry Reding clock-names = "core"; 2689*2838cfddSThierry Reding 2690*2838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2691*2838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2692*2838cfddSThierry Reding reset-names = "apb", "core"; 2693*2838cfddSThierry Reding 2694*2838cfddSThierry Reding interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2695*2838cfddSThierry Reding interrupt-names = "intr"; 2696*2838cfddSThierry Reding 2697*2838cfddSThierry Reding nvidia,bpmp = <&bpmp 0>; 2698*2838cfddSThierry Reding 2699*2838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 2700*2838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 2701*2838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 2702*2838cfddSThierry Reding 2703*2838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2704*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2705*2838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 2706*2838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2707*2838cfddSThierry Reding iommu-map-mask = <0x0>; 2708*2838cfddSThierry Reding dma-coherent; 2709*2838cfddSThierry Reding }; 2710*2838cfddSThierry Reding 27112602c32fSVidya Sagar pcie@141a0000 { 2712f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 27132602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2714644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2715644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2716644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2717644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 27182602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 27192602c32fSVidya Sagar 27202602c32fSVidya Sagar status = "disabled"; 27212602c32fSVidya Sagar 27222602c32fSVidya Sagar #address-cells = <3>; 27232602c32fSVidya Sagar #size-cells = <2>; 27242602c32fSVidya Sagar device_type = "pci"; 27252602c32fSVidya Sagar num-lanes = <8>; 27262602c32fSVidya Sagar linux,pci-domain = <5>; 27272602c32fSVidya Sagar 2728dbb72e2cSVidya Sagar pinctrl-names = "default"; 2729dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2730dbb72e2cSVidya Sagar 2731c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2732c453cc9eSThierry Reding clock-names = "core"; 27332602c32fSVidya Sagar 27342602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27352602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27362602c32fSVidya Sagar reset-names = "apb", "core"; 27372602c32fSVidya Sagar 27382602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27392602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27402602c32fSVidya Sagar interrupt-names = "intr", "msi"; 27412602c32fSVidya Sagar 27422602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 27432602c32fSVidya Sagar 27442602c32fSVidya Sagar #interrupt-cells = <1>; 27452602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 27462602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 27472602c32fSVidya Sagar 27482602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 27492602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27502602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 27512602c32fSVidya Sagar 27522602c32fSVidya Sagar bus-range = <0x0 0xff>; 2753d5237c7cSThierry Reding 27548a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 27558a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 27568a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2757d5237c7cSThierry Reding 2758d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2759d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2760ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2761ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2762ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2763ba02920cSVidya Sagar dma-coherent; 27642602c32fSVidya Sagar }; 27652602c32fSVidya Sagar 2766b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2767bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27680c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2769644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2770644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2771644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2772644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27730c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27740c988b73SVidya Sagar 27750c988b73SVidya Sagar status = "disabled"; 27760c988b73SVidya Sagar 27770c988b73SVidya Sagar num-lanes = <8>; 27780c988b73SVidya Sagar num-ib-windows = <2>; 27790c988b73SVidya Sagar num-ob-windows = <8>; 27800c988b73SVidya Sagar 27810c988b73SVidya Sagar pinctrl-names = "default"; 27820c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 27830c988b73SVidya Sagar 27840c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 27850c988b73SVidya Sagar clock-names = "core"; 27860c988b73SVidya Sagar 27870c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27880c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27890c988b73SVidya Sagar reset-names = "apb", "core"; 27900c988b73SVidya Sagar 27910c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27920c988b73SVidya Sagar interrupt-names = "intr"; 27930c988b73SVidya Sagar 27940c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 27950c988b73SVidya Sagar 27960c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27970c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27980c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2799ba02920cSVidya Sagar 2800ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2801ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2802ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2803ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2804ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2805ba02920cSVidya Sagar dma-coherent; 28060c988b73SVidya Sagar }; 28070c988b73SVidya Sagar 2808*2838cfddSThierry Reding gpu@17000000 { 2809*2838cfddSThierry Reding compatible = "nvidia,gv11b"; 2810*2838cfddSThierry Reding reg = <0x0 0x17000000 0x0 0x1000000>, 2811*2838cfddSThierry Reding <0x0 0x18000000 0x0 0x1000000>; 2812*2838cfddSThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2813*2838cfddSThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2814*2838cfddSThierry Reding interrupt-names = "stall", "nonstall"; 2815*2838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2816*2838cfddSThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 2817*2838cfddSThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 2818*2838cfddSThierry Reding clock-names = "gpu", "pwr", "fuse"; 2819*2838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 2820*2838cfddSThierry Reding reset-names = "gpu"; 2821*2838cfddSThierry Reding dma-coherent; 2822*2838cfddSThierry Reding 2823*2838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2824*2838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2825*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2826*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2827*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2828*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2829*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2830*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2831*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2832*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2833*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2834*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2835*2838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2836*2838cfddSThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 2837*2838cfddSThierry Reding "read-1", "read-1-hp", "write-1", 2838*2838cfddSThierry Reding "read-2", "read-2-hp", "write-2", 2839*2838cfddSThierry Reding "read-3", "read-3-hp", "write-3"; 2840*2838cfddSThierry Reding }; 2841*2838cfddSThierry Reding }; 2842*2838cfddSThierry Reding 2843e867fe41SThierry Reding sram@40000000 { 28445425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28455425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 2846*2838cfddSThierry Reding 28475425fb15SMikko Perttunen #address-cells = <1>; 28485425fb15SMikko Perttunen #size-cells = <1>; 28495425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 2850*2838cfddSThierry Reding 285161192a9dSMikko Perttunen no-memory-wc; 28525425fb15SMikko Perttunen 2853e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28545425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28555425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28565425fb15SMikko Perttunen pool; 28575425fb15SMikko Perttunen }; 28585425fb15SMikko Perttunen 2859e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28605425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28615425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28625425fb15SMikko Perttunen pool; 28635425fb15SMikko Perttunen }; 28645425fb15SMikko Perttunen }; 28655425fb15SMikko Perttunen 28665425fb15SMikko Perttunen bpmp: bpmp { 28675425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28685425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28695425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28707fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28715425fb15SMikko Perttunen #clock-cells = <1>; 28725425fb15SMikko Perttunen #reset-cells = <1>; 28735425fb15SMikko Perttunen #power-domain-cells = <1>; 2874d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2875d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2876d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2877d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2878d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2879c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28805425fb15SMikko Perttunen 28815425fb15SMikko Perttunen bpmp_i2c: i2c { 28825425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28835425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28845425fb15SMikko Perttunen #address-cells = <1>; 28855425fb15SMikko Perttunen #size-cells = <0>; 28865425fb15SMikko Perttunen }; 28875425fb15SMikko Perttunen 28885425fb15SMikko Perttunen bpmp_thermal: thermal { 28895425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28905425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28915425fb15SMikko Perttunen }; 28925425fb15SMikko Perttunen }; 28935425fb15SMikko Perttunen 28947780a034SMikko Perttunen cpus { 2895d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2896d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28977780a034SMikko Perttunen #address-cells = <1>; 28987780a034SMikko Perttunen #size-cells = <0>; 28997780a034SMikko Perttunen 2900b45d322cSThierry Reding cpu0_0: cpu@0 { 290131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29027780a034SMikko Perttunen device_type = "cpu"; 2903b45d322cSThierry Reding reg = <0x000>; 29047780a034SMikko Perttunen enable-method = "psci"; 2905b45d322cSThierry Reding i-cache-size = <131072>; 2906b45d322cSThierry Reding i-cache-line-size = <64>; 2907b45d322cSThierry Reding i-cache-sets = <512>; 2908b45d322cSThierry Reding d-cache-size = <65536>; 2909b45d322cSThierry Reding d-cache-line-size = <64>; 2910b45d322cSThierry Reding d-cache-sets = <256>; 2911b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29127780a034SMikko Perttunen }; 29137780a034SMikko Perttunen 2914b45d322cSThierry Reding cpu0_1: cpu@1 { 291531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29167780a034SMikko Perttunen device_type = "cpu"; 2917b45d322cSThierry Reding reg = <0x001>; 29187780a034SMikko Perttunen enable-method = "psci"; 2919b45d322cSThierry Reding i-cache-size = <131072>; 2920b45d322cSThierry Reding i-cache-line-size = <64>; 2921b45d322cSThierry Reding i-cache-sets = <512>; 2922b45d322cSThierry Reding d-cache-size = <65536>; 2923b45d322cSThierry Reding d-cache-line-size = <64>; 2924b45d322cSThierry Reding d-cache-sets = <256>; 2925b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29267780a034SMikko Perttunen }; 29277780a034SMikko Perttunen 2928b45d322cSThierry Reding cpu1_0: cpu@100 { 292931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29307780a034SMikko Perttunen device_type = "cpu"; 29317780a034SMikko Perttunen reg = <0x100>; 29327780a034SMikko Perttunen enable-method = "psci"; 2933b45d322cSThierry Reding i-cache-size = <131072>; 2934b45d322cSThierry Reding i-cache-line-size = <64>; 2935b45d322cSThierry Reding i-cache-sets = <512>; 2936b45d322cSThierry Reding d-cache-size = <65536>; 2937b45d322cSThierry Reding d-cache-line-size = <64>; 2938b45d322cSThierry Reding d-cache-sets = <256>; 2939b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29407780a034SMikko Perttunen }; 29417780a034SMikko Perttunen 2942b45d322cSThierry Reding cpu1_1: cpu@101 { 294331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29447780a034SMikko Perttunen device_type = "cpu"; 29457780a034SMikko Perttunen reg = <0x101>; 29467780a034SMikko Perttunen enable-method = "psci"; 2947b45d322cSThierry Reding i-cache-size = <131072>; 2948b45d322cSThierry Reding i-cache-line-size = <64>; 2949b45d322cSThierry Reding i-cache-sets = <512>; 2950b45d322cSThierry Reding d-cache-size = <65536>; 2951b45d322cSThierry Reding d-cache-line-size = <64>; 2952b45d322cSThierry Reding d-cache-sets = <256>; 2953b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29547780a034SMikko Perttunen }; 29557780a034SMikko Perttunen 2956b45d322cSThierry Reding cpu2_0: cpu@200 { 295731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29587780a034SMikko Perttunen device_type = "cpu"; 29597780a034SMikko Perttunen reg = <0x200>; 29607780a034SMikko Perttunen enable-method = "psci"; 2961b45d322cSThierry Reding i-cache-size = <131072>; 2962b45d322cSThierry Reding i-cache-line-size = <64>; 2963b45d322cSThierry Reding i-cache-sets = <512>; 2964b45d322cSThierry Reding d-cache-size = <65536>; 2965b45d322cSThierry Reding d-cache-line-size = <64>; 2966b45d322cSThierry Reding d-cache-sets = <256>; 2967b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29687780a034SMikko Perttunen }; 29697780a034SMikko Perttunen 2970b45d322cSThierry Reding cpu2_1: cpu@201 { 297131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29727780a034SMikko Perttunen device_type = "cpu"; 29737780a034SMikko Perttunen reg = <0x201>; 29747780a034SMikko Perttunen enable-method = "psci"; 2975b45d322cSThierry Reding i-cache-size = <131072>; 2976b45d322cSThierry Reding i-cache-line-size = <64>; 2977b45d322cSThierry Reding i-cache-sets = <512>; 2978b45d322cSThierry Reding d-cache-size = <65536>; 2979b45d322cSThierry Reding d-cache-line-size = <64>; 2980b45d322cSThierry Reding d-cache-sets = <256>; 2981b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29827780a034SMikko Perttunen }; 29837780a034SMikko Perttunen 2984b45d322cSThierry Reding cpu3_0: cpu@300 { 298531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29867780a034SMikko Perttunen device_type = "cpu"; 2987b45d322cSThierry Reding reg = <0x300>; 29887780a034SMikko Perttunen enable-method = "psci"; 2989b45d322cSThierry Reding i-cache-size = <131072>; 2990b45d322cSThierry Reding i-cache-line-size = <64>; 2991b45d322cSThierry Reding i-cache-sets = <512>; 2992b45d322cSThierry Reding d-cache-size = <65536>; 2993b45d322cSThierry Reding d-cache-line-size = <64>; 2994b45d322cSThierry Reding d-cache-sets = <256>; 2995b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29967780a034SMikko Perttunen }; 29977780a034SMikko Perttunen 2998b45d322cSThierry Reding cpu3_1: cpu@301 { 299931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 30007780a034SMikko Perttunen device_type = "cpu"; 3001b45d322cSThierry Reding reg = <0x301>; 30027780a034SMikko Perttunen enable-method = "psci"; 3003b45d322cSThierry Reding i-cache-size = <131072>; 3004b45d322cSThierry Reding i-cache-line-size = <64>; 3005b45d322cSThierry Reding i-cache-sets = <512>; 3006b45d322cSThierry Reding d-cache-size = <65536>; 3007b45d322cSThierry Reding d-cache-line-size = <64>; 3008b45d322cSThierry Reding d-cache-sets = <256>; 3009b45d322cSThierry Reding next-level-cache = <&l2c_3>; 3010b45d322cSThierry Reding }; 3011b45d322cSThierry Reding 3012b45d322cSThierry Reding cpu-map { 3013b45d322cSThierry Reding cluster0 { 3014b45d322cSThierry Reding core0 { 3015b45d322cSThierry Reding cpu = <&cpu0_0>; 3016b45d322cSThierry Reding }; 3017b45d322cSThierry Reding 3018b45d322cSThierry Reding core1 { 3019b45d322cSThierry Reding cpu = <&cpu0_1>; 3020b45d322cSThierry Reding }; 3021b45d322cSThierry Reding }; 3022b45d322cSThierry Reding 3023b45d322cSThierry Reding cluster1 { 3024b45d322cSThierry Reding core0 { 3025b45d322cSThierry Reding cpu = <&cpu1_0>; 3026b45d322cSThierry Reding }; 3027b45d322cSThierry Reding 3028b45d322cSThierry Reding core1 { 3029b45d322cSThierry Reding cpu = <&cpu1_1>; 3030b45d322cSThierry Reding }; 3031b45d322cSThierry Reding }; 3032b45d322cSThierry Reding 3033b45d322cSThierry Reding cluster2 { 3034b45d322cSThierry Reding core0 { 3035b45d322cSThierry Reding cpu = <&cpu2_0>; 3036b45d322cSThierry Reding }; 3037b45d322cSThierry Reding 3038b45d322cSThierry Reding core1 { 3039b45d322cSThierry Reding cpu = <&cpu2_1>; 3040b45d322cSThierry Reding }; 3041b45d322cSThierry Reding }; 3042b45d322cSThierry Reding 3043b45d322cSThierry Reding cluster3 { 3044b45d322cSThierry Reding core0 { 3045b45d322cSThierry Reding cpu = <&cpu3_0>; 3046b45d322cSThierry Reding }; 3047b45d322cSThierry Reding 3048b45d322cSThierry Reding core1 { 3049b45d322cSThierry Reding cpu = <&cpu3_1>; 3050b45d322cSThierry Reding }; 3051b45d322cSThierry Reding }; 3052b45d322cSThierry Reding }; 3053b45d322cSThierry Reding 3054b45d322cSThierry Reding l2c_0: l2-cache0 { 305527f1568bSPierre Gondois compatible = "cache"; 305627f1568bSPierre Gondois cache-unified; 3057b45d322cSThierry Reding cache-size = <2097152>; 3058b45d322cSThierry Reding cache-line-size = <64>; 3059b45d322cSThierry Reding cache-sets = <2048>; 306027f1568bSPierre Gondois cache-level = <2>; 3061b45d322cSThierry Reding next-level-cache = <&l3c>; 3062b45d322cSThierry Reding }; 3063b45d322cSThierry Reding 3064b45d322cSThierry Reding l2c_1: l2-cache1 { 306527f1568bSPierre Gondois compatible = "cache"; 306627f1568bSPierre Gondois cache-unified; 3067b45d322cSThierry Reding cache-size = <2097152>; 3068b45d322cSThierry Reding cache-line-size = <64>; 3069b45d322cSThierry Reding cache-sets = <2048>; 307027f1568bSPierre Gondois cache-level = <2>; 3071b45d322cSThierry Reding next-level-cache = <&l3c>; 3072b45d322cSThierry Reding }; 3073b45d322cSThierry Reding 3074b45d322cSThierry Reding l2c_2: l2-cache2 { 307527f1568bSPierre Gondois compatible = "cache"; 307627f1568bSPierre Gondois cache-unified; 3077b45d322cSThierry Reding cache-size = <2097152>; 3078b45d322cSThierry Reding cache-line-size = <64>; 3079b45d322cSThierry Reding cache-sets = <2048>; 308027f1568bSPierre Gondois cache-level = <2>; 3081b45d322cSThierry Reding next-level-cache = <&l3c>; 3082b45d322cSThierry Reding }; 3083b45d322cSThierry Reding 3084b45d322cSThierry Reding l2c_3: l2-cache3 { 308527f1568bSPierre Gondois compatible = "cache"; 308627f1568bSPierre Gondois cache-unified; 3087b45d322cSThierry Reding cache-size = <2097152>; 3088b45d322cSThierry Reding cache-line-size = <64>; 3089b45d322cSThierry Reding cache-sets = <2048>; 309027f1568bSPierre Gondois cache-level = <2>; 3091b45d322cSThierry Reding next-level-cache = <&l3c>; 3092b45d322cSThierry Reding }; 3093b45d322cSThierry Reding 3094b45d322cSThierry Reding l3c: l3-cache { 309527f1568bSPierre Gondois compatible = "cache"; 309627f1568bSPierre Gondois cache-unified; 3097b45d322cSThierry Reding cache-size = <4194304>; 3098b45d322cSThierry Reding cache-line-size = <64>; 309927f1568bSPierre Gondois cache-level = <3>; 3100b45d322cSThierry Reding cache-sets = <4096>; 31017780a034SMikko Perttunen }; 31027780a034SMikko Perttunen }; 31037780a034SMikko Perttunen 31049e79e58fSJon Hunter pmu { 3105f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 31069e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 31079e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 31089e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 31099e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 31109e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 31119e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 31129e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 31139e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 31149e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 31159e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 31169e79e58fSJon Hunter }; 31179e79e58fSJon Hunter 31187780a034SMikko Perttunen psci { 31197780a034SMikko Perttunen compatible = "arm,psci-1.0"; 31207780a034SMikko Perttunen status = "okay"; 31217780a034SMikko Perttunen method = "smc"; 31227780a034SMikko Perttunen }; 31237780a034SMikko Perttunen 31245b4f6323SSameer Pujar sound { 31255b4f6323SSameer Pujar status = "disabled"; 31265b4f6323SSameer Pujar 31275b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 31285b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31295b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 31305b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 31315b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 31325b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 31335b4f6323SSameer Pujar assigned-clock-parents = <0>, 31345b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 31355b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31365b4f6323SSameer Pujar /* 31375b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31385b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31395b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31405b4f6323SSameer Pujar */ 31415b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31425b4f6323SSameer Pujar }; 31435b4f6323SSameer Pujar 314499d9bde5SThierry Reding tcu: serial { 3145a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 3146a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3147a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3148a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 3149a38570c2SMikko Perttunen }; 3150a38570c2SMikko Perttunen 3151686ba009SThierry Reding thermal-zones { 3152fe57ff53SThierry Reding cpu-thermal { 3153fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3154686ba009SThierry Reding status = "disabled"; 3155686ba009SThierry Reding }; 3156686ba009SThierry Reding 3157fe57ff53SThierry Reding gpu-thermal { 3158fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3159686ba009SThierry Reding status = "disabled"; 3160686ba009SThierry Reding }; 3161686ba009SThierry Reding 3162fe57ff53SThierry Reding aux-thermal { 3163fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3164686ba009SThierry Reding status = "disabled"; 3165686ba009SThierry Reding }; 3166686ba009SThierry Reding 3167fe57ff53SThierry Reding pllx-thermal { 3168fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3169686ba009SThierry Reding status = "disabled"; 3170686ba009SThierry Reding }; 3171686ba009SThierry Reding 3172fe57ff53SThierry Reding ao-thermal { 3173fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3174686ba009SThierry Reding status = "disabled"; 3175686ba009SThierry Reding }; 3176686ba009SThierry Reding 3177fe57ff53SThierry Reding tj-thermal { 3178fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3179686ba009SThierry Reding status = "disabled"; 3180686ba009SThierry Reding }; 3181686ba009SThierry Reding }; 3182686ba009SThierry Reding 31835425fb15SMikko Perttunen timer { 31845425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31855425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31865425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31875425fb15SMikko Perttunen <GIC_PPI 14 31885425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31895425fb15SMikko Perttunen <GIC_PPI 11 31905425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31915425fb15SMikko Perttunen <GIC_PPI 10 31925425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31935425fb15SMikko Perttunen interrupt-parent = <&gic>; 3194b30be673SThierry Reding always-on; 31955425fb15SMikko Perttunen }; 31965425fb15SMikko Perttunen}; 3197