15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 225425fb15SMikko Perttunen #address-cells = <1>; 235425fb15SMikko Perttunen #size-cells = <1>; 245425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 255425fb15SMikko Perttunen 26a47e173eSSumit Gupta apbmisc: misc@100000 { 2709903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2809903c5eSJC Kuo reg = <0x00100000 0xf000>, 2909903c5eSJC Kuo <0x0010f000 0x1000>; 3009903c5eSJC Kuo }; 3109903c5eSJC Kuo 32f69ce393SMikko Perttunen gpio: gpio@2200000 { 33f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 34f69ce393SMikko Perttunen reg-names = "security", "gpio"; 35f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 36f69ce393SMikko Perttunen <0x2210000 0x10000>; 37f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85f69ce393SMikko Perttunen #interrupt-cells = <2>; 86f69ce393SMikko Perttunen interrupt-controller; 87f69ce393SMikko Perttunen #gpio-cells = <2>; 88f69ce393SMikko Perttunen gpio-controller; 896f380a4eSThierry Reding gpio-ranges = <&pinmux 0 0 169>; 90f69ce393SMikko Perttunen }; 91f69ce393SMikko Perttunen 92a47e173eSSumit Gupta cbb-noc@2300000 { 93a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 94a47e173eSSumit Gupta reg = <0x02300000 0x1000>; 95a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 96a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 97a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 98a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 99a47e173eSSumit Gupta status = "okay"; 100a47e173eSSumit Gupta }; 101a47e173eSSumit Gupta 102a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 103a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 104a47e173eSSumit Gupta reg = <0x2390000 0x1000>, 105a47e173eSSumit Gupta <0x23a0000 0x1000>, 106a47e173eSSumit Gupta <0x23b0000 0x1000>, 107a47e173eSSumit Gupta <0x23c0000 0x1000>, 108a47e173eSSumit Gupta <0x23d0000 0x1000>, 109a47e173eSSumit Gupta <0x23e0000 0x1000>; 110a47e173eSSumit Gupta status = "okay"; 111a47e173eSSumit Gupta }; 112a47e173eSSumit Gupta 113f89b58ceSMikko Perttunen ethernet@2490000 { 11419dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 11519dc772aSThierry Reding "nvidia,tegra186-eqos", 116f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 117f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 118f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 119f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 120f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 121f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 122f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 123f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 124f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 125f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 126f89b58ceSMikko Perttunen reset-names = "eqos"; 127d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 128d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 129d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 130c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 131f89b58ceSMikko Perttunen status = "disabled"; 132f89b58ceSMikko Perttunen 133f89b58ceSMikko Perttunen snps,write-requests = <1>; 134f89b58ceSMikko Perttunen snps,read-requests = <3>; 135f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 136f89b58ceSMikko Perttunen snps,txpbl = <16>; 137f89b58ceSMikko Perttunen snps,rxpbl = <8>; 138f89b58ceSMikko Perttunen }; 139f89b58ceSMikko Perttunen 140835553b3SAkhil R gpcdma: dma-controller@2600000 { 141835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 142835553b3SAkhil R "nvidia,tegra186-gpcdma"; 143835553b3SAkhil R reg = <0x2600000 0x210000>; 144835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 145835553b3SAkhil R reset-names = "gpcdma"; 146dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 147dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 148835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 149835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 150835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 151835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 152835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 153835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 154835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 155835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 156835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 157835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 158835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 159835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 160835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 161835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 162835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 163835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 164835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 165835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 166835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 167835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 168835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 169835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 170835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 171835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 172835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 173835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 174835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 175835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 176835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 177835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 178835553b3SAkhil R #dma-cells = <1>; 179835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 180835553b3SAkhil R dma-coherent; 181dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 182835553b3SAkhil R status = "okay"; 183835553b3SAkhil R }; 184835553b3SAkhil R 1851aaa7698SThierry Reding aconnect@2900000 { 1865d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1875d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1885d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1895d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1905d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1915d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1925d2249ddSSameer Pujar #address-cells = <1>; 1935d2249ddSSameer Pujar #size-cells = <1>; 1945d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1955d2249ddSSameer Pujar status = "disabled"; 1965d2249ddSSameer Pujar 197177208f7SSameer Pujar adma: dma-controller@2930000 { 1985d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1995d2249ddSSameer Pujar "nvidia,tegra186-adma"; 2005d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 2015d2249ddSSameer Pujar interrupt-parent = <&agic>; 2025d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2035d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2045d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2055d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2065d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2075d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2085d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2095d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2105d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2115d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2125d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2135d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2145d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2155d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2165d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2175d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2185d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2195d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2205d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2215d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2225d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2235d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2245d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2255d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2265d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2275d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2285d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2295d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2305d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2315d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2325d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2335d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2345d2249ddSSameer Pujar #dma-cells = <1>; 2355d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 2365d2249ddSSameer Pujar clock-names = "d_audio"; 2375d2249ddSSameer Pujar status = "disabled"; 2385d2249ddSSameer Pujar }; 2395d2249ddSSameer Pujar 2405d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 2415d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 2425d2249ddSSameer Pujar "nvidia,tegra210-agic"; 2435d2249ddSSameer Pujar #interrupt-cells = <3>; 2445d2249ddSSameer Pujar interrupt-controller; 2455d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 2465d2249ddSSameer Pujar <0x02a42000 0x2000>; 2475d2249ddSSameer Pujar interrupts = <GIC_SPI 145 2485d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 2495d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 2505d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 2515d2249ddSSameer Pujar clock-names = "clk"; 2525d2249ddSSameer Pujar status = "disabled"; 2535d2249ddSSameer Pujar }; 254177208f7SSameer Pujar 255177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 256177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 257177208f7SSameer Pujar "nvidia,tegra186-ahub"; 258177208f7SSameer Pujar reg = <0x02900800 0x800>; 259177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 260177208f7SSameer Pujar clock-names = "ahub"; 261177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 262177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 263177208f7SSameer Pujar #address-cells = <1>; 264177208f7SSameer Pujar #size-cells = <1>; 265177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 266177208f7SSameer Pujar status = "disabled"; 267177208f7SSameer Pujar 268177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 269177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 270177208f7SSameer Pujar "nvidia,tegra186-admaif"; 271177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 272177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 273177208f7SSameer Pujar <&adma 2>, <&adma 2>, 274177208f7SSameer Pujar <&adma 3>, <&adma 3>, 275177208f7SSameer Pujar <&adma 4>, <&adma 4>, 276177208f7SSameer Pujar <&adma 5>, <&adma 5>, 277177208f7SSameer Pujar <&adma 6>, <&adma 6>, 278177208f7SSameer Pujar <&adma 7>, <&adma 7>, 279177208f7SSameer Pujar <&adma 8>, <&adma 8>, 280177208f7SSameer Pujar <&adma 9>, <&adma 9>, 281177208f7SSameer Pujar <&adma 10>, <&adma 10>, 282177208f7SSameer Pujar <&adma 11>, <&adma 11>, 283177208f7SSameer Pujar <&adma 12>, <&adma 12>, 284177208f7SSameer Pujar <&adma 13>, <&adma 13>, 285177208f7SSameer Pujar <&adma 14>, <&adma 14>, 286177208f7SSameer Pujar <&adma 15>, <&adma 15>, 287177208f7SSameer Pujar <&adma 16>, <&adma 16>, 288177208f7SSameer Pujar <&adma 17>, <&adma 17>, 289177208f7SSameer Pujar <&adma 18>, <&adma 18>, 290177208f7SSameer Pujar <&adma 19>, <&adma 19>, 291177208f7SSameer Pujar <&adma 20>, <&adma 20>; 292177208f7SSameer Pujar dma-names = "rx1", "tx1", 293177208f7SSameer Pujar "rx2", "tx2", 294177208f7SSameer Pujar "rx3", "tx3", 295177208f7SSameer Pujar "rx4", "tx4", 296177208f7SSameer Pujar "rx5", "tx5", 297177208f7SSameer Pujar "rx6", "tx6", 298177208f7SSameer Pujar "rx7", "tx7", 299177208f7SSameer Pujar "rx8", "tx8", 300177208f7SSameer Pujar "rx9", "tx9", 301177208f7SSameer Pujar "rx10", "tx10", 302177208f7SSameer Pujar "rx11", "tx11", 303177208f7SSameer Pujar "rx12", "tx12", 304177208f7SSameer Pujar "rx13", "tx13", 305177208f7SSameer Pujar "rx14", "tx14", 306177208f7SSameer Pujar "rx15", "tx15", 307177208f7SSameer Pujar "rx16", "tx16", 308177208f7SSameer Pujar "rx17", "tx17", 309177208f7SSameer Pujar "rx18", "tx18", 310177208f7SSameer Pujar "rx19", "tx19", 311177208f7SSameer Pujar "rx20", "tx20"; 312177208f7SSameer Pujar status = "disabled"; 313cd0c2edfSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 314cd0c2edfSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 315cd0c2edfSThierry Reding interconnect-names = "dma-mem", "write"; 316cd0c2edfSThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 317177208f7SSameer Pujar }; 318177208f7SSameer Pujar 319177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 320177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 321177208f7SSameer Pujar "nvidia,tegra210-i2s"; 322177208f7SSameer Pujar reg = <0x2901000 0x100>; 323177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 324177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 325177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 326177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 327177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 328177208f7SSameer Pujar assigned-clock-rates = <1536000>; 329177208f7SSameer Pujar sound-name-prefix = "I2S1"; 330177208f7SSameer Pujar status = "disabled"; 331177208f7SSameer Pujar }; 332177208f7SSameer Pujar 333177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 334177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 335177208f7SSameer Pujar "nvidia,tegra210-i2s"; 336177208f7SSameer Pujar reg = <0x2901100 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 338177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 339177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 340177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 341177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 342177208f7SSameer Pujar assigned-clock-rates = <1536000>; 343177208f7SSameer Pujar sound-name-prefix = "I2S2"; 344177208f7SSameer Pujar status = "disabled"; 345177208f7SSameer Pujar }; 346177208f7SSameer Pujar 347177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 348177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 349177208f7SSameer Pujar "nvidia,tegra210-i2s"; 350177208f7SSameer Pujar reg = <0x2901200 0x100>; 351177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 352177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 353177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 354177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 355177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 356177208f7SSameer Pujar assigned-clock-rates = <1536000>; 357177208f7SSameer Pujar sound-name-prefix = "I2S3"; 358177208f7SSameer Pujar status = "disabled"; 359177208f7SSameer Pujar }; 360177208f7SSameer Pujar 361177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 362177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 363177208f7SSameer Pujar "nvidia,tegra210-i2s"; 364177208f7SSameer Pujar reg = <0x2901300 0x100>; 365177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 366177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 367177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 368177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 369177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 370177208f7SSameer Pujar assigned-clock-rates = <1536000>; 371177208f7SSameer Pujar sound-name-prefix = "I2S4"; 372177208f7SSameer Pujar status = "disabled"; 373177208f7SSameer Pujar }; 374177208f7SSameer Pujar 375177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 376177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 377177208f7SSameer Pujar "nvidia,tegra210-i2s"; 378177208f7SSameer Pujar reg = <0x2901400 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 380177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 381177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 382177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 383177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 384177208f7SSameer Pujar assigned-clock-rates = <1536000>; 385177208f7SSameer Pujar sound-name-prefix = "I2S5"; 386177208f7SSameer Pujar status = "disabled"; 387177208f7SSameer Pujar }; 388177208f7SSameer Pujar 389177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 390177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 391177208f7SSameer Pujar "nvidia,tegra210-i2s"; 392177208f7SSameer Pujar reg = <0x2901500 0x100>; 393177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 394177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 395177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 396177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 397177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 398177208f7SSameer Pujar assigned-clock-rates = <1536000>; 399177208f7SSameer Pujar sound-name-prefix = "I2S6"; 400177208f7SSameer Pujar status = "disabled"; 401177208f7SSameer Pujar }; 402177208f7SSameer Pujar 403177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 404177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 405177208f7SSameer Pujar "nvidia,tegra210-dmic"; 406177208f7SSameer Pujar reg = <0x2904000 0x100>; 407177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 408177208f7SSameer Pujar clock-names = "dmic"; 409177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 410177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 411177208f7SSameer Pujar assigned-clock-rates = <3072000>; 412177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 413177208f7SSameer Pujar status = "disabled"; 414177208f7SSameer Pujar }; 415177208f7SSameer Pujar 416177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 417177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 418177208f7SSameer Pujar "nvidia,tegra210-dmic"; 419177208f7SSameer Pujar reg = <0x2904100 0x100>; 420177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 421177208f7SSameer Pujar clock-names = "dmic"; 422177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 423177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 424177208f7SSameer Pujar assigned-clock-rates = <3072000>; 425177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 426177208f7SSameer Pujar status = "disabled"; 427177208f7SSameer Pujar }; 428177208f7SSameer Pujar 429177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 430177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 431177208f7SSameer Pujar "nvidia,tegra210-dmic"; 432177208f7SSameer Pujar reg = <0x2904200 0x100>; 433177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 434177208f7SSameer Pujar clock-names = "dmic"; 435177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 436177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 437177208f7SSameer Pujar assigned-clock-rates = <3072000>; 438177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 439177208f7SSameer Pujar status = "disabled"; 440177208f7SSameer Pujar }; 441177208f7SSameer Pujar 442177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 443177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 444177208f7SSameer Pujar "nvidia,tegra210-dmic"; 445177208f7SSameer Pujar reg = <0x2904300 0x100>; 446177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 447177208f7SSameer Pujar clock-names = "dmic"; 448177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 449177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 450177208f7SSameer Pujar assigned-clock-rates = <3072000>; 451177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 452177208f7SSameer Pujar status = "disabled"; 453177208f7SSameer Pujar }; 454177208f7SSameer Pujar 455177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 456177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 457177208f7SSameer Pujar "nvidia,tegra186-dspk"; 458177208f7SSameer Pujar reg = <0x2905000 0x100>; 459177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 460177208f7SSameer Pujar clock-names = "dspk"; 461177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 462177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 463177208f7SSameer Pujar assigned-clock-rates = <12288000>; 464177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 465177208f7SSameer Pujar status = "disabled"; 466177208f7SSameer Pujar }; 467177208f7SSameer Pujar 468177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 469177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 470177208f7SSameer Pujar "nvidia,tegra186-dspk"; 471177208f7SSameer Pujar reg = <0x2905100 0x100>; 472177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 473177208f7SSameer Pujar clock-names = "dspk"; 474177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 475177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 476177208f7SSameer Pujar assigned-clock-rates = <12288000>; 477177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 478177208f7SSameer Pujar status = "disabled"; 479177208f7SSameer Pujar }; 480848f3290SSameer Pujar 481848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 482848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 483848f3290SSameer Pujar "nvidia,tegra210-sfc"; 484848f3290SSameer Pujar reg = <0x2902000 0x200>; 485848f3290SSameer Pujar sound-name-prefix = "SFC1"; 486848f3290SSameer Pujar status = "disabled"; 487848f3290SSameer Pujar }; 488848f3290SSameer Pujar 489848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 490848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 491848f3290SSameer Pujar "nvidia,tegra210-sfc"; 492848f3290SSameer Pujar reg = <0x2902200 0x200>; 493848f3290SSameer Pujar sound-name-prefix = "SFC2"; 494848f3290SSameer Pujar status = "disabled"; 495848f3290SSameer Pujar }; 496848f3290SSameer Pujar 497848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 498848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 499848f3290SSameer Pujar "nvidia,tegra210-sfc"; 500848f3290SSameer Pujar reg = <0x2902400 0x200>; 501848f3290SSameer Pujar sound-name-prefix = "SFC3"; 502848f3290SSameer Pujar status = "disabled"; 503848f3290SSameer Pujar }; 504848f3290SSameer Pujar 505848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 506848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 507848f3290SSameer Pujar "nvidia,tegra210-sfc"; 508848f3290SSameer Pujar reg = <0x2902600 0x200>; 509848f3290SSameer Pujar sound-name-prefix = "SFC4"; 510848f3290SSameer Pujar status = "disabled"; 511848f3290SSameer Pujar }; 512848f3290SSameer Pujar 513848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 514848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 515848f3290SSameer Pujar "nvidia,tegra210-mvc"; 516848f3290SSameer Pujar reg = <0x290a000 0x200>; 517848f3290SSameer Pujar sound-name-prefix = "MVC1"; 518848f3290SSameer Pujar status = "disabled"; 519848f3290SSameer Pujar }; 520848f3290SSameer Pujar 521848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 522848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 523848f3290SSameer Pujar "nvidia,tegra210-mvc"; 524848f3290SSameer Pujar reg = <0x290a200 0x200>; 525848f3290SSameer Pujar sound-name-prefix = "MVC2"; 526848f3290SSameer Pujar status = "disabled"; 527848f3290SSameer Pujar }; 528848f3290SSameer Pujar 529848f3290SSameer Pujar tegra_amx1: amx@2903000 { 530848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 531848f3290SSameer Pujar reg = <0x2903000 0x100>; 532848f3290SSameer Pujar sound-name-prefix = "AMX1"; 533848f3290SSameer Pujar status = "disabled"; 534848f3290SSameer Pujar }; 535848f3290SSameer Pujar 536848f3290SSameer Pujar tegra_amx2: amx@2903100 { 537848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 538848f3290SSameer Pujar reg = <0x2903100 0x100>; 539848f3290SSameer Pujar sound-name-prefix = "AMX2"; 540848f3290SSameer Pujar status = "disabled"; 541848f3290SSameer Pujar }; 542848f3290SSameer Pujar 543848f3290SSameer Pujar tegra_amx3: amx@2903200 { 544848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 545848f3290SSameer Pujar reg = <0x2903200 0x100>; 546848f3290SSameer Pujar sound-name-prefix = "AMX3"; 547848f3290SSameer Pujar status = "disabled"; 548848f3290SSameer Pujar }; 549848f3290SSameer Pujar 550848f3290SSameer Pujar tegra_amx4: amx@2903300 { 551848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 552848f3290SSameer Pujar reg = <0x2903300 0x100>; 553848f3290SSameer Pujar sound-name-prefix = "AMX4"; 554848f3290SSameer Pujar status = "disabled"; 555848f3290SSameer Pujar }; 556848f3290SSameer Pujar 557848f3290SSameer Pujar tegra_adx1: adx@2903800 { 558848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 559848f3290SSameer Pujar "nvidia,tegra210-adx"; 560848f3290SSameer Pujar reg = <0x2903800 0x100>; 561848f3290SSameer Pujar sound-name-prefix = "ADX1"; 562848f3290SSameer Pujar status = "disabled"; 563848f3290SSameer Pujar }; 564848f3290SSameer Pujar 565848f3290SSameer Pujar tegra_adx2: adx@2903900 { 566848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 567848f3290SSameer Pujar "nvidia,tegra210-adx"; 568848f3290SSameer Pujar reg = <0x2903900 0x100>; 569848f3290SSameer Pujar sound-name-prefix = "ADX2"; 570848f3290SSameer Pujar status = "disabled"; 571848f3290SSameer Pujar }; 572848f3290SSameer Pujar 573848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 574848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 575848f3290SSameer Pujar "nvidia,tegra210-adx"; 576848f3290SSameer Pujar reg = <0x2903a00 0x100>; 577848f3290SSameer Pujar sound-name-prefix = "ADX3"; 578848f3290SSameer Pujar status = "disabled"; 579848f3290SSameer Pujar }; 580848f3290SSameer Pujar 581848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 582848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 583848f3290SSameer Pujar "nvidia,tegra210-adx"; 584848f3290SSameer Pujar reg = <0x2903b00 0x100>; 585848f3290SSameer Pujar sound-name-prefix = "ADX4"; 586848f3290SSameer Pujar status = "disabled"; 587848f3290SSameer Pujar }; 588848f3290SSameer Pujar 5894b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5904b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 5914b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5924b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5934b6a1b7cSSameer Pujar #address-cells = <1>; 5944b6a1b7cSSameer Pujar #size-cells = <1>; 5954b6a1b7cSSameer Pujar ranges; 5964b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5974b6a1b7cSSameer Pujar status = "disabled"; 5984b6a1b7cSSameer Pujar 5994b6a1b7cSSameer Pujar equalizer@2908100 { 6004b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 6014b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 6024b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 6034b6a1b7cSSameer Pujar }; 6044b6a1b7cSSameer Pujar 6054b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 6064b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 6074b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 6084b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 6094b6a1b7cSSameer Pujar }; 6104b6a1b7cSSameer Pujar }; 6114b6a1b7cSSameer Pujar 612848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 613848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 614848f3290SSameer Pujar "nvidia,tegra210-amixer"; 615848f3290SSameer Pujar reg = <0x290bb00 0x800>; 616848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 617848f3290SSameer Pujar status = "disabled"; 618848f3290SSameer Pujar }; 61947a08153SSameer Pujar 62047a08153SSameer Pujar tegra_asrc: asrc@2910000 { 62147a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 62247a08153SSameer Pujar "nvidia,tegra186-asrc"; 62347a08153SSameer Pujar reg = <0x2910000 0x2000>; 62447a08153SSameer Pujar sound-name-prefix = "ASRC1"; 62547a08153SSameer Pujar status = "disabled"; 62647a08153SSameer Pujar }; 627177208f7SSameer Pujar }; 6285d2249ddSSameer Pujar }; 6295d2249ddSSameer Pujar 630dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 631dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 6326f380a4eSThierry Reding reg = <0x2430000 0x17000>; 633dbb72e2cSVidya Sagar status = "okay"; 634dbb72e2cSVidya Sagar 635dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 636dbb72e2cSVidya Sagar pex_rst { 637dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 638dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 639dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6406b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 641dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 642dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 643dbb72e2cSVidya Sagar }; 644dbb72e2cSVidya Sagar }; 645dbb72e2cSVidya Sagar 646dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 647dbb72e2cSVidya Sagar clkreq { 648dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 649dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 650dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 6516b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 652dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 653dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654dbb72e2cSVidya Sagar }; 655dbb72e2cSVidya Sagar }; 656dbb72e2cSVidya Sagar }; 657dbb72e2cSVidya Sagar 658be9b887fSThierry Reding mc: memory-controller@2c00000 { 659be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 660000b99e5SAshish Mhetre reg = <0x02c00000 0x10000>, /* MC-SID */ 661000b99e5SAshish Mhetre <0x02c10000 0x10000>, /* MC Broadcast*/ 662000b99e5SAshish Mhetre <0x02c20000 0x10000>, /* MC0 */ 663000b99e5SAshish Mhetre <0x02c30000 0x10000>, /* MC1 */ 664000b99e5SAshish Mhetre <0x02c40000 0x10000>, /* MC2 */ 665000b99e5SAshish Mhetre <0x02c50000 0x10000>, /* MC3 */ 666000b99e5SAshish Mhetre <0x02b80000 0x10000>, /* MC4 */ 667000b99e5SAshish Mhetre <0x02b90000 0x10000>, /* MC5 */ 668000b99e5SAshish Mhetre <0x02ba0000 0x10000>, /* MC6 */ 669000b99e5SAshish Mhetre <0x02bb0000 0x10000>, /* MC7 */ 670000b99e5SAshish Mhetre <0x01700000 0x10000>, /* MC8 */ 671000b99e5SAshish Mhetre <0x01710000 0x10000>, /* MC9 */ 672000b99e5SAshish Mhetre <0x01720000 0x10000>, /* MC10 */ 673000b99e5SAshish Mhetre <0x01730000 0x10000>, /* MC11 */ 674000b99e5SAshish Mhetre <0x01740000 0x10000>, /* MC12 */ 675000b99e5SAshish Mhetre <0x01750000 0x10000>, /* MC13 */ 676000b99e5SAshish Mhetre <0x01760000 0x10000>, /* MC14 */ 677000b99e5SAshish Mhetre <0x01770000 0x10000>; /* MC15 */ 678000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 679000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 680000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6818613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 682d5237c7cSThierry Reding #interconnect-cells = <1>; 683be9b887fSThierry Reding status = "disabled"; 684be9b887fSThierry Reding 685be9b887fSThierry Reding #address-cells = <2>; 686be9b887fSThierry Reding #size-cells = <2>; 687be9b887fSThierry Reding 688be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 689be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 690be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 691be9b887fSThierry Reding 692be9b887fSThierry Reding /* 693be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 694be9b887fSThierry Reding * controller selects the XBAR format used when memory 695be9b887fSThierry Reding * is accessed. This is used to transparently access 696be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 697be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 698be9b887fSThierry Reding * 699be9b887fSThierry Reding * As a consequence, the operating system must ensure 700be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 701be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 702be9b887fSThierry Reding * devices require access to the XBAR switch, their 703be9b887fSThierry Reding * drivers must set this bit explicitly. 704be9b887fSThierry Reding * 705be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 706be9b887fSThierry Reding */ 707be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 708be9b887fSThierry Reding 709be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 710be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 711be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 712be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 713cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 714be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 715be9b887fSThierry Reding clock-names = "emc"; 716be9b887fSThierry Reding 717d5237c7cSThierry Reding #interconnect-cells = <0>; 718d5237c7cSThierry Reding 719be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 720be9b887fSThierry Reding }; 721be9b887fSThierry Reding }; 722be9b887fSThierry Reding 7235aa9083eSThierry Reding timer@3010000 { 7245aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 7255aa9083eSThierry Reding reg = <0x03010000 0x000e0000>; 7265aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7275aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7285aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7295aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7305aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7345aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7355aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7365aa9083eSThierry Reding status = "okay"; 7375aa9083eSThierry Reding }; 7385aa9083eSThierry Reding 7395425fb15SMikko Perttunen uarta: serial@3100000 { 7405425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7415425fb15SMikko Perttunen reg = <0x03100000 0x40>; 7425425fb15SMikko Perttunen reg-shift = <2>; 7435425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7445425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7455425fb15SMikko Perttunen clock-names = "serial"; 7465425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7475425fb15SMikko Perttunen reset-names = "serial"; 7485425fb15SMikko Perttunen status = "disabled"; 7495425fb15SMikko Perttunen }; 7505425fb15SMikko Perttunen 7515425fb15SMikko Perttunen uartb: serial@3110000 { 7525425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7535425fb15SMikko Perttunen reg = <0x03110000 0x40>; 7545425fb15SMikko Perttunen reg-shift = <2>; 7555425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7565425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7575425fb15SMikko Perttunen clock-names = "serial"; 7585425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7595425fb15SMikko Perttunen reset-names = "serial"; 7605425fb15SMikko Perttunen status = "disabled"; 7615425fb15SMikko Perttunen }; 7625425fb15SMikko Perttunen 7635425fb15SMikko Perttunen uartd: serial@3130000 { 7645425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7655425fb15SMikko Perttunen reg = <0x03130000 0x40>; 7665425fb15SMikko Perttunen reg-shift = <2>; 7675425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7695425fb15SMikko Perttunen clock-names = "serial"; 7705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7715425fb15SMikko Perttunen reset-names = "serial"; 7725425fb15SMikko Perttunen status = "disabled"; 7735425fb15SMikko Perttunen }; 7745425fb15SMikko Perttunen 7755425fb15SMikko Perttunen uarte: serial@3140000 { 7765425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7775425fb15SMikko Perttunen reg = <0x03140000 0x40>; 7785425fb15SMikko Perttunen reg-shift = <2>; 7795425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7805425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7815425fb15SMikko Perttunen clock-names = "serial"; 7825425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7835425fb15SMikko Perttunen reset-names = "serial"; 7845425fb15SMikko Perttunen status = "disabled"; 7855425fb15SMikko Perttunen }; 7865425fb15SMikko Perttunen 7875425fb15SMikko Perttunen uartf: serial@3150000 { 7885425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7895425fb15SMikko Perttunen reg = <0x03150000 0x40>; 7905425fb15SMikko Perttunen reg-shift = <2>; 7915425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7935425fb15SMikko Perttunen clock-names = "serial"; 7945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7955425fb15SMikko Perttunen reset-names = "serial"; 7965425fb15SMikko Perttunen status = "disabled"; 7975425fb15SMikko Perttunen }; 7985425fb15SMikko Perttunen 7995425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 800d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8015425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 8025425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8035425fb15SMikko Perttunen #address-cells = <1>; 8045425fb15SMikko Perttunen #size-cells = <0>; 8055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8065425fb15SMikko Perttunen clock-names = "div-clk"; 8075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8085425fb15SMikko Perttunen reset-names = "i2c"; 8098e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8108e442805SAkhil R dma-coherent; 8118e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8128e442805SAkhil R dma-names = "rx", "tx"; 8135425fb15SMikko Perttunen status = "disabled"; 8145425fb15SMikko Perttunen }; 8155425fb15SMikko Perttunen 8165425fb15SMikko Perttunen uarth: serial@3170000 { 8175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8185425fb15SMikko Perttunen reg = <0x03170000 0x40>; 8195425fb15SMikko Perttunen reg-shift = <2>; 8205425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8225425fb15SMikko Perttunen clock-names = "serial"; 8235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8245425fb15SMikko Perttunen reset-names = "serial"; 8255425fb15SMikko Perttunen status = "disabled"; 8265425fb15SMikko Perttunen }; 8275425fb15SMikko Perttunen 8285425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 829d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8305425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 8315425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8325425fb15SMikko Perttunen #address-cells = <1>; 8335425fb15SMikko Perttunen #size-cells = <0>; 8345425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8355425fb15SMikko Perttunen clock-names = "div-clk"; 8365425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8375425fb15SMikko Perttunen reset-names = "i2c"; 8388e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8398e442805SAkhil R dma-coherent; 8408e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8418e442805SAkhil R dma-names = "rx", "tx"; 8425425fb15SMikko Perttunen status = "disabled"; 8435425fb15SMikko Perttunen }; 8445425fb15SMikko Perttunen 8455425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8465425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 847d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8485425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 8495425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8505425fb15SMikko Perttunen #address-cells = <1>; 8515425fb15SMikko Perttunen #size-cells = <0>; 8525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8535425fb15SMikko Perttunen clock-names = "div-clk"; 8545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8555425fb15SMikko Perttunen reset-names = "i2c"; 856a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 857a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 858a4131561SThierry Reding pinctrl-names = "default", "idle"; 8598e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8608e442805SAkhil R dma-coherent; 8618e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8628e442805SAkhil R dma-names = "rx", "tx"; 8635425fb15SMikko Perttunen status = "disabled"; 8645425fb15SMikko Perttunen }; 8655425fb15SMikko Perttunen 8665425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8675425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 868d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8695425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 8705425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8715425fb15SMikko Perttunen #address-cells = <1>; 8725425fb15SMikko Perttunen #size-cells = <0>; 8735425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8745425fb15SMikko Perttunen clock-names = "div-clk"; 8755425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8765425fb15SMikko Perttunen reset-names = "i2c"; 877a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 878a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 879a4131561SThierry Reding pinctrl-names = "default", "idle"; 8808e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 8818e442805SAkhil R dma-coherent; 8828e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8838e442805SAkhil R dma-names = "rx", "tx"; 8845425fb15SMikko Perttunen status = "disabled"; 8855425fb15SMikko Perttunen }; 8865425fb15SMikko Perttunen 887a4131561SThierry Reding /* shares pads with dpaux2 */ 888a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 889d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8905425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 8915425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8925425fb15SMikko Perttunen #address-cells = <1>; 8935425fb15SMikko Perttunen #size-cells = <0>; 8945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8955425fb15SMikko Perttunen clock-names = "div-clk"; 8965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8975425fb15SMikko Perttunen reset-names = "i2c"; 898a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 899a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 900a4131561SThierry Reding pinctrl-names = "default", "idle"; 9018e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9028e442805SAkhil R dma-coherent; 9038e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 9048e442805SAkhil R dma-names = "rx", "tx"; 9055425fb15SMikko Perttunen status = "disabled"; 9065425fb15SMikko Perttunen }; 9075425fb15SMikko Perttunen 908a4131561SThierry Reding /* shares pads with dpaux3 */ 909a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 910d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9115425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 9125425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9135425fb15SMikko Perttunen #address-cells = <1>; 9145425fb15SMikko Perttunen #size-cells = <0>; 9155425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9165425fb15SMikko Perttunen clock-names = "div-clk"; 9175425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9185425fb15SMikko Perttunen reset-names = "i2c"; 919a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 920a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 921a4131561SThierry Reding pinctrl-names = "default", "idle"; 9228e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 9238e442805SAkhil R dma-coherent; 9248e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9258e442805SAkhil R dma-names = "rx", "tx"; 9265425fb15SMikko Perttunen status = "disabled"; 9275425fb15SMikko Perttunen }; 9285425fb15SMikko Perttunen 92996ded827SSowjanya Komatineni spi@3270000 { 93096ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 93196ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 93296ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 93396ded827SSowjanya Komatineni #address-cells = <1>; 93496ded827SSowjanya Komatineni #size-cells = <0>; 93596ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 93696ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 93796ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 93896ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 93996ded827SSowjanya Komatineni reset-names = "qspi"; 94096ded827SSowjanya Komatineni status = "disabled"; 94196ded827SSowjanya Komatineni }; 94296ded827SSowjanya Komatineni 94396ded827SSowjanya Komatineni spi@3300000 { 94496ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 94596ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 94696ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 94796ded827SSowjanya Komatineni #address-cells = <1>; 94896ded827SSowjanya Komatineni #size-cells = <0>; 94996ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 95096ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 95196ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 95296ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 95396ded827SSowjanya Komatineni reset-names = "qspi"; 95496ded827SSowjanya Komatineni status = "disabled"; 95596ded827SSowjanya Komatineni }; 95696ded827SSowjanya Komatineni 9576a574ec7SThierry Reding pwm1: pwm@3280000 { 9586a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9596a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9606a574ec7SThierry Reding reg = <0x3280000 0x10000>; 9616a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9626a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9636a574ec7SThierry Reding reset-names = "pwm"; 9646a574ec7SThierry Reding status = "disabled"; 9656a574ec7SThierry Reding #pwm-cells = <2>; 9666a574ec7SThierry Reding }; 9676a574ec7SThierry Reding 9686a574ec7SThierry Reding pwm2: pwm@3290000 { 9696a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9706a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9716a574ec7SThierry Reding reg = <0x3290000 0x10000>; 9726a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9736a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9746a574ec7SThierry Reding reset-names = "pwm"; 9756a574ec7SThierry Reding status = "disabled"; 9766a574ec7SThierry Reding #pwm-cells = <2>; 9776a574ec7SThierry Reding }; 9786a574ec7SThierry Reding 9796a574ec7SThierry Reding pwm3: pwm@32a0000 { 9806a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9816a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9826a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 9836a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9846a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9856a574ec7SThierry Reding reset-names = "pwm"; 9866a574ec7SThierry Reding status = "disabled"; 9876a574ec7SThierry Reding #pwm-cells = <2>; 9886a574ec7SThierry Reding }; 9896a574ec7SThierry Reding 9906a574ec7SThierry Reding pwm5: pwm@32c0000 { 9916a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9926a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9936a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 9946a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9956a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9966a574ec7SThierry Reding reset-names = "pwm"; 9976a574ec7SThierry Reding status = "disabled"; 9986a574ec7SThierry Reding #pwm-cells = <2>; 9996a574ec7SThierry Reding }; 10006a574ec7SThierry Reding 10016a574ec7SThierry Reding pwm6: pwm@32d0000 { 10026a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10036a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10046a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 10056a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 10066a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 10076a574ec7SThierry Reding reset-names = "pwm"; 10086a574ec7SThierry Reding status = "disabled"; 10096a574ec7SThierry Reding #pwm-cells = <2>; 10106a574ec7SThierry Reding }; 10116a574ec7SThierry Reding 10126a574ec7SThierry Reding pwm7: pwm@32e0000 { 10136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10156a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 10166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 10176a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 10186a574ec7SThierry Reding reset-names = "pwm"; 10196a574ec7SThierry Reding status = "disabled"; 10206a574ec7SThierry Reding #pwm-cells = <2>; 10216a574ec7SThierry Reding }; 10226a574ec7SThierry Reding 10236a574ec7SThierry Reding pwm8: pwm@32f0000 { 10246a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 10256a574ec7SThierry Reding "nvidia,tegra186-pwm"; 10266a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 10276a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10286a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10296a574ec7SThierry Reding reset-names = "pwm"; 10306a574ec7SThierry Reding status = "disabled"; 10316a574ec7SThierry Reding #pwm-cells = <2>; 10326a574ec7SThierry Reding }; 10336a574ec7SThierry Reding 103467bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10352c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10365425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 10375425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1038c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1039c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1040c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10417ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10427ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10437ac853baSAniruddha Rao assigned-clock-parents = 10447ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10457ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10465425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10475425fb15SMikko Perttunen reset-names = "sdhci"; 1048d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1049d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1050d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1051c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1052ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1053ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1054ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10554e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10564e0f1229SSowjanya Komatineni <0x07>; 10574e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10584e0f1229SSowjanya Komatineni <0x07>; 10594e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10614e0f1229SSowjanya Komatineni <0x07>; 10624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10644e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10654e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1066ff21087eSPrathamesh Shete sd-uhs-sdr25; 1067ff21087eSPrathamesh Shete sd-uhs-sdr50; 1068ff21087eSPrathamesh Shete sd-uhs-ddr50; 1069ff21087eSPrathamesh Shete sd-uhs-sdr104; 10705425fb15SMikko Perttunen status = "disabled"; 10715425fb15SMikko Perttunen }; 10725425fb15SMikko Perttunen 107367bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10742c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10755425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 10765425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1077c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1078c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1079c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10807ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10817ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10827ac853baSAniruddha Rao assigned-clock-parents = 10837ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10847ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10865425fb15SMikko Perttunen reset-names = "sdhci"; 1087d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1088d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1089d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1090c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1091ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1092ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1093ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10944e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10974e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10984e0f1229SSowjanya Komatineni <0x07>; 10994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 11004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11014e0f1229SSowjanya Komatineni <0x07>; 11024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 11034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 11044e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 11054e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1106ff21087eSPrathamesh Shete sd-uhs-sdr25; 1107ff21087eSPrathamesh Shete sd-uhs-sdr50; 1108ff21087eSPrathamesh Shete sd-uhs-ddr50; 1109ff21087eSPrathamesh Shete sd-uhs-sdr104; 11105425fb15SMikko Perttunen status = "disabled"; 11115425fb15SMikko Perttunen }; 11125425fb15SMikko Perttunen 111367bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11142c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 11155425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 11165425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1117c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1118c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1119c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1120351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1121351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1122351648d0SSowjanya Komatineni assigned-clock-parents = 1123351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11255425fb15SMikko Perttunen reset-names = "sdhci"; 1126d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1127d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1128d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1129c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11304e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11344e0f1229SSowjanya Komatineni <0x0a>; 11354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11374e0f1229SSowjanya Komatineni <0x0a>; 11384e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11394e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11404e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1141c2fee443SPrathamesh Shete cap-mmc-highspeed; 1142c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1143c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1144c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1145c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1146dfd3cb6fSSowjanya Komatineni supports-cqe; 11475425fb15SMikko Perttunen status = "disabled"; 11485425fb15SMikko Perttunen }; 11495425fb15SMikko Perttunen 11504878cc0cSSameer Pujar hda@3510000 { 11514878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 11524878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 11534878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11544878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 115548f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 115648f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 115748f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11584878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1159146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1160146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11614878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1162d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1163d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1164d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1165c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11664878cc0cSSameer Pujar status = "disabled"; 11674878cc0cSSameer Pujar }; 11684878cc0cSSameer Pujar 1169fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1170fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 1171fab7a039SJC Kuo reg = <0x03520000 0x1000>, 1172fab7a039SJC Kuo <0x03540000 0x1000>; 1173fab7a039SJC Kuo reg-names = "padctl", "ao"; 11746450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1175fab7a039SJC Kuo 1176fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1177fab7a039SJC Kuo reset-names = "padctl"; 1178fab7a039SJC Kuo 1179fab7a039SJC Kuo status = "disabled"; 1180fab7a039SJC Kuo 1181fab7a039SJC Kuo pads { 1182fab7a039SJC Kuo usb2 { 1183fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1184fab7a039SJC Kuo clock-names = "trk"; 1185fab7a039SJC Kuo 1186fab7a039SJC Kuo lanes { 1187fab7a039SJC Kuo usb2-0 { 1188fab7a039SJC Kuo nvidia,function = "xusb"; 1189fab7a039SJC Kuo status = "disabled"; 1190fab7a039SJC Kuo #phy-cells = <0>; 1191fab7a039SJC Kuo }; 1192fab7a039SJC Kuo 1193fab7a039SJC Kuo usb2-1 { 1194fab7a039SJC Kuo nvidia,function = "xusb"; 1195fab7a039SJC Kuo status = "disabled"; 1196fab7a039SJC Kuo #phy-cells = <0>; 1197fab7a039SJC Kuo }; 1198fab7a039SJC Kuo 1199fab7a039SJC Kuo usb2-2 { 1200fab7a039SJC Kuo nvidia,function = "xusb"; 1201fab7a039SJC Kuo status = "disabled"; 1202fab7a039SJC Kuo #phy-cells = <0>; 1203fab7a039SJC Kuo }; 1204fab7a039SJC Kuo 1205fab7a039SJC Kuo usb2-3 { 1206fab7a039SJC Kuo nvidia,function = "xusb"; 1207fab7a039SJC Kuo status = "disabled"; 1208fab7a039SJC Kuo #phy-cells = <0>; 1209fab7a039SJC Kuo }; 1210fab7a039SJC Kuo }; 1211fab7a039SJC Kuo }; 1212fab7a039SJC Kuo 1213fab7a039SJC Kuo usb3 { 1214fab7a039SJC Kuo lanes { 1215fab7a039SJC Kuo usb3-0 { 1216fab7a039SJC Kuo nvidia,function = "xusb"; 1217fab7a039SJC Kuo status = "disabled"; 1218fab7a039SJC Kuo #phy-cells = <0>; 1219fab7a039SJC Kuo }; 1220fab7a039SJC Kuo 1221fab7a039SJC Kuo usb3-1 { 1222fab7a039SJC Kuo nvidia,function = "xusb"; 1223fab7a039SJC Kuo status = "disabled"; 1224fab7a039SJC Kuo #phy-cells = <0>; 1225fab7a039SJC Kuo }; 1226fab7a039SJC Kuo 1227fab7a039SJC Kuo usb3-2 { 1228fab7a039SJC Kuo nvidia,function = "xusb"; 1229fab7a039SJC Kuo status = "disabled"; 1230fab7a039SJC Kuo #phy-cells = <0>; 1231fab7a039SJC Kuo }; 1232fab7a039SJC Kuo 1233fab7a039SJC Kuo usb3-3 { 1234fab7a039SJC Kuo nvidia,function = "xusb"; 1235fab7a039SJC Kuo status = "disabled"; 1236fab7a039SJC Kuo #phy-cells = <0>; 1237fab7a039SJC Kuo }; 1238fab7a039SJC Kuo }; 1239fab7a039SJC Kuo }; 1240fab7a039SJC Kuo }; 1241fab7a039SJC Kuo 1242fab7a039SJC Kuo ports { 1243fab7a039SJC Kuo usb2-0 { 1244fab7a039SJC Kuo status = "disabled"; 1245fab7a039SJC Kuo }; 1246fab7a039SJC Kuo 1247fab7a039SJC Kuo usb2-1 { 1248fab7a039SJC Kuo status = "disabled"; 1249fab7a039SJC Kuo }; 1250fab7a039SJC Kuo 1251fab7a039SJC Kuo usb2-2 { 1252fab7a039SJC Kuo status = "disabled"; 1253fab7a039SJC Kuo }; 1254fab7a039SJC Kuo 1255fab7a039SJC Kuo usb2-3 { 1256fab7a039SJC Kuo status = "disabled"; 1257fab7a039SJC Kuo }; 1258fab7a039SJC Kuo 1259fab7a039SJC Kuo usb3-0 { 1260fab7a039SJC Kuo status = "disabled"; 1261fab7a039SJC Kuo }; 1262fab7a039SJC Kuo 1263fab7a039SJC Kuo usb3-1 { 1264fab7a039SJC Kuo status = "disabled"; 1265fab7a039SJC Kuo }; 1266fab7a039SJC Kuo 1267fab7a039SJC Kuo usb3-2 { 1268fab7a039SJC Kuo status = "disabled"; 1269fab7a039SJC Kuo }; 1270fab7a039SJC Kuo 1271fab7a039SJC Kuo usb3-3 { 1272fab7a039SJC Kuo status = "disabled"; 1273fab7a039SJC Kuo }; 1274fab7a039SJC Kuo }; 1275fab7a039SJC Kuo }; 1276fab7a039SJC Kuo 1277bc8788b2SNagarjuna Kristam usb@3550000 { 1278bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1279bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1280bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1281bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1282bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1283bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1284bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1285bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1286bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1287bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1288c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1289c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1290c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1291c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1292bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1293bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1294bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1295bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1296bc8788b2SNagarjuna Kristam status = "disabled"; 1297bc8788b2SNagarjuna Kristam }; 1298bc8788b2SNagarjuna Kristam 1299fab7a039SJC Kuo usb@3610000 { 1300fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1301fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1302fab7a039SJC Kuo <0x03600000 0x10000>; 1303fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1304fab7a039SJC Kuo 1305fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1306a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1307fab7a039SJC Kuo 1308fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1309fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1310fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1311fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1312fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1313fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1314fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1315fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1316fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1317fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1318fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1319fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1320fab7a039SJC Kuo "pll_e"; 1321c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1322c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1323c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1324c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1325fab7a039SJC Kuo 1326fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1327fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1328fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1329fab7a039SJC Kuo 1330fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1331fab7a039SJC Kuo status = "disabled"; 1332fab7a039SJC Kuo }; 1333fab7a039SJC Kuo 133409903c5eSJC Kuo fuse@3820000 { 133509903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 133609903c5eSJC Kuo reg = <0x03820000 0x10000>; 133709903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 133809903c5eSJC Kuo clock-names = "fuse"; 133909903c5eSJC Kuo }; 134009903c5eSJC Kuo 13415425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13425425fb15SMikko Perttunen compatible = "arm,gic-400"; 13435425fb15SMikko Perttunen #interrupt-cells = <3>; 13445425fb15SMikko Perttunen interrupt-controller; 13455425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 13465425fb15SMikko Perttunen <0x03882000 0x2000>, 13475425fb15SMikko Perttunen <0x03884000 0x2000>, 13485425fb15SMikko Perttunen <0x03886000 0x2000>; 13495425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13505425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13515425fb15SMikko Perttunen interrupt-parent = <&gic>; 13525425fb15SMikko Perttunen }; 13535425fb15SMikko Perttunen 1354badb80beSThierry Reding cec@3960000 { 1355badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1356badb80beSThierry Reding reg = <0x03960000 0x10000>; 1357badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1358badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1359badb80beSThierry Reding clock-names = "cec"; 1360badb80beSThierry Reding status = "disabled"; 1361badb80beSThierry Reding }; 1362badb80beSThierry Reding 13638fbd2d11SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 13648fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 13658fbd2d11SDipen Patel reg = <0x3aa0000 0x10000>; 13668fbd2d11SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 13678fbd2d11SDipen Patel nvidia,int-threshold = <1>; 13688fbd2d11SDipen Patel nvidia,slices = <11>; 13698fbd2d11SDipen Patel #timestamp-cells = <1>; 13708fbd2d11SDipen Patel status = "okay"; 13718fbd2d11SDipen Patel }; 13728fbd2d11SDipen Patel 13735425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1374cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13755425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1376a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1377a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1378a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1379a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1380a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1381a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1382a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1383a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1384a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1385a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1386a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1387a38570c2SMikko Perttunen "shared7"; 1388a38570c2SMikko Perttunen #mbox-cells = <2>; 1389a38570c2SMikko Perttunen }; 1390a38570c2SMikko Perttunen 13912602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13922602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13932602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 13942602c32fSVidya Sagar reg-names = "ctl"; 13952602c32fSVidya Sagar 13962602c32fSVidya Sagar #phy-cells = <0>; 13972602c32fSVidya Sagar }; 13982602c32fSVidya Sagar 13992602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 14002602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14012602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 14022602c32fSVidya Sagar reg-names = "ctl"; 14032602c32fSVidya Sagar 14042602c32fSVidya Sagar #phy-cells = <0>; 14052602c32fSVidya Sagar }; 14062602c32fSVidya Sagar 14072602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 14082602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14092602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 14102602c32fSVidya Sagar reg-names = "ctl"; 14112602c32fSVidya Sagar 14122602c32fSVidya Sagar #phy-cells = <0>; 14132602c32fSVidya Sagar }; 14142602c32fSVidya Sagar 14152602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14162602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14172602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 14182602c32fSVidya Sagar reg-names = "ctl"; 14192602c32fSVidya Sagar 14202602c32fSVidya Sagar #phy-cells = <0>; 14212602c32fSVidya Sagar }; 14222602c32fSVidya Sagar 14232602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14242602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14252602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 14262602c32fSVidya Sagar reg-names = "ctl"; 14272602c32fSVidya Sagar 14282602c32fSVidya Sagar #phy-cells = <0>; 14292602c32fSVidya Sagar }; 14302602c32fSVidya Sagar 14312602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14322602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14332602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 14342602c32fSVidya Sagar reg-names = "ctl"; 14352602c32fSVidya Sagar 14362602c32fSVidya Sagar #phy-cells = <0>; 14372602c32fSVidya Sagar }; 14382602c32fSVidya Sagar 14392602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14402602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14412602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 14422602c32fSVidya Sagar reg-names = "ctl"; 14432602c32fSVidya Sagar 14442602c32fSVidya Sagar #phy-cells = <0>; 14452602c32fSVidya Sagar }; 14462602c32fSVidya Sagar 14472602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14482602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14492602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 14502602c32fSVidya Sagar reg-names = "ctl"; 14512602c32fSVidya Sagar 14522602c32fSVidya Sagar #phy-cells = <0>; 14532602c32fSVidya Sagar }; 14542602c32fSVidya Sagar 14552602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14562602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14572602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 14582602c32fSVidya Sagar reg-names = "ctl"; 14592602c32fSVidya Sagar 14602602c32fSVidya Sagar #phy-cells = <0>; 14612602c32fSVidya Sagar }; 14622602c32fSVidya Sagar 14632602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14642602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14652602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 14662602c32fSVidya Sagar reg-names = "ctl"; 14672602c32fSVidya Sagar 14682602c32fSVidya Sagar #phy-cells = <0>; 14692602c32fSVidya Sagar }; 14702602c32fSVidya Sagar 14712602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14722602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14732602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 14742602c32fSVidya Sagar reg-names = "ctl"; 14752602c32fSVidya Sagar 14762602c32fSVidya Sagar #phy-cells = <0>; 14772602c32fSVidya Sagar }; 14782602c32fSVidya Sagar 14792602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14802602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14812602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 14822602c32fSVidya Sagar reg-names = "ctl"; 14832602c32fSVidya Sagar 14842602c32fSVidya Sagar #phy-cells = <0>; 14852602c32fSVidya Sagar }; 14862602c32fSVidya Sagar 14872602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14892602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 14902602c32fSVidya Sagar reg-names = "ctl"; 14912602c32fSVidya Sagar 14922602c32fSVidya Sagar #phy-cells = <0>; 14932602c32fSVidya Sagar }; 14942602c32fSVidya Sagar 14952602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14972602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 14982602c32fSVidya Sagar reg-names = "ctl"; 14992602c32fSVidya Sagar 15002602c32fSVidya Sagar #phy-cells = <0>; 15012602c32fSVidya Sagar }; 15022602c32fSVidya Sagar 15032602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 15042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15052602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 15062602c32fSVidya Sagar reg-names = "ctl"; 15072602c32fSVidya Sagar 15082602c32fSVidya Sagar #phy-cells = <0>; 15092602c32fSVidya Sagar }; 15102602c32fSVidya Sagar 15112602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 15122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15132602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 15142602c32fSVidya Sagar reg-names = "ctl"; 15152602c32fSVidya Sagar 15162602c32fSVidya Sagar #phy-cells = <0>; 15172602c32fSVidya Sagar }; 15182602c32fSVidya Sagar 15192602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15212602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 15222602c32fSVidya Sagar reg-names = "ctl"; 15232602c32fSVidya Sagar 15242602c32fSVidya Sagar #phy-cells = <0>; 15252602c32fSVidya Sagar }; 15262602c32fSVidya Sagar 15272602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15292602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 15302602c32fSVidya Sagar reg-names = "ctl"; 15312602c32fSVidya Sagar 15322602c32fSVidya Sagar #phy-cells = <0>; 15332602c32fSVidya Sagar }; 15342602c32fSVidya Sagar 15352602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15372602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 15382602c32fSVidya Sagar reg-names = "ctl"; 15392602c32fSVidya Sagar 15402602c32fSVidya Sagar #phy-cells = <0>; 15412602c32fSVidya Sagar }; 15422602c32fSVidya Sagar 15432602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15452602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 15462602c32fSVidya Sagar reg-names = "ctl"; 15472602c32fSVidya Sagar 15482602c32fSVidya Sagar #phy-cells = <0>; 15492602c32fSVidya Sagar }; 15502602c32fSVidya Sagar 1551a47e173eSSumit Gupta sce-noc@b600000 { 1552a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 1553a47e173eSSumit Gupta reg = <0xb600000 0x1000>; 1554a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1555a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1556a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1557a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1558a47e173eSSumit Gupta status = "okay"; 1559a47e173eSSumit Gupta }; 1560a47e173eSSumit Gupta 1561a47e173eSSumit Gupta rce-noc@be00000 { 1562a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 1563a47e173eSSumit Gupta reg = <0xbe00000 0x1000>; 1564a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1565a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1566a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1567a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1568a47e173eSSumit Gupta status = "okay"; 1569a47e173eSSumit Gupta }; 1570a47e173eSSumit Gupta 1571a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1572cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15731741e187SDipen Patel reg = <0x0c150000 0x90000>; 1574a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1575a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1576a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1577a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1578a38570c2SMikko Perttunen /* 1579a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1580a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1581a38570c2SMikko Perttunen */ 1582a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15835425fb15SMikko Perttunen #mbox-cells = <2>; 15845425fb15SMikko Perttunen }; 15855425fb15SMikko Perttunen 15868fbd2d11SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 15878fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 15888fbd2d11SDipen Patel reg = <0xc1e0000 0x10000>; 15898fbd2d11SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 15908fbd2d11SDipen Patel nvidia,int-threshold = <1>; 15918fbd2d11SDipen Patel nvidia,slices = <3>; 15928fbd2d11SDipen Patel #timestamp-cells = <1>; 15938fbd2d11SDipen Patel status = "okay"; 15948fbd2d11SDipen Patel }; 15958fbd2d11SDipen Patel 15965425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1597d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15985425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 15995425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 16005425fb15SMikko Perttunen #address-cells = <1>; 16015425fb15SMikko Perttunen #size-cells = <0>; 16025425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 16035425fb15SMikko Perttunen clock-names = "div-clk"; 16045425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 16055425fb15SMikko Perttunen reset-names = "i2c"; 16068e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16078e442805SAkhil R dma-coherent; 16088e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 16098e442805SAkhil R dma-names = "rx", "tx"; 16105425fb15SMikko Perttunen status = "disabled"; 16115425fb15SMikko Perttunen }; 16125425fb15SMikko Perttunen 16135425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1614d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 16155425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 16165425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16175425fb15SMikko Perttunen #address-cells = <1>; 16185425fb15SMikko Perttunen #size-cells = <0>; 16195425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16205425fb15SMikko Perttunen clock-names = "div-clk"; 16215425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16225425fb15SMikko Perttunen reset-names = "i2c"; 16238e442805SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 16248e442805SAkhil R dma-coherent; 16258e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16268e442805SAkhil R dma-names = "rx", "tx"; 16275425fb15SMikko Perttunen status = "disabled"; 16285425fb15SMikko Perttunen }; 16295425fb15SMikko Perttunen 16305425fb15SMikko Perttunen uartc: serial@c280000 { 16315425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16325425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 16335425fb15SMikko Perttunen reg-shift = <2>; 16345425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16365425fb15SMikko Perttunen clock-names = "serial"; 16375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16385425fb15SMikko Perttunen reset-names = "serial"; 16395425fb15SMikko Perttunen status = "disabled"; 16405425fb15SMikko Perttunen }; 16415425fb15SMikko Perttunen 16425425fb15SMikko Perttunen uartg: serial@c290000 { 16435425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16445425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 16455425fb15SMikko Perttunen reg-shift = <2>; 16465425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16475425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16485425fb15SMikko Perttunen clock-names = "serial"; 16495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16505425fb15SMikko Perttunen reset-names = "serial"; 16515425fb15SMikko Perttunen status = "disabled"; 16525425fb15SMikko Perttunen }; 16535425fb15SMikko Perttunen 165437e5a31dSThierry Reding rtc: rtc@c2a0000 { 165537e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 165637e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 165737e5a31dSThierry Reding interrupt-parent = <&pmc>; 165837e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 165937e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 166037e5a31dSThierry Reding clock-names = "rtc"; 166137e5a31dSThierry Reding status = "disabled"; 166237e5a31dSThierry Reding }; 166337e5a31dSThierry Reding 16644d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16654d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16664d286331SThierry Reding reg-names = "security", "gpio"; 16674d286331SThierry Reding reg = <0xc2f0000 0x1000>, 16684d286331SThierry Reding <0xc2f1000 0x1000>; 16690a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16700a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16710a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16720a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16734d286331SThierry Reding gpio-controller; 16744d286331SThierry Reding #gpio-cells = <2>; 16754d286331SThierry Reding interrupt-controller; 16764d286331SThierry Reding #interrupt-cells = <2>; 16776f380a4eSThierry Reding gpio-range = <&pinmux_aon 0 0 30>; 16786f380a4eSThierry Reding }; 16796f380a4eSThierry Reding 16806f380a4eSThierry Reding pinmux_aon: pinmux@c300000 { 16816f380a4eSThierry Reding compatible = "nvidia,tegra194-pinmux-aon"; 16826f380a4eSThierry Reding reg = <0xc300000 0x4000>; 16836f380a4eSThierry Reding 16846f380a4eSThierry Reding status = "okay"; 16854d286331SThierry Reding }; 16864d286331SThierry Reding 16876a574ec7SThierry Reding pwm4: pwm@c340000 { 16886a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16896a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16906a574ec7SThierry Reding reg = <0xc340000 0x10000>; 16916a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16926a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16936a574ec7SThierry Reding reset-names = "pwm"; 16946a574ec7SThierry Reding status = "disabled"; 16956a574ec7SThierry Reding #pwm-cells = <2>; 16966a574ec7SThierry Reding }; 16976a574ec7SThierry Reding 169838ecf1e5SThierry Reding pmc: pmc@c360000 { 16995425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 17005425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 17015425fb15SMikko Perttunen <0x0c370000 0x10000>, 17025425fb15SMikko Perttunen <0x0c380000 0x10000>, 17035425fb15SMikko Perttunen <0x0c390000 0x10000>, 17045425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 17055425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 170638ecf1e5SThierry Reding 170738ecf1e5SThierry Reding #interrupt-cells = <2>; 170838ecf1e5SThierry Reding interrupt-controller; 1709ff21087eSPrathamesh Shete sdmmc1_3v3: sdmmc1-3v3 { 1710ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1711ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1712ff21087eSPrathamesh Shete }; 1713ff21087eSPrathamesh Shete 1714ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1715ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1716ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1717ff21087eSPrathamesh Shete }; 1718ff21087eSPrathamesh Shete sdmmc3_3v3: sdmmc3-3v3 { 1719ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1720ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1721ff21087eSPrathamesh Shete }; 1722ff21087eSPrathamesh Shete 1723ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1724ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1725ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1726ff21087eSPrathamesh Shete }; 1727ff21087eSPrathamesh Shete 17285425fb15SMikko Perttunen }; 17293db6d3baSThierry Reding 1730a47e173eSSumit Gupta aon-noc@c600000 { 1731a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 1732a47e173eSSumit Gupta reg = <0xc600000 0x1000>; 1733a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1734a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1735a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1736a47e173eSSumit Gupta status = "okay"; 1737a47e173eSSumit Gupta }; 1738a47e173eSSumit Gupta 1739a47e173eSSumit Gupta bpmp-noc@d600000 { 1740a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 1741a47e173eSSumit Gupta reg = <0xd600000 0x1000>; 1742a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1743a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1744a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1745a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1746a47e173eSSumit Gupta status = "okay"; 1747a47e173eSSumit Gupta }; 1748a47e173eSSumit Gupta 1749e762232fSJon Hunter iommu@10000000 { 1750e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1751e762232fSJon Hunter reg = <0x10000000 0x800000>; 1752e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1817e762232fSJon Hunter stream-match-mask = <0x7f80>; 1818e762232fSJon Hunter #global-interrupts = <1>; 1819e762232fSJon Hunter #iommu-cells = <1>; 1820e762232fSJon Hunter 1821e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1822ebea268eSJon Hunter status = "disabled"; 1823e762232fSJon Hunter }; 1824e762232fSJon Hunter 1825c7289b1cSThierry Reding smmu: iommu@12000000 { 1826c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1827c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1828c7289b1cSThierry Reding <0x11000000 0x800000>; 1829c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1895c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1896c7289b1cSThierry Reding #global-interrupts = <2>; 1897c7289b1cSThierry Reding #iommu-cells = <1>; 1898c7289b1cSThierry Reding 1899c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1900c7289b1cSThierry Reding status = "okay"; 1901c7289b1cSThierry Reding }; 1902c7289b1cSThierry Reding 19033db6d3baSThierry Reding host1x@13e00000 { 1904ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 19053db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 19063db6d3baSThierry Reding <0x13e10000 0x10000>; 19073db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 19083db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 19093db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1910052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 19113db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 19123db6d3baSThierry Reding clock-names = "host1x"; 19133db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 19143db6d3baSThierry Reding reset-names = "host1x"; 19153db6d3baSThierry Reding 19163db6d3baSThierry Reding #address-cells = <1>; 19173db6d3baSThierry Reding #size-cells = <1>; 19183db6d3baSThierry Reding 1919e25770feSMikko Perttunen ranges = <0x14800000 0x14800000 0x02800000>; 1920d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1921d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1922c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 19233db6d3baSThierry Reding 1924e30cf101SMikko Perttunen /* Context isolation domains */ 1925b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1926b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1927b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1928b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1929b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1930b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1931b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1932b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1933e30cf101SMikko Perttunen 193478a05873SMikko Perttunen nvdec@15140000 { 193578a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 193678a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 193778a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 193878a05873SMikko Perttunen clock-names = "nvdec"; 193978a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 194078a05873SMikko Perttunen reset-names = "nvdec"; 194178a05873SMikko Perttunen 194278a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 194378a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 194478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 194578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 194678a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 194778a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 194878a05873SMikko Perttunen dma-coherent; 194978a05873SMikko Perttunen 195078a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 195178a05873SMikko Perttunen }; 195278a05873SMikko Perttunen 19533db6d3baSThierry Reding display-hub@15200000 { 1954aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1955611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 19563db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19573db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19583db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19593db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19603db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19613db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19623db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19633db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19643db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19653db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19663db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19673db6d3baSThierry Reding clock-names = "disp", "hub"; 19683db6d3baSThierry Reding status = "disabled"; 19693db6d3baSThierry Reding 19703db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19713db6d3baSThierry Reding 19723db6d3baSThierry Reding #address-cells = <1>; 19733db6d3baSThierry Reding #size-cells = <1>; 19743db6d3baSThierry Reding 19753db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 19763db6d3baSThierry Reding 19773db6d3baSThierry Reding display@15200000 { 19783db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19793db6d3baSThierry Reding reg = <0x15200000 0x10000>; 19803db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19813db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19823db6d3baSThierry Reding clock-names = "dc"; 19833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19843db6d3baSThierry Reding reset-names = "dc"; 19853db6d3baSThierry Reding 19863db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1987d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1988d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1989d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19903db6d3baSThierry Reding 19913db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19923db6d3baSThierry Reding nvidia,head = <0>; 19933db6d3baSThierry Reding }; 19943db6d3baSThierry Reding 19953db6d3baSThierry Reding display@15210000 { 19963db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19973db6d3baSThierry Reding reg = <0x15210000 0x10000>; 19983db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19993db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 20003db6d3baSThierry Reding clock-names = "dc"; 20013db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 20023db6d3baSThierry Reding reset-names = "dc"; 20033db6d3baSThierry Reding 20043db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2005d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2006d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2007d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20083db6d3baSThierry Reding 20093db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20103db6d3baSThierry Reding nvidia,head = <1>; 20113db6d3baSThierry Reding }; 20123db6d3baSThierry Reding 20133db6d3baSThierry Reding display@15220000 { 20143db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20153db6d3baSThierry Reding reg = <0x15220000 0x10000>; 20163db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 20173db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 20183db6d3baSThierry Reding clock-names = "dc"; 20193db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 20203db6d3baSThierry Reding reset-names = "dc"; 20213db6d3baSThierry Reding 20223db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2023d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2024d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2025d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20263db6d3baSThierry Reding 20273db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20283db6d3baSThierry Reding nvidia,head = <2>; 20293db6d3baSThierry Reding }; 20303db6d3baSThierry Reding 20313db6d3baSThierry Reding display@15230000 { 20323db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20333db6d3baSThierry Reding reg = <0x15230000 0x10000>; 20343db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20353db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20363db6d3baSThierry Reding clock-names = "dc"; 20373db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20383db6d3baSThierry Reding reset-names = "dc"; 20393db6d3baSThierry Reding 20403db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2041d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2042d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2043d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20443db6d3baSThierry Reding 20453db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20463db6d3baSThierry Reding nvidia,head = <3>; 20473db6d3baSThierry Reding }; 20483db6d3baSThierry Reding }; 20493db6d3baSThierry Reding 20508d424ec2SThierry Reding vic@15340000 { 20518d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 20528d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 20538d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20548d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20558d424ec2SThierry Reding clock-names = "vic"; 20568d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20578d424ec2SThierry Reding reset-names = "vic"; 20588d424ec2SThierry Reding 20598d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2060d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2061d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2062d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2063c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2064a52280c8SJon Hunter dma-coherent; 20658d424ec2SThierry Reding }; 20668d424ec2SThierry Reding 2067f7eb2785SJon Hunter nvjpg@15380000 { 2068f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 2069f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 2070f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2071f7eb2785SJon Hunter clock-names = "nvjpg"; 2072f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2073f7eb2785SJon Hunter reset-names = "nvjpg"; 2074f7eb2785SJon Hunter 2075f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2076f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2077f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2078f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2079f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2080f7eb2785SJon Hunter dma-coherent; 2081f7eb2785SJon Hunter }; 2082f7eb2785SJon Hunter 208378a05873SMikko Perttunen nvdec@15480000 { 208478a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 208578a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 208678a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 208778a05873SMikko Perttunen clock-names = "nvdec"; 208878a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 208978a05873SMikko Perttunen reset-names = "nvdec"; 209078a05873SMikko Perttunen 209178a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 209278a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 209378a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 209478a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 209578a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 209678a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 209778a05873SMikko Perttunen dma-coherent; 209878a05873SMikko Perttunen 209978a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 210078a05873SMikko Perttunen }; 210178a05873SMikko Perttunen 2102f7eb2785SJon Hunter nvenc@154c0000 { 2103f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2104f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 2105f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2106f7eb2785SJon Hunter clock-names = "nvenc"; 2107f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2108f7eb2785SJon Hunter reset-names = "nvenc"; 2109f7eb2785SJon Hunter 2110f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2111f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2112f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2113f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2114f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2115f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2116f7eb2785SJon Hunter dma-coherent; 2117f7eb2785SJon Hunter 2118f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2119f7eb2785SJon Hunter }; 2120f7eb2785SJon Hunter 21213db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21223db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21233db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 21243db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21253db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21263db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21273db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21283db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21293db6d3baSThierry Reding reset-names = "dpaux"; 21303db6d3baSThierry Reding status = "disabled"; 21313db6d3baSThierry Reding 21323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21333db6d3baSThierry Reding 21343db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21353db6d3baSThierry Reding groups = "dpaux-io"; 21363db6d3baSThierry Reding function = "aux"; 21373db6d3baSThierry Reding }; 21383db6d3baSThierry Reding 21393db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21403db6d3baSThierry Reding groups = "dpaux-io"; 21413db6d3baSThierry Reding function = "i2c"; 21423db6d3baSThierry Reding }; 21433db6d3baSThierry Reding 21443db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21453db6d3baSThierry Reding groups = "dpaux-io"; 21463db6d3baSThierry Reding function = "off"; 21473db6d3baSThierry Reding }; 21483db6d3baSThierry Reding 21493db6d3baSThierry Reding i2c-bus { 21503db6d3baSThierry Reding #address-cells = <1>; 21513db6d3baSThierry Reding #size-cells = <0>; 21523db6d3baSThierry Reding }; 21533db6d3baSThierry Reding }; 21543db6d3baSThierry Reding 21553db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21563db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21573db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 21583db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21593db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21603db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21613db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21623db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21633db6d3baSThierry Reding reset-names = "dpaux"; 21643db6d3baSThierry Reding status = "disabled"; 21653db6d3baSThierry Reding 21663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21673db6d3baSThierry Reding 21683db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21693db6d3baSThierry Reding groups = "dpaux-io"; 21703db6d3baSThierry Reding function = "aux"; 21713db6d3baSThierry Reding }; 21723db6d3baSThierry Reding 21733db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21743db6d3baSThierry Reding groups = "dpaux-io"; 21753db6d3baSThierry Reding function = "i2c"; 21763db6d3baSThierry Reding }; 21773db6d3baSThierry Reding 21783db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21793db6d3baSThierry Reding groups = "dpaux-io"; 21803db6d3baSThierry Reding function = "off"; 21813db6d3baSThierry Reding }; 21823db6d3baSThierry Reding 21833db6d3baSThierry Reding i2c-bus { 21843db6d3baSThierry Reding #address-cells = <1>; 21853db6d3baSThierry Reding #size-cells = <0>; 21863db6d3baSThierry Reding }; 21873db6d3baSThierry Reding }; 21883db6d3baSThierry Reding 21893db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21903db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21913db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 21923db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21933db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21953db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21963db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21973db6d3baSThierry Reding reset-names = "dpaux"; 21983db6d3baSThierry Reding status = "disabled"; 21993db6d3baSThierry Reding 22003db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22013db6d3baSThierry Reding 22023db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 22033db6d3baSThierry Reding groups = "dpaux-io"; 22043db6d3baSThierry Reding function = "aux"; 22053db6d3baSThierry Reding }; 22063db6d3baSThierry Reding 22073db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 22083db6d3baSThierry Reding groups = "dpaux-io"; 22093db6d3baSThierry Reding function = "i2c"; 22103db6d3baSThierry Reding }; 22113db6d3baSThierry Reding 22123db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 22133db6d3baSThierry Reding groups = "dpaux-io"; 22143db6d3baSThierry Reding function = "off"; 22153db6d3baSThierry Reding }; 22163db6d3baSThierry Reding 22173db6d3baSThierry Reding i2c-bus { 22183db6d3baSThierry Reding #address-cells = <1>; 22193db6d3baSThierry Reding #size-cells = <0>; 22203db6d3baSThierry Reding }; 22213db6d3baSThierry Reding }; 22223db6d3baSThierry Reding 22233db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22243db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 22253db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 22263db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22273db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22293db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22303db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22313db6d3baSThierry Reding reset-names = "dpaux"; 22323db6d3baSThierry Reding status = "disabled"; 22333db6d3baSThierry Reding 22343db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22353db6d3baSThierry Reding 22363db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22373db6d3baSThierry Reding groups = "dpaux-io"; 22383db6d3baSThierry Reding function = "aux"; 22393db6d3baSThierry Reding }; 22403db6d3baSThierry Reding 22413db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22423db6d3baSThierry Reding groups = "dpaux-io"; 22433db6d3baSThierry Reding function = "i2c"; 22443db6d3baSThierry Reding }; 22453db6d3baSThierry Reding 22463db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22473db6d3baSThierry Reding groups = "dpaux-io"; 22483db6d3baSThierry Reding function = "off"; 22493db6d3baSThierry Reding }; 22503db6d3baSThierry Reding 22513db6d3baSThierry Reding i2c-bus { 22523db6d3baSThierry Reding #address-cells = <1>; 22533db6d3baSThierry Reding #size-cells = <0>; 22543db6d3baSThierry Reding }; 22553db6d3baSThierry Reding }; 22563db6d3baSThierry Reding 2257f7eb2785SJon Hunter nvenc@15a80000 { 2258f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 2259f7eb2785SJon Hunter reg = <0x15a80000 0x00040000>; 2260f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2261f7eb2785SJon Hunter clock-names = "nvenc"; 2262f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2263f7eb2785SJon Hunter reset-names = "nvenc"; 2264f7eb2785SJon Hunter 2265f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2266f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2267f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2268f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2269f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2270f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2271f7eb2785SJon Hunter dma-coherent; 2272f7eb2785SJon Hunter 2273f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2274f7eb2785SJon Hunter }; 2275f7eb2785SJon Hunter 22763db6d3baSThierry Reding sor0: sor@15b00000 { 22773db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22783db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 22793db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22823db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22843db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22863db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22873db6d3baSThierry Reding "pad"; 22883db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22893db6d3baSThierry Reding reset-names = "sor"; 22903db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22913db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22923db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22933db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22943db6d3baSThierry Reding status = "disabled"; 22953db6d3baSThierry Reding 22963db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22973db6d3baSThierry Reding nvidia,interface = <0>; 22983db6d3baSThierry Reding }; 22993db6d3baSThierry Reding 23003db6d3baSThierry Reding sor1: sor@15b40000 { 23013db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 2302939e7430SThierry Reding reg = <0x15b40000 0x40000>; 23033db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 23043db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 23053db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 23063db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 23073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23083db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 23103db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23113db6d3baSThierry Reding "pad"; 23123db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 23133db6d3baSThierry Reding reset-names = "sor"; 23143db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 23153db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 23163db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 23173db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23183db6d3baSThierry Reding status = "disabled"; 23193db6d3baSThierry Reding 23203db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23213db6d3baSThierry Reding nvidia,interface = <1>; 23223db6d3baSThierry Reding }; 23233db6d3baSThierry Reding 23243db6d3baSThierry Reding sor2: sor@15b80000 { 23253db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23263db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 23273db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23283db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23323db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23343db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23353db6d3baSThierry Reding "pad"; 23363db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23373db6d3baSThierry Reding reset-names = "sor"; 23383db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23393db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23403db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23413db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23423db6d3baSThierry Reding status = "disabled"; 23433db6d3baSThierry Reding 23443db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23453db6d3baSThierry Reding nvidia,interface = <2>; 23463db6d3baSThierry Reding }; 23473db6d3baSThierry Reding 23483db6d3baSThierry Reding sor3: sor@15bc0000 { 23493db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23503db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 23513db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23523db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23553db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23563db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23573db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23583db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23593db6d3baSThierry Reding "pad"; 23603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23613db6d3baSThierry Reding reset-names = "sor"; 23623db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23633db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23643db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23653db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23663db6d3baSThierry Reding status = "disabled"; 23673db6d3baSThierry Reding 23683db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23693db6d3baSThierry Reding nvidia,interface = <3>; 23703db6d3baSThierry Reding }; 23713db6d3baSThierry Reding }; 23720f134e39SThierry Reding 23730f134e39SThierry Reding gpu@17000000 { 23740f134e39SThierry Reding compatible = "nvidia,gv11b"; 2375818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 2376818ae79aSThierry Reding <0x18000000 0x1000000>; 23770f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 23780f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 23790f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 23800f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 23810f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 23820f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 23830f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 23840f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 23850f134e39SThierry Reding reset-names = "gpu"; 23860f134e39SThierry Reding dma-coherent; 23870f134e39SThierry Reding 23880f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 23890f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 23900f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 23910f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 23920f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 23930f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 23940f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 23950f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 23960f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 23970f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 23980f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 23990f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 24000f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 24010f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 24020f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 24030f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 24040f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 24050f134e39SThierry Reding }; 24065425fb15SMikko Perttunen }; 24075425fb15SMikko Perttunen 24082602c32fSVidya Sagar pcie@14100000 { 2409f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24102602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2411644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2412644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2413644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2414644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24152602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24162602c32fSVidya Sagar 24172602c32fSVidya Sagar status = "disabled"; 24182602c32fSVidya Sagar 24192602c32fSVidya Sagar #address-cells = <3>; 24202602c32fSVidya Sagar #size-cells = <2>; 24212602c32fSVidya Sagar device_type = "pci"; 24222602c32fSVidya Sagar num-lanes = <1>; 24232602c32fSVidya Sagar linux,pci-domain = <1>; 24242602c32fSVidya Sagar 24252602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 24262602c32fSVidya Sagar clock-names = "core"; 24272602c32fSVidya Sagar 24282602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 24292602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 24302602c32fSVidya Sagar reset-names = "apb", "core"; 24312602c32fSVidya Sagar 24322602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24332602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24342602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24352602c32fSVidya Sagar 24362602c32fSVidya Sagar #interrupt-cells = <1>; 24372602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24382602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 24392602c32fSVidya Sagar 24402602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 24412602c32fSVidya Sagar 24422602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24432602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24442602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24452602c32fSVidya Sagar 24462602c32fSVidya Sagar bus-range = <0x0 0xff>; 2447d5237c7cSThierry Reding 24488a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24498a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24508a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2451d5237c7cSThierry Reding 2452d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2453d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2454ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2455ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2456ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2457ba02920cSVidya Sagar dma-coherent; 24582602c32fSVidya Sagar }; 24592602c32fSVidya Sagar 24602602c32fSVidya Sagar pcie@14120000 { 2461f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24622602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2463644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2464644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2465644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2466644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24672602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24682602c32fSVidya Sagar 24692602c32fSVidya Sagar status = "disabled"; 24702602c32fSVidya Sagar 24712602c32fSVidya Sagar #address-cells = <3>; 24722602c32fSVidya Sagar #size-cells = <2>; 24732602c32fSVidya Sagar device_type = "pci"; 24742602c32fSVidya Sagar num-lanes = <1>; 24752602c32fSVidya Sagar linux,pci-domain = <2>; 24762602c32fSVidya Sagar 24772602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24782602c32fSVidya Sagar clock-names = "core"; 24792602c32fSVidya Sagar 24802602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24812602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24822602c32fSVidya Sagar reset-names = "apb", "core"; 24832602c32fSVidya Sagar 24842602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24852602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24862602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24872602c32fSVidya Sagar 24882602c32fSVidya Sagar #interrupt-cells = <1>; 24892602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24902602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24912602c32fSVidya Sagar 24922602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24932602c32fSVidya Sagar 24942602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24952602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24962602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24972602c32fSVidya Sagar 24982602c32fSVidya Sagar bus-range = <0x0 0xff>; 2499d5237c7cSThierry Reding 25008a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25018a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 25028a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2503d5237c7cSThierry Reding 2504d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2505d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2506ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2507ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2508ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2509ba02920cSVidya Sagar dma-coherent; 25102602c32fSVidya Sagar }; 25112602c32fSVidya Sagar 25122602c32fSVidya Sagar pcie@14140000 { 2513f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25142602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2515644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2516644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2517644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2518644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25192602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25202602c32fSVidya Sagar 25212602c32fSVidya Sagar status = "disabled"; 25222602c32fSVidya Sagar 25232602c32fSVidya Sagar #address-cells = <3>; 25242602c32fSVidya Sagar #size-cells = <2>; 25252602c32fSVidya Sagar device_type = "pci"; 25262602c32fSVidya Sagar num-lanes = <1>; 25272602c32fSVidya Sagar linux,pci-domain = <3>; 25282602c32fSVidya Sagar 25292602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 25302602c32fSVidya Sagar clock-names = "core"; 25312602c32fSVidya Sagar 25322602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 25332602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 25342602c32fSVidya Sagar reset-names = "apb", "core"; 25352602c32fSVidya Sagar 25362602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25372602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25382602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25392602c32fSVidya Sagar 25402602c32fSVidya Sagar #interrupt-cells = <1>; 25412602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25422602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 25432602c32fSVidya Sagar 25442602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 25452602c32fSVidya Sagar 25462602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25472602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25482602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25492602c32fSVidya Sagar 25502602c32fSVidya Sagar bus-range = <0x0 0xff>; 2551d5237c7cSThierry Reding 25528a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25538a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25548a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2555d5237c7cSThierry Reding 2556d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2557d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2558ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2559ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2560ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2561ba02920cSVidya Sagar dma-coherent; 25622602c32fSVidya Sagar }; 25632602c32fSVidya Sagar 25642602c32fSVidya Sagar pcie@14160000 { 2565f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25662602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2567644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2568644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2569644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2570644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25712602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25722602c32fSVidya Sagar 25732602c32fSVidya Sagar status = "disabled"; 25742602c32fSVidya Sagar 25752602c32fSVidya Sagar #address-cells = <3>; 25762602c32fSVidya Sagar #size-cells = <2>; 25772602c32fSVidya Sagar device_type = "pci"; 25782602c32fSVidya Sagar num-lanes = <4>; 25792602c32fSVidya Sagar linux,pci-domain = <4>; 25802602c32fSVidya Sagar 25812602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25822602c32fSVidya Sagar clock-names = "core"; 25832602c32fSVidya Sagar 25842602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25852602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25862602c32fSVidya Sagar reset-names = "apb", "core"; 25872602c32fSVidya Sagar 25882602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25892602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25902602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25912602c32fSVidya Sagar 25922602c32fSVidya Sagar #interrupt-cells = <1>; 25932602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25942602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25952602c32fSVidya Sagar 25962602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25972602c32fSVidya Sagar 25982602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25992602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26002602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26012602c32fSVidya Sagar 26022602c32fSVidya Sagar bus-range = <0x0 0xff>; 2603d5237c7cSThierry Reding 26048a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26058a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26068a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2607d5237c7cSThierry Reding 2608d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2609d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2610ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2611ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2612ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2613ba02920cSVidya Sagar dma-coherent; 26142602c32fSVidya Sagar }; 26152602c32fSVidya Sagar 26162602c32fSVidya Sagar pcie@14180000 { 2617f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26182602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2619644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2620644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2621644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2622644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26232602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26242602c32fSVidya Sagar 26252602c32fSVidya Sagar status = "disabled"; 26262602c32fSVidya Sagar 26272602c32fSVidya Sagar #address-cells = <3>; 26282602c32fSVidya Sagar #size-cells = <2>; 26292602c32fSVidya Sagar device_type = "pci"; 26302602c32fSVidya Sagar num-lanes = <8>; 26312602c32fSVidya Sagar linux,pci-domain = <0>; 26322602c32fSVidya Sagar 26332602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26342602c32fSVidya Sagar clock-names = "core"; 26352602c32fSVidya Sagar 26362602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26372602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26382602c32fSVidya Sagar reset-names = "apb", "core"; 26392602c32fSVidya Sagar 26402602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26412602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26422602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26432602c32fSVidya Sagar 26442602c32fSVidya Sagar #interrupt-cells = <1>; 26452602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26462602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26472602c32fSVidya Sagar 26482602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26492602c32fSVidya Sagar 26502602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26512602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26522602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26532602c32fSVidya Sagar 26542602c32fSVidya Sagar bus-range = <0x0 0xff>; 2655d5237c7cSThierry Reding 26568a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26578a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26588a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2659d5237c7cSThierry Reding 2660d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2661d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2662ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2663ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2664ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2665ba02920cSVidya Sagar dma-coherent; 26662602c32fSVidya Sagar }; 26672602c32fSVidya Sagar 26682602c32fSVidya Sagar pcie@141a0000 { 2669f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26702602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2671644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2672644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2673644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2674644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26752602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26762602c32fSVidya Sagar 26772602c32fSVidya Sagar status = "disabled"; 26782602c32fSVidya Sagar 26792602c32fSVidya Sagar #address-cells = <3>; 26802602c32fSVidya Sagar #size-cells = <2>; 26812602c32fSVidya Sagar device_type = "pci"; 26822602c32fSVidya Sagar num-lanes = <8>; 26832602c32fSVidya Sagar linux,pci-domain = <5>; 26842602c32fSVidya Sagar 2685dbb72e2cSVidya Sagar pinctrl-names = "default"; 2686dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2687dbb72e2cSVidya Sagar 2688c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2689c453cc9eSThierry Reding clock-names = "core"; 26902602c32fSVidya Sagar 26912602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 26922602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 26932602c32fSVidya Sagar reset-names = "apb", "core"; 26942602c32fSVidya Sagar 26952602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26962602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26972602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26982602c32fSVidya Sagar 26992602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 27002602c32fSVidya Sagar 27012602c32fSVidya Sagar #interrupt-cells = <1>; 27022602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 27032602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 27042602c32fSVidya Sagar 27052602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 27062602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27072602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 27082602c32fSVidya Sagar 27092602c32fSVidya Sagar bus-range = <0x0 0xff>; 2710d5237c7cSThierry Reding 27118a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 27128a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 27138a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2714d5237c7cSThierry Reding 2715d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2716d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2717ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2718ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2719ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2720ba02920cSVidya Sagar dma-coherent; 27212602c32fSVidya Sagar }; 27222602c32fSVidya Sagar 2723b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2724bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27250c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2726644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2727644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2728644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2729644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27300c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27310c988b73SVidya Sagar 27320c988b73SVidya Sagar status = "disabled"; 27330c988b73SVidya Sagar 27340c988b73SVidya Sagar num-lanes = <4>; 27350c988b73SVidya Sagar num-ib-windows = <2>; 27360c988b73SVidya Sagar num-ob-windows = <8>; 27370c988b73SVidya Sagar 27380c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 27390c988b73SVidya Sagar clock-names = "core"; 27400c988b73SVidya Sagar 27410c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 27420c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 27430c988b73SVidya Sagar reset-names = "apb", "core"; 27440c988b73SVidya Sagar 27450c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27460c988b73SVidya Sagar interrupt-names = "intr"; 27470c988b73SVidya Sagar 27480c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 27490c988b73SVidya Sagar 27500c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27510c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27520c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2753ba02920cSVidya Sagar 2754ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2755ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2756ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2757ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2758ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2759ba02920cSVidya Sagar dma-coherent; 27600c988b73SVidya Sagar }; 27610c988b73SVidya Sagar 2762b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2763bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27640c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2765644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2766644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2767644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2768644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27690c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27700c988b73SVidya Sagar 27710c988b73SVidya Sagar status = "disabled"; 27720c988b73SVidya Sagar 27730c988b73SVidya Sagar num-lanes = <8>; 27740c988b73SVidya Sagar num-ib-windows = <2>; 27750c988b73SVidya Sagar num-ob-windows = <8>; 27760c988b73SVidya Sagar 27770c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 27780c988b73SVidya Sagar clock-names = "core"; 27790c988b73SVidya Sagar 27800c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 27810c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 27820c988b73SVidya Sagar reset-names = "apb", "core"; 27830c988b73SVidya Sagar 27840c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27850c988b73SVidya Sagar interrupt-names = "intr"; 27860c988b73SVidya Sagar 27870c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 27880c988b73SVidya Sagar 27890c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27900c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27910c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2792ba02920cSVidya Sagar 2793ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2794ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2795ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2796ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2797ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2798ba02920cSVidya Sagar dma-coherent; 27990c988b73SVidya Sagar }; 28000c988b73SVidya Sagar 2801b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2802bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 28030c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2804644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2805644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2806644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2807644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 28080c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 28090c988b73SVidya Sagar 28100c988b73SVidya Sagar status = "disabled"; 28110c988b73SVidya Sagar 28120c988b73SVidya Sagar num-lanes = <8>; 28130c988b73SVidya Sagar num-ib-windows = <2>; 28140c988b73SVidya Sagar num-ob-windows = <8>; 28150c988b73SVidya Sagar 28160c988b73SVidya Sagar pinctrl-names = "default"; 28170c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 28180c988b73SVidya Sagar 28190c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 28200c988b73SVidya Sagar clock-names = "core"; 28210c988b73SVidya Sagar 28220c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 28230c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 28240c988b73SVidya Sagar reset-names = "apb", "core"; 28250c988b73SVidya Sagar 28260c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 28270c988b73SVidya Sagar interrupt-names = "intr"; 28280c988b73SVidya Sagar 28290c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 28300c988b73SVidya Sagar 28310c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 28320c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 28330c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2834ba02920cSVidya Sagar 2835ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2836ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2837ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2838ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2839ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2840ba02920cSVidya Sagar dma-coherent; 28410c988b73SVidya Sagar }; 28420c988b73SVidya Sagar 2843e867fe41SThierry Reding sram@40000000 { 28445425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28455425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 28465425fb15SMikko Perttunen #address-cells = <1>; 28475425fb15SMikko Perttunen #size-cells = <1>; 28485425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 284961192a9dSMikko Perttunen no-memory-wc; 28505425fb15SMikko Perttunen 2851e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28525425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28535425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28545425fb15SMikko Perttunen pool; 28555425fb15SMikko Perttunen }; 28565425fb15SMikko Perttunen 2857e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28585425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28595425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28605425fb15SMikko Perttunen pool; 28615425fb15SMikko Perttunen }; 28625425fb15SMikko Perttunen }; 28635425fb15SMikko Perttunen 28645425fb15SMikko Perttunen bpmp: bpmp { 28655425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28665425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28675425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28687fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28695425fb15SMikko Perttunen #clock-cells = <1>; 28705425fb15SMikko Perttunen #reset-cells = <1>; 28715425fb15SMikko Perttunen #power-domain-cells = <1>; 2872d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2873d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2874d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2875d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2876d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2877c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28785425fb15SMikko Perttunen 28795425fb15SMikko Perttunen bpmp_i2c: i2c { 28805425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28815425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28825425fb15SMikko Perttunen #address-cells = <1>; 28835425fb15SMikko Perttunen #size-cells = <0>; 28845425fb15SMikko Perttunen }; 28855425fb15SMikko Perttunen 28865425fb15SMikko Perttunen bpmp_thermal: thermal { 28875425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28885425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28895425fb15SMikko Perttunen }; 28905425fb15SMikko Perttunen }; 28915425fb15SMikko Perttunen 28927780a034SMikko Perttunen cpus { 2893d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2894d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28957780a034SMikko Perttunen #address-cells = <1>; 28967780a034SMikko Perttunen #size-cells = <0>; 28977780a034SMikko Perttunen 2898b45d322cSThierry Reding cpu0_0: cpu@0 { 289931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29007780a034SMikko Perttunen device_type = "cpu"; 2901b45d322cSThierry Reding reg = <0x000>; 29027780a034SMikko Perttunen enable-method = "psci"; 2903b45d322cSThierry Reding i-cache-size = <131072>; 2904b45d322cSThierry Reding i-cache-line-size = <64>; 2905b45d322cSThierry Reding i-cache-sets = <512>; 2906b45d322cSThierry Reding d-cache-size = <65536>; 2907b45d322cSThierry Reding d-cache-line-size = <64>; 2908b45d322cSThierry Reding d-cache-sets = <256>; 2909b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29107780a034SMikko Perttunen }; 29117780a034SMikko Perttunen 2912b45d322cSThierry Reding cpu0_1: cpu@1 { 291331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29147780a034SMikko Perttunen device_type = "cpu"; 2915b45d322cSThierry Reding reg = <0x001>; 29167780a034SMikko Perttunen enable-method = "psci"; 2917b45d322cSThierry Reding i-cache-size = <131072>; 2918b45d322cSThierry Reding i-cache-line-size = <64>; 2919b45d322cSThierry Reding i-cache-sets = <512>; 2920b45d322cSThierry Reding d-cache-size = <65536>; 2921b45d322cSThierry Reding d-cache-line-size = <64>; 2922b45d322cSThierry Reding d-cache-sets = <256>; 2923b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29247780a034SMikko Perttunen }; 29257780a034SMikko Perttunen 2926b45d322cSThierry Reding cpu1_0: cpu@100 { 292731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29287780a034SMikko Perttunen device_type = "cpu"; 29297780a034SMikko Perttunen reg = <0x100>; 29307780a034SMikko Perttunen enable-method = "psci"; 2931b45d322cSThierry Reding i-cache-size = <131072>; 2932b45d322cSThierry Reding i-cache-line-size = <64>; 2933b45d322cSThierry Reding i-cache-sets = <512>; 2934b45d322cSThierry Reding d-cache-size = <65536>; 2935b45d322cSThierry Reding d-cache-line-size = <64>; 2936b45d322cSThierry Reding d-cache-sets = <256>; 2937b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29387780a034SMikko Perttunen }; 29397780a034SMikko Perttunen 2940b45d322cSThierry Reding cpu1_1: cpu@101 { 294131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29427780a034SMikko Perttunen device_type = "cpu"; 29437780a034SMikko Perttunen reg = <0x101>; 29447780a034SMikko Perttunen enable-method = "psci"; 2945b45d322cSThierry Reding i-cache-size = <131072>; 2946b45d322cSThierry Reding i-cache-line-size = <64>; 2947b45d322cSThierry Reding i-cache-sets = <512>; 2948b45d322cSThierry Reding d-cache-size = <65536>; 2949b45d322cSThierry Reding d-cache-line-size = <64>; 2950b45d322cSThierry Reding d-cache-sets = <256>; 2951b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29527780a034SMikko Perttunen }; 29537780a034SMikko Perttunen 2954b45d322cSThierry Reding cpu2_0: cpu@200 { 295531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29567780a034SMikko Perttunen device_type = "cpu"; 29577780a034SMikko Perttunen reg = <0x200>; 29587780a034SMikko Perttunen enable-method = "psci"; 2959b45d322cSThierry Reding i-cache-size = <131072>; 2960b45d322cSThierry Reding i-cache-line-size = <64>; 2961b45d322cSThierry Reding i-cache-sets = <512>; 2962b45d322cSThierry Reding d-cache-size = <65536>; 2963b45d322cSThierry Reding d-cache-line-size = <64>; 2964b45d322cSThierry Reding d-cache-sets = <256>; 2965b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29667780a034SMikko Perttunen }; 29677780a034SMikko Perttunen 2968b45d322cSThierry Reding cpu2_1: cpu@201 { 296931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29707780a034SMikko Perttunen device_type = "cpu"; 29717780a034SMikko Perttunen reg = <0x201>; 29727780a034SMikko Perttunen enable-method = "psci"; 2973b45d322cSThierry Reding i-cache-size = <131072>; 2974b45d322cSThierry Reding i-cache-line-size = <64>; 2975b45d322cSThierry Reding i-cache-sets = <512>; 2976b45d322cSThierry Reding d-cache-size = <65536>; 2977b45d322cSThierry Reding d-cache-line-size = <64>; 2978b45d322cSThierry Reding d-cache-sets = <256>; 2979b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29807780a034SMikko Perttunen }; 29817780a034SMikko Perttunen 2982b45d322cSThierry Reding cpu3_0: cpu@300 { 298331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29847780a034SMikko Perttunen device_type = "cpu"; 2985b45d322cSThierry Reding reg = <0x300>; 29867780a034SMikko Perttunen enable-method = "psci"; 2987b45d322cSThierry Reding i-cache-size = <131072>; 2988b45d322cSThierry Reding i-cache-line-size = <64>; 2989b45d322cSThierry Reding i-cache-sets = <512>; 2990b45d322cSThierry Reding d-cache-size = <65536>; 2991b45d322cSThierry Reding d-cache-line-size = <64>; 2992b45d322cSThierry Reding d-cache-sets = <256>; 2993b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29947780a034SMikko Perttunen }; 29957780a034SMikko Perttunen 2996b45d322cSThierry Reding cpu3_1: cpu@301 { 299731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29987780a034SMikko Perttunen device_type = "cpu"; 2999b45d322cSThierry Reding reg = <0x301>; 30007780a034SMikko Perttunen enable-method = "psci"; 3001b45d322cSThierry Reding i-cache-size = <131072>; 3002b45d322cSThierry Reding i-cache-line-size = <64>; 3003b45d322cSThierry Reding i-cache-sets = <512>; 3004b45d322cSThierry Reding d-cache-size = <65536>; 3005b45d322cSThierry Reding d-cache-line-size = <64>; 3006b45d322cSThierry Reding d-cache-sets = <256>; 3007b45d322cSThierry Reding next-level-cache = <&l2c_3>; 3008b45d322cSThierry Reding }; 3009b45d322cSThierry Reding 3010b45d322cSThierry Reding cpu-map { 3011b45d322cSThierry Reding cluster0 { 3012b45d322cSThierry Reding core0 { 3013b45d322cSThierry Reding cpu = <&cpu0_0>; 3014b45d322cSThierry Reding }; 3015b45d322cSThierry Reding 3016b45d322cSThierry Reding core1 { 3017b45d322cSThierry Reding cpu = <&cpu0_1>; 3018b45d322cSThierry Reding }; 3019b45d322cSThierry Reding }; 3020b45d322cSThierry Reding 3021b45d322cSThierry Reding cluster1 { 3022b45d322cSThierry Reding core0 { 3023b45d322cSThierry Reding cpu = <&cpu1_0>; 3024b45d322cSThierry Reding }; 3025b45d322cSThierry Reding 3026b45d322cSThierry Reding core1 { 3027b45d322cSThierry Reding cpu = <&cpu1_1>; 3028b45d322cSThierry Reding }; 3029b45d322cSThierry Reding }; 3030b45d322cSThierry Reding 3031b45d322cSThierry Reding cluster2 { 3032b45d322cSThierry Reding core0 { 3033b45d322cSThierry Reding cpu = <&cpu2_0>; 3034b45d322cSThierry Reding }; 3035b45d322cSThierry Reding 3036b45d322cSThierry Reding core1 { 3037b45d322cSThierry Reding cpu = <&cpu2_1>; 3038b45d322cSThierry Reding }; 3039b45d322cSThierry Reding }; 3040b45d322cSThierry Reding 3041b45d322cSThierry Reding cluster3 { 3042b45d322cSThierry Reding core0 { 3043b45d322cSThierry Reding cpu = <&cpu3_0>; 3044b45d322cSThierry Reding }; 3045b45d322cSThierry Reding 3046b45d322cSThierry Reding core1 { 3047b45d322cSThierry Reding cpu = <&cpu3_1>; 3048b45d322cSThierry Reding }; 3049b45d322cSThierry Reding }; 3050b45d322cSThierry Reding }; 3051b45d322cSThierry Reding 3052b45d322cSThierry Reding l2c_0: l2-cache0 { 3053*27f1568bSPierre Gondois compatible = "cache"; 3054*27f1568bSPierre Gondois cache-unified; 3055b45d322cSThierry Reding cache-size = <2097152>; 3056b45d322cSThierry Reding cache-line-size = <64>; 3057b45d322cSThierry Reding cache-sets = <2048>; 3058*27f1568bSPierre Gondois cache-level = <2>; 3059b45d322cSThierry Reding next-level-cache = <&l3c>; 3060b45d322cSThierry Reding }; 3061b45d322cSThierry Reding 3062b45d322cSThierry Reding l2c_1: l2-cache1 { 3063*27f1568bSPierre Gondois compatible = "cache"; 3064*27f1568bSPierre Gondois cache-unified; 3065b45d322cSThierry Reding cache-size = <2097152>; 3066b45d322cSThierry Reding cache-line-size = <64>; 3067b45d322cSThierry Reding cache-sets = <2048>; 3068*27f1568bSPierre Gondois cache-level = <2>; 3069b45d322cSThierry Reding next-level-cache = <&l3c>; 3070b45d322cSThierry Reding }; 3071b45d322cSThierry Reding 3072b45d322cSThierry Reding l2c_2: l2-cache2 { 3073*27f1568bSPierre Gondois compatible = "cache"; 3074*27f1568bSPierre Gondois cache-unified; 3075b45d322cSThierry Reding cache-size = <2097152>; 3076b45d322cSThierry Reding cache-line-size = <64>; 3077b45d322cSThierry Reding cache-sets = <2048>; 3078*27f1568bSPierre Gondois cache-level = <2>; 3079b45d322cSThierry Reding next-level-cache = <&l3c>; 3080b45d322cSThierry Reding }; 3081b45d322cSThierry Reding 3082b45d322cSThierry Reding l2c_3: l2-cache3 { 3083*27f1568bSPierre Gondois compatible = "cache"; 3084*27f1568bSPierre Gondois cache-unified; 3085b45d322cSThierry Reding cache-size = <2097152>; 3086b45d322cSThierry Reding cache-line-size = <64>; 3087b45d322cSThierry Reding cache-sets = <2048>; 3088*27f1568bSPierre Gondois cache-level = <2>; 3089b45d322cSThierry Reding next-level-cache = <&l3c>; 3090b45d322cSThierry Reding }; 3091b45d322cSThierry Reding 3092b45d322cSThierry Reding l3c: l3-cache { 3093*27f1568bSPierre Gondois compatible = "cache"; 3094*27f1568bSPierre Gondois cache-unified; 3095b45d322cSThierry Reding cache-size = <4194304>; 3096b45d322cSThierry Reding cache-line-size = <64>; 3097*27f1568bSPierre Gondois cache-level = <3>; 3098b45d322cSThierry Reding cache-sets = <4096>; 30997780a034SMikko Perttunen }; 31007780a034SMikko Perttunen }; 31017780a034SMikko Perttunen 31029e79e58fSJon Hunter pmu { 3103f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 31049e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 31059e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 31069e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 31079e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 31089e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 31099e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 31109e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 31119e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 31129e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 31139e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 31149e79e58fSJon Hunter }; 31159e79e58fSJon Hunter 31167780a034SMikko Perttunen psci { 31177780a034SMikko Perttunen compatible = "arm,psci-1.0"; 31187780a034SMikko Perttunen status = "okay"; 31197780a034SMikko Perttunen method = "smc"; 31207780a034SMikko Perttunen }; 31217780a034SMikko Perttunen 31225b4f6323SSameer Pujar sound { 31235b4f6323SSameer Pujar status = "disabled"; 31245b4f6323SSameer Pujar 31255b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 31265b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31275b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 31285b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 31295b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 31305b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 31315b4f6323SSameer Pujar assigned-clock-parents = <0>, 31325b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 31335b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31345b4f6323SSameer Pujar /* 31355b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31365b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31375b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31385b4f6323SSameer Pujar */ 31395b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31405b4f6323SSameer Pujar }; 31415b4f6323SSameer Pujar 314299d9bde5SThierry Reding tcu: serial { 3143a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 3144a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3145a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3146a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 3147a38570c2SMikko Perttunen }; 3148a38570c2SMikko Perttunen 3149686ba009SThierry Reding thermal-zones { 3150fe57ff53SThierry Reding cpu-thermal { 3151fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3152686ba009SThierry Reding status = "disabled"; 3153686ba009SThierry Reding }; 3154686ba009SThierry Reding 3155fe57ff53SThierry Reding gpu-thermal { 3156fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3157686ba009SThierry Reding status = "disabled"; 3158686ba009SThierry Reding }; 3159686ba009SThierry Reding 3160fe57ff53SThierry Reding aux-thermal { 3161fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3162686ba009SThierry Reding status = "disabled"; 3163686ba009SThierry Reding }; 3164686ba009SThierry Reding 3165fe57ff53SThierry Reding pllx-thermal { 3166fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3167686ba009SThierry Reding status = "disabled"; 3168686ba009SThierry Reding }; 3169686ba009SThierry Reding 3170fe57ff53SThierry Reding ao-thermal { 3171fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3172686ba009SThierry Reding status = "disabled"; 3173686ba009SThierry Reding }; 3174686ba009SThierry Reding 3175fe57ff53SThierry Reding tj-thermal { 3176fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3177686ba009SThierry Reding status = "disabled"; 3178686ba009SThierry Reding }; 3179686ba009SThierry Reding }; 3180686ba009SThierry Reding 31815425fb15SMikko Perttunen timer { 31825425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31835425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31845425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31855425fb15SMikko Perttunen <GIC_PPI 14 31865425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31875425fb15SMikko Perttunen <GIC_PPI 11 31885425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31895425fb15SMikko Perttunen <GIC_PPI 10 31905425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31915425fb15SMikko Perttunen interrupt-parent = <&gic>; 3192b30be673SThierry Reding always-on; 31935425fb15SMikko Perttunen }; 31945425fb15SMikko Perttunen}; 3195