15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 65425fb15SMikko Perttunen#include <dt-bindings/reset/tegra194-reset.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 95425fb15SMikko Perttunen 105425fb15SMikko Perttunen/ { 115425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 125425fb15SMikko Perttunen interrupt-parent = <&gic>; 135425fb15SMikko Perttunen #address-cells = <2>; 145425fb15SMikko Perttunen #size-cells = <2>; 155425fb15SMikko Perttunen 165425fb15SMikko Perttunen /* control backbone */ 175425fb15SMikko Perttunen cbb { 185425fb15SMikko Perttunen compatible = "simple-bus"; 195425fb15SMikko Perttunen #address-cells = <1>; 205425fb15SMikko Perttunen #size-cells = <1>; 215425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 225425fb15SMikko Perttunen 23f69ce393SMikko Perttunen gpio: gpio@2200000 { 24f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 25f69ce393SMikko Perttunen reg-names = "security", "gpio"; 26f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 27f69ce393SMikko Perttunen <0x2210000 0x10000>; 28f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 29f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 30f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 31f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 32f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 33f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 34f69ce393SMikko Perttunen #interrupt-cells = <2>; 35f69ce393SMikko Perttunen interrupt-controller; 36f69ce393SMikko Perttunen #gpio-cells = <2>; 37f69ce393SMikko Perttunen gpio-controller; 38f69ce393SMikko Perttunen }; 39f69ce393SMikko Perttunen 40f89b58ceSMikko Perttunen ethernet@2490000 { 41f89b58ceSMikko Perttunen compatible = "nvidia,tegra186-eqos", 42f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 43f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 44f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 45f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 46f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 47f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 48f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 49f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 50f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 52f89b58ceSMikko Perttunen reset-names = "eqos"; 53f89b58ceSMikko Perttunen status = "disabled"; 54f89b58ceSMikko Perttunen 55f89b58ceSMikko Perttunen snps,write-requests = <1>; 56f89b58ceSMikko Perttunen snps,read-requests = <3>; 57f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 58f89b58ceSMikko Perttunen snps,txpbl = <16>; 59f89b58ceSMikko Perttunen snps,rxpbl = <8>; 60f89b58ceSMikko Perttunen }; 61f89b58ceSMikko Perttunen 625d2249ddSSameer Pujar aconnect { 635d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 645d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 655d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 665d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 675d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 685d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 695d2249ddSSameer Pujar #address-cells = <1>; 705d2249ddSSameer Pujar #size-cells = <1>; 715d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 725d2249ddSSameer Pujar status = "disabled"; 735d2249ddSSameer Pujar 745d2249ddSSameer Pujar dma-controller@2930000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 765d2249ddSSameer Pujar "nvidia,tegra186-adma"; 775d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 785d2249ddSSameer Pujar interrupt-parent = <&agic>; 795d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 805d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 815d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 825d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 835d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 845d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 855d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 865d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 875d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 885d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 895d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1115d2249ddSSameer Pujar #dma-cells = <1>; 1125d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1135d2249ddSSameer Pujar clock-names = "d_audio"; 1145d2249ddSSameer Pujar status = "disabled"; 1155d2249ddSSameer Pujar }; 1165d2249ddSSameer Pujar 1175d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1185d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1195d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1205d2249ddSSameer Pujar #interrupt-cells = <3>; 1215d2249ddSSameer Pujar interrupt-controller; 1225d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1235d2249ddSSameer Pujar <0x02a42000 0x2000>; 1245d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1255d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1265d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1275d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1285d2249ddSSameer Pujar clock-names = "clk"; 1295d2249ddSSameer Pujar status = "disabled"; 1305d2249ddSSameer Pujar }; 1315d2249ddSSameer Pujar }; 1325d2249ddSSameer Pujar 1335425fb15SMikko Perttunen uarta: serial@3100000 { 1345425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1355425fb15SMikko Perttunen reg = <0x03100000 0x40>; 1365425fb15SMikko Perttunen reg-shift = <2>; 1375425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 1395425fb15SMikko Perttunen clock-names = "serial"; 1405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 1415425fb15SMikko Perttunen reset-names = "serial"; 1425425fb15SMikko Perttunen status = "disabled"; 1435425fb15SMikko Perttunen }; 1445425fb15SMikko Perttunen 1455425fb15SMikko Perttunen uartb: serial@3110000 { 1465425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1475425fb15SMikko Perttunen reg = <0x03110000 0x40>; 1485425fb15SMikko Perttunen reg-shift = <2>; 1495425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1505425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 1515425fb15SMikko Perttunen clock-names = "serial"; 1525425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 1535425fb15SMikko Perttunen reset-names = "serial"; 1545425fb15SMikko Perttunen status = "disabled"; 1555425fb15SMikko Perttunen }; 1565425fb15SMikko Perttunen 1575425fb15SMikko Perttunen uartd: serial@3130000 { 1585425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1595425fb15SMikko Perttunen reg = <0x03130000 0x40>; 1605425fb15SMikko Perttunen reg-shift = <2>; 1615425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1625425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 1635425fb15SMikko Perttunen clock-names = "serial"; 1645425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 1655425fb15SMikko Perttunen reset-names = "serial"; 1665425fb15SMikko Perttunen status = "disabled"; 1675425fb15SMikko Perttunen }; 1685425fb15SMikko Perttunen 1695425fb15SMikko Perttunen uarte: serial@3140000 { 1705425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1715425fb15SMikko Perttunen reg = <0x03140000 0x40>; 1725425fb15SMikko Perttunen reg-shift = <2>; 1735425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1745425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 1755425fb15SMikko Perttunen clock-names = "serial"; 1765425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 1775425fb15SMikko Perttunen reset-names = "serial"; 1785425fb15SMikko Perttunen status = "disabled"; 1795425fb15SMikko Perttunen }; 1805425fb15SMikko Perttunen 1815425fb15SMikko Perttunen uartf: serial@3150000 { 1825425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1835425fb15SMikko Perttunen reg = <0x03150000 0x40>; 1845425fb15SMikko Perttunen reg-shift = <2>; 1855425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1865425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 1875425fb15SMikko Perttunen clock-names = "serial"; 1885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 1895425fb15SMikko Perttunen reset-names = "serial"; 1905425fb15SMikko Perttunen status = "disabled"; 1915425fb15SMikko Perttunen }; 1925425fb15SMikko Perttunen 1935425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 194d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 1955425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 1965425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1975425fb15SMikko Perttunen #address-cells = <1>; 1985425fb15SMikko Perttunen #size-cells = <0>; 1995425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2005425fb15SMikko Perttunen clock-names = "div-clk"; 2015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2025425fb15SMikko Perttunen reset-names = "i2c"; 2035425fb15SMikko Perttunen status = "disabled"; 2045425fb15SMikko Perttunen }; 2055425fb15SMikko Perttunen 2065425fb15SMikko Perttunen uarth: serial@3170000 { 2075425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2085425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2095425fb15SMikko Perttunen reg-shift = <2>; 2105425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 2125425fb15SMikko Perttunen clock-names = "serial"; 2135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 2145425fb15SMikko Perttunen reset-names = "serial"; 2155425fb15SMikko Perttunen status = "disabled"; 2165425fb15SMikko Perttunen }; 2175425fb15SMikko Perttunen 2185425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 219d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2205425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 2215425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2225425fb15SMikko Perttunen #address-cells = <1>; 2235425fb15SMikko Perttunen #size-cells = <0>; 2245425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 2255425fb15SMikko Perttunen clock-names = "div-clk"; 2265425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 2275425fb15SMikko Perttunen reset-names = "i2c"; 2285425fb15SMikko Perttunen status = "disabled"; 2295425fb15SMikko Perttunen }; 2305425fb15SMikko Perttunen 2315425fb15SMikko Perttunen /* shares pads with dpaux1 */ 2325425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 233d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2345425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 2355425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2365425fb15SMikko Perttunen #address-cells = <1>; 2375425fb15SMikko Perttunen #size-cells = <0>; 2385425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 2395425fb15SMikko Perttunen clock-names = "div-clk"; 2405425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 2415425fb15SMikko Perttunen reset-names = "i2c"; 2425425fb15SMikko Perttunen status = "disabled"; 2435425fb15SMikko Perttunen }; 2445425fb15SMikko Perttunen 2455425fb15SMikko Perttunen /* shares pads with dpaux0 */ 2465425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 247d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2485425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 2495425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2505425fb15SMikko Perttunen #address-cells = <1>; 2515425fb15SMikko Perttunen #size-cells = <0>; 2525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 2535425fb15SMikko Perttunen clock-names = "div-clk"; 2545425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 2555425fb15SMikko Perttunen reset-names = "i2c"; 2565425fb15SMikko Perttunen status = "disabled"; 2575425fb15SMikko Perttunen }; 2585425fb15SMikko Perttunen 2595425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 260d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2615425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 2625425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2635425fb15SMikko Perttunen #address-cells = <1>; 2645425fb15SMikko Perttunen #size-cells = <0>; 2655425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 2665425fb15SMikko Perttunen clock-names = "div-clk"; 2675425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 2685425fb15SMikko Perttunen reset-names = "i2c"; 2695425fb15SMikko Perttunen status = "disabled"; 2705425fb15SMikko Perttunen }; 2715425fb15SMikko Perttunen 2725425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 273d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2745425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 2755425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2765425fb15SMikko Perttunen #address-cells = <1>; 2775425fb15SMikko Perttunen #size-cells = <0>; 2785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 2795425fb15SMikko Perttunen clock-names = "div-clk"; 2805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 2815425fb15SMikko Perttunen reset-names = "i2c"; 2825425fb15SMikko Perttunen status = "disabled"; 2835425fb15SMikko Perttunen }; 2845425fb15SMikko Perttunen 2856a574ec7SThierry Reding pwm1: pwm@3280000 { 2866a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2876a574ec7SThierry Reding "nvidia,tegra186-pwm"; 2886a574ec7SThierry Reding reg = <0x3280000 0x10000>; 2896a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 2906a574ec7SThierry Reding clock-names = "pwm"; 2916a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 2926a574ec7SThierry Reding reset-names = "pwm"; 2936a574ec7SThierry Reding status = "disabled"; 2946a574ec7SThierry Reding #pwm-cells = <2>; 2956a574ec7SThierry Reding }; 2966a574ec7SThierry Reding 2976a574ec7SThierry Reding pwm2: pwm@3290000 { 2986a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 2996a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3006a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3016a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3026a574ec7SThierry Reding clock-names = "pwm"; 3036a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3046a574ec7SThierry Reding reset-names = "pwm"; 3056a574ec7SThierry Reding status = "disabled"; 3066a574ec7SThierry Reding #pwm-cells = <2>; 3076a574ec7SThierry Reding }; 3086a574ec7SThierry Reding 3096a574ec7SThierry Reding pwm3: pwm@32a0000 { 3106a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3116a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3126a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 3136a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 3146a574ec7SThierry Reding clock-names = "pwm"; 3156a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 3166a574ec7SThierry Reding reset-names = "pwm"; 3176a574ec7SThierry Reding status = "disabled"; 3186a574ec7SThierry Reding #pwm-cells = <2>; 3196a574ec7SThierry Reding }; 3206a574ec7SThierry Reding 3216a574ec7SThierry Reding pwm5: pwm@32c0000 { 3226a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3236a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3246a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 3256a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 3266a574ec7SThierry Reding clock-names = "pwm"; 3276a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 3286a574ec7SThierry Reding reset-names = "pwm"; 3296a574ec7SThierry Reding status = "disabled"; 3306a574ec7SThierry Reding #pwm-cells = <2>; 3316a574ec7SThierry Reding }; 3326a574ec7SThierry Reding 3336a574ec7SThierry Reding pwm6: pwm@32d0000 { 3346a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3356a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3366a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 3376a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 3386a574ec7SThierry Reding clock-names = "pwm"; 3396a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 3406a574ec7SThierry Reding reset-names = "pwm"; 3416a574ec7SThierry Reding status = "disabled"; 3426a574ec7SThierry Reding #pwm-cells = <2>; 3436a574ec7SThierry Reding }; 3446a574ec7SThierry Reding 3456a574ec7SThierry Reding pwm7: pwm@32e0000 { 3466a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3476a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3486a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 3496a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 3506a574ec7SThierry Reding clock-names = "pwm"; 3516a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 3526a574ec7SThierry Reding reset-names = "pwm"; 3536a574ec7SThierry Reding status = "disabled"; 3546a574ec7SThierry Reding #pwm-cells = <2>; 3556a574ec7SThierry Reding }; 3566a574ec7SThierry Reding 3576a574ec7SThierry Reding pwm8: pwm@32f0000 { 3586a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3596a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3606a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 3616a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 3626a574ec7SThierry Reding clock-names = "pwm"; 3636a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 3646a574ec7SThierry Reding reset-names = "pwm"; 3656a574ec7SThierry Reding status = "disabled"; 3666a574ec7SThierry Reding #pwm-cells = <2>; 3676a574ec7SThierry Reding }; 3686a574ec7SThierry Reding 3695425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 3705425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3715425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 3725425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3735425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 3745425fb15SMikko Perttunen clock-names = "sdhci"; 3755425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 3765425fb15SMikko Perttunen reset-names = "sdhci"; 3774e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 3784e0f1229SSowjanya Komatineni <0x07>; 3794e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 3804e0f1229SSowjanya Komatineni <0x07>; 3814e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 3834e0f1229SSowjanya Komatineni <0x07>; 3844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3864e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 3874e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 3885425fb15SMikko Perttunen status = "disabled"; 3895425fb15SMikko Perttunen }; 3905425fb15SMikko Perttunen 3915425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 3925425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 3935425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 3945425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 3955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 3965425fb15SMikko Perttunen clock-names = "sdhci"; 3975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 3985425fb15SMikko Perttunen reset-names = "sdhci"; 3994e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 4024e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4034e0f1229SSowjanya Komatineni <0x07>; 4044e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4054e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4064e0f1229SSowjanya Komatineni <0x07>; 4074e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4094e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4104e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4115425fb15SMikko Perttunen status = "disabled"; 4125425fb15SMikko Perttunen }; 4135425fb15SMikko Perttunen 4145425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 4155425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4165425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 4175425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 4185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 4195425fb15SMikko Perttunen clock-names = "sdhci"; 420351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 421351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 422351648d0SSowjanya Komatineni assigned-clock-parents = 423351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 4245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 4255425fb15SMikko Perttunen reset-names = "sdhci"; 4264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 4274e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 4284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 4294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4304e0f1229SSowjanya Komatineni <0x0a>; 4314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 4324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4334e0f1229SSowjanya Komatineni <0x0a>; 4344e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 4354e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 4364e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 437dfd3cb6fSSowjanya Komatineni supports-cqe; 4385425fb15SMikko Perttunen status = "disabled"; 4395425fb15SMikko Perttunen }; 4405425fb15SMikko Perttunen 4414878cc0cSSameer Pujar hda@3510000 { 4424878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 4434878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 4444878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4454878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 4464878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 4474878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 4484878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 4494878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 4504878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 4514878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 4524878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 4534878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 4544878cc0cSSameer Pujar status = "disabled"; 4554878cc0cSSameer Pujar }; 4564878cc0cSSameer Pujar 4575425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 4585425fb15SMikko Perttunen compatible = "arm,gic-400"; 4595425fb15SMikko Perttunen #interrupt-cells = <3>; 4605425fb15SMikko Perttunen interrupt-controller; 4615425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 4625425fb15SMikko Perttunen <0x03882000 0x2000>, 4635425fb15SMikko Perttunen <0x03884000 0x2000>, 4645425fb15SMikko Perttunen <0x03886000 0x2000>; 4655425fb15SMikko Perttunen interrupts = <GIC_PPI 9 4665425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4675425fb15SMikko Perttunen interrupt-parent = <&gic>; 4685425fb15SMikko Perttunen }; 4695425fb15SMikko Perttunen 470badb80beSThierry Reding cec@3960000 { 471badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 472badb80beSThierry Reding reg = <0x03960000 0x10000>; 473badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 474badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 475badb80beSThierry Reding clock-names = "cec"; 476badb80beSThierry Reding status = "disabled"; 477badb80beSThierry Reding }; 478badb80beSThierry Reding 4795425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 480a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 4815425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 482a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 483a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 484a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 485a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 486a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 487a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 488a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 489a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 490a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 491a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 492a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 493a38570c2SMikko Perttunen "shared7"; 494a38570c2SMikko Perttunen #mbox-cells = <2>; 495a38570c2SMikko Perttunen }; 496a38570c2SMikko Perttunen 4972602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 4982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 4992602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 5002602c32fSVidya Sagar reg-names = "ctl"; 5012602c32fSVidya Sagar 5022602c32fSVidya Sagar #phy-cells = <0>; 5032602c32fSVidya Sagar }; 5042602c32fSVidya Sagar 5052602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 5062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5072602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 5082602c32fSVidya Sagar reg-names = "ctl"; 5092602c32fSVidya Sagar 5102602c32fSVidya Sagar #phy-cells = <0>; 5112602c32fSVidya Sagar }; 5122602c32fSVidya Sagar 5132602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 5142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5152602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 5162602c32fSVidya Sagar reg-names = "ctl"; 5172602c32fSVidya Sagar 5182602c32fSVidya Sagar #phy-cells = <0>; 5192602c32fSVidya Sagar }; 5202602c32fSVidya Sagar 5212602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 5222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5232602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 5242602c32fSVidya Sagar reg-names = "ctl"; 5252602c32fSVidya Sagar 5262602c32fSVidya Sagar #phy-cells = <0>; 5272602c32fSVidya Sagar }; 5282602c32fSVidya Sagar 5292602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 5302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5312602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 5322602c32fSVidya Sagar reg-names = "ctl"; 5332602c32fSVidya Sagar 5342602c32fSVidya Sagar #phy-cells = <0>; 5352602c32fSVidya Sagar }; 5362602c32fSVidya Sagar 5372602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 5382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5392602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 5402602c32fSVidya Sagar reg-names = "ctl"; 5412602c32fSVidya Sagar 5422602c32fSVidya Sagar #phy-cells = <0>; 5432602c32fSVidya Sagar }; 5442602c32fSVidya Sagar 5452602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 5462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5472602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 5482602c32fSVidya Sagar reg-names = "ctl"; 5492602c32fSVidya Sagar 5502602c32fSVidya Sagar #phy-cells = <0>; 5512602c32fSVidya Sagar }; 5522602c32fSVidya Sagar 5532602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 5542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5552602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 5562602c32fSVidya Sagar reg-names = "ctl"; 5572602c32fSVidya Sagar 5582602c32fSVidya Sagar #phy-cells = <0>; 5592602c32fSVidya Sagar }; 5602602c32fSVidya Sagar 5612602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 5622602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5632602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 5642602c32fSVidya Sagar reg-names = "ctl"; 5652602c32fSVidya Sagar 5662602c32fSVidya Sagar #phy-cells = <0>; 5672602c32fSVidya Sagar }; 5682602c32fSVidya Sagar 5692602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 5702602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5712602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 5722602c32fSVidya Sagar reg-names = "ctl"; 5732602c32fSVidya Sagar 5742602c32fSVidya Sagar #phy-cells = <0>; 5752602c32fSVidya Sagar }; 5762602c32fSVidya Sagar 5772602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 5782602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5792602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 5802602c32fSVidya Sagar reg-names = "ctl"; 5812602c32fSVidya Sagar 5822602c32fSVidya Sagar #phy-cells = <0>; 5832602c32fSVidya Sagar }; 5842602c32fSVidya Sagar 5852602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 5862602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5872602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 5882602c32fSVidya Sagar reg-names = "ctl"; 5892602c32fSVidya Sagar 5902602c32fSVidya Sagar #phy-cells = <0>; 5912602c32fSVidya Sagar }; 5922602c32fSVidya Sagar 5932602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 5942602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5952602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 5962602c32fSVidya Sagar reg-names = "ctl"; 5972602c32fSVidya Sagar 5982602c32fSVidya Sagar #phy-cells = <0>; 5992602c32fSVidya Sagar }; 6002602c32fSVidya Sagar 6012602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 6022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6032602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 6042602c32fSVidya Sagar reg-names = "ctl"; 6052602c32fSVidya Sagar 6062602c32fSVidya Sagar #phy-cells = <0>; 6072602c32fSVidya Sagar }; 6082602c32fSVidya Sagar 6092602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 6102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6112602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 6122602c32fSVidya Sagar reg-names = "ctl"; 6132602c32fSVidya Sagar 6142602c32fSVidya Sagar #phy-cells = <0>; 6152602c32fSVidya Sagar }; 6162602c32fSVidya Sagar 6172602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 6182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6192602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 6202602c32fSVidya Sagar reg-names = "ctl"; 6212602c32fSVidya Sagar 6222602c32fSVidya Sagar #phy-cells = <0>; 6232602c32fSVidya Sagar }; 6242602c32fSVidya Sagar 6252602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 6262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6272602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 6282602c32fSVidya Sagar reg-names = "ctl"; 6292602c32fSVidya Sagar 6302602c32fSVidya Sagar #phy-cells = <0>; 6312602c32fSVidya Sagar }; 6322602c32fSVidya Sagar 6332602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 6342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6352602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 6362602c32fSVidya Sagar reg-names = "ctl"; 6372602c32fSVidya Sagar 6382602c32fSVidya Sagar #phy-cells = <0>; 6392602c32fSVidya Sagar }; 6402602c32fSVidya Sagar 6412602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 6422602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6432602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 6442602c32fSVidya Sagar reg-names = "ctl"; 6452602c32fSVidya Sagar 6462602c32fSVidya Sagar #phy-cells = <0>; 6472602c32fSVidya Sagar }; 6482602c32fSVidya Sagar 6492602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 6502602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6512602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 6522602c32fSVidya Sagar reg-names = "ctl"; 6532602c32fSVidya Sagar 6542602c32fSVidya Sagar #phy-cells = <0>; 6552602c32fSVidya Sagar }; 6562602c32fSVidya Sagar 657a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 658a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 659a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 660a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 661a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 662a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 663a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 664a38570c2SMikko Perttunen /* 665a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 666a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 667a38570c2SMikko Perttunen */ 668a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 6695425fb15SMikko Perttunen #mbox-cells = <2>; 6705425fb15SMikko Perttunen }; 6715425fb15SMikko Perttunen 6725425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 673d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6745425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 6755425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 6765425fb15SMikko Perttunen #address-cells = <1>; 6775425fb15SMikko Perttunen #size-cells = <0>; 6785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 6795425fb15SMikko Perttunen clock-names = "div-clk"; 6805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 6815425fb15SMikko Perttunen reset-names = "i2c"; 6825425fb15SMikko Perttunen status = "disabled"; 6835425fb15SMikko Perttunen }; 6845425fb15SMikko Perttunen 6855425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 686d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6875425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 6885425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6895425fb15SMikko Perttunen #address-cells = <1>; 6905425fb15SMikko Perttunen #size-cells = <0>; 6915425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 6925425fb15SMikko Perttunen clock-names = "div-clk"; 6935425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 6945425fb15SMikko Perttunen reset-names = "i2c"; 6955425fb15SMikko Perttunen status = "disabled"; 6965425fb15SMikko Perttunen }; 6975425fb15SMikko Perttunen 6985425fb15SMikko Perttunen uartc: serial@c280000 { 6995425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7005425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 7015425fb15SMikko Perttunen reg-shift = <2>; 7025425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 7035425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 7045425fb15SMikko Perttunen clock-names = "serial"; 7055425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 7065425fb15SMikko Perttunen reset-names = "serial"; 7075425fb15SMikko Perttunen status = "disabled"; 7085425fb15SMikko Perttunen }; 7095425fb15SMikko Perttunen 7105425fb15SMikko Perttunen uartg: serial@c290000 { 7115425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7125425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 7135425fb15SMikko Perttunen reg-shift = <2>; 7145425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 7155425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 7165425fb15SMikko Perttunen clock-names = "serial"; 7175425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 7185425fb15SMikko Perttunen reset-names = "serial"; 7195425fb15SMikko Perttunen status = "disabled"; 7205425fb15SMikko Perttunen }; 7215425fb15SMikko Perttunen 72237e5a31dSThierry Reding rtc: rtc@c2a0000 { 72337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 72437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 72537e5a31dSThierry Reding interrupt-parent = <&pmc>; 72637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 72737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 72837e5a31dSThierry Reding clock-names = "rtc"; 72937e5a31dSThierry Reding status = "disabled"; 73037e5a31dSThierry Reding }; 73137e5a31dSThierry Reding 7324d286331SThierry Reding gpio_aon: gpio@c2f0000 { 7334d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 7344d286331SThierry Reding reg-names = "security", "gpio"; 7354d286331SThierry Reding reg = <0xc2f0000 0x1000>, 7364d286331SThierry Reding <0xc2f1000 0x1000>; 7374d286331SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 7384d286331SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 7394d286331SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 7404d286331SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 7414d286331SThierry Reding gpio-controller; 7424d286331SThierry Reding #gpio-cells = <2>; 7434d286331SThierry Reding interrupt-controller; 7444d286331SThierry Reding #interrupt-cells = <2>; 7454d286331SThierry Reding }; 7464d286331SThierry Reding 7476a574ec7SThierry Reding pwm4: pwm@c340000 { 7486a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7496a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7506a574ec7SThierry Reding reg = <0xc340000 0x10000>; 7516a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 7526a574ec7SThierry Reding clock-names = "pwm"; 7536a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 7546a574ec7SThierry Reding reset-names = "pwm"; 7556a574ec7SThierry Reding status = "disabled"; 7566a574ec7SThierry Reding #pwm-cells = <2>; 7576a574ec7SThierry Reding }; 7586a574ec7SThierry Reding 75938ecf1e5SThierry Reding pmc: pmc@c360000 { 7605425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 7615425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 7625425fb15SMikko Perttunen <0x0c370000 0x10000>, 7635425fb15SMikko Perttunen <0x0c380000 0x10000>, 7645425fb15SMikko Perttunen <0x0c390000 0x10000>, 7655425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 7665425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 76738ecf1e5SThierry Reding 76838ecf1e5SThierry Reding #interrupt-cells = <2>; 76938ecf1e5SThierry Reding interrupt-controller; 7705425fb15SMikko Perttunen }; 7713db6d3baSThierry Reding 7723db6d3baSThierry Reding host1x@13e00000 { 7733db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 7743db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 7753db6d3baSThierry Reding <0x13e10000 0x10000>; 7763db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 7773db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 7783db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 7793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 7803db6d3baSThierry Reding clock-names = "host1x"; 7813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 7823db6d3baSThierry Reding reset-names = "host1x"; 7833db6d3baSThierry Reding 7843db6d3baSThierry Reding #address-cells = <1>; 7853db6d3baSThierry Reding #size-cells = <1>; 7863db6d3baSThierry Reding 7873db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 7883db6d3baSThierry Reding 7893db6d3baSThierry Reding display-hub@15200000 { 7903db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 791611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 7923db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 7933db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 7943db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 7953db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 7963db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 7973db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 7983db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 7993db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 8003db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 8013db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 8023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 8033db6d3baSThierry Reding clock-names = "disp", "hub"; 8043db6d3baSThierry Reding status = "disabled"; 8053db6d3baSThierry Reding 8063db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8073db6d3baSThierry Reding 8083db6d3baSThierry Reding #address-cells = <1>; 8093db6d3baSThierry Reding #size-cells = <1>; 8103db6d3baSThierry Reding 8113db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 8123db6d3baSThierry Reding 8133db6d3baSThierry Reding display@15200000 { 8143db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8153db6d3baSThierry Reding reg = <0x15200000 0x10000>; 8163db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 8173db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 8183db6d3baSThierry Reding clock-names = "dc"; 8193db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 8203db6d3baSThierry Reding reset-names = "dc"; 8213db6d3baSThierry Reding 8223db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8233db6d3baSThierry Reding 8243db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8253db6d3baSThierry Reding nvidia,head = <0>; 8263db6d3baSThierry Reding }; 8273db6d3baSThierry Reding 8283db6d3baSThierry Reding display@15210000 { 8293db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8303db6d3baSThierry Reding reg = <0x15210000 0x10000>; 8313db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 8323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 8333db6d3baSThierry Reding clock-names = "dc"; 8343db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 8353db6d3baSThierry Reding reset-names = "dc"; 8363db6d3baSThierry Reding 8373db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 8383db6d3baSThierry Reding 8393db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8403db6d3baSThierry Reding nvidia,head = <1>; 8413db6d3baSThierry Reding }; 8423db6d3baSThierry Reding 8433db6d3baSThierry Reding display@15220000 { 8443db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8453db6d3baSThierry Reding reg = <0x15220000 0x10000>; 8463db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 8473db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 8483db6d3baSThierry Reding clock-names = "dc"; 8493db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 8503db6d3baSThierry Reding reset-names = "dc"; 8513db6d3baSThierry Reding 8523db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 8533db6d3baSThierry Reding 8543db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8553db6d3baSThierry Reding nvidia,head = <2>; 8563db6d3baSThierry Reding }; 8573db6d3baSThierry Reding 8583db6d3baSThierry Reding display@15230000 { 8593db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8603db6d3baSThierry Reding reg = <0x15230000 0x10000>; 8613db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 8623db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 8633db6d3baSThierry Reding clock-names = "dc"; 8643db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 8653db6d3baSThierry Reding reset-names = "dc"; 8663db6d3baSThierry Reding 8673db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 8683db6d3baSThierry Reding 8693db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8703db6d3baSThierry Reding nvidia,head = <3>; 8713db6d3baSThierry Reding }; 8723db6d3baSThierry Reding }; 8733db6d3baSThierry Reding 8748d424ec2SThierry Reding vic@15340000 { 8758d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 8768d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 8778d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 8788d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 8798d424ec2SThierry Reding clock-names = "vic"; 8808d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 8818d424ec2SThierry Reding reset-names = "vic"; 8828d424ec2SThierry Reding 8838d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 8848d424ec2SThierry Reding }; 8858d424ec2SThierry Reding 8863db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 8873db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 8883db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 8893db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 8903db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 8913db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 8923db6d3baSThierry Reding clock-names = "dpaux", "parent"; 8933db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 8943db6d3baSThierry Reding reset-names = "dpaux"; 8953db6d3baSThierry Reding status = "disabled"; 8963db6d3baSThierry Reding 8973db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8983db6d3baSThierry Reding 8993db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 9003db6d3baSThierry Reding groups = "dpaux-io"; 9013db6d3baSThierry Reding function = "aux"; 9023db6d3baSThierry Reding }; 9033db6d3baSThierry Reding 9043db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 9053db6d3baSThierry Reding groups = "dpaux-io"; 9063db6d3baSThierry Reding function = "i2c"; 9073db6d3baSThierry Reding }; 9083db6d3baSThierry Reding 9093db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 9103db6d3baSThierry Reding groups = "dpaux-io"; 9113db6d3baSThierry Reding function = "off"; 9123db6d3baSThierry Reding }; 9133db6d3baSThierry Reding 9143db6d3baSThierry Reding i2c-bus { 9153db6d3baSThierry Reding #address-cells = <1>; 9163db6d3baSThierry Reding #size-cells = <0>; 9173db6d3baSThierry Reding }; 9183db6d3baSThierry Reding }; 9193db6d3baSThierry Reding 9203db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 9213db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9223db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 9233db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 9243db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 9253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9263db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9273db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 9283db6d3baSThierry Reding reset-names = "dpaux"; 9293db6d3baSThierry Reding status = "disabled"; 9303db6d3baSThierry Reding 9313db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9323db6d3baSThierry Reding 9333db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 9343db6d3baSThierry Reding groups = "dpaux-io"; 9353db6d3baSThierry Reding function = "aux"; 9363db6d3baSThierry Reding }; 9373db6d3baSThierry Reding 9383db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 9393db6d3baSThierry Reding groups = "dpaux-io"; 9403db6d3baSThierry Reding function = "i2c"; 9413db6d3baSThierry Reding }; 9423db6d3baSThierry Reding 9433db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 9443db6d3baSThierry Reding groups = "dpaux-io"; 9453db6d3baSThierry Reding function = "off"; 9463db6d3baSThierry Reding }; 9473db6d3baSThierry Reding 9483db6d3baSThierry Reding i2c-bus { 9493db6d3baSThierry Reding #address-cells = <1>; 9503db6d3baSThierry Reding #size-cells = <0>; 9513db6d3baSThierry Reding }; 9523db6d3baSThierry Reding }; 9533db6d3baSThierry Reding 9543db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 9553db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9563db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 9573db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 9583db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 9593db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9603db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9613db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 9623db6d3baSThierry Reding reset-names = "dpaux"; 9633db6d3baSThierry Reding status = "disabled"; 9643db6d3baSThierry Reding 9653db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9663db6d3baSThierry Reding 9673db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 9683db6d3baSThierry Reding groups = "dpaux-io"; 9693db6d3baSThierry Reding function = "aux"; 9703db6d3baSThierry Reding }; 9713db6d3baSThierry Reding 9723db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 9733db6d3baSThierry Reding groups = "dpaux-io"; 9743db6d3baSThierry Reding function = "i2c"; 9753db6d3baSThierry Reding }; 9763db6d3baSThierry Reding 9773db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 9783db6d3baSThierry Reding groups = "dpaux-io"; 9793db6d3baSThierry Reding function = "off"; 9803db6d3baSThierry Reding }; 9813db6d3baSThierry Reding 9823db6d3baSThierry Reding i2c-bus { 9833db6d3baSThierry Reding #address-cells = <1>; 9843db6d3baSThierry Reding #size-cells = <0>; 9853db6d3baSThierry Reding }; 9863db6d3baSThierry Reding }; 9873db6d3baSThierry Reding 9883db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 9893db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9903db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 9913db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 9923db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 9933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9943db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9953db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 9963db6d3baSThierry Reding reset-names = "dpaux"; 9973db6d3baSThierry Reding status = "disabled"; 9983db6d3baSThierry Reding 9993db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10003db6d3baSThierry Reding 10013db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 10023db6d3baSThierry Reding groups = "dpaux-io"; 10033db6d3baSThierry Reding function = "aux"; 10043db6d3baSThierry Reding }; 10053db6d3baSThierry Reding 10063db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 10073db6d3baSThierry Reding groups = "dpaux-io"; 10083db6d3baSThierry Reding function = "i2c"; 10093db6d3baSThierry Reding }; 10103db6d3baSThierry Reding 10113db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 10123db6d3baSThierry Reding groups = "dpaux-io"; 10133db6d3baSThierry Reding function = "off"; 10143db6d3baSThierry Reding }; 10153db6d3baSThierry Reding 10163db6d3baSThierry Reding i2c-bus { 10173db6d3baSThierry Reding #address-cells = <1>; 10183db6d3baSThierry Reding #size-cells = <0>; 10193db6d3baSThierry Reding }; 10203db6d3baSThierry Reding }; 10213db6d3baSThierry Reding 10223db6d3baSThierry Reding sor0: sor@15b00000 { 10233db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 10243db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 10253db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 10263db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 10273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 10283db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 10293db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 10303db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 10313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 10323db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 10333db6d3baSThierry Reding "pad"; 10343db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 10353db6d3baSThierry Reding reset-names = "sor"; 10363db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 10373db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 10383db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 10393db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 10403db6d3baSThierry Reding status = "disabled"; 10413db6d3baSThierry Reding 10423db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10433db6d3baSThierry Reding nvidia,interface = <0>; 10443db6d3baSThierry Reding }; 10453db6d3baSThierry Reding 10463db6d3baSThierry Reding sor1: sor@15b40000 { 10473db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 10483db6d3baSThierry Reding reg = <0x155c0000 0x40000>; 10493db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 10503db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 10513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 10523db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 10533db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 10543db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 10553db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 10563db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 10573db6d3baSThierry Reding "pad"; 10583db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 10593db6d3baSThierry Reding reset-names = "sor"; 10603db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 10613db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 10623db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 10633db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 10643db6d3baSThierry Reding status = "disabled"; 10653db6d3baSThierry Reding 10663db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10673db6d3baSThierry Reding nvidia,interface = <1>; 10683db6d3baSThierry Reding }; 10693db6d3baSThierry Reding 10703db6d3baSThierry Reding sor2: sor@15b80000 { 10713db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 10723db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 10733db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 10743db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 10753db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 10763db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 10773db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 10783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 10793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 10803db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 10813db6d3baSThierry Reding "pad"; 10823db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 10833db6d3baSThierry Reding reset-names = "sor"; 10843db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 10853db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 10863db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 10873db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 10883db6d3baSThierry Reding status = "disabled"; 10893db6d3baSThierry Reding 10903db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10913db6d3baSThierry Reding nvidia,interface = <2>; 10923db6d3baSThierry Reding }; 10933db6d3baSThierry Reding 10943db6d3baSThierry Reding sor3: sor@15bc0000 { 10953db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 10963db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 10973db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 10983db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 10993db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 11003db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 11013db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11023db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11033db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 11043db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11053db6d3baSThierry Reding "pad"; 11063db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 11073db6d3baSThierry Reding reset-names = "sor"; 11083db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 11093db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 11103db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 11113db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11123db6d3baSThierry Reding status = "disabled"; 11133db6d3baSThierry Reding 11143db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11153db6d3baSThierry Reding nvidia,interface = <3>; 11163db6d3baSThierry Reding }; 11173db6d3baSThierry Reding }; 11185425fb15SMikko Perttunen }; 11195425fb15SMikko Perttunen 11202602c32fSVidya Sagar pcie@14100000 { 11212602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 11222602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 11232602c32fSVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 11242602c32fSVidya Sagar 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 11252602c32fSVidya Sagar 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 11262602c32fSVidya Sagar 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 11272602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 11282602c32fSVidya Sagar 11292602c32fSVidya Sagar status = "disabled"; 11302602c32fSVidya Sagar 11312602c32fSVidya Sagar #address-cells = <3>; 11322602c32fSVidya Sagar #size-cells = <2>; 11332602c32fSVidya Sagar device_type = "pci"; 11342602c32fSVidya Sagar num-lanes = <1>; 11352602c32fSVidya Sagar num-viewport = <8>; 11362602c32fSVidya Sagar linux,pci-domain = <1>; 11372602c32fSVidya Sagar 11382602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 11392602c32fSVidya Sagar clock-names = "core"; 11402602c32fSVidya Sagar 11412602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 11422602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 11432602c32fSVidya Sagar reset-names = "apb", "core"; 11442602c32fSVidya Sagar 11452602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 11462602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 11472602c32fSVidya Sagar interrupt-names = "intr", "msi"; 11482602c32fSVidya Sagar 11492602c32fSVidya Sagar #interrupt-cells = <1>; 11502602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 11512602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 11522602c32fSVidya Sagar 11532602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 11542602c32fSVidya Sagar 11552602c32fSVidya Sagar supports-clkreq; 11562602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 11572602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 11582602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 11592602c32fSVidya Sagar 11602602c32fSVidya Sagar bus-range = <0x0 0xff>; 11612602c32fSVidya Sagar ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 11622602c32fSVidya Sagar 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 11632602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 11642602c32fSVidya Sagar }; 11652602c32fSVidya Sagar 11662602c32fSVidya Sagar pcie@14120000 { 11672602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 11682602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 11692602c32fSVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 11702602c32fSVidya Sagar 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 11712602c32fSVidya Sagar 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 11722602c32fSVidya Sagar 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 11732602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 11742602c32fSVidya Sagar 11752602c32fSVidya Sagar status = "disabled"; 11762602c32fSVidya Sagar 11772602c32fSVidya Sagar #address-cells = <3>; 11782602c32fSVidya Sagar #size-cells = <2>; 11792602c32fSVidya Sagar device_type = "pci"; 11802602c32fSVidya Sagar num-lanes = <1>; 11812602c32fSVidya Sagar num-viewport = <8>; 11822602c32fSVidya Sagar linux,pci-domain = <2>; 11832602c32fSVidya Sagar 11842602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 11852602c32fSVidya Sagar clock-names = "core"; 11862602c32fSVidya Sagar 11872602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 11882602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 11892602c32fSVidya Sagar reset-names = "apb", "core"; 11902602c32fSVidya Sagar 11912602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 11922602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 11932602c32fSVidya Sagar interrupt-names = "intr", "msi"; 11942602c32fSVidya Sagar 11952602c32fSVidya Sagar #interrupt-cells = <1>; 11962602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 11972602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 11982602c32fSVidya Sagar 11992602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 12002602c32fSVidya Sagar 12012602c32fSVidya Sagar supports-clkreq; 12022602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12032602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12042602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12052602c32fSVidya Sagar 12062602c32fSVidya Sagar bus-range = <0x0 0xff>; 12072602c32fSVidya Sagar ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12082602c32fSVidya Sagar 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12092602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12102602c32fSVidya Sagar }; 12112602c32fSVidya Sagar 12122602c32fSVidya Sagar pcie@14140000 { 12132602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12142602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 12152602c32fSVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 12162602c32fSVidya Sagar 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 12172602c32fSVidya Sagar 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12182602c32fSVidya Sagar 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12192602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12202602c32fSVidya Sagar 12212602c32fSVidya Sagar status = "disabled"; 12222602c32fSVidya Sagar 12232602c32fSVidya Sagar #address-cells = <3>; 12242602c32fSVidya Sagar #size-cells = <2>; 12252602c32fSVidya Sagar device_type = "pci"; 12262602c32fSVidya Sagar num-lanes = <1>; 12272602c32fSVidya Sagar num-viewport = <8>; 12282602c32fSVidya Sagar linux,pci-domain = <3>; 12292602c32fSVidya Sagar 12302602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 12312602c32fSVidya Sagar clock-names = "core"; 12322602c32fSVidya Sagar 12332602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 12342602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 12352602c32fSVidya Sagar reset-names = "apb", "core"; 12362602c32fSVidya Sagar 12372602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12382602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12392602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12402602c32fSVidya Sagar 12412602c32fSVidya Sagar #interrupt-cells = <1>; 12422602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12432602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 12442602c32fSVidya Sagar 12452602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 12462602c32fSVidya Sagar 12472602c32fSVidya Sagar supports-clkreq; 12482602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12492602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12502602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12512602c32fSVidya Sagar 12522602c32fSVidya Sagar bus-range = <0x0 0xff>; 12532602c32fSVidya Sagar ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12542602c32fSVidya Sagar 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12552602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12562602c32fSVidya Sagar }; 12572602c32fSVidya Sagar 12582602c32fSVidya Sagar pcie@14160000 { 12592602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12602602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 12612602c32fSVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 12622602c32fSVidya Sagar 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 12632602c32fSVidya Sagar 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12642602c32fSVidya Sagar 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12652602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12662602c32fSVidya Sagar 12672602c32fSVidya Sagar status = "disabled"; 12682602c32fSVidya Sagar 12692602c32fSVidya Sagar #address-cells = <3>; 12702602c32fSVidya Sagar #size-cells = <2>; 12712602c32fSVidya Sagar device_type = "pci"; 12722602c32fSVidya Sagar num-lanes = <4>; 12732602c32fSVidya Sagar num-viewport = <8>; 12742602c32fSVidya Sagar linux,pci-domain = <4>; 12752602c32fSVidya Sagar 12762602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 12772602c32fSVidya Sagar clock-names = "core"; 12782602c32fSVidya Sagar 12792602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 12802602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 12812602c32fSVidya Sagar reset-names = "apb", "core"; 12822602c32fSVidya Sagar 12832602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12842602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12852602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12862602c32fSVidya Sagar 12872602c32fSVidya Sagar #interrupt-cells = <1>; 12882602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12892602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 12902602c32fSVidya Sagar 12912602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 12922602c32fSVidya Sagar 12932602c32fSVidya Sagar supports-clkreq; 12942602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12952602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12962602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12972602c32fSVidya Sagar 12982602c32fSVidya Sagar bus-range = <0x0 0xff>; 12992602c32fSVidya Sagar ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13002602c32fSVidya Sagar 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13012602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13022602c32fSVidya Sagar }; 13032602c32fSVidya Sagar 13042602c32fSVidya Sagar pcie@14180000 { 13052602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13062602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 13072602c32fSVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 13082602c32fSVidya Sagar 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 13092602c32fSVidya Sagar 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13102602c32fSVidya Sagar 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13112602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13122602c32fSVidya Sagar 13132602c32fSVidya Sagar status = "disabled"; 13142602c32fSVidya Sagar 13152602c32fSVidya Sagar #address-cells = <3>; 13162602c32fSVidya Sagar #size-cells = <2>; 13172602c32fSVidya Sagar device_type = "pci"; 13182602c32fSVidya Sagar num-lanes = <8>; 13192602c32fSVidya Sagar num-viewport = <8>; 13202602c32fSVidya Sagar linux,pci-domain = <0>; 13212602c32fSVidya Sagar 13222602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 13232602c32fSVidya Sagar clock-names = "core"; 13242602c32fSVidya Sagar 13252602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 13262602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 13272602c32fSVidya Sagar reset-names = "apb", "core"; 13282602c32fSVidya Sagar 13292602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13302602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13312602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13322602c32fSVidya Sagar 13332602c32fSVidya Sagar #interrupt-cells = <1>; 13342602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13352602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 13362602c32fSVidya Sagar 13372602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 13382602c32fSVidya Sagar 13392602c32fSVidya Sagar supports-clkreq; 13402602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13412602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13422602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13432602c32fSVidya Sagar 13442602c32fSVidya Sagar bus-range = <0x0 0xff>; 13452602c32fSVidya Sagar ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13462602c32fSVidya Sagar 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13472602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13482602c32fSVidya Sagar }; 13492602c32fSVidya Sagar 13502602c32fSVidya Sagar pcie@141a0000 { 13512602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13522602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 13532602c32fSVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 13542602c32fSVidya Sagar 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 13552602c32fSVidya Sagar 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13562602c32fSVidya Sagar 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13572602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13582602c32fSVidya Sagar 13592602c32fSVidya Sagar status = "disabled"; 13602602c32fSVidya Sagar 13612602c32fSVidya Sagar #address-cells = <3>; 13622602c32fSVidya Sagar #size-cells = <2>; 13632602c32fSVidya Sagar device_type = "pci"; 13642602c32fSVidya Sagar num-lanes = <8>; 13652602c32fSVidya Sagar num-viewport = <8>; 13662602c32fSVidya Sagar linux,pci-domain = <5>; 13672602c32fSVidya Sagar 13682602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 13692602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 13702602c32fSVidya Sagar clock-names = "core", "core_m"; 13712602c32fSVidya Sagar 13722602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 13732602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 13742602c32fSVidya Sagar reset-names = "apb", "core"; 13752602c32fSVidya Sagar 13762602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13772602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13782602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13792602c32fSVidya Sagar 13802602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 13812602c32fSVidya Sagar 13822602c32fSVidya Sagar #interrupt-cells = <1>; 13832602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13842602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 13852602c32fSVidya Sagar 13862602c32fSVidya Sagar supports-clkreq; 13872602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13882602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13892602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13902602c32fSVidya Sagar 13912602c32fSVidya Sagar bus-range = <0x0 0xff>; 13922602c32fSVidya Sagar ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13932602c32fSVidya Sagar 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13942602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13952602c32fSVidya Sagar }; 13962602c32fSVidya Sagar 13975425fb15SMikko Perttunen sysram@40000000 { 13985425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 13995425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 14005425fb15SMikko Perttunen #address-cells = <1>; 14015425fb15SMikko Perttunen #size-cells = <1>; 14025425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 14035425fb15SMikko Perttunen 14045425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 14055425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 14065425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 14075425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 14085425fb15SMikko Perttunen pool; 14095425fb15SMikko Perttunen }; 14105425fb15SMikko Perttunen 14115425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 14125425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 14135425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 14145425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 14155425fb15SMikko Perttunen pool; 14165425fb15SMikko Perttunen }; 14175425fb15SMikko Perttunen }; 14185425fb15SMikko Perttunen 14195425fb15SMikko Perttunen bpmp: bpmp { 14205425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 14215425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 14225425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 14235425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 14245425fb15SMikko Perttunen #clock-cells = <1>; 14255425fb15SMikko Perttunen #reset-cells = <1>; 14265425fb15SMikko Perttunen #power-domain-cells = <1>; 14275425fb15SMikko Perttunen 14285425fb15SMikko Perttunen bpmp_i2c: i2c { 14295425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 14305425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 14315425fb15SMikko Perttunen #address-cells = <1>; 14325425fb15SMikko Perttunen #size-cells = <0>; 14335425fb15SMikko Perttunen }; 14345425fb15SMikko Perttunen 14355425fb15SMikko Perttunen bpmp_thermal: thermal { 14365425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 14375425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 14385425fb15SMikko Perttunen }; 14395425fb15SMikko Perttunen }; 14405425fb15SMikko Perttunen 14417780a034SMikko Perttunen cpus { 14427780a034SMikko Perttunen #address-cells = <1>; 14437780a034SMikko Perttunen #size-cells = <0>; 14447780a034SMikko Perttunen 14457780a034SMikko Perttunen cpu@0 { 144631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14477780a034SMikko Perttunen device_type = "cpu"; 14487780a034SMikko Perttunen reg = <0x10000>; 14497780a034SMikko Perttunen enable-method = "psci"; 14507780a034SMikko Perttunen }; 14517780a034SMikko Perttunen 14527780a034SMikko Perttunen cpu@1 { 145331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14547780a034SMikko Perttunen device_type = "cpu"; 14557780a034SMikko Perttunen reg = <0x10001>; 14567780a034SMikko Perttunen enable-method = "psci"; 14577780a034SMikko Perttunen }; 14587780a034SMikko Perttunen 14597780a034SMikko Perttunen cpu@2 { 146031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14617780a034SMikko Perttunen device_type = "cpu"; 14627780a034SMikko Perttunen reg = <0x100>; 14637780a034SMikko Perttunen enable-method = "psci"; 14647780a034SMikko Perttunen }; 14657780a034SMikko Perttunen 14667780a034SMikko Perttunen cpu@3 { 146731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14687780a034SMikko Perttunen device_type = "cpu"; 14697780a034SMikko Perttunen reg = <0x101>; 14707780a034SMikko Perttunen enable-method = "psci"; 14717780a034SMikko Perttunen }; 14727780a034SMikko Perttunen 14737780a034SMikko Perttunen cpu@4 { 147431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14757780a034SMikko Perttunen device_type = "cpu"; 14767780a034SMikko Perttunen reg = <0x200>; 14777780a034SMikko Perttunen enable-method = "psci"; 14787780a034SMikko Perttunen }; 14797780a034SMikko Perttunen 14807780a034SMikko Perttunen cpu@5 { 148131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14827780a034SMikko Perttunen device_type = "cpu"; 14837780a034SMikko Perttunen reg = <0x201>; 14847780a034SMikko Perttunen enable-method = "psci"; 14857780a034SMikko Perttunen }; 14867780a034SMikko Perttunen 14877780a034SMikko Perttunen cpu@6 { 148831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14897780a034SMikko Perttunen device_type = "cpu"; 14907780a034SMikko Perttunen reg = <0x10300>; 14917780a034SMikko Perttunen enable-method = "psci"; 14927780a034SMikko Perttunen }; 14937780a034SMikko Perttunen 14947780a034SMikko Perttunen cpu@7 { 149531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14967780a034SMikko Perttunen device_type = "cpu"; 14977780a034SMikko Perttunen reg = <0x10301>; 14987780a034SMikko Perttunen enable-method = "psci"; 14997780a034SMikko Perttunen }; 15007780a034SMikko Perttunen }; 15017780a034SMikko Perttunen 15027780a034SMikko Perttunen psci { 15037780a034SMikko Perttunen compatible = "arm,psci-1.0"; 15047780a034SMikko Perttunen status = "okay"; 15057780a034SMikko Perttunen method = "smc"; 15067780a034SMikko Perttunen }; 15077780a034SMikko Perttunen 1508a38570c2SMikko Perttunen tcu: tcu { 1509a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 1510a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1511a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1512a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 1513a38570c2SMikko Perttunen }; 1514a38570c2SMikko Perttunen 1515686ba009SThierry Reding thermal-zones { 1516686ba009SThierry Reding cpu { 1517686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1518686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1519686ba009SThierry Reding status = "disabled"; 1520686ba009SThierry Reding }; 1521686ba009SThierry Reding 1522686ba009SThierry Reding gpu { 1523686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1524686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1525686ba009SThierry Reding status = "disabled"; 1526686ba009SThierry Reding }; 1527686ba009SThierry Reding 1528686ba009SThierry Reding aux { 1529686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1530686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1531686ba009SThierry Reding status = "disabled"; 1532686ba009SThierry Reding }; 1533686ba009SThierry Reding 1534686ba009SThierry Reding pllx { 1535686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1536686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1537686ba009SThierry Reding status = "disabled"; 1538686ba009SThierry Reding }; 1539686ba009SThierry Reding 1540686ba009SThierry Reding ao { 1541686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1542686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 1543686ba009SThierry Reding status = "disabled"; 1544686ba009SThierry Reding }; 1545686ba009SThierry Reding 1546686ba009SThierry Reding tj { 1547686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1548686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1549686ba009SThierry Reding status = "disabled"; 1550686ba009SThierry Reding }; 1551686ba009SThierry Reding }; 1552686ba009SThierry Reding 15535425fb15SMikko Perttunen timer { 15545425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 15555425fb15SMikko Perttunen interrupts = <GIC_PPI 13 15565425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 15575425fb15SMikko Perttunen <GIC_PPI 14 15585425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 15595425fb15SMikko Perttunen <GIC_PPI 11 15605425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 15615425fb15SMikko Perttunen <GIC_PPI 10 15625425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 15635425fb15SMikko Perttunen interrupt-parent = <&gic>; 1564b30be673SThierry Reding always-on; 15655425fb15SMikko Perttunen }; 15665425fb15SMikko Perttunen}; 1567