15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 105425fb15SMikko Perttunen 115425fb15SMikko Perttunen/ { 125425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 135425fb15SMikko Perttunen interrupt-parent = <&gic>; 145425fb15SMikko Perttunen #address-cells = <2>; 155425fb15SMikko Perttunen #size-cells = <2>; 165425fb15SMikko Perttunen 175425fb15SMikko Perttunen /* control backbone */ 18eef97c2aSThierry Reding cbb@0 { 195425fb15SMikko Perttunen compatible = "simple-bus"; 205425fb15SMikko Perttunen #address-cells = <1>; 215425fb15SMikko Perttunen #size-cells = <1>; 225425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 235425fb15SMikko Perttunen 24f69ce393SMikko Perttunen gpio: gpio@2200000 { 25f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 26f69ce393SMikko Perttunen reg-names = "security", "gpio"; 27f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 28f69ce393SMikko Perttunen <0x2210000 0x10000>; 29f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 30f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 31f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 32f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 33f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 34f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 35f69ce393SMikko Perttunen #interrupt-cells = <2>; 36f69ce393SMikko Perttunen interrupt-controller; 37f69ce393SMikko Perttunen #gpio-cells = <2>; 38f69ce393SMikko Perttunen gpio-controller; 39f69ce393SMikko Perttunen }; 40f69ce393SMikko Perttunen 41f89b58ceSMikko Perttunen ethernet@2490000 { 4219dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 4319dc772aSThierry Reding "nvidia,tegra186-eqos", 44f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 45f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 46f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 47f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 48f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 49f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 50f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 51f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 52f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 53f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 54f89b58ceSMikko Perttunen reset-names = "eqos"; 55f89b58ceSMikko Perttunen status = "disabled"; 56f89b58ceSMikko Perttunen 57f89b58ceSMikko Perttunen snps,write-requests = <1>; 58f89b58ceSMikko Perttunen snps,read-requests = <3>; 59f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 60f89b58ceSMikko Perttunen snps,txpbl = <16>; 61f89b58ceSMikko Perttunen snps,rxpbl = <8>; 62f89b58ceSMikko Perttunen }; 63f89b58ceSMikko Perttunen 641aaa7698SThierry Reding aconnect@2900000 { 655d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 665d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 675d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 685d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 695d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 705d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 715d2249ddSSameer Pujar #address-cells = <1>; 725d2249ddSSameer Pujar #size-cells = <1>; 735d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 745d2249ddSSameer Pujar status = "disabled"; 755d2249ddSSameer Pujar 765d2249ddSSameer Pujar dma-controller@2930000 { 775d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 785d2249ddSSameer Pujar "nvidia,tegra186-adma"; 795d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 805d2249ddSSameer Pujar interrupt-parent = <&agic>; 815d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 825d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 835d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 845d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 855d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 865d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 875d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 885d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 895d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1135d2249ddSSameer Pujar #dma-cells = <1>; 1145d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1155d2249ddSSameer Pujar clock-names = "d_audio"; 1165d2249ddSSameer Pujar status = "disabled"; 1175d2249ddSSameer Pujar }; 1185d2249ddSSameer Pujar 1195d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1205d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1215d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1225d2249ddSSameer Pujar #interrupt-cells = <3>; 1235d2249ddSSameer Pujar interrupt-controller; 1245d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1255d2249ddSSameer Pujar <0x02a42000 0x2000>; 1265d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1275d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1285d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1295d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1305d2249ddSSameer Pujar clock-names = "clk"; 1315d2249ddSSameer Pujar status = "disabled"; 1325d2249ddSSameer Pujar }; 1335d2249ddSSameer Pujar }; 1345d2249ddSSameer Pujar 135dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 136dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 137dbb72e2cSVidya Sagar reg = <0x2430000 0x17000 138dbb72e2cSVidya Sagar 0xc300000 0x4000>; 139dbb72e2cSVidya Sagar 140dbb72e2cSVidya Sagar status = "okay"; 141dbb72e2cSVidya Sagar 142dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 143dbb72e2cSVidya Sagar pex_rst { 144dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 145dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 146dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 147dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 148dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 149dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 150dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 151dbb72e2cSVidya Sagar }; 152dbb72e2cSVidya Sagar }; 153dbb72e2cSVidya Sagar 154dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 155dbb72e2cSVidya Sagar clkreq { 156dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 157dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 158dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 159dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 160dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 161dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 162dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163dbb72e2cSVidya Sagar }; 164dbb72e2cSVidya Sagar }; 165dbb72e2cSVidya Sagar }; 166dbb72e2cSVidya Sagar 1675425fb15SMikko Perttunen uarta: serial@3100000 { 1685425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1695425fb15SMikko Perttunen reg = <0x03100000 0x40>; 1705425fb15SMikko Perttunen reg-shift = <2>; 1715425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1725425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 1735425fb15SMikko Perttunen clock-names = "serial"; 1745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 1755425fb15SMikko Perttunen reset-names = "serial"; 1765425fb15SMikko Perttunen status = "disabled"; 1775425fb15SMikko Perttunen }; 1785425fb15SMikko Perttunen 1795425fb15SMikko Perttunen uartb: serial@3110000 { 1805425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1815425fb15SMikko Perttunen reg = <0x03110000 0x40>; 1825425fb15SMikko Perttunen reg-shift = <2>; 1835425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1845425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 1855425fb15SMikko Perttunen clock-names = "serial"; 1865425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 1875425fb15SMikko Perttunen reset-names = "serial"; 1885425fb15SMikko Perttunen status = "disabled"; 1895425fb15SMikko Perttunen }; 1905425fb15SMikko Perttunen 1915425fb15SMikko Perttunen uartd: serial@3130000 { 1925425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1935425fb15SMikko Perttunen reg = <0x03130000 0x40>; 1945425fb15SMikko Perttunen reg-shift = <2>; 1955425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1965425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 1975425fb15SMikko Perttunen clock-names = "serial"; 1985425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 1995425fb15SMikko Perttunen reset-names = "serial"; 2005425fb15SMikko Perttunen status = "disabled"; 2015425fb15SMikko Perttunen }; 2025425fb15SMikko Perttunen 2035425fb15SMikko Perttunen uarte: serial@3140000 { 2045425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2055425fb15SMikko Perttunen reg = <0x03140000 0x40>; 2065425fb15SMikko Perttunen reg-shift = <2>; 2075425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 2095425fb15SMikko Perttunen clock-names = "serial"; 2105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 2115425fb15SMikko Perttunen reset-names = "serial"; 2125425fb15SMikko Perttunen status = "disabled"; 2135425fb15SMikko Perttunen }; 2145425fb15SMikko Perttunen 2155425fb15SMikko Perttunen uartf: serial@3150000 { 2165425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2175425fb15SMikko Perttunen reg = <0x03150000 0x40>; 2185425fb15SMikko Perttunen reg-shift = <2>; 2195425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2205425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 2215425fb15SMikko Perttunen clock-names = "serial"; 2225425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 2235425fb15SMikko Perttunen reset-names = "serial"; 2245425fb15SMikko Perttunen status = "disabled"; 2255425fb15SMikko Perttunen }; 2265425fb15SMikko Perttunen 2275425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 228d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2295425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 2305425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2315425fb15SMikko Perttunen #address-cells = <1>; 2325425fb15SMikko Perttunen #size-cells = <0>; 2335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2345425fb15SMikko Perttunen clock-names = "div-clk"; 2355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2365425fb15SMikko Perttunen reset-names = "i2c"; 2375425fb15SMikko Perttunen status = "disabled"; 2385425fb15SMikko Perttunen }; 2395425fb15SMikko Perttunen 2405425fb15SMikko Perttunen uarth: serial@3170000 { 2415425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2425425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2435425fb15SMikko Perttunen reg-shift = <2>; 2445425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 2465425fb15SMikko Perttunen clock-names = "serial"; 2475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 2485425fb15SMikko Perttunen reset-names = "serial"; 2495425fb15SMikko Perttunen status = "disabled"; 2505425fb15SMikko Perttunen }; 2515425fb15SMikko Perttunen 2525425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 253d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2545425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 2555425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2565425fb15SMikko Perttunen #address-cells = <1>; 2575425fb15SMikko Perttunen #size-cells = <0>; 2585425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 2595425fb15SMikko Perttunen clock-names = "div-clk"; 2605425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 2615425fb15SMikko Perttunen reset-names = "i2c"; 2625425fb15SMikko Perttunen status = "disabled"; 2635425fb15SMikko Perttunen }; 2645425fb15SMikko Perttunen 2655425fb15SMikko Perttunen /* shares pads with dpaux1 */ 2665425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 267d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2685425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 2695425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2705425fb15SMikko Perttunen #address-cells = <1>; 2715425fb15SMikko Perttunen #size-cells = <0>; 2725425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 2735425fb15SMikko Perttunen clock-names = "div-clk"; 2745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 2755425fb15SMikko Perttunen reset-names = "i2c"; 2765425fb15SMikko Perttunen status = "disabled"; 2775425fb15SMikko Perttunen }; 2785425fb15SMikko Perttunen 2795425fb15SMikko Perttunen /* shares pads with dpaux0 */ 2805425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 281d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2825425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 2835425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2845425fb15SMikko Perttunen #address-cells = <1>; 2855425fb15SMikko Perttunen #size-cells = <0>; 2865425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 2875425fb15SMikko Perttunen clock-names = "div-clk"; 2885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 2895425fb15SMikko Perttunen reset-names = "i2c"; 2905425fb15SMikko Perttunen status = "disabled"; 2915425fb15SMikko Perttunen }; 2925425fb15SMikko Perttunen 2935425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 294d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2955425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 2965425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2975425fb15SMikko Perttunen #address-cells = <1>; 2985425fb15SMikko Perttunen #size-cells = <0>; 2995425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 3005425fb15SMikko Perttunen clock-names = "div-clk"; 3015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 3025425fb15SMikko Perttunen reset-names = "i2c"; 3035425fb15SMikko Perttunen status = "disabled"; 3045425fb15SMikko Perttunen }; 3055425fb15SMikko Perttunen 3065425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 307d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3085425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 3095425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3105425fb15SMikko Perttunen #address-cells = <1>; 3115425fb15SMikko Perttunen #size-cells = <0>; 3125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 3135425fb15SMikko Perttunen clock-names = "div-clk"; 3145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 3155425fb15SMikko Perttunen reset-names = "i2c"; 3165425fb15SMikko Perttunen status = "disabled"; 3175425fb15SMikko Perttunen }; 3185425fb15SMikko Perttunen 3196a574ec7SThierry Reding pwm1: pwm@3280000 { 3206a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3216a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3226a574ec7SThierry Reding reg = <0x3280000 0x10000>; 3236a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 3246a574ec7SThierry Reding clock-names = "pwm"; 3256a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 3266a574ec7SThierry Reding reset-names = "pwm"; 3276a574ec7SThierry Reding status = "disabled"; 3286a574ec7SThierry Reding #pwm-cells = <2>; 3296a574ec7SThierry Reding }; 3306a574ec7SThierry Reding 3316a574ec7SThierry Reding pwm2: pwm@3290000 { 3326a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3336a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3346a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3356a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3366a574ec7SThierry Reding clock-names = "pwm"; 3376a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3386a574ec7SThierry Reding reset-names = "pwm"; 3396a574ec7SThierry Reding status = "disabled"; 3406a574ec7SThierry Reding #pwm-cells = <2>; 3416a574ec7SThierry Reding }; 3426a574ec7SThierry Reding 3436a574ec7SThierry Reding pwm3: pwm@32a0000 { 3446a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3456a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3466a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 3476a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 3486a574ec7SThierry Reding clock-names = "pwm"; 3496a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 3506a574ec7SThierry Reding reset-names = "pwm"; 3516a574ec7SThierry Reding status = "disabled"; 3526a574ec7SThierry Reding #pwm-cells = <2>; 3536a574ec7SThierry Reding }; 3546a574ec7SThierry Reding 3556a574ec7SThierry Reding pwm5: pwm@32c0000 { 3566a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3576a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3586a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 3596a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 3606a574ec7SThierry Reding clock-names = "pwm"; 3616a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 3626a574ec7SThierry Reding reset-names = "pwm"; 3636a574ec7SThierry Reding status = "disabled"; 3646a574ec7SThierry Reding #pwm-cells = <2>; 3656a574ec7SThierry Reding }; 3666a574ec7SThierry Reding 3676a574ec7SThierry Reding pwm6: pwm@32d0000 { 3686a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3696a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3706a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 3716a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 3726a574ec7SThierry Reding clock-names = "pwm"; 3736a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 3746a574ec7SThierry Reding reset-names = "pwm"; 3756a574ec7SThierry Reding status = "disabled"; 3766a574ec7SThierry Reding #pwm-cells = <2>; 3776a574ec7SThierry Reding }; 3786a574ec7SThierry Reding 3796a574ec7SThierry Reding pwm7: pwm@32e0000 { 3806a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3816a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3826a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 3836a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 3846a574ec7SThierry Reding clock-names = "pwm"; 3856a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 3866a574ec7SThierry Reding reset-names = "pwm"; 3876a574ec7SThierry Reding status = "disabled"; 3886a574ec7SThierry Reding #pwm-cells = <2>; 3896a574ec7SThierry Reding }; 3906a574ec7SThierry Reding 3916a574ec7SThierry Reding pwm8: pwm@32f0000 { 3926a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3936a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3946a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 3956a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 3966a574ec7SThierry Reding clock-names = "pwm"; 3976a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 3986a574ec7SThierry Reding reset-names = "pwm"; 3996a574ec7SThierry Reding status = "disabled"; 4006a574ec7SThierry Reding #pwm-cells = <2>; 4016a574ec7SThierry Reding }; 4026a574ec7SThierry Reding 4035425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 4045425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4055425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 4065425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 4075425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 4085425fb15SMikko Perttunen clock-names = "sdhci"; 4095425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 4105425fb15SMikko Perttunen reset-names = "sdhci"; 4114e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 4124e0f1229SSowjanya Komatineni <0x07>; 4134e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4144e0f1229SSowjanya Komatineni <0x07>; 4154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4174e0f1229SSowjanya Komatineni <0x07>; 4184e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4194e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4204e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4214e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4225425fb15SMikko Perttunen status = "disabled"; 4235425fb15SMikko Perttunen }; 4245425fb15SMikko Perttunen 4255425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 4265425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4275425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 4285425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 4295425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 4305425fb15SMikko Perttunen clock-names = "sdhci"; 4315425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 4325425fb15SMikko Perttunen reset-names = "sdhci"; 4334e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 4364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4374e0f1229SSowjanya Komatineni <0x07>; 4384e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4404e0f1229SSowjanya Komatineni <0x07>; 4414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4434e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4444e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4455425fb15SMikko Perttunen status = "disabled"; 4465425fb15SMikko Perttunen }; 4475425fb15SMikko Perttunen 4485425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 4495425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4505425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 4515425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 4525425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 4535425fb15SMikko Perttunen clock-names = "sdhci"; 454351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 455351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 456351648d0SSowjanya Komatineni assigned-clock-parents = 457351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 4585425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 4595425fb15SMikko Perttunen reset-names = "sdhci"; 4604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 4614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 4624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 4634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4644e0f1229SSowjanya Komatineni <0x0a>; 4654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 4664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4674e0f1229SSowjanya Komatineni <0x0a>; 4684e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 4694e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 4704e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 471dfd3cb6fSSowjanya Komatineni supports-cqe; 4725425fb15SMikko Perttunen status = "disabled"; 4735425fb15SMikko Perttunen }; 4745425fb15SMikko Perttunen 4754878cc0cSSameer Pujar hda@3510000 { 4764878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 4774878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 4784878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4794878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 4804878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 4814878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 4824878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 4834878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 4844878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 4854878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 4864878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 4874878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 4884878cc0cSSameer Pujar status = "disabled"; 4894878cc0cSSameer Pujar }; 4904878cc0cSSameer Pujar 4915425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 4925425fb15SMikko Perttunen compatible = "arm,gic-400"; 4935425fb15SMikko Perttunen #interrupt-cells = <3>; 4945425fb15SMikko Perttunen interrupt-controller; 4955425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 4965425fb15SMikko Perttunen <0x03882000 0x2000>, 4975425fb15SMikko Perttunen <0x03884000 0x2000>, 4985425fb15SMikko Perttunen <0x03886000 0x2000>; 4995425fb15SMikko Perttunen interrupts = <GIC_PPI 9 5005425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 5015425fb15SMikko Perttunen interrupt-parent = <&gic>; 5025425fb15SMikko Perttunen }; 5035425fb15SMikko Perttunen 504badb80beSThierry Reding cec@3960000 { 505badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 506badb80beSThierry Reding reg = <0x03960000 0x10000>; 507badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 508badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 509badb80beSThierry Reding clock-names = "cec"; 510badb80beSThierry Reding status = "disabled"; 511badb80beSThierry Reding }; 512badb80beSThierry Reding 5135425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 514a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 5155425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 516a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 517a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 518a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 519a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 520a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 521a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 522a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 523a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 524a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 525a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 526a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 527a38570c2SMikko Perttunen "shared7"; 528a38570c2SMikko Perttunen #mbox-cells = <2>; 529a38570c2SMikko Perttunen }; 530a38570c2SMikko Perttunen 5312602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 5322602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5332602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 5342602c32fSVidya Sagar reg-names = "ctl"; 5352602c32fSVidya Sagar 5362602c32fSVidya Sagar #phy-cells = <0>; 5372602c32fSVidya Sagar }; 5382602c32fSVidya Sagar 5392602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 5402602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5412602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 5422602c32fSVidya Sagar reg-names = "ctl"; 5432602c32fSVidya Sagar 5442602c32fSVidya Sagar #phy-cells = <0>; 5452602c32fSVidya Sagar }; 5462602c32fSVidya Sagar 5472602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 5482602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5492602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 5502602c32fSVidya Sagar reg-names = "ctl"; 5512602c32fSVidya Sagar 5522602c32fSVidya Sagar #phy-cells = <0>; 5532602c32fSVidya Sagar }; 5542602c32fSVidya Sagar 5552602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 5562602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5572602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 5582602c32fSVidya Sagar reg-names = "ctl"; 5592602c32fSVidya Sagar 5602602c32fSVidya Sagar #phy-cells = <0>; 5612602c32fSVidya Sagar }; 5622602c32fSVidya Sagar 5632602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 5642602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5652602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 5662602c32fSVidya Sagar reg-names = "ctl"; 5672602c32fSVidya Sagar 5682602c32fSVidya Sagar #phy-cells = <0>; 5692602c32fSVidya Sagar }; 5702602c32fSVidya Sagar 5712602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 5722602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5732602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 5742602c32fSVidya Sagar reg-names = "ctl"; 5752602c32fSVidya Sagar 5762602c32fSVidya Sagar #phy-cells = <0>; 5772602c32fSVidya Sagar }; 5782602c32fSVidya Sagar 5792602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 5802602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5812602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 5822602c32fSVidya Sagar reg-names = "ctl"; 5832602c32fSVidya Sagar 5842602c32fSVidya Sagar #phy-cells = <0>; 5852602c32fSVidya Sagar }; 5862602c32fSVidya Sagar 5872602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 5882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5892602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 5902602c32fSVidya Sagar reg-names = "ctl"; 5912602c32fSVidya Sagar 5922602c32fSVidya Sagar #phy-cells = <0>; 5932602c32fSVidya Sagar }; 5942602c32fSVidya Sagar 5952602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 5962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5972602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 5982602c32fSVidya Sagar reg-names = "ctl"; 5992602c32fSVidya Sagar 6002602c32fSVidya Sagar #phy-cells = <0>; 6012602c32fSVidya Sagar }; 6022602c32fSVidya Sagar 6032602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 6042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6052602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 6062602c32fSVidya Sagar reg-names = "ctl"; 6072602c32fSVidya Sagar 6082602c32fSVidya Sagar #phy-cells = <0>; 6092602c32fSVidya Sagar }; 6102602c32fSVidya Sagar 6112602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 6122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6132602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 6142602c32fSVidya Sagar reg-names = "ctl"; 6152602c32fSVidya Sagar 6162602c32fSVidya Sagar #phy-cells = <0>; 6172602c32fSVidya Sagar }; 6182602c32fSVidya Sagar 6192602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 6202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6212602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 6222602c32fSVidya Sagar reg-names = "ctl"; 6232602c32fSVidya Sagar 6242602c32fSVidya Sagar #phy-cells = <0>; 6252602c32fSVidya Sagar }; 6262602c32fSVidya Sagar 6272602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 6282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6292602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 6302602c32fSVidya Sagar reg-names = "ctl"; 6312602c32fSVidya Sagar 6322602c32fSVidya Sagar #phy-cells = <0>; 6332602c32fSVidya Sagar }; 6342602c32fSVidya Sagar 6352602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 6362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6372602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 6382602c32fSVidya Sagar reg-names = "ctl"; 6392602c32fSVidya Sagar 6402602c32fSVidya Sagar #phy-cells = <0>; 6412602c32fSVidya Sagar }; 6422602c32fSVidya Sagar 6432602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 6442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6452602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 6462602c32fSVidya Sagar reg-names = "ctl"; 6472602c32fSVidya Sagar 6482602c32fSVidya Sagar #phy-cells = <0>; 6492602c32fSVidya Sagar }; 6502602c32fSVidya Sagar 6512602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 6522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6532602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 6542602c32fSVidya Sagar reg-names = "ctl"; 6552602c32fSVidya Sagar 6562602c32fSVidya Sagar #phy-cells = <0>; 6572602c32fSVidya Sagar }; 6582602c32fSVidya Sagar 6592602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 6602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6612602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 6622602c32fSVidya Sagar reg-names = "ctl"; 6632602c32fSVidya Sagar 6642602c32fSVidya Sagar #phy-cells = <0>; 6652602c32fSVidya Sagar }; 6662602c32fSVidya Sagar 6672602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 6682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6692602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 6702602c32fSVidya Sagar reg-names = "ctl"; 6712602c32fSVidya Sagar 6722602c32fSVidya Sagar #phy-cells = <0>; 6732602c32fSVidya Sagar }; 6742602c32fSVidya Sagar 6752602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 6762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6772602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 6782602c32fSVidya Sagar reg-names = "ctl"; 6792602c32fSVidya Sagar 6802602c32fSVidya Sagar #phy-cells = <0>; 6812602c32fSVidya Sagar }; 6822602c32fSVidya Sagar 6832602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 6842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6852602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 6862602c32fSVidya Sagar reg-names = "ctl"; 6872602c32fSVidya Sagar 6882602c32fSVidya Sagar #phy-cells = <0>; 6892602c32fSVidya Sagar }; 6902602c32fSVidya Sagar 691a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 692a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 693a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 694a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 695a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 696a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 697a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 698a38570c2SMikko Perttunen /* 699a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 700a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 701a38570c2SMikko Perttunen */ 702a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 7035425fb15SMikko Perttunen #mbox-cells = <2>; 7045425fb15SMikko Perttunen }; 7055425fb15SMikko Perttunen 7065425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 707d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7085425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 7095425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 7105425fb15SMikko Perttunen #address-cells = <1>; 7115425fb15SMikko Perttunen #size-cells = <0>; 7125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 7135425fb15SMikko Perttunen clock-names = "div-clk"; 7145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 7155425fb15SMikko Perttunen reset-names = "i2c"; 7165425fb15SMikko Perttunen status = "disabled"; 7175425fb15SMikko Perttunen }; 7185425fb15SMikko Perttunen 7195425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 720d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7215425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 7225425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 7235425fb15SMikko Perttunen #address-cells = <1>; 7245425fb15SMikko Perttunen #size-cells = <0>; 7255425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 7265425fb15SMikko Perttunen clock-names = "div-clk"; 7275425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 7285425fb15SMikko Perttunen reset-names = "i2c"; 7295425fb15SMikko Perttunen status = "disabled"; 7305425fb15SMikko Perttunen }; 7315425fb15SMikko Perttunen 7325425fb15SMikko Perttunen uartc: serial@c280000 { 7335425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7345425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 7355425fb15SMikko Perttunen reg-shift = <2>; 7365425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 7375425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 7385425fb15SMikko Perttunen clock-names = "serial"; 7395425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 7405425fb15SMikko Perttunen reset-names = "serial"; 7415425fb15SMikko Perttunen status = "disabled"; 7425425fb15SMikko Perttunen }; 7435425fb15SMikko Perttunen 7445425fb15SMikko Perttunen uartg: serial@c290000 { 7455425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7465425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 7475425fb15SMikko Perttunen reg-shift = <2>; 7485425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 7495425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 7505425fb15SMikko Perttunen clock-names = "serial"; 7515425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 7525425fb15SMikko Perttunen reset-names = "serial"; 7535425fb15SMikko Perttunen status = "disabled"; 7545425fb15SMikko Perttunen }; 7555425fb15SMikko Perttunen 75637e5a31dSThierry Reding rtc: rtc@c2a0000 { 75737e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 75837e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 75937e5a31dSThierry Reding interrupt-parent = <&pmc>; 76037e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 76137e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 76237e5a31dSThierry Reding clock-names = "rtc"; 76337e5a31dSThierry Reding status = "disabled"; 76437e5a31dSThierry Reding }; 76537e5a31dSThierry Reding 7664d286331SThierry Reding gpio_aon: gpio@c2f0000 { 7674d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 7684d286331SThierry Reding reg-names = "security", "gpio"; 7694d286331SThierry Reding reg = <0xc2f0000 0x1000>, 7704d286331SThierry Reding <0xc2f1000 0x1000>; 7714d286331SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 7724d286331SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 7734d286331SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 7744d286331SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 7754d286331SThierry Reding gpio-controller; 7764d286331SThierry Reding #gpio-cells = <2>; 7774d286331SThierry Reding interrupt-controller; 7784d286331SThierry Reding #interrupt-cells = <2>; 7794d286331SThierry Reding }; 7804d286331SThierry Reding 7816a574ec7SThierry Reding pwm4: pwm@c340000 { 7826a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7836a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7846a574ec7SThierry Reding reg = <0xc340000 0x10000>; 7856a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 7866a574ec7SThierry Reding clock-names = "pwm"; 7876a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 7886a574ec7SThierry Reding reset-names = "pwm"; 7896a574ec7SThierry Reding status = "disabled"; 7906a574ec7SThierry Reding #pwm-cells = <2>; 7916a574ec7SThierry Reding }; 7926a574ec7SThierry Reding 79338ecf1e5SThierry Reding pmc: pmc@c360000 { 7945425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 7955425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 7965425fb15SMikko Perttunen <0x0c370000 0x10000>, 7975425fb15SMikko Perttunen <0x0c380000 0x10000>, 7985425fb15SMikko Perttunen <0x0c390000 0x10000>, 7995425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 8005425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 80138ecf1e5SThierry Reding 80238ecf1e5SThierry Reding #interrupt-cells = <2>; 80338ecf1e5SThierry Reding interrupt-controller; 8045425fb15SMikko Perttunen }; 8053db6d3baSThierry Reding 8063db6d3baSThierry Reding host1x@13e00000 { 8073db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 8083db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 8093db6d3baSThierry Reding <0x13e10000 0x10000>; 8103db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 8113db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 8123db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 8133db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 8143db6d3baSThierry Reding clock-names = "host1x"; 8153db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 8163db6d3baSThierry Reding reset-names = "host1x"; 8173db6d3baSThierry Reding 8183db6d3baSThierry Reding #address-cells = <1>; 8193db6d3baSThierry Reding #size-cells = <1>; 8203db6d3baSThierry Reding 8213db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 8223db6d3baSThierry Reding 8233db6d3baSThierry Reding display-hub@15200000 { 8243db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 825611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 8263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 8273db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 8283db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 8293db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 8303db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 8313db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 8323db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 8333db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 8343db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 8353db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 8363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 8373db6d3baSThierry Reding clock-names = "disp", "hub"; 8383db6d3baSThierry Reding status = "disabled"; 8393db6d3baSThierry Reding 8403db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8413db6d3baSThierry Reding 8423db6d3baSThierry Reding #address-cells = <1>; 8433db6d3baSThierry Reding #size-cells = <1>; 8443db6d3baSThierry Reding 8453db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 8463db6d3baSThierry Reding 8473db6d3baSThierry Reding display@15200000 { 8483db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8493db6d3baSThierry Reding reg = <0x15200000 0x10000>; 8503db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 8513db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 8523db6d3baSThierry Reding clock-names = "dc"; 8533db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 8543db6d3baSThierry Reding reset-names = "dc"; 8553db6d3baSThierry Reding 8563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8573db6d3baSThierry Reding 8583db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8593db6d3baSThierry Reding nvidia,head = <0>; 8603db6d3baSThierry Reding }; 8613db6d3baSThierry Reding 8623db6d3baSThierry Reding display@15210000 { 8633db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8643db6d3baSThierry Reding reg = <0x15210000 0x10000>; 8653db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 8663db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 8673db6d3baSThierry Reding clock-names = "dc"; 8683db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 8693db6d3baSThierry Reding reset-names = "dc"; 8703db6d3baSThierry Reding 8713db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 8723db6d3baSThierry Reding 8733db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8743db6d3baSThierry Reding nvidia,head = <1>; 8753db6d3baSThierry Reding }; 8763db6d3baSThierry Reding 8773db6d3baSThierry Reding display@15220000 { 8783db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8793db6d3baSThierry Reding reg = <0x15220000 0x10000>; 8803db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 8813db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 8823db6d3baSThierry Reding clock-names = "dc"; 8833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 8843db6d3baSThierry Reding reset-names = "dc"; 8853db6d3baSThierry Reding 8863db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 8873db6d3baSThierry Reding 8883db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 8893db6d3baSThierry Reding nvidia,head = <2>; 8903db6d3baSThierry Reding }; 8913db6d3baSThierry Reding 8923db6d3baSThierry Reding display@15230000 { 8933db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 8943db6d3baSThierry Reding reg = <0x15230000 0x10000>; 8953db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 8963db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 8973db6d3baSThierry Reding clock-names = "dc"; 8983db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 8993db6d3baSThierry Reding reset-names = "dc"; 9003db6d3baSThierry Reding 9013db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 9023db6d3baSThierry Reding 9033db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 9043db6d3baSThierry Reding nvidia,head = <3>; 9053db6d3baSThierry Reding }; 9063db6d3baSThierry Reding }; 9073db6d3baSThierry Reding 9088d424ec2SThierry Reding vic@15340000 { 9098d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 9108d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 9118d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 9128d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 9138d424ec2SThierry Reding clock-names = "vic"; 9148d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 9158d424ec2SThierry Reding reset-names = "vic"; 9168d424ec2SThierry Reding 9178d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 9188d424ec2SThierry Reding }; 9198d424ec2SThierry Reding 9203db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 9213db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9223db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 9233db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 9243db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 9253db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9263db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9273db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 9283db6d3baSThierry Reding reset-names = "dpaux"; 9293db6d3baSThierry Reding status = "disabled"; 9303db6d3baSThierry Reding 9313db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9323db6d3baSThierry Reding 9333db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 9343db6d3baSThierry Reding groups = "dpaux-io"; 9353db6d3baSThierry Reding function = "aux"; 9363db6d3baSThierry Reding }; 9373db6d3baSThierry Reding 9383db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 9393db6d3baSThierry Reding groups = "dpaux-io"; 9403db6d3baSThierry Reding function = "i2c"; 9413db6d3baSThierry Reding }; 9423db6d3baSThierry Reding 9433db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 9443db6d3baSThierry Reding groups = "dpaux-io"; 9453db6d3baSThierry Reding function = "off"; 9463db6d3baSThierry Reding }; 9473db6d3baSThierry Reding 9483db6d3baSThierry Reding i2c-bus { 9493db6d3baSThierry Reding #address-cells = <1>; 9503db6d3baSThierry Reding #size-cells = <0>; 9513db6d3baSThierry Reding }; 9523db6d3baSThierry Reding }; 9533db6d3baSThierry Reding 9543db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 9553db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9563db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 9573db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 9583db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 9593db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9603db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9613db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 9623db6d3baSThierry Reding reset-names = "dpaux"; 9633db6d3baSThierry Reding status = "disabled"; 9643db6d3baSThierry Reding 9653db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9663db6d3baSThierry Reding 9673db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 9683db6d3baSThierry Reding groups = "dpaux-io"; 9693db6d3baSThierry Reding function = "aux"; 9703db6d3baSThierry Reding }; 9713db6d3baSThierry Reding 9723db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 9733db6d3baSThierry Reding groups = "dpaux-io"; 9743db6d3baSThierry Reding function = "i2c"; 9753db6d3baSThierry Reding }; 9763db6d3baSThierry Reding 9773db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 9783db6d3baSThierry Reding groups = "dpaux-io"; 9793db6d3baSThierry Reding function = "off"; 9803db6d3baSThierry Reding }; 9813db6d3baSThierry Reding 9823db6d3baSThierry Reding i2c-bus { 9833db6d3baSThierry Reding #address-cells = <1>; 9843db6d3baSThierry Reding #size-cells = <0>; 9853db6d3baSThierry Reding }; 9863db6d3baSThierry Reding }; 9873db6d3baSThierry Reding 9883db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 9893db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9903db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 9913db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 9923db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 9933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9943db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9953db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 9963db6d3baSThierry Reding reset-names = "dpaux"; 9973db6d3baSThierry Reding status = "disabled"; 9983db6d3baSThierry Reding 9993db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10003db6d3baSThierry Reding 10013db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 10023db6d3baSThierry Reding groups = "dpaux-io"; 10033db6d3baSThierry Reding function = "aux"; 10043db6d3baSThierry Reding }; 10053db6d3baSThierry Reding 10063db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 10073db6d3baSThierry Reding groups = "dpaux-io"; 10083db6d3baSThierry Reding function = "i2c"; 10093db6d3baSThierry Reding }; 10103db6d3baSThierry Reding 10113db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 10123db6d3baSThierry Reding groups = "dpaux-io"; 10133db6d3baSThierry Reding function = "off"; 10143db6d3baSThierry Reding }; 10153db6d3baSThierry Reding 10163db6d3baSThierry Reding i2c-bus { 10173db6d3baSThierry Reding #address-cells = <1>; 10183db6d3baSThierry Reding #size-cells = <0>; 10193db6d3baSThierry Reding }; 10203db6d3baSThierry Reding }; 10213db6d3baSThierry Reding 10223db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 10233db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 10243db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 10253db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 10263db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 10273db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 10283db6d3baSThierry Reding clock-names = "dpaux", "parent"; 10293db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 10303db6d3baSThierry Reding reset-names = "dpaux"; 10313db6d3baSThierry Reding status = "disabled"; 10323db6d3baSThierry Reding 10333db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10343db6d3baSThierry Reding 10353db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 10363db6d3baSThierry Reding groups = "dpaux-io"; 10373db6d3baSThierry Reding function = "aux"; 10383db6d3baSThierry Reding }; 10393db6d3baSThierry Reding 10403db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 10413db6d3baSThierry Reding groups = "dpaux-io"; 10423db6d3baSThierry Reding function = "i2c"; 10433db6d3baSThierry Reding }; 10443db6d3baSThierry Reding 10453db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 10463db6d3baSThierry Reding groups = "dpaux-io"; 10473db6d3baSThierry Reding function = "off"; 10483db6d3baSThierry Reding }; 10493db6d3baSThierry Reding 10503db6d3baSThierry Reding i2c-bus { 10513db6d3baSThierry Reding #address-cells = <1>; 10523db6d3baSThierry Reding #size-cells = <0>; 10533db6d3baSThierry Reding }; 10543db6d3baSThierry Reding }; 10553db6d3baSThierry Reding 10563db6d3baSThierry Reding sor0: sor@15b00000 { 10573db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 10583db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 10593db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 10603db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 10613db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 10623db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 10633db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 10643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 10653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 10663db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 10673db6d3baSThierry Reding "pad"; 10683db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 10693db6d3baSThierry Reding reset-names = "sor"; 10703db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 10713db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 10723db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 10733db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 10743db6d3baSThierry Reding status = "disabled"; 10753db6d3baSThierry Reding 10763db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10773db6d3baSThierry Reding nvidia,interface = <0>; 10783db6d3baSThierry Reding }; 10793db6d3baSThierry Reding 10803db6d3baSThierry Reding sor1: sor@15b40000 { 10813db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1082939e7430SThierry Reding reg = <0x15b40000 0x40000>; 10833db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 10843db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 10853db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 10863db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 10873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 10883db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 10893db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 10903db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 10913db6d3baSThierry Reding "pad"; 10923db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 10933db6d3baSThierry Reding reset-names = "sor"; 10943db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 10953db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 10963db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 10973db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 10983db6d3baSThierry Reding status = "disabled"; 10993db6d3baSThierry Reding 11003db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11013db6d3baSThierry Reding nvidia,interface = <1>; 11023db6d3baSThierry Reding }; 11033db6d3baSThierry Reding 11043db6d3baSThierry Reding sor2: sor@15b80000 { 11053db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 11063db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 11073db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 11083db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 11093db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 11103db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 11113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11133db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 11143db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11153db6d3baSThierry Reding "pad"; 11163db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 11173db6d3baSThierry Reding reset-names = "sor"; 11183db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 11193db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 11203db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 11213db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11223db6d3baSThierry Reding status = "disabled"; 11233db6d3baSThierry Reding 11243db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11253db6d3baSThierry Reding nvidia,interface = <2>; 11263db6d3baSThierry Reding }; 11273db6d3baSThierry Reding 11283db6d3baSThierry Reding sor3: sor@15bc0000 { 11293db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 11303db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 11313db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 11323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 11333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 11343db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 11353db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11363db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11373db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 11383db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11393db6d3baSThierry Reding "pad"; 11403db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 11413db6d3baSThierry Reding reset-names = "sor"; 11423db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 11433db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 11443db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 11453db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11463db6d3baSThierry Reding status = "disabled"; 11473db6d3baSThierry Reding 11483db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11493db6d3baSThierry Reding nvidia,interface = <3>; 11503db6d3baSThierry Reding }; 11513db6d3baSThierry Reding }; 11525425fb15SMikko Perttunen }; 11535425fb15SMikko Perttunen 11542602c32fSVidya Sagar pcie@14100000 { 11552602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 11562602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 11572602c32fSVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 11582602c32fSVidya Sagar 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 11592602c32fSVidya Sagar 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 11602602c32fSVidya Sagar 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 11612602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 11622602c32fSVidya Sagar 11632602c32fSVidya Sagar status = "disabled"; 11642602c32fSVidya Sagar 11652602c32fSVidya Sagar #address-cells = <3>; 11662602c32fSVidya Sagar #size-cells = <2>; 11672602c32fSVidya Sagar device_type = "pci"; 11682602c32fSVidya Sagar num-lanes = <1>; 11692602c32fSVidya Sagar num-viewport = <8>; 11702602c32fSVidya Sagar linux,pci-domain = <1>; 11712602c32fSVidya Sagar 11722602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 11732602c32fSVidya Sagar clock-names = "core"; 11742602c32fSVidya Sagar 11752602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 11762602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 11772602c32fSVidya Sagar reset-names = "apb", "core"; 11782602c32fSVidya Sagar 11792602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 11802602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 11812602c32fSVidya Sagar interrupt-names = "intr", "msi"; 11822602c32fSVidya Sagar 11832602c32fSVidya Sagar #interrupt-cells = <1>; 11842602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 11852602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 11862602c32fSVidya Sagar 11872602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 11882602c32fSVidya Sagar 11892602c32fSVidya Sagar supports-clkreq; 11902602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 11912602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 11922602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 11932602c32fSVidya Sagar 11942602c32fSVidya Sagar bus-range = <0x0 0xff>; 11952602c32fSVidya Sagar ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 11962602c32fSVidya Sagar 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 11972602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 11982602c32fSVidya Sagar }; 11992602c32fSVidya Sagar 12002602c32fSVidya Sagar pcie@14120000 { 12012602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12022602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 12032602c32fSVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 12042602c32fSVidya Sagar 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 12052602c32fSVidya Sagar 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12062602c32fSVidya Sagar 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12072602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12082602c32fSVidya Sagar 12092602c32fSVidya Sagar status = "disabled"; 12102602c32fSVidya Sagar 12112602c32fSVidya Sagar #address-cells = <3>; 12122602c32fSVidya Sagar #size-cells = <2>; 12132602c32fSVidya Sagar device_type = "pci"; 12142602c32fSVidya Sagar num-lanes = <1>; 12152602c32fSVidya Sagar num-viewport = <8>; 12162602c32fSVidya Sagar linux,pci-domain = <2>; 12172602c32fSVidya Sagar 12182602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 12192602c32fSVidya Sagar clock-names = "core"; 12202602c32fSVidya Sagar 12212602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 12222602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 12232602c32fSVidya Sagar reset-names = "apb", "core"; 12242602c32fSVidya Sagar 12252602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12262602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12272602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12282602c32fSVidya Sagar 12292602c32fSVidya Sagar #interrupt-cells = <1>; 12302602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12312602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 12322602c32fSVidya Sagar 12332602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 12342602c32fSVidya Sagar 12352602c32fSVidya Sagar supports-clkreq; 12362602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12372602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12382602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12392602c32fSVidya Sagar 12402602c32fSVidya Sagar bus-range = <0x0 0xff>; 12412602c32fSVidya Sagar ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12422602c32fSVidya Sagar 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12432602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12442602c32fSVidya Sagar }; 12452602c32fSVidya Sagar 12462602c32fSVidya Sagar pcie@14140000 { 12472602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12482602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 12492602c32fSVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 12502602c32fSVidya Sagar 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 12512602c32fSVidya Sagar 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12522602c32fSVidya Sagar 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12532602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12542602c32fSVidya Sagar 12552602c32fSVidya Sagar status = "disabled"; 12562602c32fSVidya Sagar 12572602c32fSVidya Sagar #address-cells = <3>; 12582602c32fSVidya Sagar #size-cells = <2>; 12592602c32fSVidya Sagar device_type = "pci"; 12602602c32fSVidya Sagar num-lanes = <1>; 12612602c32fSVidya Sagar num-viewport = <8>; 12622602c32fSVidya Sagar linux,pci-domain = <3>; 12632602c32fSVidya Sagar 12642602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 12652602c32fSVidya Sagar clock-names = "core"; 12662602c32fSVidya Sagar 12672602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 12682602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 12692602c32fSVidya Sagar reset-names = "apb", "core"; 12702602c32fSVidya Sagar 12712602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12722602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12732602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12742602c32fSVidya Sagar 12752602c32fSVidya Sagar #interrupt-cells = <1>; 12762602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12772602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 12782602c32fSVidya Sagar 12792602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 12802602c32fSVidya Sagar 12812602c32fSVidya Sagar supports-clkreq; 12822602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12832602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12842602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12852602c32fSVidya Sagar 12862602c32fSVidya Sagar bus-range = <0x0 0xff>; 12872602c32fSVidya Sagar ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12882602c32fSVidya Sagar 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12892602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12902602c32fSVidya Sagar }; 12912602c32fSVidya Sagar 12922602c32fSVidya Sagar pcie@14160000 { 12932602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12942602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 12952602c32fSVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 12962602c32fSVidya Sagar 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 12972602c32fSVidya Sagar 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12982602c32fSVidya Sagar 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12992602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13002602c32fSVidya Sagar 13012602c32fSVidya Sagar status = "disabled"; 13022602c32fSVidya Sagar 13032602c32fSVidya Sagar #address-cells = <3>; 13042602c32fSVidya Sagar #size-cells = <2>; 13052602c32fSVidya Sagar device_type = "pci"; 13062602c32fSVidya Sagar num-lanes = <4>; 13072602c32fSVidya Sagar num-viewport = <8>; 13082602c32fSVidya Sagar linux,pci-domain = <4>; 13092602c32fSVidya Sagar 13102602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 13112602c32fSVidya Sagar clock-names = "core"; 13122602c32fSVidya Sagar 13132602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 13142602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 13152602c32fSVidya Sagar reset-names = "apb", "core"; 13162602c32fSVidya Sagar 13172602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13182602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13192602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13202602c32fSVidya Sagar 13212602c32fSVidya Sagar #interrupt-cells = <1>; 13222602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13232602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 13242602c32fSVidya Sagar 13252602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 13262602c32fSVidya Sagar 13272602c32fSVidya Sagar supports-clkreq; 13282602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13292602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13302602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13312602c32fSVidya Sagar 13322602c32fSVidya Sagar bus-range = <0x0 0xff>; 13332602c32fSVidya Sagar ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13342602c32fSVidya Sagar 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13352602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13362602c32fSVidya Sagar }; 13372602c32fSVidya Sagar 13382602c32fSVidya Sagar pcie@14180000 { 13392602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13402602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 13412602c32fSVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 13422602c32fSVidya Sagar 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 13432602c32fSVidya Sagar 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13442602c32fSVidya Sagar 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13452602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13462602c32fSVidya Sagar 13472602c32fSVidya Sagar status = "disabled"; 13482602c32fSVidya Sagar 13492602c32fSVidya Sagar #address-cells = <3>; 13502602c32fSVidya Sagar #size-cells = <2>; 13512602c32fSVidya Sagar device_type = "pci"; 13522602c32fSVidya Sagar num-lanes = <8>; 13532602c32fSVidya Sagar num-viewport = <8>; 13542602c32fSVidya Sagar linux,pci-domain = <0>; 13552602c32fSVidya Sagar 13562602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 13572602c32fSVidya Sagar clock-names = "core"; 13582602c32fSVidya Sagar 13592602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 13602602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 13612602c32fSVidya Sagar reset-names = "apb", "core"; 13622602c32fSVidya Sagar 13632602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13642602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13652602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13662602c32fSVidya Sagar 13672602c32fSVidya Sagar #interrupt-cells = <1>; 13682602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13692602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 13702602c32fSVidya Sagar 13712602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 13722602c32fSVidya Sagar 13732602c32fSVidya Sagar supports-clkreq; 13742602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13752602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13762602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13772602c32fSVidya Sagar 13782602c32fSVidya Sagar bus-range = <0x0 0xff>; 13792602c32fSVidya Sagar ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13802602c32fSVidya Sagar 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13812602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13822602c32fSVidya Sagar }; 13832602c32fSVidya Sagar 13842602c32fSVidya Sagar pcie@141a0000 { 13852602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13862602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 13872602c32fSVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 13882602c32fSVidya Sagar 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 13892602c32fSVidya Sagar 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13902602c32fSVidya Sagar 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13912602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13922602c32fSVidya Sagar 13932602c32fSVidya Sagar status = "disabled"; 13942602c32fSVidya Sagar 13952602c32fSVidya Sagar #address-cells = <3>; 13962602c32fSVidya Sagar #size-cells = <2>; 13972602c32fSVidya Sagar device_type = "pci"; 13982602c32fSVidya Sagar num-lanes = <8>; 13992602c32fSVidya Sagar num-viewport = <8>; 14002602c32fSVidya Sagar linux,pci-domain = <5>; 14012602c32fSVidya Sagar 1402dbb72e2cSVidya Sagar pinctrl-names = "default"; 1403dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1404dbb72e2cSVidya Sagar 14052602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 14062602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 14072602c32fSVidya Sagar clock-names = "core", "core_m"; 14082602c32fSVidya Sagar 14092602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 14102602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 14112602c32fSVidya Sagar reset-names = "apb", "core"; 14122602c32fSVidya Sagar 14132602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14142602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14152602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14162602c32fSVidya Sagar 14172602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 14182602c32fSVidya Sagar 14192602c32fSVidya Sagar #interrupt-cells = <1>; 14202602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14212602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 14222602c32fSVidya Sagar 14232602c32fSVidya Sagar supports-clkreq; 14242602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14252602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14262602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14272602c32fSVidya Sagar 14282602c32fSVidya Sagar bus-range = <0x0 0xff>; 14292602c32fSVidya Sagar ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14302602c32fSVidya Sagar 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 14312602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 14322602c32fSVidya Sagar }; 14332602c32fSVidya Sagar 14345425fb15SMikko Perttunen sysram@40000000 { 14355425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 14365425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 14375425fb15SMikko Perttunen #address-cells = <1>; 14385425fb15SMikko Perttunen #size-cells = <1>; 14395425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 14405425fb15SMikko Perttunen 14415425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 14425425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 14435425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 14445425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 14455425fb15SMikko Perttunen pool; 14465425fb15SMikko Perttunen }; 14475425fb15SMikko Perttunen 14485425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 14495425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 14505425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 14515425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 14525425fb15SMikko Perttunen pool; 14535425fb15SMikko Perttunen }; 14545425fb15SMikko Perttunen }; 14555425fb15SMikko Perttunen 14565425fb15SMikko Perttunen bpmp: bpmp { 14575425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 14585425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 14595425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 14605425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 14615425fb15SMikko Perttunen #clock-cells = <1>; 14625425fb15SMikko Perttunen #reset-cells = <1>; 14635425fb15SMikko Perttunen #power-domain-cells = <1>; 14645425fb15SMikko Perttunen 14655425fb15SMikko Perttunen bpmp_i2c: i2c { 14665425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 14675425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 14685425fb15SMikko Perttunen #address-cells = <1>; 14695425fb15SMikko Perttunen #size-cells = <0>; 14705425fb15SMikko Perttunen }; 14715425fb15SMikko Perttunen 14725425fb15SMikko Perttunen bpmp_thermal: thermal { 14735425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 14745425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 14755425fb15SMikko Perttunen }; 14765425fb15SMikko Perttunen }; 14775425fb15SMikko Perttunen 14787780a034SMikko Perttunen cpus { 14797780a034SMikko Perttunen #address-cells = <1>; 14807780a034SMikko Perttunen #size-cells = <0>; 14817780a034SMikko Perttunen 1482b45d322cSThierry Reding cpu0_0: cpu@0 { 148331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14847780a034SMikko Perttunen device_type = "cpu"; 1485b45d322cSThierry Reding reg = <0x000>; 14867780a034SMikko Perttunen enable-method = "psci"; 1487b45d322cSThierry Reding i-cache-size = <131072>; 1488b45d322cSThierry Reding i-cache-line-size = <64>; 1489b45d322cSThierry Reding i-cache-sets = <512>; 1490b45d322cSThierry Reding d-cache-size = <65536>; 1491b45d322cSThierry Reding d-cache-line-size = <64>; 1492b45d322cSThierry Reding d-cache-sets = <256>; 1493b45d322cSThierry Reding next-level-cache = <&l2c_0>; 14947780a034SMikko Perttunen }; 14957780a034SMikko Perttunen 1496b45d322cSThierry Reding cpu0_1: cpu@1 { 149731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 14987780a034SMikko Perttunen device_type = "cpu"; 1499b45d322cSThierry Reding reg = <0x001>; 15007780a034SMikko Perttunen enable-method = "psci"; 1501b45d322cSThierry Reding i-cache-size = <131072>; 1502b45d322cSThierry Reding i-cache-line-size = <64>; 1503b45d322cSThierry Reding i-cache-sets = <512>; 1504b45d322cSThierry Reding d-cache-size = <65536>; 1505b45d322cSThierry Reding d-cache-line-size = <64>; 1506b45d322cSThierry Reding d-cache-sets = <256>; 1507b45d322cSThierry Reding next-level-cache = <&l2c_0>; 15087780a034SMikko Perttunen }; 15097780a034SMikko Perttunen 1510b45d322cSThierry Reding cpu1_0: cpu@100 { 151131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15127780a034SMikko Perttunen device_type = "cpu"; 15137780a034SMikko Perttunen reg = <0x100>; 15147780a034SMikko Perttunen enable-method = "psci"; 1515b45d322cSThierry Reding i-cache-size = <131072>; 1516b45d322cSThierry Reding i-cache-line-size = <64>; 1517b45d322cSThierry Reding i-cache-sets = <512>; 1518b45d322cSThierry Reding d-cache-size = <65536>; 1519b45d322cSThierry Reding d-cache-line-size = <64>; 1520b45d322cSThierry Reding d-cache-sets = <256>; 1521b45d322cSThierry Reding next-level-cache = <&l2c_1>; 15227780a034SMikko Perttunen }; 15237780a034SMikko Perttunen 1524b45d322cSThierry Reding cpu1_1: cpu@101 { 152531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15267780a034SMikko Perttunen device_type = "cpu"; 15277780a034SMikko Perttunen reg = <0x101>; 15287780a034SMikko Perttunen enable-method = "psci"; 1529b45d322cSThierry Reding i-cache-size = <131072>; 1530b45d322cSThierry Reding i-cache-line-size = <64>; 1531b45d322cSThierry Reding i-cache-sets = <512>; 1532b45d322cSThierry Reding d-cache-size = <65536>; 1533b45d322cSThierry Reding d-cache-line-size = <64>; 1534b45d322cSThierry Reding d-cache-sets = <256>; 1535b45d322cSThierry Reding next-level-cache = <&l2c_1>; 15367780a034SMikko Perttunen }; 15377780a034SMikko Perttunen 1538b45d322cSThierry Reding cpu2_0: cpu@200 { 153931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15407780a034SMikko Perttunen device_type = "cpu"; 15417780a034SMikko Perttunen reg = <0x200>; 15427780a034SMikko Perttunen enable-method = "psci"; 1543b45d322cSThierry Reding i-cache-size = <131072>; 1544b45d322cSThierry Reding i-cache-line-size = <64>; 1545b45d322cSThierry Reding i-cache-sets = <512>; 1546b45d322cSThierry Reding d-cache-size = <65536>; 1547b45d322cSThierry Reding d-cache-line-size = <64>; 1548b45d322cSThierry Reding d-cache-sets = <256>; 1549b45d322cSThierry Reding next-level-cache = <&l2c_2>; 15507780a034SMikko Perttunen }; 15517780a034SMikko Perttunen 1552b45d322cSThierry Reding cpu2_1: cpu@201 { 155331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15547780a034SMikko Perttunen device_type = "cpu"; 15557780a034SMikko Perttunen reg = <0x201>; 15567780a034SMikko Perttunen enable-method = "psci"; 1557b45d322cSThierry Reding i-cache-size = <131072>; 1558b45d322cSThierry Reding i-cache-line-size = <64>; 1559b45d322cSThierry Reding i-cache-sets = <512>; 1560b45d322cSThierry Reding d-cache-size = <65536>; 1561b45d322cSThierry Reding d-cache-line-size = <64>; 1562b45d322cSThierry Reding d-cache-sets = <256>; 1563b45d322cSThierry Reding next-level-cache = <&l2c_2>; 15647780a034SMikko Perttunen }; 15657780a034SMikko Perttunen 1566b45d322cSThierry Reding cpu3_0: cpu@300 { 156731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15687780a034SMikko Perttunen device_type = "cpu"; 1569b45d322cSThierry Reding reg = <0x300>; 15707780a034SMikko Perttunen enable-method = "psci"; 1571b45d322cSThierry Reding i-cache-size = <131072>; 1572b45d322cSThierry Reding i-cache-line-size = <64>; 1573b45d322cSThierry Reding i-cache-sets = <512>; 1574b45d322cSThierry Reding d-cache-size = <65536>; 1575b45d322cSThierry Reding d-cache-line-size = <64>; 1576b45d322cSThierry Reding d-cache-sets = <256>; 1577b45d322cSThierry Reding next-level-cache = <&l2c_3>; 15787780a034SMikko Perttunen }; 15797780a034SMikko Perttunen 1580b45d322cSThierry Reding cpu3_1: cpu@301 { 158131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15827780a034SMikko Perttunen device_type = "cpu"; 1583b45d322cSThierry Reding reg = <0x301>; 15847780a034SMikko Perttunen enable-method = "psci"; 1585b45d322cSThierry Reding i-cache-size = <131072>; 1586b45d322cSThierry Reding i-cache-line-size = <64>; 1587b45d322cSThierry Reding i-cache-sets = <512>; 1588b45d322cSThierry Reding d-cache-size = <65536>; 1589b45d322cSThierry Reding d-cache-line-size = <64>; 1590b45d322cSThierry Reding d-cache-sets = <256>; 1591b45d322cSThierry Reding next-level-cache = <&l2c_3>; 1592b45d322cSThierry Reding }; 1593b45d322cSThierry Reding 1594b45d322cSThierry Reding cpu-map { 1595b45d322cSThierry Reding cluster0 { 1596b45d322cSThierry Reding core0 { 1597b45d322cSThierry Reding cpu = <&cpu0_0>; 1598b45d322cSThierry Reding }; 1599b45d322cSThierry Reding 1600b45d322cSThierry Reding core1 { 1601b45d322cSThierry Reding cpu = <&cpu0_1>; 1602b45d322cSThierry Reding }; 1603b45d322cSThierry Reding }; 1604b45d322cSThierry Reding 1605b45d322cSThierry Reding cluster1 { 1606b45d322cSThierry Reding core0 { 1607b45d322cSThierry Reding cpu = <&cpu1_0>; 1608b45d322cSThierry Reding }; 1609b45d322cSThierry Reding 1610b45d322cSThierry Reding core1 { 1611b45d322cSThierry Reding cpu = <&cpu1_1>; 1612b45d322cSThierry Reding }; 1613b45d322cSThierry Reding }; 1614b45d322cSThierry Reding 1615b45d322cSThierry Reding cluster2 { 1616b45d322cSThierry Reding core0 { 1617b45d322cSThierry Reding cpu = <&cpu2_0>; 1618b45d322cSThierry Reding }; 1619b45d322cSThierry Reding 1620b45d322cSThierry Reding core1 { 1621b45d322cSThierry Reding cpu = <&cpu2_1>; 1622b45d322cSThierry Reding }; 1623b45d322cSThierry Reding }; 1624b45d322cSThierry Reding 1625b45d322cSThierry Reding cluster3 { 1626b45d322cSThierry Reding core0 { 1627b45d322cSThierry Reding cpu = <&cpu3_0>; 1628b45d322cSThierry Reding }; 1629b45d322cSThierry Reding 1630b45d322cSThierry Reding core1 { 1631b45d322cSThierry Reding cpu = <&cpu3_1>; 1632b45d322cSThierry Reding }; 1633b45d322cSThierry Reding }; 1634b45d322cSThierry Reding }; 1635b45d322cSThierry Reding 1636b45d322cSThierry Reding l2c_0: l2-cache0 { 1637b45d322cSThierry Reding cache-size = <2097152>; 1638b45d322cSThierry Reding cache-line-size = <64>; 1639b45d322cSThierry Reding cache-sets = <2048>; 1640b45d322cSThierry Reding next-level-cache = <&l3c>; 1641b45d322cSThierry Reding }; 1642b45d322cSThierry Reding 1643b45d322cSThierry Reding l2c_1: l2-cache1 { 1644b45d322cSThierry Reding cache-size = <2097152>; 1645b45d322cSThierry Reding cache-line-size = <64>; 1646b45d322cSThierry Reding cache-sets = <2048>; 1647b45d322cSThierry Reding next-level-cache = <&l3c>; 1648b45d322cSThierry Reding }; 1649b45d322cSThierry Reding 1650b45d322cSThierry Reding l2c_2: l2-cache2 { 1651b45d322cSThierry Reding cache-size = <2097152>; 1652b45d322cSThierry Reding cache-line-size = <64>; 1653b45d322cSThierry Reding cache-sets = <2048>; 1654b45d322cSThierry Reding next-level-cache = <&l3c>; 1655b45d322cSThierry Reding }; 1656b45d322cSThierry Reding 1657b45d322cSThierry Reding l2c_3: l2-cache3 { 1658b45d322cSThierry Reding cache-size = <2097152>; 1659b45d322cSThierry Reding cache-line-size = <64>; 1660b45d322cSThierry Reding cache-sets = <2048>; 1661b45d322cSThierry Reding next-level-cache = <&l3c>; 1662b45d322cSThierry Reding }; 1663b45d322cSThierry Reding 1664b45d322cSThierry Reding l3c: l3-cache { 1665b45d322cSThierry Reding cache-size = <4194304>; 1666b45d322cSThierry Reding cache-line-size = <64>; 1667b45d322cSThierry Reding cache-sets = <4096>; 16687780a034SMikko Perttunen }; 16697780a034SMikko Perttunen }; 16707780a034SMikko Perttunen 16717780a034SMikko Perttunen psci { 16727780a034SMikko Perttunen compatible = "arm,psci-1.0"; 16737780a034SMikko Perttunen status = "okay"; 16747780a034SMikko Perttunen method = "smc"; 16757780a034SMikko Perttunen }; 16767780a034SMikko Perttunen 1677a38570c2SMikko Perttunen tcu: tcu { 1678a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 1679a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1680a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1681a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 1682a38570c2SMikko Perttunen }; 1683a38570c2SMikko Perttunen 1684686ba009SThierry Reding thermal-zones { 1685686ba009SThierry Reding cpu { 1686686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1687686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1688686ba009SThierry Reding status = "disabled"; 1689686ba009SThierry Reding }; 1690686ba009SThierry Reding 1691686ba009SThierry Reding gpu { 1692686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1693686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1694686ba009SThierry Reding status = "disabled"; 1695686ba009SThierry Reding }; 1696686ba009SThierry Reding 1697686ba009SThierry Reding aux { 1698686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1699686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1700686ba009SThierry Reding status = "disabled"; 1701686ba009SThierry Reding }; 1702686ba009SThierry Reding 1703686ba009SThierry Reding pllx { 1704686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1705686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1706686ba009SThierry Reding status = "disabled"; 1707686ba009SThierry Reding }; 1708686ba009SThierry Reding 1709686ba009SThierry Reding ao { 1710686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1711686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 1712686ba009SThierry Reding status = "disabled"; 1713686ba009SThierry Reding }; 1714686ba009SThierry Reding 1715686ba009SThierry Reding tj { 1716686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1717686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1718686ba009SThierry Reding status = "disabled"; 1719686ba009SThierry Reding }; 1720686ba009SThierry Reding }; 1721686ba009SThierry Reding 17225425fb15SMikko Perttunen timer { 17235425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 17245425fb15SMikko Perttunen interrupts = <GIC_PPI 13 17255425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17265425fb15SMikko Perttunen <GIC_PPI 14 17275425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17285425fb15SMikko Perttunen <GIC_PPI 11 17295425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17305425fb15SMikko Perttunen <GIC_PPI 10 17315425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 17325425fb15SMikko Perttunen interrupt-parent = <&gic>; 1733b30be673SThierry Reding always-on; 17345425fb15SMikko Perttunen }; 17355425fb15SMikko Perttunen}; 1736