15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 63d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 64d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 65f89b58ceSMikko Perttunen status = "disabled"; 66f89b58ceSMikko Perttunen 67f89b58ceSMikko Perttunen snps,write-requests = <1>; 68f89b58ceSMikko Perttunen snps,read-requests = <3>; 69f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 70f89b58ceSMikko Perttunen snps,txpbl = <16>; 71f89b58ceSMikko Perttunen snps,rxpbl = <8>; 72f89b58ceSMikko Perttunen }; 73f89b58ceSMikko Perttunen 741aaa7698SThierry Reding aconnect@2900000 { 755d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 765d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 775d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 785d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 795d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 805d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 815d2249ddSSameer Pujar #address-cells = <1>; 825d2249ddSSameer Pujar #size-cells = <1>; 835d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 845d2249ddSSameer Pujar status = "disabled"; 855d2249ddSSameer Pujar 86177208f7SSameer Pujar adma: dma-controller@2930000 { 875d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 885d2249ddSSameer Pujar "nvidia,tegra186-adma"; 895d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 905d2249ddSSameer Pujar interrupt-parent = <&agic>; 915d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1235d2249ddSSameer Pujar #dma-cells = <1>; 1245d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1255d2249ddSSameer Pujar clock-names = "d_audio"; 1265d2249ddSSameer Pujar status = "disabled"; 1275d2249ddSSameer Pujar }; 1285d2249ddSSameer Pujar 1295d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1315d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1325d2249ddSSameer Pujar #interrupt-cells = <3>; 1335d2249ddSSameer Pujar interrupt-controller; 1345d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1355d2249ddSSameer Pujar <0x02a42000 0x2000>; 1365d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1375d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1385d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 146177208f7SSameer Pujar "nvidia,tegra186-ahub"; 147177208f7SSameer Pujar reg = <0x02900800 0x800>; 148177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 149177208f7SSameer Pujar clock-names = "ahub"; 150177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 151177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 152177208f7SSameer Pujar #address-cells = <1>; 153177208f7SSameer Pujar #size-cells = <1>; 154177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 155177208f7SSameer Pujar status = "disabled"; 156177208f7SSameer Pujar 157177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 158177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 159177208f7SSameer Pujar "nvidia,tegra186-admaif"; 160177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 161177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 162177208f7SSameer Pujar <&adma 2>, <&adma 2>, 163177208f7SSameer Pujar <&adma 3>, <&adma 3>, 164177208f7SSameer Pujar <&adma 4>, <&adma 4>, 165177208f7SSameer Pujar <&adma 5>, <&adma 5>, 166177208f7SSameer Pujar <&adma 6>, <&adma 6>, 167177208f7SSameer Pujar <&adma 7>, <&adma 7>, 168177208f7SSameer Pujar <&adma 8>, <&adma 8>, 169177208f7SSameer Pujar <&adma 9>, <&adma 9>, 170177208f7SSameer Pujar <&adma 10>, <&adma 10>, 171177208f7SSameer Pujar <&adma 11>, <&adma 11>, 172177208f7SSameer Pujar <&adma 12>, <&adma 12>, 173177208f7SSameer Pujar <&adma 13>, <&adma 13>, 174177208f7SSameer Pujar <&adma 14>, <&adma 14>, 175177208f7SSameer Pujar <&adma 15>, <&adma 15>, 176177208f7SSameer Pujar <&adma 16>, <&adma 16>, 177177208f7SSameer Pujar <&adma 17>, <&adma 17>, 178177208f7SSameer Pujar <&adma 18>, <&adma 18>, 179177208f7SSameer Pujar <&adma 19>, <&adma 19>, 180177208f7SSameer Pujar <&adma 20>, <&adma 20>; 181177208f7SSameer Pujar dma-names = "rx1", "tx1", 182177208f7SSameer Pujar "rx2", "tx2", 183177208f7SSameer Pujar "rx3", "tx3", 184177208f7SSameer Pujar "rx4", "tx4", 185177208f7SSameer Pujar "rx5", "tx5", 186177208f7SSameer Pujar "rx6", "tx6", 187177208f7SSameer Pujar "rx7", "tx7", 188177208f7SSameer Pujar "rx8", "tx8", 189177208f7SSameer Pujar "rx9", "tx9", 190177208f7SSameer Pujar "rx10", "tx10", 191177208f7SSameer Pujar "rx11", "tx11", 192177208f7SSameer Pujar "rx12", "tx12", 193177208f7SSameer Pujar "rx13", "tx13", 194177208f7SSameer Pujar "rx14", "tx14", 195177208f7SSameer Pujar "rx15", "tx15", 196177208f7SSameer Pujar "rx16", "tx16", 197177208f7SSameer Pujar "rx17", "tx17", 198177208f7SSameer Pujar "rx18", "tx18", 199177208f7SSameer Pujar "rx19", "tx19", 200177208f7SSameer Pujar "rx20", "tx20"; 201177208f7SSameer Pujar status = "disabled"; 202177208f7SSameer Pujar }; 203177208f7SSameer Pujar 204177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 205177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 206177208f7SSameer Pujar "nvidia,tegra210-i2s"; 207177208f7SSameer Pujar reg = <0x2901000 0x100>; 208177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 209177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 210177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 211177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 212177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 213177208f7SSameer Pujar assigned-clock-rates = <1536000>; 214177208f7SSameer Pujar sound-name-prefix = "I2S1"; 215177208f7SSameer Pujar status = "disabled"; 216177208f7SSameer Pujar }; 217177208f7SSameer Pujar 218177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 219177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 220177208f7SSameer Pujar "nvidia,tegra210-i2s"; 221177208f7SSameer Pujar reg = <0x2901100 0x100>; 222177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 223177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 224177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 225177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 226177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 227177208f7SSameer Pujar assigned-clock-rates = <1536000>; 228177208f7SSameer Pujar sound-name-prefix = "I2S2"; 229177208f7SSameer Pujar status = "disabled"; 230177208f7SSameer Pujar }; 231177208f7SSameer Pujar 232177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 233177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 234177208f7SSameer Pujar "nvidia,tegra210-i2s"; 235177208f7SSameer Pujar reg = <0x2901200 0x100>; 236177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 237177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 238177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 239177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 240177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 241177208f7SSameer Pujar assigned-clock-rates = <1536000>; 242177208f7SSameer Pujar sound-name-prefix = "I2S3"; 243177208f7SSameer Pujar status = "disabled"; 244177208f7SSameer Pujar }; 245177208f7SSameer Pujar 246177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 247177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 248177208f7SSameer Pujar "nvidia,tegra210-i2s"; 249177208f7SSameer Pujar reg = <0x2901300 0x100>; 250177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 251177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 252177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 253177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 254177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 255177208f7SSameer Pujar assigned-clock-rates = <1536000>; 256177208f7SSameer Pujar sound-name-prefix = "I2S4"; 257177208f7SSameer Pujar status = "disabled"; 258177208f7SSameer Pujar }; 259177208f7SSameer Pujar 260177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 261177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 262177208f7SSameer Pujar "nvidia,tegra210-i2s"; 263177208f7SSameer Pujar reg = <0x2901400 0x100>; 264177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 265177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 266177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 267177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 268177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 269177208f7SSameer Pujar assigned-clock-rates = <1536000>; 270177208f7SSameer Pujar sound-name-prefix = "I2S5"; 271177208f7SSameer Pujar status = "disabled"; 272177208f7SSameer Pujar }; 273177208f7SSameer Pujar 274177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 275177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 276177208f7SSameer Pujar "nvidia,tegra210-i2s"; 277177208f7SSameer Pujar reg = <0x2901500 0x100>; 278177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 279177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 280177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 281177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 282177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 283177208f7SSameer Pujar assigned-clock-rates = <1536000>; 284177208f7SSameer Pujar sound-name-prefix = "I2S6"; 285177208f7SSameer Pujar status = "disabled"; 286177208f7SSameer Pujar }; 287177208f7SSameer Pujar 288177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 289177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 290177208f7SSameer Pujar "nvidia,tegra210-dmic"; 291177208f7SSameer Pujar reg = <0x2904000 0x100>; 292177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 293177208f7SSameer Pujar clock-names = "dmic"; 294177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 295177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 296177208f7SSameer Pujar assigned-clock-rates = <3072000>; 297177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 298177208f7SSameer Pujar status = "disabled"; 299177208f7SSameer Pujar }; 300177208f7SSameer Pujar 301177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 302177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 303177208f7SSameer Pujar "nvidia,tegra210-dmic"; 304177208f7SSameer Pujar reg = <0x2904100 0x100>; 305177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 306177208f7SSameer Pujar clock-names = "dmic"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <3072000>; 310177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 315177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 316177208f7SSameer Pujar "nvidia,tegra210-dmic"; 317177208f7SSameer Pujar reg = <0x2904200 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 319177208f7SSameer Pujar clock-names = "dmic"; 320177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 321177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 322177208f7SSameer Pujar assigned-clock-rates = <3072000>; 323177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 324177208f7SSameer Pujar status = "disabled"; 325177208f7SSameer Pujar }; 326177208f7SSameer Pujar 327177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 328177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 329177208f7SSameer Pujar "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904300 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 341177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 342177208f7SSameer Pujar "nvidia,tegra186-dspk"; 343177208f7SSameer Pujar reg = <0x2905000 0x100>; 344177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 345177208f7SSameer Pujar clock-names = "dspk"; 346177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 347177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 348177208f7SSameer Pujar assigned-clock-rates = <12288000>; 349177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 350177208f7SSameer Pujar status = "disabled"; 351177208f7SSameer Pujar }; 352177208f7SSameer Pujar 353177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 354177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 355177208f7SSameer Pujar "nvidia,tegra186-dspk"; 356177208f7SSameer Pujar reg = <0x2905100 0x100>; 357177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 358177208f7SSameer Pujar clock-names = "dspk"; 359177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 360177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 361177208f7SSameer Pujar assigned-clock-rates = <12288000>; 362177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 363177208f7SSameer Pujar status = "disabled"; 364177208f7SSameer Pujar }; 365177208f7SSameer Pujar }; 3665d2249ddSSameer Pujar }; 3675d2249ddSSameer Pujar 368dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 369dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 370644c569dSThierry Reding reg = <0x2430000 0x17000>, 371644c569dSThierry Reding <0xc300000 0x4000>; 372dbb72e2cSVidya Sagar 373dbb72e2cSVidya Sagar status = "okay"; 374dbb72e2cSVidya Sagar 375dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 376dbb72e2cSVidya Sagar pex_rst { 377dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 378dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 379dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 380dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 381dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 382dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 383dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384dbb72e2cSVidya Sagar }; 385dbb72e2cSVidya Sagar }; 386dbb72e2cSVidya Sagar 387dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 388dbb72e2cSVidya Sagar clkreq { 389dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 390dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 392dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 394dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 395dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 396dbb72e2cSVidya Sagar }; 397dbb72e2cSVidya Sagar }; 398dbb72e2cSVidya Sagar }; 399dbb72e2cSVidya Sagar 400be9b887fSThierry Reding mc: memory-controller@2c00000 { 401be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 402be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 403be9b887fSThierry Reding <0x02b80000 0x040000>, 404be9b887fSThierry Reding <0x01700000 0x100000>; 4058613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 406d5237c7cSThierry Reding #interconnect-cells = <1>; 407be9b887fSThierry Reding status = "disabled"; 408be9b887fSThierry Reding 409be9b887fSThierry Reding #address-cells = <2>; 410be9b887fSThierry Reding #size-cells = <2>; 411be9b887fSThierry Reding 412be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 413be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 414be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 415be9b887fSThierry Reding 416be9b887fSThierry Reding /* 417be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 418be9b887fSThierry Reding * controller selects the XBAR format used when memory 419be9b887fSThierry Reding * is accessed. This is used to transparently access 420be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 421be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 422be9b887fSThierry Reding * 423be9b887fSThierry Reding * As a consequence, the operating system must ensure 424be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 425be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 426be9b887fSThierry Reding * devices require access to the XBAR switch, their 427be9b887fSThierry Reding * drivers must set this bit explicitly. 428be9b887fSThierry Reding * 429be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 430be9b887fSThierry Reding */ 431be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 432be9b887fSThierry Reding 433be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 434be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 435be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 436be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 437be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 438be9b887fSThierry Reding clock-names = "emc"; 439be9b887fSThierry Reding 440d5237c7cSThierry Reding #interconnect-cells = <0>; 441d5237c7cSThierry Reding 442be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 443be9b887fSThierry Reding }; 444be9b887fSThierry Reding }; 445be9b887fSThierry Reding 4465425fb15SMikko Perttunen uarta: serial@3100000 { 4475425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4485425fb15SMikko Perttunen reg = <0x03100000 0x40>; 4495425fb15SMikko Perttunen reg-shift = <2>; 4505425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 4525425fb15SMikko Perttunen clock-names = "serial"; 4535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 4545425fb15SMikko Perttunen reset-names = "serial"; 4555425fb15SMikko Perttunen status = "disabled"; 4565425fb15SMikko Perttunen }; 4575425fb15SMikko Perttunen 4585425fb15SMikko Perttunen uartb: serial@3110000 { 4595425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4605425fb15SMikko Perttunen reg = <0x03110000 0x40>; 4615425fb15SMikko Perttunen reg-shift = <2>; 4625425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4635425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 4645425fb15SMikko Perttunen clock-names = "serial"; 4655425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 4665425fb15SMikko Perttunen reset-names = "serial"; 4675425fb15SMikko Perttunen status = "disabled"; 4685425fb15SMikko Perttunen }; 4695425fb15SMikko Perttunen 4705425fb15SMikko Perttunen uartd: serial@3130000 { 4715425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4725425fb15SMikko Perttunen reg = <0x03130000 0x40>; 4735425fb15SMikko Perttunen reg-shift = <2>; 4745425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 4755425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 4765425fb15SMikko Perttunen clock-names = "serial"; 4775425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 4785425fb15SMikko Perttunen reset-names = "serial"; 4795425fb15SMikko Perttunen status = "disabled"; 4805425fb15SMikko Perttunen }; 4815425fb15SMikko Perttunen 4825425fb15SMikko Perttunen uarte: serial@3140000 { 4835425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4845425fb15SMikko Perttunen reg = <0x03140000 0x40>; 4855425fb15SMikko Perttunen reg-shift = <2>; 4865425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 4875425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 4885425fb15SMikko Perttunen clock-names = "serial"; 4895425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 4905425fb15SMikko Perttunen reset-names = "serial"; 4915425fb15SMikko Perttunen status = "disabled"; 4925425fb15SMikko Perttunen }; 4935425fb15SMikko Perttunen 4945425fb15SMikko Perttunen uartf: serial@3150000 { 4955425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4965425fb15SMikko Perttunen reg = <0x03150000 0x40>; 4975425fb15SMikko Perttunen reg-shift = <2>; 4985425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 4995425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 5005425fb15SMikko Perttunen clock-names = "serial"; 5015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 5025425fb15SMikko Perttunen reset-names = "serial"; 5035425fb15SMikko Perttunen status = "disabled"; 5045425fb15SMikko Perttunen }; 5055425fb15SMikko Perttunen 5065425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 507d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5085425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 5095425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 5105425fb15SMikko Perttunen #address-cells = <1>; 5115425fb15SMikko Perttunen #size-cells = <0>; 5125425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 5135425fb15SMikko Perttunen clock-names = "div-clk"; 5145425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 5155425fb15SMikko Perttunen reset-names = "i2c"; 5165425fb15SMikko Perttunen status = "disabled"; 5175425fb15SMikko Perttunen }; 5185425fb15SMikko Perttunen 5195425fb15SMikko Perttunen uarth: serial@3170000 { 5205425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5215425fb15SMikko Perttunen reg = <0x03170000 0x40>; 5225425fb15SMikko Perttunen reg-shift = <2>; 5235425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 5245425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 5255425fb15SMikko Perttunen clock-names = "serial"; 5265425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 5275425fb15SMikko Perttunen reset-names = "serial"; 5285425fb15SMikko Perttunen status = "disabled"; 5295425fb15SMikko Perttunen }; 5305425fb15SMikko Perttunen 5315425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 532d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5335425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 5345425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5355425fb15SMikko Perttunen #address-cells = <1>; 5365425fb15SMikko Perttunen #size-cells = <0>; 5375425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 5385425fb15SMikko Perttunen clock-names = "div-clk"; 5395425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 5405425fb15SMikko Perttunen reset-names = "i2c"; 5415425fb15SMikko Perttunen status = "disabled"; 5425425fb15SMikko Perttunen }; 5435425fb15SMikko Perttunen 5445425fb15SMikko Perttunen /* shares pads with dpaux1 */ 5455425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 546d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5475425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 5485425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 5495425fb15SMikko Perttunen #address-cells = <1>; 5505425fb15SMikko Perttunen #size-cells = <0>; 5515425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 5525425fb15SMikko Perttunen clock-names = "div-clk"; 5535425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 5545425fb15SMikko Perttunen reset-names = "i2c"; 555a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 556a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 557a4131561SThierry Reding pinctrl-names = "default", "idle"; 5585425fb15SMikko Perttunen status = "disabled"; 5595425fb15SMikko Perttunen }; 5605425fb15SMikko Perttunen 5615425fb15SMikko Perttunen /* shares pads with dpaux0 */ 5625425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 563d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5645425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 5655425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 5665425fb15SMikko Perttunen #address-cells = <1>; 5675425fb15SMikko Perttunen #size-cells = <0>; 5685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 5695425fb15SMikko Perttunen clock-names = "div-clk"; 5705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 5715425fb15SMikko Perttunen reset-names = "i2c"; 572a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 573a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 574a4131561SThierry Reding pinctrl-names = "default", "idle"; 5755425fb15SMikko Perttunen status = "disabled"; 5765425fb15SMikko Perttunen }; 5775425fb15SMikko Perttunen 578a4131561SThierry Reding /* shares pads with dpaux2 */ 579a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 580d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5815425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 5825425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 5835425fb15SMikko Perttunen #address-cells = <1>; 5845425fb15SMikko Perttunen #size-cells = <0>; 5855425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 5865425fb15SMikko Perttunen clock-names = "div-clk"; 5875425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 5885425fb15SMikko Perttunen reset-names = "i2c"; 589a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 590a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 591a4131561SThierry Reding pinctrl-names = "default", "idle"; 5925425fb15SMikko Perttunen status = "disabled"; 5935425fb15SMikko Perttunen }; 5945425fb15SMikko Perttunen 595a4131561SThierry Reding /* shares pads with dpaux3 */ 596a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 597d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5985425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 5995425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 6005425fb15SMikko Perttunen #address-cells = <1>; 6015425fb15SMikko Perttunen #size-cells = <0>; 6025425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 6035425fb15SMikko Perttunen clock-names = "div-clk"; 6045425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 6055425fb15SMikko Perttunen reset-names = "i2c"; 606a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 607a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 608a4131561SThierry Reding pinctrl-names = "default", "idle"; 6095425fb15SMikko Perttunen status = "disabled"; 6105425fb15SMikko Perttunen }; 6115425fb15SMikko Perttunen 6126a574ec7SThierry Reding pwm1: pwm@3280000 { 6136a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6146a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6156a574ec7SThierry Reding reg = <0x3280000 0x10000>; 6166a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 6176a574ec7SThierry Reding clock-names = "pwm"; 6186a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 6196a574ec7SThierry Reding reset-names = "pwm"; 6206a574ec7SThierry Reding status = "disabled"; 6216a574ec7SThierry Reding #pwm-cells = <2>; 6226a574ec7SThierry Reding }; 6236a574ec7SThierry Reding 6246a574ec7SThierry Reding pwm2: pwm@3290000 { 6256a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6266a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6276a574ec7SThierry Reding reg = <0x3290000 0x10000>; 6286a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 6296a574ec7SThierry Reding clock-names = "pwm"; 6306a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 6316a574ec7SThierry Reding reset-names = "pwm"; 6326a574ec7SThierry Reding status = "disabled"; 6336a574ec7SThierry Reding #pwm-cells = <2>; 6346a574ec7SThierry Reding }; 6356a574ec7SThierry Reding 6366a574ec7SThierry Reding pwm3: pwm@32a0000 { 6376a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6386a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6396a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 6406a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 6416a574ec7SThierry Reding clock-names = "pwm"; 6426a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 6436a574ec7SThierry Reding reset-names = "pwm"; 6446a574ec7SThierry Reding status = "disabled"; 6456a574ec7SThierry Reding #pwm-cells = <2>; 6466a574ec7SThierry Reding }; 6476a574ec7SThierry Reding 6486a574ec7SThierry Reding pwm5: pwm@32c0000 { 6496a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6506a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6516a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 6526a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 6536a574ec7SThierry Reding clock-names = "pwm"; 6546a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 6556a574ec7SThierry Reding reset-names = "pwm"; 6566a574ec7SThierry Reding status = "disabled"; 6576a574ec7SThierry Reding #pwm-cells = <2>; 6586a574ec7SThierry Reding }; 6596a574ec7SThierry Reding 6606a574ec7SThierry Reding pwm6: pwm@32d0000 { 6616a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6626a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6636a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 6646a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 6656a574ec7SThierry Reding clock-names = "pwm"; 6666a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 6676a574ec7SThierry Reding reset-names = "pwm"; 6686a574ec7SThierry Reding status = "disabled"; 6696a574ec7SThierry Reding #pwm-cells = <2>; 6706a574ec7SThierry Reding }; 6716a574ec7SThierry Reding 6726a574ec7SThierry Reding pwm7: pwm@32e0000 { 6736a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6746a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6756a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 6766a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 6776a574ec7SThierry Reding clock-names = "pwm"; 6786a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 6796a574ec7SThierry Reding reset-names = "pwm"; 6806a574ec7SThierry Reding status = "disabled"; 6816a574ec7SThierry Reding #pwm-cells = <2>; 6826a574ec7SThierry Reding }; 6836a574ec7SThierry Reding 6846a574ec7SThierry Reding pwm8: pwm@32f0000 { 6856a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6866a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6876a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 6886a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 6896a574ec7SThierry Reding clock-names = "pwm"; 6906a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 6916a574ec7SThierry Reding reset-names = "pwm"; 6926a574ec7SThierry Reding status = "disabled"; 6936a574ec7SThierry Reding #pwm-cells = <2>; 6946a574ec7SThierry Reding }; 6956a574ec7SThierry Reding 69667bb17f6SThierry Reding sdmmc1: mmc@3400000 { 6972c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 6985425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 6995425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 700c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 701c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 702c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7035425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 7045425fb15SMikko Perttunen reset-names = "sdhci"; 705d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 706d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 707d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 7094e0f1229SSowjanya Komatineni <0x07>; 7104e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7114e0f1229SSowjanya Komatineni <0x07>; 7124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7134e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7144e0f1229SSowjanya Komatineni <0x07>; 7154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7174e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7184e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7195425fb15SMikko Perttunen status = "disabled"; 7205425fb15SMikko Perttunen }; 7215425fb15SMikko Perttunen 72267bb17f6SThierry Reding sdmmc3: mmc@3440000 { 7232c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7245425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 7255425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 726c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 727c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 728c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7295425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 7305425fb15SMikko Perttunen reset-names = "sdhci"; 731d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 732d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 733d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 7354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 7364e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 7374e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7384e0f1229SSowjanya Komatineni <0x07>; 7394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7414e0f1229SSowjanya Komatineni <0x07>; 7424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7434e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7444e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7454e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7465425fb15SMikko Perttunen status = "disabled"; 7475425fb15SMikko Perttunen }; 7485425fb15SMikko Perttunen 74967bb17f6SThierry Reding sdmmc4: mmc@3460000 { 7502c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7515425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 7525425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 753c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 754c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 755c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 756351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 757351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 758351648d0SSowjanya Komatineni assigned-clock-parents = 759351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 7605425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 7615425fb15SMikko Perttunen reset-names = "sdhci"; 762d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 763d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 764d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 7664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 7674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 7684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7694e0f1229SSowjanya Komatineni <0x0a>; 7704e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 7714e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7724e0f1229SSowjanya Komatineni <0x0a>; 7734e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 7744e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 7754e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 776dfd3cb6fSSowjanya Komatineni supports-cqe; 7775425fb15SMikko Perttunen status = "disabled"; 7785425fb15SMikko Perttunen }; 7795425fb15SMikko Perttunen 7804878cc0cSSameer Pujar hda@3510000 { 7814878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 7824878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 7834878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 7844878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 7854878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 7864878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 7874878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 7884878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 7894878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 7904878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 7914878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 7924878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 793d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 794d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 795d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 7964878cc0cSSameer Pujar status = "disabled"; 7974878cc0cSSameer Pujar }; 7984878cc0cSSameer Pujar 799fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 800fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 801fab7a039SJC Kuo reg = <0x03520000 0x1000>, 802fab7a039SJC Kuo <0x03540000 0x1000>; 803fab7a039SJC Kuo reg-names = "padctl", "ao"; 804fab7a039SJC Kuo 805fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 806fab7a039SJC Kuo reset-names = "padctl"; 807fab7a039SJC Kuo 808fab7a039SJC Kuo status = "disabled"; 809fab7a039SJC Kuo 810fab7a039SJC Kuo pads { 811fab7a039SJC Kuo usb2 { 812fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 813fab7a039SJC Kuo clock-names = "trk"; 814fab7a039SJC Kuo 815fab7a039SJC Kuo lanes { 816fab7a039SJC Kuo usb2-0 { 817fab7a039SJC Kuo nvidia,function = "xusb"; 818fab7a039SJC Kuo status = "disabled"; 819fab7a039SJC Kuo #phy-cells = <0>; 820fab7a039SJC Kuo }; 821fab7a039SJC Kuo 822fab7a039SJC Kuo usb2-1 { 823fab7a039SJC Kuo nvidia,function = "xusb"; 824fab7a039SJC Kuo status = "disabled"; 825fab7a039SJC Kuo #phy-cells = <0>; 826fab7a039SJC Kuo }; 827fab7a039SJC Kuo 828fab7a039SJC Kuo usb2-2 { 829fab7a039SJC Kuo nvidia,function = "xusb"; 830fab7a039SJC Kuo status = "disabled"; 831fab7a039SJC Kuo #phy-cells = <0>; 832fab7a039SJC Kuo }; 833fab7a039SJC Kuo 834fab7a039SJC Kuo usb2-3 { 835fab7a039SJC Kuo nvidia,function = "xusb"; 836fab7a039SJC Kuo status = "disabled"; 837fab7a039SJC Kuo #phy-cells = <0>; 838fab7a039SJC Kuo }; 839fab7a039SJC Kuo }; 840fab7a039SJC Kuo }; 841fab7a039SJC Kuo 842fab7a039SJC Kuo usb3 { 843fab7a039SJC Kuo lanes { 844fab7a039SJC Kuo usb3-0 { 845fab7a039SJC Kuo nvidia,function = "xusb"; 846fab7a039SJC Kuo status = "disabled"; 847fab7a039SJC Kuo #phy-cells = <0>; 848fab7a039SJC Kuo }; 849fab7a039SJC Kuo 850fab7a039SJC Kuo usb3-1 { 851fab7a039SJC Kuo nvidia,function = "xusb"; 852fab7a039SJC Kuo status = "disabled"; 853fab7a039SJC Kuo #phy-cells = <0>; 854fab7a039SJC Kuo }; 855fab7a039SJC Kuo 856fab7a039SJC Kuo usb3-2 { 857fab7a039SJC Kuo nvidia,function = "xusb"; 858fab7a039SJC Kuo status = "disabled"; 859fab7a039SJC Kuo #phy-cells = <0>; 860fab7a039SJC Kuo }; 861fab7a039SJC Kuo 862fab7a039SJC Kuo usb3-3 { 863fab7a039SJC Kuo nvidia,function = "xusb"; 864fab7a039SJC Kuo status = "disabled"; 865fab7a039SJC Kuo #phy-cells = <0>; 866fab7a039SJC Kuo }; 867fab7a039SJC Kuo }; 868fab7a039SJC Kuo }; 869fab7a039SJC Kuo }; 870fab7a039SJC Kuo 871fab7a039SJC Kuo ports { 872fab7a039SJC Kuo usb2-0 { 873fab7a039SJC Kuo status = "disabled"; 874fab7a039SJC Kuo }; 875fab7a039SJC Kuo 876fab7a039SJC Kuo usb2-1 { 877fab7a039SJC Kuo status = "disabled"; 878fab7a039SJC Kuo }; 879fab7a039SJC Kuo 880fab7a039SJC Kuo usb2-2 { 881fab7a039SJC Kuo status = "disabled"; 882fab7a039SJC Kuo }; 883fab7a039SJC Kuo 884fab7a039SJC Kuo usb2-3 { 885fab7a039SJC Kuo status = "disabled"; 886fab7a039SJC Kuo }; 887fab7a039SJC Kuo 888fab7a039SJC Kuo usb3-0 { 889fab7a039SJC Kuo status = "disabled"; 890fab7a039SJC Kuo }; 891fab7a039SJC Kuo 892fab7a039SJC Kuo usb3-1 { 893fab7a039SJC Kuo status = "disabled"; 894fab7a039SJC Kuo }; 895fab7a039SJC Kuo 896fab7a039SJC Kuo usb3-2 { 897fab7a039SJC Kuo status = "disabled"; 898fab7a039SJC Kuo }; 899fab7a039SJC Kuo 900fab7a039SJC Kuo usb3-3 { 901fab7a039SJC Kuo status = "disabled"; 902fab7a039SJC Kuo }; 903fab7a039SJC Kuo }; 904fab7a039SJC Kuo }; 905fab7a039SJC Kuo 906bc8788b2SNagarjuna Kristam usb@3550000 { 907bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 908bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 909bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 910bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 911bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 912bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 913bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 914bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 915bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 916bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 917bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 918bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 919bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 920bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 921bc8788b2SNagarjuna Kristam status = "disabled"; 922bc8788b2SNagarjuna Kristam }; 923bc8788b2SNagarjuna Kristam 924fab7a039SJC Kuo usb@3610000 { 925fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 926fab7a039SJC Kuo reg = <0x03610000 0x40000>, 927fab7a039SJC Kuo <0x03600000 0x10000>; 928fab7a039SJC Kuo reg-names = "hcd", "fpci"; 929fab7a039SJC Kuo 930fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 931a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 932fab7a039SJC Kuo 933fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 934fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 935fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 936fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 937fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 938fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 939fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 940fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 941fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 942fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 943fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 944fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 945fab7a039SJC Kuo "pll_e"; 946fab7a039SJC Kuo 947fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 948fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 949fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 950fab7a039SJC Kuo 951fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 952fab7a039SJC Kuo status = "disabled"; 953fab7a039SJC Kuo }; 954fab7a039SJC Kuo 95509903c5eSJC Kuo fuse@3820000 { 95609903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 95709903c5eSJC Kuo reg = <0x03820000 0x10000>; 95809903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 95909903c5eSJC Kuo clock-names = "fuse"; 96009903c5eSJC Kuo }; 96109903c5eSJC Kuo 9625425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 9635425fb15SMikko Perttunen compatible = "arm,gic-400"; 9645425fb15SMikko Perttunen #interrupt-cells = <3>; 9655425fb15SMikko Perttunen interrupt-controller; 9665425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 9675425fb15SMikko Perttunen <0x03882000 0x2000>, 9685425fb15SMikko Perttunen <0x03884000 0x2000>, 9695425fb15SMikko Perttunen <0x03886000 0x2000>; 9705425fb15SMikko Perttunen interrupts = <GIC_PPI 9 9715425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 9725425fb15SMikko Perttunen interrupt-parent = <&gic>; 9735425fb15SMikko Perttunen }; 9745425fb15SMikko Perttunen 975badb80beSThierry Reding cec@3960000 { 976badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 977badb80beSThierry Reding reg = <0x03960000 0x10000>; 978badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 979badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 980badb80beSThierry Reding clock-names = "cec"; 981badb80beSThierry Reding status = "disabled"; 982badb80beSThierry Reding }; 983badb80beSThierry Reding 9845425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 985a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 9865425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 987a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 988a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 989a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 990a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 991a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 992a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 993a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 994a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 995a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 996a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 997a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 998a38570c2SMikko Perttunen "shared7"; 999a38570c2SMikko Perttunen #mbox-cells = <2>; 1000a38570c2SMikko Perttunen }; 1001a38570c2SMikko Perttunen 10022602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 10032602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10042602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 10052602c32fSVidya Sagar reg-names = "ctl"; 10062602c32fSVidya Sagar 10072602c32fSVidya Sagar #phy-cells = <0>; 10082602c32fSVidya Sagar }; 10092602c32fSVidya Sagar 10102602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 10112602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10122602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 10132602c32fSVidya Sagar reg-names = "ctl"; 10142602c32fSVidya Sagar 10152602c32fSVidya Sagar #phy-cells = <0>; 10162602c32fSVidya Sagar }; 10172602c32fSVidya Sagar 10182602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 10192602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10202602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 10212602c32fSVidya Sagar reg-names = "ctl"; 10222602c32fSVidya Sagar 10232602c32fSVidya Sagar #phy-cells = <0>; 10242602c32fSVidya Sagar }; 10252602c32fSVidya Sagar 10262602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 10272602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10282602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 10292602c32fSVidya Sagar reg-names = "ctl"; 10302602c32fSVidya Sagar 10312602c32fSVidya Sagar #phy-cells = <0>; 10322602c32fSVidya Sagar }; 10332602c32fSVidya Sagar 10342602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 10352602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10362602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 10372602c32fSVidya Sagar reg-names = "ctl"; 10382602c32fSVidya Sagar 10392602c32fSVidya Sagar #phy-cells = <0>; 10402602c32fSVidya Sagar }; 10412602c32fSVidya Sagar 10422602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 10432602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10442602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 10452602c32fSVidya Sagar reg-names = "ctl"; 10462602c32fSVidya Sagar 10472602c32fSVidya Sagar #phy-cells = <0>; 10482602c32fSVidya Sagar }; 10492602c32fSVidya Sagar 10502602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 10512602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10522602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 10532602c32fSVidya Sagar reg-names = "ctl"; 10542602c32fSVidya Sagar 10552602c32fSVidya Sagar #phy-cells = <0>; 10562602c32fSVidya Sagar }; 10572602c32fSVidya Sagar 10582602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 10592602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10602602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 10612602c32fSVidya Sagar reg-names = "ctl"; 10622602c32fSVidya Sagar 10632602c32fSVidya Sagar #phy-cells = <0>; 10642602c32fSVidya Sagar }; 10652602c32fSVidya Sagar 10662602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 10672602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10682602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 10692602c32fSVidya Sagar reg-names = "ctl"; 10702602c32fSVidya Sagar 10712602c32fSVidya Sagar #phy-cells = <0>; 10722602c32fSVidya Sagar }; 10732602c32fSVidya Sagar 10742602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 10752602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10762602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 10772602c32fSVidya Sagar reg-names = "ctl"; 10782602c32fSVidya Sagar 10792602c32fSVidya Sagar #phy-cells = <0>; 10802602c32fSVidya Sagar }; 10812602c32fSVidya Sagar 10822602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 10832602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10842602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 10852602c32fSVidya Sagar reg-names = "ctl"; 10862602c32fSVidya Sagar 10872602c32fSVidya Sagar #phy-cells = <0>; 10882602c32fSVidya Sagar }; 10892602c32fSVidya Sagar 10902602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 10912602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10922602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 10932602c32fSVidya Sagar reg-names = "ctl"; 10942602c32fSVidya Sagar 10952602c32fSVidya Sagar #phy-cells = <0>; 10962602c32fSVidya Sagar }; 10972602c32fSVidya Sagar 10982602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 10992602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11002602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 11012602c32fSVidya Sagar reg-names = "ctl"; 11022602c32fSVidya Sagar 11032602c32fSVidya Sagar #phy-cells = <0>; 11042602c32fSVidya Sagar }; 11052602c32fSVidya Sagar 11062602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 11072602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11082602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 11092602c32fSVidya Sagar reg-names = "ctl"; 11102602c32fSVidya Sagar 11112602c32fSVidya Sagar #phy-cells = <0>; 11122602c32fSVidya Sagar }; 11132602c32fSVidya Sagar 11142602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 11152602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11162602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 11172602c32fSVidya Sagar reg-names = "ctl"; 11182602c32fSVidya Sagar 11192602c32fSVidya Sagar #phy-cells = <0>; 11202602c32fSVidya Sagar }; 11212602c32fSVidya Sagar 11222602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 11232602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11242602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 11252602c32fSVidya Sagar reg-names = "ctl"; 11262602c32fSVidya Sagar 11272602c32fSVidya Sagar #phy-cells = <0>; 11282602c32fSVidya Sagar }; 11292602c32fSVidya Sagar 11302602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 11312602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11322602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 11332602c32fSVidya Sagar reg-names = "ctl"; 11342602c32fSVidya Sagar 11352602c32fSVidya Sagar #phy-cells = <0>; 11362602c32fSVidya Sagar }; 11372602c32fSVidya Sagar 11382602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 11392602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11402602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 11412602c32fSVidya Sagar reg-names = "ctl"; 11422602c32fSVidya Sagar 11432602c32fSVidya Sagar #phy-cells = <0>; 11442602c32fSVidya Sagar }; 11452602c32fSVidya Sagar 11462602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 11472602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11482602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 11492602c32fSVidya Sagar reg-names = "ctl"; 11502602c32fSVidya Sagar 11512602c32fSVidya Sagar #phy-cells = <0>; 11522602c32fSVidya Sagar }; 11532602c32fSVidya Sagar 11542602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 11552602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11562602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 11572602c32fSVidya Sagar reg-names = "ctl"; 11582602c32fSVidya Sagar 11592602c32fSVidya Sagar #phy-cells = <0>; 11602602c32fSVidya Sagar }; 11612602c32fSVidya Sagar 1162a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1163a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 11641741e187SDipen Patel reg = <0x0c150000 0x90000>; 1165a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1166a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1167a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1168a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1169a38570c2SMikko Perttunen /* 1170a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1171a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1172a38570c2SMikko Perttunen */ 1173a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 11745425fb15SMikko Perttunen #mbox-cells = <2>; 11755425fb15SMikko Perttunen }; 11765425fb15SMikko Perttunen 11775425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1178d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 11795425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 11805425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 11815425fb15SMikko Perttunen #address-cells = <1>; 11825425fb15SMikko Perttunen #size-cells = <0>; 11835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 11845425fb15SMikko Perttunen clock-names = "div-clk"; 11855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 11865425fb15SMikko Perttunen reset-names = "i2c"; 11875425fb15SMikko Perttunen status = "disabled"; 11885425fb15SMikko Perttunen }; 11895425fb15SMikko Perttunen 11905425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1191d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 11925425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 11935425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 11945425fb15SMikko Perttunen #address-cells = <1>; 11955425fb15SMikko Perttunen #size-cells = <0>; 11965425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 11975425fb15SMikko Perttunen clock-names = "div-clk"; 11985425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 11995425fb15SMikko Perttunen reset-names = "i2c"; 12005425fb15SMikko Perttunen status = "disabled"; 12015425fb15SMikko Perttunen }; 12025425fb15SMikko Perttunen 12035425fb15SMikko Perttunen uartc: serial@c280000 { 12045425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12055425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 12065425fb15SMikko Perttunen reg-shift = <2>; 12075425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 12085425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 12095425fb15SMikko Perttunen clock-names = "serial"; 12105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 12115425fb15SMikko Perttunen reset-names = "serial"; 12125425fb15SMikko Perttunen status = "disabled"; 12135425fb15SMikko Perttunen }; 12145425fb15SMikko Perttunen 12155425fb15SMikko Perttunen uartg: serial@c290000 { 12165425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12175425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 12185425fb15SMikko Perttunen reg-shift = <2>; 12195425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 12205425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 12215425fb15SMikko Perttunen clock-names = "serial"; 12225425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 12235425fb15SMikko Perttunen reset-names = "serial"; 12245425fb15SMikko Perttunen status = "disabled"; 12255425fb15SMikko Perttunen }; 12265425fb15SMikko Perttunen 122737e5a31dSThierry Reding rtc: rtc@c2a0000 { 122837e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 122937e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 123037e5a31dSThierry Reding interrupt-parent = <&pmc>; 123137e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 123237e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 123337e5a31dSThierry Reding clock-names = "rtc"; 123437e5a31dSThierry Reding status = "disabled"; 123537e5a31dSThierry Reding }; 123637e5a31dSThierry Reding 12374d286331SThierry Reding gpio_aon: gpio@c2f0000 { 12384d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 12394d286331SThierry Reding reg-names = "security", "gpio"; 12404d286331SThierry Reding reg = <0xc2f0000 0x1000>, 12414d286331SThierry Reding <0xc2f1000 0x1000>; 124275b5608aSThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 12434d286331SThierry Reding gpio-controller; 12444d286331SThierry Reding #gpio-cells = <2>; 12454d286331SThierry Reding interrupt-controller; 12464d286331SThierry Reding #interrupt-cells = <2>; 12474d286331SThierry Reding }; 12484d286331SThierry Reding 12496a574ec7SThierry Reding pwm4: pwm@c340000 { 12506a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 12516a574ec7SThierry Reding "nvidia,tegra186-pwm"; 12526a574ec7SThierry Reding reg = <0xc340000 0x10000>; 12536a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 12546a574ec7SThierry Reding clock-names = "pwm"; 12556a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 12566a574ec7SThierry Reding reset-names = "pwm"; 12576a574ec7SThierry Reding status = "disabled"; 12586a574ec7SThierry Reding #pwm-cells = <2>; 12596a574ec7SThierry Reding }; 12606a574ec7SThierry Reding 126138ecf1e5SThierry Reding pmc: pmc@c360000 { 12625425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 12635425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 12645425fb15SMikko Perttunen <0x0c370000 0x10000>, 12655425fb15SMikko Perttunen <0x0c380000 0x10000>, 12665425fb15SMikko Perttunen <0x0c390000 0x10000>, 12675425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 12685425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 126938ecf1e5SThierry Reding 127038ecf1e5SThierry Reding #interrupt-cells = <2>; 127138ecf1e5SThierry Reding interrupt-controller; 12725425fb15SMikko Perttunen }; 12733db6d3baSThierry Reding 12743db6d3baSThierry Reding host1x@13e00000 { 1275ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 12763db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 12773db6d3baSThierry Reding <0x13e10000 0x10000>; 12783db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 12793db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 12803db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1281052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 12823db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 12833db6d3baSThierry Reding clock-names = "host1x"; 12843db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 12853db6d3baSThierry Reding reset-names = "host1x"; 12863db6d3baSThierry Reding 12873db6d3baSThierry Reding #address-cells = <1>; 12883db6d3baSThierry Reding #size-cells = <1>; 12893db6d3baSThierry Reding 12903db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1291d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1292d5237c7cSThierry Reding interconnect-names = "dma-mem"; 12933db6d3baSThierry Reding 12943db6d3baSThierry Reding display-hub@15200000 { 1295aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1296611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 12973db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 12983db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 12993db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 13003db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 13013db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 13023db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 13033db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 13043db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 13053db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 13063db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 13073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 13083db6d3baSThierry Reding clock-names = "disp", "hub"; 13093db6d3baSThierry Reding status = "disabled"; 13103db6d3baSThierry Reding 13113db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 13123db6d3baSThierry Reding 13133db6d3baSThierry Reding #address-cells = <1>; 13143db6d3baSThierry Reding #size-cells = <1>; 13153db6d3baSThierry Reding 13163db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 13173db6d3baSThierry Reding 13183db6d3baSThierry Reding display@15200000 { 13193db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13203db6d3baSThierry Reding reg = <0x15200000 0x10000>; 13213db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 13223db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 13233db6d3baSThierry Reding clock-names = "dc"; 13243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 13253db6d3baSThierry Reding reset-names = "dc"; 13263db6d3baSThierry Reding 13273db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1328d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1329d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1330d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13313db6d3baSThierry Reding 13323db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13333db6d3baSThierry Reding nvidia,head = <0>; 13343db6d3baSThierry Reding }; 13353db6d3baSThierry Reding 13363db6d3baSThierry Reding display@15210000 { 13373db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13383db6d3baSThierry Reding reg = <0x15210000 0x10000>; 13393db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 13403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 13413db6d3baSThierry Reding clock-names = "dc"; 13423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 13433db6d3baSThierry Reding reset-names = "dc"; 13443db6d3baSThierry Reding 13453db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1346d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1347d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1348d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13493db6d3baSThierry Reding 13503db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13513db6d3baSThierry Reding nvidia,head = <1>; 13523db6d3baSThierry Reding }; 13533db6d3baSThierry Reding 13543db6d3baSThierry Reding display@15220000 { 13553db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13563db6d3baSThierry Reding reg = <0x15220000 0x10000>; 13573db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 13583db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 13593db6d3baSThierry Reding clock-names = "dc"; 13603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 13613db6d3baSThierry Reding reset-names = "dc"; 13623db6d3baSThierry Reding 13633db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1364d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1365d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1366d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13673db6d3baSThierry Reding 13683db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13693db6d3baSThierry Reding nvidia,head = <2>; 13703db6d3baSThierry Reding }; 13713db6d3baSThierry Reding 13723db6d3baSThierry Reding display@15230000 { 13733db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 13743db6d3baSThierry Reding reg = <0x15230000 0x10000>; 13753db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 13763db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 13773db6d3baSThierry Reding clock-names = "dc"; 13783db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 13793db6d3baSThierry Reding reset-names = "dc"; 13803db6d3baSThierry Reding 13813db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1382d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1383d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1384d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 13853db6d3baSThierry Reding 13863db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 13873db6d3baSThierry Reding nvidia,head = <3>; 13883db6d3baSThierry Reding }; 13893db6d3baSThierry Reding }; 13903db6d3baSThierry Reding 13918d424ec2SThierry Reding vic@15340000 { 13928d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 13938d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 13948d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 13958d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 13968d424ec2SThierry Reding clock-names = "vic"; 13978d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 13988d424ec2SThierry Reding reset-names = "vic"; 13998d424ec2SThierry Reding 14008d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1401d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1402d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1403d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 14048d424ec2SThierry Reding }; 14058d424ec2SThierry Reding 14063db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 14073db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 14083db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 14093db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 14103db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 14113db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 14123db6d3baSThierry Reding clock-names = "dpaux", "parent"; 14133db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 14143db6d3baSThierry Reding reset-names = "dpaux"; 14153db6d3baSThierry Reding status = "disabled"; 14163db6d3baSThierry Reding 14173db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14183db6d3baSThierry Reding 14193db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 14203db6d3baSThierry Reding groups = "dpaux-io"; 14213db6d3baSThierry Reding function = "aux"; 14223db6d3baSThierry Reding }; 14233db6d3baSThierry Reding 14243db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 14253db6d3baSThierry Reding groups = "dpaux-io"; 14263db6d3baSThierry Reding function = "i2c"; 14273db6d3baSThierry Reding }; 14283db6d3baSThierry Reding 14293db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 14303db6d3baSThierry Reding groups = "dpaux-io"; 14313db6d3baSThierry Reding function = "off"; 14323db6d3baSThierry Reding }; 14333db6d3baSThierry Reding 14343db6d3baSThierry Reding i2c-bus { 14353db6d3baSThierry Reding #address-cells = <1>; 14363db6d3baSThierry Reding #size-cells = <0>; 14373db6d3baSThierry Reding }; 14383db6d3baSThierry Reding }; 14393db6d3baSThierry Reding 14403db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 14413db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 14423db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 14433db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 14443db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 14453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 14463db6d3baSThierry Reding clock-names = "dpaux", "parent"; 14473db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 14483db6d3baSThierry Reding reset-names = "dpaux"; 14493db6d3baSThierry Reding status = "disabled"; 14503db6d3baSThierry Reding 14513db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14523db6d3baSThierry Reding 14533db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 14543db6d3baSThierry Reding groups = "dpaux-io"; 14553db6d3baSThierry Reding function = "aux"; 14563db6d3baSThierry Reding }; 14573db6d3baSThierry Reding 14583db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 14593db6d3baSThierry Reding groups = "dpaux-io"; 14603db6d3baSThierry Reding function = "i2c"; 14613db6d3baSThierry Reding }; 14623db6d3baSThierry Reding 14633db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 14643db6d3baSThierry Reding groups = "dpaux-io"; 14653db6d3baSThierry Reding function = "off"; 14663db6d3baSThierry Reding }; 14673db6d3baSThierry Reding 14683db6d3baSThierry Reding i2c-bus { 14693db6d3baSThierry Reding #address-cells = <1>; 14703db6d3baSThierry Reding #size-cells = <0>; 14713db6d3baSThierry Reding }; 14723db6d3baSThierry Reding }; 14733db6d3baSThierry Reding 14743db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 14753db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 14763db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 14773db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 14783db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 14793db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 14803db6d3baSThierry Reding clock-names = "dpaux", "parent"; 14813db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 14823db6d3baSThierry Reding reset-names = "dpaux"; 14833db6d3baSThierry Reding status = "disabled"; 14843db6d3baSThierry Reding 14853db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14863db6d3baSThierry Reding 14873db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 14883db6d3baSThierry Reding groups = "dpaux-io"; 14893db6d3baSThierry Reding function = "aux"; 14903db6d3baSThierry Reding }; 14913db6d3baSThierry Reding 14923db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 14933db6d3baSThierry Reding groups = "dpaux-io"; 14943db6d3baSThierry Reding function = "i2c"; 14953db6d3baSThierry Reding }; 14963db6d3baSThierry Reding 14973db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 14983db6d3baSThierry Reding groups = "dpaux-io"; 14993db6d3baSThierry Reding function = "off"; 15003db6d3baSThierry Reding }; 15013db6d3baSThierry Reding 15023db6d3baSThierry Reding i2c-bus { 15033db6d3baSThierry Reding #address-cells = <1>; 15043db6d3baSThierry Reding #size-cells = <0>; 15053db6d3baSThierry Reding }; 15063db6d3baSThierry Reding }; 15073db6d3baSThierry Reding 15083db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 15093db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15103db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 15113db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 15123db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 15133db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15143db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15153db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 15163db6d3baSThierry Reding reset-names = "dpaux"; 15173db6d3baSThierry Reding status = "disabled"; 15183db6d3baSThierry Reding 15193db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15203db6d3baSThierry Reding 15213db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 15223db6d3baSThierry Reding groups = "dpaux-io"; 15233db6d3baSThierry Reding function = "aux"; 15243db6d3baSThierry Reding }; 15253db6d3baSThierry Reding 15263db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 15273db6d3baSThierry Reding groups = "dpaux-io"; 15283db6d3baSThierry Reding function = "i2c"; 15293db6d3baSThierry Reding }; 15303db6d3baSThierry Reding 15313db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 15323db6d3baSThierry Reding groups = "dpaux-io"; 15333db6d3baSThierry Reding function = "off"; 15343db6d3baSThierry Reding }; 15353db6d3baSThierry Reding 15363db6d3baSThierry Reding i2c-bus { 15373db6d3baSThierry Reding #address-cells = <1>; 15383db6d3baSThierry Reding #size-cells = <0>; 15393db6d3baSThierry Reding }; 15403db6d3baSThierry Reding }; 15413db6d3baSThierry Reding 15423db6d3baSThierry Reding sor0: sor@15b00000 { 15433db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 15443db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 15453db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 15463db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 15473db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 15483db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 15493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 15503db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 15513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 15523db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 15533db6d3baSThierry Reding "pad"; 15543db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 15553db6d3baSThierry Reding reset-names = "sor"; 15563db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 15573db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 15583db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 15593db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 15603db6d3baSThierry Reding status = "disabled"; 15613db6d3baSThierry Reding 15623db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15633db6d3baSThierry Reding nvidia,interface = <0>; 15643db6d3baSThierry Reding }; 15653db6d3baSThierry Reding 15663db6d3baSThierry Reding sor1: sor@15b40000 { 15673db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1568939e7430SThierry Reding reg = <0x15b40000 0x40000>; 15693db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 15703db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 15713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 15723db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 15733db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 15743db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 15753db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 15763db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 15773db6d3baSThierry Reding "pad"; 15783db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 15793db6d3baSThierry Reding reset-names = "sor"; 15803db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 15813db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 15823db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 15833db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 15843db6d3baSThierry Reding status = "disabled"; 15853db6d3baSThierry Reding 15863db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15873db6d3baSThierry Reding nvidia,interface = <1>; 15883db6d3baSThierry Reding }; 15893db6d3baSThierry Reding 15903db6d3baSThierry Reding sor2: sor@15b80000 { 15913db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 15923db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 15933db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 15943db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 15953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 15963db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 15973db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 15983db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 15993db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 16003db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16013db6d3baSThierry Reding "pad"; 16023db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 16033db6d3baSThierry Reding reset-names = "sor"; 16043db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 16053db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 16063db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 16073db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16083db6d3baSThierry Reding status = "disabled"; 16093db6d3baSThierry Reding 16103db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16113db6d3baSThierry Reding nvidia,interface = <2>; 16123db6d3baSThierry Reding }; 16133db6d3baSThierry Reding 16143db6d3baSThierry Reding sor3: sor@15bc0000 { 16153db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 16163db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 16173db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 16183db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 16193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 16203db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 16213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 16223db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 16233db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 16243db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 16253db6d3baSThierry Reding "pad"; 16263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 16273db6d3baSThierry Reding reset-names = "sor"; 16283db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 16293db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 16303db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 16313db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 16323db6d3baSThierry Reding status = "disabled"; 16333db6d3baSThierry Reding 16343db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16353db6d3baSThierry Reding nvidia,interface = <3>; 16363db6d3baSThierry Reding }; 16373db6d3baSThierry Reding }; 16380f134e39SThierry Reding 16390f134e39SThierry Reding gpu@17000000 { 16400f134e39SThierry Reding compatible = "nvidia,gv11b"; 1641818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1642818ae79aSThierry Reding <0x18000000 0x1000000>; 16430f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 16440f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 16450f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 16460f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 16470f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 16480f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 16490f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 16500f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 16510f134e39SThierry Reding reset-names = "gpu"; 16520f134e39SThierry Reding dma-coherent; 16530f134e39SThierry Reding 16540f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 16550f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 16560f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 16570f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 16580f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 16590f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 16600f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 16610f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 16620f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 16630f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 16640f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 16650f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 16660f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 16670f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 16680f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 16690f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 16700f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 16710f134e39SThierry Reding }; 16725425fb15SMikko Perttunen }; 16735425fb15SMikko Perttunen 16742602c32fSVidya Sagar pcie@14100000 { 1675f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 16762602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1677644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1678644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1679644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1680644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 16812602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 16822602c32fSVidya Sagar 16832602c32fSVidya Sagar status = "disabled"; 16842602c32fSVidya Sagar 16852602c32fSVidya Sagar #address-cells = <3>; 16862602c32fSVidya Sagar #size-cells = <2>; 16872602c32fSVidya Sagar device_type = "pci"; 16882602c32fSVidya Sagar num-lanes = <1>; 16892602c32fSVidya Sagar num-viewport = <8>; 16902602c32fSVidya Sagar linux,pci-domain = <1>; 16912602c32fSVidya Sagar 16922602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 16932602c32fSVidya Sagar clock-names = "core"; 16942602c32fSVidya Sagar 16952602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 16962602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 16972602c32fSVidya Sagar reset-names = "apb", "core"; 16982602c32fSVidya Sagar 16992602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17002602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17012602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17022602c32fSVidya Sagar 17032602c32fSVidya Sagar #interrupt-cells = <1>; 17042602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17052602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 17062602c32fSVidya Sagar 17072602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 17082602c32fSVidya Sagar 17092602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17102602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17112602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17122602c32fSVidya Sagar 17132602c32fSVidya Sagar bus-range = <0x0 0xff>; 1714d5237c7cSThierry Reding 17158a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 17168a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 17178a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1718d5237c7cSThierry Reding 1719d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1720d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1721d5237c7cSThierry Reding interconnect-names = "read", "write"; 17222602c32fSVidya Sagar }; 17232602c32fSVidya Sagar 17242602c32fSVidya Sagar pcie@14120000 { 1725f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17262602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1727644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1728644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1729644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1730644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 17312602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 17322602c32fSVidya Sagar 17332602c32fSVidya Sagar status = "disabled"; 17342602c32fSVidya Sagar 17352602c32fSVidya Sagar #address-cells = <3>; 17362602c32fSVidya Sagar #size-cells = <2>; 17372602c32fSVidya Sagar device_type = "pci"; 17382602c32fSVidya Sagar num-lanes = <1>; 17392602c32fSVidya Sagar num-viewport = <8>; 17402602c32fSVidya Sagar linux,pci-domain = <2>; 17412602c32fSVidya Sagar 17422602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 17432602c32fSVidya Sagar clock-names = "core"; 17442602c32fSVidya Sagar 17452602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 17462602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 17472602c32fSVidya Sagar reset-names = "apb", "core"; 17482602c32fSVidya Sagar 17492602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 17502602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 17512602c32fSVidya Sagar interrupt-names = "intr", "msi"; 17522602c32fSVidya Sagar 17532602c32fSVidya Sagar #interrupt-cells = <1>; 17542602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 17552602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 17562602c32fSVidya Sagar 17572602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 17582602c32fSVidya Sagar 17592602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 17602602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 17612602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 17622602c32fSVidya Sagar 17632602c32fSVidya Sagar bus-range = <0x0 0xff>; 1764d5237c7cSThierry Reding 17658a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 17668a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 17678a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1768d5237c7cSThierry Reding 1769d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1770d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1771d5237c7cSThierry Reding interconnect-names = "read", "write"; 17722602c32fSVidya Sagar }; 17732602c32fSVidya Sagar 17742602c32fSVidya Sagar pcie@14140000 { 1775f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 17762602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1777644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1778644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1779644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1780644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 17812602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 17822602c32fSVidya Sagar 17832602c32fSVidya Sagar status = "disabled"; 17842602c32fSVidya Sagar 17852602c32fSVidya Sagar #address-cells = <3>; 17862602c32fSVidya Sagar #size-cells = <2>; 17872602c32fSVidya Sagar device_type = "pci"; 17882602c32fSVidya Sagar num-lanes = <1>; 17892602c32fSVidya Sagar num-viewport = <8>; 17902602c32fSVidya Sagar linux,pci-domain = <3>; 17912602c32fSVidya Sagar 17922602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 17932602c32fSVidya Sagar clock-names = "core"; 17942602c32fSVidya Sagar 17952602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 17962602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 17972602c32fSVidya Sagar reset-names = "apb", "core"; 17982602c32fSVidya Sagar 17992602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18002602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18012602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18022602c32fSVidya Sagar 18032602c32fSVidya Sagar #interrupt-cells = <1>; 18042602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18052602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 18062602c32fSVidya Sagar 18072602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 18082602c32fSVidya Sagar 18092602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18102602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18112602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18122602c32fSVidya Sagar 18132602c32fSVidya Sagar bus-range = <0x0 0xff>; 1814d5237c7cSThierry Reding 18158a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 18168a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 18178a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1818d5237c7cSThierry Reding 1819d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1820d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1821d5237c7cSThierry Reding interconnect-names = "read", "write"; 18222602c32fSVidya Sagar }; 18232602c32fSVidya Sagar 18242602c32fSVidya Sagar pcie@14160000 { 1825f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18262602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1827644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1828644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 1829644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1830644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18312602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18322602c32fSVidya Sagar 18332602c32fSVidya Sagar status = "disabled"; 18342602c32fSVidya Sagar 18352602c32fSVidya Sagar #address-cells = <3>; 18362602c32fSVidya Sagar #size-cells = <2>; 18372602c32fSVidya Sagar device_type = "pci"; 18382602c32fSVidya Sagar num-lanes = <4>; 18392602c32fSVidya Sagar num-viewport = <8>; 18402602c32fSVidya Sagar linux,pci-domain = <4>; 18412602c32fSVidya Sagar 18422602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 18432602c32fSVidya Sagar clock-names = "core"; 18442602c32fSVidya Sagar 18452602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 18462602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 18472602c32fSVidya Sagar reset-names = "apb", "core"; 18482602c32fSVidya Sagar 18492602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18502602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18512602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18522602c32fSVidya Sagar 18532602c32fSVidya Sagar #interrupt-cells = <1>; 18542602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18552602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 18562602c32fSVidya Sagar 18572602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 18582602c32fSVidya Sagar 18592602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18602602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18612602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18622602c32fSVidya Sagar 18632602c32fSVidya Sagar bus-range = <0x0 0xff>; 1864d5237c7cSThierry Reding 18658a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 18668a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 18678a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1868d5237c7cSThierry Reding 1869d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 1870d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 1871d5237c7cSThierry Reding interconnect-names = "read", "write"; 18722602c32fSVidya Sagar }; 18732602c32fSVidya Sagar 18742602c32fSVidya Sagar pcie@14180000 { 1875f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18762602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1877644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 1878644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 1879644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1880644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18812602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18822602c32fSVidya Sagar 18832602c32fSVidya Sagar status = "disabled"; 18842602c32fSVidya Sagar 18852602c32fSVidya Sagar #address-cells = <3>; 18862602c32fSVidya Sagar #size-cells = <2>; 18872602c32fSVidya Sagar device_type = "pci"; 18882602c32fSVidya Sagar num-lanes = <8>; 18892602c32fSVidya Sagar num-viewport = <8>; 18902602c32fSVidya Sagar linux,pci-domain = <0>; 18912602c32fSVidya Sagar 18922602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 18932602c32fSVidya Sagar clock-names = "core"; 18942602c32fSVidya Sagar 18952602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 18962602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 18972602c32fSVidya Sagar reset-names = "apb", "core"; 18982602c32fSVidya Sagar 18992602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19002602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19012602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19022602c32fSVidya Sagar 19032602c32fSVidya Sagar #interrupt-cells = <1>; 19042602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19052602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 19062602c32fSVidya Sagar 19072602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 19082602c32fSVidya Sagar 19092602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19102602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19112602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19122602c32fSVidya Sagar 19132602c32fSVidya Sagar bus-range = <0x0 0xff>; 1914d5237c7cSThierry Reding 19158a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 19168a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 19178a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1918d5237c7cSThierry Reding 1919d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 1920d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 1921d5237c7cSThierry Reding interconnect-names = "read", "write"; 19222602c32fSVidya Sagar }; 19232602c32fSVidya Sagar 19242602c32fSVidya Sagar pcie@141a0000 { 1925f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19262602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1927644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 1928644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 1929644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1930644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19312602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19322602c32fSVidya Sagar 19332602c32fSVidya Sagar status = "disabled"; 19342602c32fSVidya Sagar 19352602c32fSVidya Sagar #address-cells = <3>; 19362602c32fSVidya Sagar #size-cells = <2>; 19372602c32fSVidya Sagar device_type = "pci"; 19382602c32fSVidya Sagar num-lanes = <8>; 19392602c32fSVidya Sagar num-viewport = <8>; 19402602c32fSVidya Sagar linux,pci-domain = <5>; 19412602c32fSVidya Sagar 1942dbb72e2cSVidya Sagar pinctrl-names = "default"; 1943dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1944dbb72e2cSVidya Sagar 19452602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 19462602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 19472602c32fSVidya Sagar clock-names = "core", "core_m"; 19482602c32fSVidya Sagar 19492602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 19502602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 19512602c32fSVidya Sagar reset-names = "apb", "core"; 19522602c32fSVidya Sagar 19532602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19542602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19552602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19562602c32fSVidya Sagar 19572602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 19582602c32fSVidya Sagar 19592602c32fSVidya Sagar #interrupt-cells = <1>; 19602602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19612602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 19622602c32fSVidya Sagar 19632602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19642602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19652602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19662602c32fSVidya Sagar 19672602c32fSVidya Sagar bus-range = <0x0 0xff>; 1968d5237c7cSThierry Reding 19698a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 19708a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 19718a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1972d5237c7cSThierry Reding 1973d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 1974d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 1975d5237c7cSThierry Reding interconnect-names = "read", "write"; 19762602c32fSVidya Sagar }; 19772602c32fSVidya Sagar 19780c988b73SVidya Sagar pcie_ep@14160000 { 19790c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 19800c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1981644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 1982644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1983644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 1984644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 19850c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 19860c988b73SVidya Sagar 19870c988b73SVidya Sagar status = "disabled"; 19880c988b73SVidya Sagar 19890c988b73SVidya Sagar num-lanes = <4>; 19900c988b73SVidya Sagar num-ib-windows = <2>; 19910c988b73SVidya Sagar num-ob-windows = <8>; 19920c988b73SVidya Sagar 19930c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 19940c988b73SVidya Sagar clock-names = "core"; 19950c988b73SVidya Sagar 19960c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 19970c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 19980c988b73SVidya Sagar reset-names = "apb", "core"; 19990c988b73SVidya Sagar 20000c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20010c988b73SVidya Sagar interrupt-names = "intr"; 20020c988b73SVidya Sagar 20030c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 20040c988b73SVidya Sagar 20050c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 20060c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20070c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20080c988b73SVidya Sagar }; 20090c988b73SVidya Sagar 20100c988b73SVidya Sagar pcie_ep@14180000 { 20110c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 20120c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2013644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2014644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2015644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2016644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 20170c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 20180c988b73SVidya Sagar 20190c988b73SVidya Sagar status = "disabled"; 20200c988b73SVidya Sagar 20210c988b73SVidya Sagar num-lanes = <8>; 20220c988b73SVidya Sagar num-ib-windows = <2>; 20230c988b73SVidya Sagar num-ob-windows = <8>; 20240c988b73SVidya Sagar 20250c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 20260c988b73SVidya Sagar clock-names = "core"; 20270c988b73SVidya Sagar 20280c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 20290c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 20300c988b73SVidya Sagar reset-names = "apb", "core"; 20310c988b73SVidya Sagar 20320c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20330c988b73SVidya Sagar interrupt-names = "intr"; 20340c988b73SVidya Sagar 20350c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 20360c988b73SVidya Sagar 20370c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 20380c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20390c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20400c988b73SVidya Sagar }; 20410c988b73SVidya Sagar 20420c988b73SVidya Sagar pcie_ep@141a0000 { 20430c988b73SVidya Sagar compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 20440c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2045644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2046644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2047644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2048644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 20490c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 20500c988b73SVidya Sagar 20510c988b73SVidya Sagar status = "disabled"; 20520c988b73SVidya Sagar 20530c988b73SVidya Sagar num-lanes = <8>; 20540c988b73SVidya Sagar num-ib-windows = <2>; 20550c988b73SVidya Sagar num-ob-windows = <8>; 20560c988b73SVidya Sagar 20570c988b73SVidya Sagar pinctrl-names = "default"; 20580c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 20590c988b73SVidya Sagar 20600c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 20610c988b73SVidya Sagar clock-names = "core"; 20620c988b73SVidya Sagar 20630c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 20640c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 20650c988b73SVidya Sagar reset-names = "apb", "core"; 20660c988b73SVidya Sagar 20670c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 20680c988b73SVidya Sagar interrupt-names = "intr"; 20690c988b73SVidya Sagar 20700c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 20710c988b73SVidya Sagar 20720c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 20730c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20740c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20750c988b73SVidya Sagar }; 20760c988b73SVidya Sagar 2077e867fe41SThierry Reding sram@40000000 { 20785425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 20795425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 20805425fb15SMikko Perttunen #address-cells = <1>; 20815425fb15SMikko Perttunen #size-cells = <1>; 20825425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 20835425fb15SMikko Perttunen 2084e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 20855425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 20865425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 20875425fb15SMikko Perttunen pool; 20885425fb15SMikko Perttunen }; 20895425fb15SMikko Perttunen 2090e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 20915425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 20925425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 20935425fb15SMikko Perttunen pool; 20945425fb15SMikko Perttunen }; 20955425fb15SMikko Perttunen }; 20965425fb15SMikko Perttunen 20975425fb15SMikko Perttunen bpmp: bpmp { 20985425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 20995425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 21005425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 21015425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 21025425fb15SMikko Perttunen #clock-cells = <1>; 21035425fb15SMikko Perttunen #reset-cells = <1>; 21045425fb15SMikko Perttunen #power-domain-cells = <1>; 2105d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2106d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2107d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2108d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2109d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 21105425fb15SMikko Perttunen 21115425fb15SMikko Perttunen bpmp_i2c: i2c { 21125425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 21135425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 21145425fb15SMikko Perttunen #address-cells = <1>; 21155425fb15SMikko Perttunen #size-cells = <0>; 21165425fb15SMikko Perttunen }; 21175425fb15SMikko Perttunen 21185425fb15SMikko Perttunen bpmp_thermal: thermal { 21195425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 21205425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 21215425fb15SMikko Perttunen }; 21225425fb15SMikko Perttunen }; 21235425fb15SMikko Perttunen 21247780a034SMikko Perttunen cpus { 2125d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2126d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 21277780a034SMikko Perttunen #address-cells = <1>; 21287780a034SMikko Perttunen #size-cells = <0>; 21297780a034SMikko Perttunen 2130b45d322cSThierry Reding cpu0_0: cpu@0 { 213131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21327780a034SMikko Perttunen device_type = "cpu"; 2133b45d322cSThierry Reding reg = <0x000>; 21347780a034SMikko Perttunen enable-method = "psci"; 2135b45d322cSThierry Reding i-cache-size = <131072>; 2136b45d322cSThierry Reding i-cache-line-size = <64>; 2137b45d322cSThierry Reding i-cache-sets = <512>; 2138b45d322cSThierry Reding d-cache-size = <65536>; 2139b45d322cSThierry Reding d-cache-line-size = <64>; 2140b45d322cSThierry Reding d-cache-sets = <256>; 2141b45d322cSThierry Reding next-level-cache = <&l2c_0>; 21427780a034SMikko Perttunen }; 21437780a034SMikko Perttunen 2144b45d322cSThierry Reding cpu0_1: cpu@1 { 214531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21467780a034SMikko Perttunen device_type = "cpu"; 2147b45d322cSThierry Reding reg = <0x001>; 21487780a034SMikko Perttunen enable-method = "psci"; 2149b45d322cSThierry Reding i-cache-size = <131072>; 2150b45d322cSThierry Reding i-cache-line-size = <64>; 2151b45d322cSThierry Reding i-cache-sets = <512>; 2152b45d322cSThierry Reding d-cache-size = <65536>; 2153b45d322cSThierry Reding d-cache-line-size = <64>; 2154b45d322cSThierry Reding d-cache-sets = <256>; 2155b45d322cSThierry Reding next-level-cache = <&l2c_0>; 21567780a034SMikko Perttunen }; 21577780a034SMikko Perttunen 2158b45d322cSThierry Reding cpu1_0: cpu@100 { 215931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21607780a034SMikko Perttunen device_type = "cpu"; 21617780a034SMikko Perttunen reg = <0x100>; 21627780a034SMikko Perttunen enable-method = "psci"; 2163b45d322cSThierry Reding i-cache-size = <131072>; 2164b45d322cSThierry Reding i-cache-line-size = <64>; 2165b45d322cSThierry Reding i-cache-sets = <512>; 2166b45d322cSThierry Reding d-cache-size = <65536>; 2167b45d322cSThierry Reding d-cache-line-size = <64>; 2168b45d322cSThierry Reding d-cache-sets = <256>; 2169b45d322cSThierry Reding next-level-cache = <&l2c_1>; 21707780a034SMikko Perttunen }; 21717780a034SMikko Perttunen 2172b45d322cSThierry Reding cpu1_1: cpu@101 { 217331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21747780a034SMikko Perttunen device_type = "cpu"; 21757780a034SMikko Perttunen reg = <0x101>; 21767780a034SMikko Perttunen enable-method = "psci"; 2177b45d322cSThierry Reding i-cache-size = <131072>; 2178b45d322cSThierry Reding i-cache-line-size = <64>; 2179b45d322cSThierry Reding i-cache-sets = <512>; 2180b45d322cSThierry Reding d-cache-size = <65536>; 2181b45d322cSThierry Reding d-cache-line-size = <64>; 2182b45d322cSThierry Reding d-cache-sets = <256>; 2183b45d322cSThierry Reding next-level-cache = <&l2c_1>; 21847780a034SMikko Perttunen }; 21857780a034SMikko Perttunen 2186b45d322cSThierry Reding cpu2_0: cpu@200 { 218731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 21887780a034SMikko Perttunen device_type = "cpu"; 21897780a034SMikko Perttunen reg = <0x200>; 21907780a034SMikko Perttunen enable-method = "psci"; 2191b45d322cSThierry Reding i-cache-size = <131072>; 2192b45d322cSThierry Reding i-cache-line-size = <64>; 2193b45d322cSThierry Reding i-cache-sets = <512>; 2194b45d322cSThierry Reding d-cache-size = <65536>; 2195b45d322cSThierry Reding d-cache-line-size = <64>; 2196b45d322cSThierry Reding d-cache-sets = <256>; 2197b45d322cSThierry Reding next-level-cache = <&l2c_2>; 21987780a034SMikko Perttunen }; 21997780a034SMikko Perttunen 2200b45d322cSThierry Reding cpu2_1: cpu@201 { 220131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22027780a034SMikko Perttunen device_type = "cpu"; 22037780a034SMikko Perttunen reg = <0x201>; 22047780a034SMikko Perttunen enable-method = "psci"; 2205b45d322cSThierry Reding i-cache-size = <131072>; 2206b45d322cSThierry Reding i-cache-line-size = <64>; 2207b45d322cSThierry Reding i-cache-sets = <512>; 2208b45d322cSThierry Reding d-cache-size = <65536>; 2209b45d322cSThierry Reding d-cache-line-size = <64>; 2210b45d322cSThierry Reding d-cache-sets = <256>; 2211b45d322cSThierry Reding next-level-cache = <&l2c_2>; 22127780a034SMikko Perttunen }; 22137780a034SMikko Perttunen 2214b45d322cSThierry Reding cpu3_0: cpu@300 { 221531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22167780a034SMikko Perttunen device_type = "cpu"; 2217b45d322cSThierry Reding reg = <0x300>; 22187780a034SMikko Perttunen enable-method = "psci"; 2219b45d322cSThierry Reding i-cache-size = <131072>; 2220b45d322cSThierry Reding i-cache-line-size = <64>; 2221b45d322cSThierry Reding i-cache-sets = <512>; 2222b45d322cSThierry Reding d-cache-size = <65536>; 2223b45d322cSThierry Reding d-cache-line-size = <64>; 2224b45d322cSThierry Reding d-cache-sets = <256>; 2225b45d322cSThierry Reding next-level-cache = <&l2c_3>; 22267780a034SMikko Perttunen }; 22277780a034SMikko Perttunen 2228b45d322cSThierry Reding cpu3_1: cpu@301 { 222931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 22307780a034SMikko Perttunen device_type = "cpu"; 2231b45d322cSThierry Reding reg = <0x301>; 22327780a034SMikko Perttunen enable-method = "psci"; 2233b45d322cSThierry Reding i-cache-size = <131072>; 2234b45d322cSThierry Reding i-cache-line-size = <64>; 2235b45d322cSThierry Reding i-cache-sets = <512>; 2236b45d322cSThierry Reding d-cache-size = <65536>; 2237b45d322cSThierry Reding d-cache-line-size = <64>; 2238b45d322cSThierry Reding d-cache-sets = <256>; 2239b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2240b45d322cSThierry Reding }; 2241b45d322cSThierry Reding 2242b45d322cSThierry Reding cpu-map { 2243b45d322cSThierry Reding cluster0 { 2244b45d322cSThierry Reding core0 { 2245b45d322cSThierry Reding cpu = <&cpu0_0>; 2246b45d322cSThierry Reding }; 2247b45d322cSThierry Reding 2248b45d322cSThierry Reding core1 { 2249b45d322cSThierry Reding cpu = <&cpu0_1>; 2250b45d322cSThierry Reding }; 2251b45d322cSThierry Reding }; 2252b45d322cSThierry Reding 2253b45d322cSThierry Reding cluster1 { 2254b45d322cSThierry Reding core0 { 2255b45d322cSThierry Reding cpu = <&cpu1_0>; 2256b45d322cSThierry Reding }; 2257b45d322cSThierry Reding 2258b45d322cSThierry Reding core1 { 2259b45d322cSThierry Reding cpu = <&cpu1_1>; 2260b45d322cSThierry Reding }; 2261b45d322cSThierry Reding }; 2262b45d322cSThierry Reding 2263b45d322cSThierry Reding cluster2 { 2264b45d322cSThierry Reding core0 { 2265b45d322cSThierry Reding cpu = <&cpu2_0>; 2266b45d322cSThierry Reding }; 2267b45d322cSThierry Reding 2268b45d322cSThierry Reding core1 { 2269b45d322cSThierry Reding cpu = <&cpu2_1>; 2270b45d322cSThierry Reding }; 2271b45d322cSThierry Reding }; 2272b45d322cSThierry Reding 2273b45d322cSThierry Reding cluster3 { 2274b45d322cSThierry Reding core0 { 2275b45d322cSThierry Reding cpu = <&cpu3_0>; 2276b45d322cSThierry Reding }; 2277b45d322cSThierry Reding 2278b45d322cSThierry Reding core1 { 2279b45d322cSThierry Reding cpu = <&cpu3_1>; 2280b45d322cSThierry Reding }; 2281b45d322cSThierry Reding }; 2282b45d322cSThierry Reding }; 2283b45d322cSThierry Reding 2284b45d322cSThierry Reding l2c_0: l2-cache0 { 2285b45d322cSThierry Reding cache-size = <2097152>; 2286b45d322cSThierry Reding cache-line-size = <64>; 2287b45d322cSThierry Reding cache-sets = <2048>; 2288b45d322cSThierry Reding next-level-cache = <&l3c>; 2289b45d322cSThierry Reding }; 2290b45d322cSThierry Reding 2291b45d322cSThierry Reding l2c_1: l2-cache1 { 2292b45d322cSThierry Reding cache-size = <2097152>; 2293b45d322cSThierry Reding cache-line-size = <64>; 2294b45d322cSThierry Reding cache-sets = <2048>; 2295b45d322cSThierry Reding next-level-cache = <&l3c>; 2296b45d322cSThierry Reding }; 2297b45d322cSThierry Reding 2298b45d322cSThierry Reding l2c_2: l2-cache2 { 2299b45d322cSThierry Reding cache-size = <2097152>; 2300b45d322cSThierry Reding cache-line-size = <64>; 2301b45d322cSThierry Reding cache-sets = <2048>; 2302b45d322cSThierry Reding next-level-cache = <&l3c>; 2303b45d322cSThierry Reding }; 2304b45d322cSThierry Reding 2305b45d322cSThierry Reding l2c_3: l2-cache3 { 2306b45d322cSThierry Reding cache-size = <2097152>; 2307b45d322cSThierry Reding cache-line-size = <64>; 2308b45d322cSThierry Reding cache-sets = <2048>; 2309b45d322cSThierry Reding next-level-cache = <&l3c>; 2310b45d322cSThierry Reding }; 2311b45d322cSThierry Reding 2312b45d322cSThierry Reding l3c: l3-cache { 2313b45d322cSThierry Reding cache-size = <4194304>; 2314b45d322cSThierry Reding cache-line-size = <64>; 2315b45d322cSThierry Reding cache-sets = <4096>; 23167780a034SMikko Perttunen }; 23177780a034SMikko Perttunen }; 23187780a034SMikko Perttunen 23197780a034SMikko Perttunen psci { 23207780a034SMikko Perttunen compatible = "arm,psci-1.0"; 23217780a034SMikko Perttunen status = "okay"; 23227780a034SMikko Perttunen method = "smc"; 23237780a034SMikko Perttunen }; 23247780a034SMikko Perttunen 2325a38570c2SMikko Perttunen tcu: tcu { 2326a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2327a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2328a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2329a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2330a38570c2SMikko Perttunen }; 2331a38570c2SMikko Perttunen 2332686ba009SThierry Reding thermal-zones { 2333686ba009SThierry Reding cpu { 2334686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2335686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2336686ba009SThierry Reding status = "disabled"; 2337686ba009SThierry Reding }; 2338686ba009SThierry Reding 2339686ba009SThierry Reding gpu { 2340686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2341686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2342686ba009SThierry Reding status = "disabled"; 2343686ba009SThierry Reding }; 2344686ba009SThierry Reding 2345686ba009SThierry Reding aux { 2346686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2347686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2348686ba009SThierry Reding status = "disabled"; 2349686ba009SThierry Reding }; 2350686ba009SThierry Reding 2351686ba009SThierry Reding pllx { 2352686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2353686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2354686ba009SThierry Reding status = "disabled"; 2355686ba009SThierry Reding }; 2356686ba009SThierry Reding 2357686ba009SThierry Reding ao { 2358686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2359686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2360686ba009SThierry Reding status = "disabled"; 2361686ba009SThierry Reding }; 2362686ba009SThierry Reding 2363686ba009SThierry Reding tj { 2364686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2365686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2366686ba009SThierry Reding status = "disabled"; 2367686ba009SThierry Reding }; 2368686ba009SThierry Reding }; 2369686ba009SThierry Reding 23705425fb15SMikko Perttunen timer { 23715425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 23725425fb15SMikko Perttunen interrupts = <GIC_PPI 13 23735425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 23745425fb15SMikko Perttunen <GIC_PPI 14 23755425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 23765425fb15SMikko Perttunen <GIC_PPI 11 23775425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 23785425fb15SMikko Perttunen <GIC_PPI 10 23795425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 23805425fb15SMikko Perttunen interrupt-parent = <&gic>; 2381b30be673SThierry Reding always-on; 23825425fb15SMikko Perttunen }; 23835425fb15SMikko Perttunen}; 2384