15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 370a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 380a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 44f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 450a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 460a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 52f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 530a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 540a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 60f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 610a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 620a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 68f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 690a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 700a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 84f69ce393SMikko Perttunen #interrupt-cells = <2>; 85f69ce393SMikko Perttunen interrupt-controller; 86f69ce393SMikko Perttunen #gpio-cells = <2>; 87f69ce393SMikko Perttunen gpio-controller; 88f69ce393SMikko Perttunen }; 89f69ce393SMikko Perttunen 90f89b58ceSMikko Perttunen ethernet@2490000 { 9119dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9219dc772aSThierry Reding "nvidia,tegra186-eqos", 93f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 94f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 95f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 96f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 97f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 101f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 102f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 103f89b58ceSMikko Perttunen reset-names = "eqos"; 104d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 105d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 106d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 107c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 108f89b58ceSMikko Perttunen status = "disabled"; 109f89b58ceSMikko Perttunen 110f89b58ceSMikko Perttunen snps,write-requests = <1>; 111f89b58ceSMikko Perttunen snps,read-requests = <3>; 112f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 113f89b58ceSMikko Perttunen snps,txpbl = <16>; 114f89b58ceSMikko Perttunen snps,rxpbl = <8>; 115f89b58ceSMikko Perttunen }; 116f89b58ceSMikko Perttunen 1171aaa7698SThierry Reding aconnect@2900000 { 1185d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1195d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1205d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1215d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1225d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1235d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1245d2249ddSSameer Pujar #address-cells = <1>; 1255d2249ddSSameer Pujar #size-cells = <1>; 1265d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar 129177208f7SSameer Pujar adma: dma-controller@2930000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1315d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1815d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1825d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1835d2249ddSSameer Pujar clock-names = "clk"; 1845d2249ddSSameer Pujar status = "disabled"; 1855d2249ddSSameer Pujar }; 186177208f7SSameer Pujar 187177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 188177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 189177208f7SSameer Pujar "nvidia,tegra186-ahub"; 190177208f7SSameer Pujar reg = <0x02900800 0x800>; 191177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 192177208f7SSameer Pujar clock-names = "ahub"; 193177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 194177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 195177208f7SSameer Pujar #address-cells = <1>; 196177208f7SSameer Pujar #size-cells = <1>; 197177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 198177208f7SSameer Pujar status = "disabled"; 199177208f7SSameer Pujar 200177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 201177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 202177208f7SSameer Pujar "nvidia,tegra186-admaif"; 203177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 204177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 205177208f7SSameer Pujar <&adma 2>, <&adma 2>, 206177208f7SSameer Pujar <&adma 3>, <&adma 3>, 207177208f7SSameer Pujar <&adma 4>, <&adma 4>, 208177208f7SSameer Pujar <&adma 5>, <&adma 5>, 209177208f7SSameer Pujar <&adma 6>, <&adma 6>, 210177208f7SSameer Pujar <&adma 7>, <&adma 7>, 211177208f7SSameer Pujar <&adma 8>, <&adma 8>, 212177208f7SSameer Pujar <&adma 9>, <&adma 9>, 213177208f7SSameer Pujar <&adma 10>, <&adma 10>, 214177208f7SSameer Pujar <&adma 11>, <&adma 11>, 215177208f7SSameer Pujar <&adma 12>, <&adma 12>, 216177208f7SSameer Pujar <&adma 13>, <&adma 13>, 217177208f7SSameer Pujar <&adma 14>, <&adma 14>, 218177208f7SSameer Pujar <&adma 15>, <&adma 15>, 219177208f7SSameer Pujar <&adma 16>, <&adma 16>, 220177208f7SSameer Pujar <&adma 17>, <&adma 17>, 221177208f7SSameer Pujar <&adma 18>, <&adma 18>, 222177208f7SSameer Pujar <&adma 19>, <&adma 19>, 223177208f7SSameer Pujar <&adma 20>, <&adma 20>; 224177208f7SSameer Pujar dma-names = "rx1", "tx1", 225177208f7SSameer Pujar "rx2", "tx2", 226177208f7SSameer Pujar "rx3", "tx3", 227177208f7SSameer Pujar "rx4", "tx4", 228177208f7SSameer Pujar "rx5", "tx5", 229177208f7SSameer Pujar "rx6", "tx6", 230177208f7SSameer Pujar "rx7", "tx7", 231177208f7SSameer Pujar "rx8", "tx8", 232177208f7SSameer Pujar "rx9", "tx9", 233177208f7SSameer Pujar "rx10", "tx10", 234177208f7SSameer Pujar "rx11", "tx11", 235177208f7SSameer Pujar "rx12", "tx12", 236177208f7SSameer Pujar "rx13", "tx13", 237177208f7SSameer Pujar "rx14", "tx14", 238177208f7SSameer Pujar "rx15", "tx15", 239177208f7SSameer Pujar "rx16", "tx16", 240177208f7SSameer Pujar "rx17", "tx17", 241177208f7SSameer Pujar "rx18", "tx18", 242177208f7SSameer Pujar "rx19", "tx19", 243177208f7SSameer Pujar "rx20", "tx20"; 244177208f7SSameer Pujar status = "disabled"; 245177208f7SSameer Pujar }; 246177208f7SSameer Pujar 247177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 248177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 249177208f7SSameer Pujar "nvidia,tegra210-i2s"; 250177208f7SSameer Pujar reg = <0x2901000 0x100>; 251177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 252177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 253177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 254177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 255177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256177208f7SSameer Pujar assigned-clock-rates = <1536000>; 257177208f7SSameer Pujar sound-name-prefix = "I2S1"; 258177208f7SSameer Pujar status = "disabled"; 259177208f7SSameer Pujar }; 260177208f7SSameer Pujar 261177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 262177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 263177208f7SSameer Pujar "nvidia,tegra210-i2s"; 264177208f7SSameer Pujar reg = <0x2901100 0x100>; 265177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 266177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 267177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 268177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 269177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270177208f7SSameer Pujar assigned-clock-rates = <1536000>; 271177208f7SSameer Pujar sound-name-prefix = "I2S2"; 272177208f7SSameer Pujar status = "disabled"; 273177208f7SSameer Pujar }; 274177208f7SSameer Pujar 275177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 276177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 277177208f7SSameer Pujar "nvidia,tegra210-i2s"; 278177208f7SSameer Pujar reg = <0x2901200 0x100>; 279177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 280177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 281177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 282177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 283177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284177208f7SSameer Pujar assigned-clock-rates = <1536000>; 285177208f7SSameer Pujar sound-name-prefix = "I2S3"; 286177208f7SSameer Pujar status = "disabled"; 287177208f7SSameer Pujar }; 288177208f7SSameer Pujar 289177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 290177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 291177208f7SSameer Pujar "nvidia,tegra210-i2s"; 292177208f7SSameer Pujar reg = <0x2901300 0x100>; 293177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 294177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 295177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 296177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 297177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 298177208f7SSameer Pujar assigned-clock-rates = <1536000>; 299177208f7SSameer Pujar sound-name-prefix = "I2S4"; 300177208f7SSameer Pujar status = "disabled"; 301177208f7SSameer Pujar }; 302177208f7SSameer Pujar 303177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 304177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 305177208f7SSameer Pujar "nvidia,tegra210-i2s"; 306177208f7SSameer Pujar reg = <0x2901400 0x100>; 307177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 308177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 309177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 310177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 311177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 312177208f7SSameer Pujar assigned-clock-rates = <1536000>; 313177208f7SSameer Pujar sound-name-prefix = "I2S5"; 314177208f7SSameer Pujar status = "disabled"; 315177208f7SSameer Pujar }; 316177208f7SSameer Pujar 317177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 318177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 319177208f7SSameer Pujar "nvidia,tegra210-i2s"; 320177208f7SSameer Pujar reg = <0x2901500 0x100>; 321177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 322177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 323177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 324177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 325177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326177208f7SSameer Pujar assigned-clock-rates = <1536000>; 327177208f7SSameer Pujar sound-name-prefix = "I2S6"; 328177208f7SSameer Pujar status = "disabled"; 329177208f7SSameer Pujar }; 330177208f7SSameer Pujar 331177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 332177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 333177208f7SSameer Pujar "nvidia,tegra210-dmic"; 334177208f7SSameer Pujar reg = <0x2904000 0x100>; 335177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 336177208f7SSameer Pujar clock-names = "dmic"; 337177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 338177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339177208f7SSameer Pujar assigned-clock-rates = <3072000>; 340177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 341177208f7SSameer Pujar status = "disabled"; 342177208f7SSameer Pujar }; 343177208f7SSameer Pujar 344177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 345177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 346177208f7SSameer Pujar "nvidia,tegra210-dmic"; 347177208f7SSameer Pujar reg = <0x2904100 0x100>; 348177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 349177208f7SSameer Pujar clock-names = "dmic"; 350177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 351177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 352177208f7SSameer Pujar assigned-clock-rates = <3072000>; 353177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 354177208f7SSameer Pujar status = "disabled"; 355177208f7SSameer Pujar }; 356177208f7SSameer Pujar 357177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 358177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 359177208f7SSameer Pujar "nvidia,tegra210-dmic"; 360177208f7SSameer Pujar reg = <0x2904200 0x100>; 361177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 362177208f7SSameer Pujar clock-names = "dmic"; 363177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 364177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 365177208f7SSameer Pujar assigned-clock-rates = <3072000>; 366177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 367177208f7SSameer Pujar status = "disabled"; 368177208f7SSameer Pujar }; 369177208f7SSameer Pujar 370177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 371177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 372177208f7SSameer Pujar "nvidia,tegra210-dmic"; 373177208f7SSameer Pujar reg = <0x2904300 0x100>; 374177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 375177208f7SSameer Pujar clock-names = "dmic"; 376177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 377177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 378177208f7SSameer Pujar assigned-clock-rates = <3072000>; 379177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 380177208f7SSameer Pujar status = "disabled"; 381177208f7SSameer Pujar }; 382177208f7SSameer Pujar 383177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 384177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 385177208f7SSameer Pujar "nvidia,tegra186-dspk"; 386177208f7SSameer Pujar reg = <0x2905000 0x100>; 387177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 388177208f7SSameer Pujar clock-names = "dspk"; 389177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 390177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 391177208f7SSameer Pujar assigned-clock-rates = <12288000>; 392177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 393177208f7SSameer Pujar status = "disabled"; 394177208f7SSameer Pujar }; 395177208f7SSameer Pujar 396177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 397177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 398177208f7SSameer Pujar "nvidia,tegra186-dspk"; 399177208f7SSameer Pujar reg = <0x2905100 0x100>; 400177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 401177208f7SSameer Pujar clock-names = "dspk"; 402177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 403177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 404177208f7SSameer Pujar assigned-clock-rates = <12288000>; 405177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 406177208f7SSameer Pujar status = "disabled"; 407177208f7SSameer Pujar }; 408848f3290SSameer Pujar 409848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 410848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 411848f3290SSameer Pujar "nvidia,tegra210-sfc"; 412848f3290SSameer Pujar reg = <0x2902000 0x200>; 413848f3290SSameer Pujar sound-name-prefix = "SFC1"; 414848f3290SSameer Pujar status = "disabled"; 415848f3290SSameer Pujar }; 416848f3290SSameer Pujar 417848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 418848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 419848f3290SSameer Pujar "nvidia,tegra210-sfc"; 420848f3290SSameer Pujar reg = <0x2902200 0x200>; 421848f3290SSameer Pujar sound-name-prefix = "SFC2"; 422848f3290SSameer Pujar status = "disabled"; 423848f3290SSameer Pujar }; 424848f3290SSameer Pujar 425848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 426848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 427848f3290SSameer Pujar "nvidia,tegra210-sfc"; 428848f3290SSameer Pujar reg = <0x2902400 0x200>; 429848f3290SSameer Pujar sound-name-prefix = "SFC3"; 430848f3290SSameer Pujar status = "disabled"; 431848f3290SSameer Pujar }; 432848f3290SSameer Pujar 433848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 434848f3290SSameer Pujar compatible = "nvidia,tegra194-sfc", 435848f3290SSameer Pujar "nvidia,tegra210-sfc"; 436848f3290SSameer Pujar reg = <0x2902600 0x200>; 437848f3290SSameer Pujar sound-name-prefix = "SFC4"; 438848f3290SSameer Pujar status = "disabled"; 439848f3290SSameer Pujar }; 440848f3290SSameer Pujar 441848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 442848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 443848f3290SSameer Pujar "nvidia,tegra210-mvc"; 444848f3290SSameer Pujar reg = <0x290a000 0x200>; 445848f3290SSameer Pujar sound-name-prefix = "MVC1"; 446848f3290SSameer Pujar status = "disabled"; 447848f3290SSameer Pujar }; 448848f3290SSameer Pujar 449848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 450848f3290SSameer Pujar compatible = "nvidia,tegra194-mvc", 451848f3290SSameer Pujar "nvidia,tegra210-mvc"; 452848f3290SSameer Pujar reg = <0x290a200 0x200>; 453848f3290SSameer Pujar sound-name-prefix = "MVC2"; 454848f3290SSameer Pujar status = "disabled"; 455848f3290SSameer Pujar }; 456848f3290SSameer Pujar 457848f3290SSameer Pujar tegra_amx1: amx@2903000 { 458848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 459848f3290SSameer Pujar reg = <0x2903000 0x100>; 460848f3290SSameer Pujar sound-name-prefix = "AMX1"; 461848f3290SSameer Pujar status = "disabled"; 462848f3290SSameer Pujar }; 463848f3290SSameer Pujar 464848f3290SSameer Pujar tegra_amx2: amx@2903100 { 465848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 466848f3290SSameer Pujar reg = <0x2903100 0x100>; 467848f3290SSameer Pujar sound-name-prefix = "AMX2"; 468848f3290SSameer Pujar status = "disabled"; 469848f3290SSameer Pujar }; 470848f3290SSameer Pujar 471848f3290SSameer Pujar tegra_amx3: amx@2903200 { 472848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 473848f3290SSameer Pujar reg = <0x2903200 0x100>; 474848f3290SSameer Pujar sound-name-prefix = "AMX3"; 475848f3290SSameer Pujar status = "disabled"; 476848f3290SSameer Pujar }; 477848f3290SSameer Pujar 478848f3290SSameer Pujar tegra_amx4: amx@2903300 { 479848f3290SSameer Pujar compatible = "nvidia,tegra194-amx"; 480848f3290SSameer Pujar reg = <0x2903300 0x100>; 481848f3290SSameer Pujar sound-name-prefix = "AMX4"; 482848f3290SSameer Pujar status = "disabled"; 483848f3290SSameer Pujar }; 484848f3290SSameer Pujar 485848f3290SSameer Pujar tegra_adx1: adx@2903800 { 486848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 487848f3290SSameer Pujar "nvidia,tegra210-adx"; 488848f3290SSameer Pujar reg = <0x2903800 0x100>; 489848f3290SSameer Pujar sound-name-prefix = "ADX1"; 490848f3290SSameer Pujar status = "disabled"; 491848f3290SSameer Pujar }; 492848f3290SSameer Pujar 493848f3290SSameer Pujar tegra_adx2: adx@2903900 { 494848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 495848f3290SSameer Pujar "nvidia,tegra210-adx"; 496848f3290SSameer Pujar reg = <0x2903900 0x100>; 497848f3290SSameer Pujar sound-name-prefix = "ADX2"; 498848f3290SSameer Pujar status = "disabled"; 499848f3290SSameer Pujar }; 500848f3290SSameer Pujar 501848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 502848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 503848f3290SSameer Pujar "nvidia,tegra210-adx"; 504848f3290SSameer Pujar reg = <0x2903a00 0x100>; 505848f3290SSameer Pujar sound-name-prefix = "ADX3"; 506848f3290SSameer Pujar status = "disabled"; 507848f3290SSameer Pujar }; 508848f3290SSameer Pujar 509848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 510848f3290SSameer Pujar compatible = "nvidia,tegra194-adx", 511848f3290SSameer Pujar "nvidia,tegra210-adx"; 512848f3290SSameer Pujar reg = <0x2903b00 0x100>; 513848f3290SSameer Pujar sound-name-prefix = "ADX4"; 514848f3290SSameer Pujar status = "disabled"; 515848f3290SSameer Pujar }; 516848f3290SSameer Pujar 517848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 518848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 519848f3290SSameer Pujar "nvidia,tegra210-amixer"; 520848f3290SSameer Pujar reg = <0x290bb00 0x800>; 521848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 522848f3290SSameer Pujar status = "disabled"; 523848f3290SSameer Pujar }; 524177208f7SSameer Pujar }; 5255d2249ddSSameer Pujar }; 5265d2249ddSSameer Pujar 527dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 528dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 529644c569dSThierry Reding reg = <0x2430000 0x17000>, 530644c569dSThierry Reding <0xc300000 0x4000>; 531dbb72e2cSVidya Sagar 532dbb72e2cSVidya Sagar status = "okay"; 533dbb72e2cSVidya Sagar 534dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 535dbb72e2cSVidya Sagar pex_rst { 536dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 537dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 538dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 539dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5406b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 541dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 542dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 543dbb72e2cSVidya Sagar }; 544dbb72e2cSVidya Sagar }; 545dbb72e2cSVidya Sagar 546dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 547dbb72e2cSVidya Sagar clkreq { 548dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 549dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 550dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 551dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5526b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 553dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 554dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555dbb72e2cSVidya Sagar }; 556dbb72e2cSVidya Sagar }; 557dbb72e2cSVidya Sagar }; 558dbb72e2cSVidya Sagar 559be9b887fSThierry Reding mc: memory-controller@2c00000 { 560be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 561be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 562be9b887fSThierry Reding <0x02b80000 0x040000>, 563be9b887fSThierry Reding <0x01700000 0x100000>; 5648613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565d5237c7cSThierry Reding #interconnect-cells = <1>; 566be9b887fSThierry Reding status = "disabled"; 567be9b887fSThierry Reding 568be9b887fSThierry Reding #address-cells = <2>; 569be9b887fSThierry Reding #size-cells = <2>; 570be9b887fSThierry Reding 571be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 572be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 573be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 574be9b887fSThierry Reding 575be9b887fSThierry Reding /* 576be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 577be9b887fSThierry Reding * controller selects the XBAR format used when memory 578be9b887fSThierry Reding * is accessed. This is used to transparently access 579be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 580be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 581be9b887fSThierry Reding * 582be9b887fSThierry Reding * As a consequence, the operating system must ensure 583be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 584be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 585be9b887fSThierry Reding * devices require access to the XBAR switch, their 586be9b887fSThierry Reding * drivers must set this bit explicitly. 587be9b887fSThierry Reding * 588be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 589be9b887fSThierry Reding */ 590be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 591be9b887fSThierry Reding 592be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 593be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 594be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 595be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 596be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 597be9b887fSThierry Reding clock-names = "emc"; 598be9b887fSThierry Reding 599d5237c7cSThierry Reding #interconnect-cells = <0>; 600d5237c7cSThierry Reding 601be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 602be9b887fSThierry Reding }; 603be9b887fSThierry Reding }; 604be9b887fSThierry Reding 6055425fb15SMikko Perttunen uarta: serial@3100000 { 6065425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6075425fb15SMikko Perttunen reg = <0x03100000 0x40>; 6085425fb15SMikko Perttunen reg-shift = <2>; 6095425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 6105425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 6115425fb15SMikko Perttunen clock-names = "serial"; 6125425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 6135425fb15SMikko Perttunen reset-names = "serial"; 6145425fb15SMikko Perttunen status = "disabled"; 6155425fb15SMikko Perttunen }; 6165425fb15SMikko Perttunen 6175425fb15SMikko Perttunen uartb: serial@3110000 { 6185425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6195425fb15SMikko Perttunen reg = <0x03110000 0x40>; 6205425fb15SMikko Perttunen reg-shift = <2>; 6215425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 6225425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 6235425fb15SMikko Perttunen clock-names = "serial"; 6245425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 6255425fb15SMikko Perttunen reset-names = "serial"; 6265425fb15SMikko Perttunen status = "disabled"; 6275425fb15SMikko Perttunen }; 6285425fb15SMikko Perttunen 6295425fb15SMikko Perttunen uartd: serial@3130000 { 6305425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6315425fb15SMikko Perttunen reg = <0x03130000 0x40>; 6325425fb15SMikko Perttunen reg-shift = <2>; 6335425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 6345425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 6355425fb15SMikko Perttunen clock-names = "serial"; 6365425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 6375425fb15SMikko Perttunen reset-names = "serial"; 6385425fb15SMikko Perttunen status = "disabled"; 6395425fb15SMikko Perttunen }; 6405425fb15SMikko Perttunen 6415425fb15SMikko Perttunen uarte: serial@3140000 { 6425425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6435425fb15SMikko Perttunen reg = <0x03140000 0x40>; 6445425fb15SMikko Perttunen reg-shift = <2>; 6455425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 6465425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 6475425fb15SMikko Perttunen clock-names = "serial"; 6485425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 6495425fb15SMikko Perttunen reset-names = "serial"; 6505425fb15SMikko Perttunen status = "disabled"; 6515425fb15SMikko Perttunen }; 6525425fb15SMikko Perttunen 6535425fb15SMikko Perttunen uartf: serial@3150000 { 6545425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6555425fb15SMikko Perttunen reg = <0x03150000 0x40>; 6565425fb15SMikko Perttunen reg-shift = <2>; 6575425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 6585425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 6595425fb15SMikko Perttunen clock-names = "serial"; 6605425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 6615425fb15SMikko Perttunen reset-names = "serial"; 6625425fb15SMikko Perttunen status = "disabled"; 6635425fb15SMikko Perttunen }; 6645425fb15SMikko Perttunen 6655425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 666d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6675425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 6685425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 6695425fb15SMikko Perttunen #address-cells = <1>; 6705425fb15SMikko Perttunen #size-cells = <0>; 6715425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 6725425fb15SMikko Perttunen clock-names = "div-clk"; 6735425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 6745425fb15SMikko Perttunen reset-names = "i2c"; 6755425fb15SMikko Perttunen status = "disabled"; 6765425fb15SMikko Perttunen }; 6775425fb15SMikko Perttunen 6785425fb15SMikko Perttunen uarth: serial@3170000 { 6795425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 6805425fb15SMikko Perttunen reg = <0x03170000 0x40>; 6815425fb15SMikko Perttunen reg-shift = <2>; 6825425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 6835425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 6845425fb15SMikko Perttunen clock-names = "serial"; 6855425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 6865425fb15SMikko Perttunen reset-names = "serial"; 6875425fb15SMikko Perttunen status = "disabled"; 6885425fb15SMikko Perttunen }; 6895425fb15SMikko Perttunen 6905425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 691d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6925425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 6935425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 6945425fb15SMikko Perttunen #address-cells = <1>; 6955425fb15SMikko Perttunen #size-cells = <0>; 6965425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 6975425fb15SMikko Perttunen clock-names = "div-clk"; 6985425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 6995425fb15SMikko Perttunen reset-names = "i2c"; 7005425fb15SMikko Perttunen status = "disabled"; 7015425fb15SMikko Perttunen }; 7025425fb15SMikko Perttunen 7035425fb15SMikko Perttunen /* shares pads with dpaux1 */ 7045425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 705d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7065425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 7075425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 7085425fb15SMikko Perttunen #address-cells = <1>; 7095425fb15SMikko Perttunen #size-cells = <0>; 7105425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 7115425fb15SMikko Perttunen clock-names = "div-clk"; 7125425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 7135425fb15SMikko Perttunen reset-names = "i2c"; 714a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 715a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 716a4131561SThierry Reding pinctrl-names = "default", "idle"; 7175425fb15SMikko Perttunen status = "disabled"; 7185425fb15SMikko Perttunen }; 7195425fb15SMikko Perttunen 7205425fb15SMikko Perttunen /* shares pads with dpaux0 */ 7215425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 722d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7235425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 7245425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7255425fb15SMikko Perttunen #address-cells = <1>; 7265425fb15SMikko Perttunen #size-cells = <0>; 7275425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 7285425fb15SMikko Perttunen clock-names = "div-clk"; 7295425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 7305425fb15SMikko Perttunen reset-names = "i2c"; 731a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 732a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 733a4131561SThierry Reding pinctrl-names = "default", "idle"; 7345425fb15SMikko Perttunen status = "disabled"; 7355425fb15SMikko Perttunen }; 7365425fb15SMikko Perttunen 737a4131561SThierry Reding /* shares pads with dpaux2 */ 738a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 739d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7405425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 7415425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 7425425fb15SMikko Perttunen #address-cells = <1>; 7435425fb15SMikko Perttunen #size-cells = <0>; 7445425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 7455425fb15SMikko Perttunen clock-names = "div-clk"; 7465425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 7475425fb15SMikko Perttunen reset-names = "i2c"; 748a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 749a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 750a4131561SThierry Reding pinctrl-names = "default", "idle"; 7515425fb15SMikko Perttunen status = "disabled"; 7525425fb15SMikko Perttunen }; 7535425fb15SMikko Perttunen 754a4131561SThierry Reding /* shares pads with dpaux3 */ 755a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 756d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7575425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 7585425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 7595425fb15SMikko Perttunen #address-cells = <1>; 7605425fb15SMikko Perttunen #size-cells = <0>; 7615425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 7625425fb15SMikko Perttunen clock-names = "div-clk"; 7635425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 7645425fb15SMikko Perttunen reset-names = "i2c"; 765a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 766a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 767a4131561SThierry Reding pinctrl-names = "default", "idle"; 7685425fb15SMikko Perttunen status = "disabled"; 7695425fb15SMikko Perttunen }; 7705425fb15SMikko Perttunen 77196ded827SSowjanya Komatineni spi@3270000 { 77296ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 77396ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 77496ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 77596ded827SSowjanya Komatineni #address-cells = <1>; 77696ded827SSowjanya Komatineni #size-cells = <0>; 77796ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 77896ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 77996ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 78096ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 78196ded827SSowjanya Komatineni reset-names = "qspi"; 78296ded827SSowjanya Komatineni status = "disabled"; 78396ded827SSowjanya Komatineni }; 78496ded827SSowjanya Komatineni 78596ded827SSowjanya Komatineni spi@3300000 { 78696ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 78796ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 78896ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 78996ded827SSowjanya Komatineni #address-cells = <1>; 79096ded827SSowjanya Komatineni #size-cells = <0>; 79196ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 79296ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 79396ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 79496ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 79596ded827SSowjanya Komatineni reset-names = "qspi"; 79696ded827SSowjanya Komatineni status = "disabled"; 79796ded827SSowjanya Komatineni }; 79896ded827SSowjanya Komatineni 7996a574ec7SThierry Reding pwm1: pwm@3280000 { 8006a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8016a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8026a574ec7SThierry Reding reg = <0x3280000 0x10000>; 8036a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 8046a574ec7SThierry Reding clock-names = "pwm"; 8056a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 8066a574ec7SThierry Reding reset-names = "pwm"; 8076a574ec7SThierry Reding status = "disabled"; 8086a574ec7SThierry Reding #pwm-cells = <2>; 8096a574ec7SThierry Reding }; 8106a574ec7SThierry Reding 8116a574ec7SThierry Reding pwm2: pwm@3290000 { 8126a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8136a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8146a574ec7SThierry Reding reg = <0x3290000 0x10000>; 8156a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 8166a574ec7SThierry Reding clock-names = "pwm"; 8176a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 8186a574ec7SThierry Reding reset-names = "pwm"; 8196a574ec7SThierry Reding status = "disabled"; 8206a574ec7SThierry Reding #pwm-cells = <2>; 8216a574ec7SThierry Reding }; 8226a574ec7SThierry Reding 8236a574ec7SThierry Reding pwm3: pwm@32a0000 { 8246a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8256a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8266a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 8276a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 8286a574ec7SThierry Reding clock-names = "pwm"; 8296a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 8306a574ec7SThierry Reding reset-names = "pwm"; 8316a574ec7SThierry Reding status = "disabled"; 8326a574ec7SThierry Reding #pwm-cells = <2>; 8336a574ec7SThierry Reding }; 8346a574ec7SThierry Reding 8356a574ec7SThierry Reding pwm5: pwm@32c0000 { 8366a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8376a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8386a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 8396a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 8406a574ec7SThierry Reding clock-names = "pwm"; 8416a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 8426a574ec7SThierry Reding reset-names = "pwm"; 8436a574ec7SThierry Reding status = "disabled"; 8446a574ec7SThierry Reding #pwm-cells = <2>; 8456a574ec7SThierry Reding }; 8466a574ec7SThierry Reding 8476a574ec7SThierry Reding pwm6: pwm@32d0000 { 8486a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8496a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8506a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 8516a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 8526a574ec7SThierry Reding clock-names = "pwm"; 8536a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 8546a574ec7SThierry Reding reset-names = "pwm"; 8556a574ec7SThierry Reding status = "disabled"; 8566a574ec7SThierry Reding #pwm-cells = <2>; 8576a574ec7SThierry Reding }; 8586a574ec7SThierry Reding 8596a574ec7SThierry Reding pwm7: pwm@32e0000 { 8606a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8616a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8626a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 8636a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 8646a574ec7SThierry Reding clock-names = "pwm"; 8656a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 8666a574ec7SThierry Reding reset-names = "pwm"; 8676a574ec7SThierry Reding status = "disabled"; 8686a574ec7SThierry Reding #pwm-cells = <2>; 8696a574ec7SThierry Reding }; 8706a574ec7SThierry Reding 8716a574ec7SThierry Reding pwm8: pwm@32f0000 { 8726a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8736a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8746a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 8756a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 8766a574ec7SThierry Reding clock-names = "pwm"; 8776a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 8786a574ec7SThierry Reding reset-names = "pwm"; 8796a574ec7SThierry Reding status = "disabled"; 8806a574ec7SThierry Reding #pwm-cells = <2>; 8816a574ec7SThierry Reding }; 8826a574ec7SThierry Reding 88367bb17f6SThierry Reding sdmmc1: mmc@3400000 { 8842c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 8855425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 8865425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 887c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 888c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 889c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8905425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 8915425fb15SMikko Perttunen reset-names = "sdhci"; 892d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 893d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 894d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 895c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 8964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 8974e0f1229SSowjanya Komatineni <0x07>; 8984e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 8994e0f1229SSowjanya Komatineni <0x07>; 9004e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9014e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9024e0f1229SSowjanya Komatineni <0x07>; 9034e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9044e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9054e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9064e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 9075425fb15SMikko Perttunen status = "disabled"; 9085425fb15SMikko Perttunen }; 9095425fb15SMikko Perttunen 91067bb17f6SThierry Reding sdmmc3: mmc@3440000 { 9112c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9125425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 9135425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 914c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 915c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 916c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9175425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 9185425fb15SMikko Perttunen reset-names = "sdhci"; 919d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 920d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 921d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 922c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 9234e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 9244e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 9254e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 9264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9274e0f1229SSowjanya Komatineni <0x07>; 9284e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 9294e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9304e0f1229SSowjanya Komatineni <0x07>; 9314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 9324e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 9334e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 9344e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 9355425fb15SMikko Perttunen status = "disabled"; 9365425fb15SMikko Perttunen }; 9375425fb15SMikko Perttunen 93867bb17f6SThierry Reding sdmmc4: mmc@3460000 { 9392c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 9405425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 9415425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 942c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 943c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 944c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 945351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 946351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 947351648d0SSowjanya Komatineni assigned-clock-parents = 948351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 9495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 9505425fb15SMikko Perttunen reset-names = "sdhci"; 951d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 952d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 953d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 954c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 9554e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 9564e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 9574e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 9584e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 9594e0f1229SSowjanya Komatineni <0x0a>; 9604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9614e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 9624e0f1229SSowjanya Komatineni <0x0a>; 9634e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 9644e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 9654e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 966dfd3cb6fSSowjanya Komatineni supports-cqe; 9675425fb15SMikko Perttunen status = "disabled"; 9685425fb15SMikko Perttunen }; 9695425fb15SMikko Perttunen 9704878cc0cSSameer Pujar hda@3510000 { 9714878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 9724878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 9734878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 9744878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 97548f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 97648f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 97748f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 9784878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 979*146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 980*146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 9814878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 982d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 983d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 984d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 985c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 9864878cc0cSSameer Pujar status = "disabled"; 9874878cc0cSSameer Pujar }; 9884878cc0cSSameer Pujar 989fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 990fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 991fab7a039SJC Kuo reg = <0x03520000 0x1000>, 992fab7a039SJC Kuo <0x03540000 0x1000>; 993fab7a039SJC Kuo reg-names = "padctl", "ao"; 9946450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 995fab7a039SJC Kuo 996fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 997fab7a039SJC Kuo reset-names = "padctl"; 998fab7a039SJC Kuo 999fab7a039SJC Kuo status = "disabled"; 1000fab7a039SJC Kuo 1001fab7a039SJC Kuo pads { 1002fab7a039SJC Kuo usb2 { 1003fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1004fab7a039SJC Kuo clock-names = "trk"; 1005fab7a039SJC Kuo 1006fab7a039SJC Kuo lanes { 1007fab7a039SJC Kuo usb2-0 { 1008fab7a039SJC Kuo nvidia,function = "xusb"; 1009fab7a039SJC Kuo status = "disabled"; 1010fab7a039SJC Kuo #phy-cells = <0>; 1011fab7a039SJC Kuo }; 1012fab7a039SJC Kuo 1013fab7a039SJC Kuo usb2-1 { 1014fab7a039SJC Kuo nvidia,function = "xusb"; 1015fab7a039SJC Kuo status = "disabled"; 1016fab7a039SJC Kuo #phy-cells = <0>; 1017fab7a039SJC Kuo }; 1018fab7a039SJC Kuo 1019fab7a039SJC Kuo usb2-2 { 1020fab7a039SJC Kuo nvidia,function = "xusb"; 1021fab7a039SJC Kuo status = "disabled"; 1022fab7a039SJC Kuo #phy-cells = <0>; 1023fab7a039SJC Kuo }; 1024fab7a039SJC Kuo 1025fab7a039SJC Kuo usb2-3 { 1026fab7a039SJC Kuo nvidia,function = "xusb"; 1027fab7a039SJC Kuo status = "disabled"; 1028fab7a039SJC Kuo #phy-cells = <0>; 1029fab7a039SJC Kuo }; 1030fab7a039SJC Kuo }; 1031fab7a039SJC Kuo }; 1032fab7a039SJC Kuo 1033fab7a039SJC Kuo usb3 { 1034fab7a039SJC Kuo lanes { 1035fab7a039SJC Kuo usb3-0 { 1036fab7a039SJC Kuo nvidia,function = "xusb"; 1037fab7a039SJC Kuo status = "disabled"; 1038fab7a039SJC Kuo #phy-cells = <0>; 1039fab7a039SJC Kuo }; 1040fab7a039SJC Kuo 1041fab7a039SJC Kuo usb3-1 { 1042fab7a039SJC Kuo nvidia,function = "xusb"; 1043fab7a039SJC Kuo status = "disabled"; 1044fab7a039SJC Kuo #phy-cells = <0>; 1045fab7a039SJC Kuo }; 1046fab7a039SJC Kuo 1047fab7a039SJC Kuo usb3-2 { 1048fab7a039SJC Kuo nvidia,function = "xusb"; 1049fab7a039SJC Kuo status = "disabled"; 1050fab7a039SJC Kuo #phy-cells = <0>; 1051fab7a039SJC Kuo }; 1052fab7a039SJC Kuo 1053fab7a039SJC Kuo usb3-3 { 1054fab7a039SJC Kuo nvidia,function = "xusb"; 1055fab7a039SJC Kuo status = "disabled"; 1056fab7a039SJC Kuo #phy-cells = <0>; 1057fab7a039SJC Kuo }; 1058fab7a039SJC Kuo }; 1059fab7a039SJC Kuo }; 1060fab7a039SJC Kuo }; 1061fab7a039SJC Kuo 1062fab7a039SJC Kuo ports { 1063fab7a039SJC Kuo usb2-0 { 1064fab7a039SJC Kuo status = "disabled"; 1065fab7a039SJC Kuo }; 1066fab7a039SJC Kuo 1067fab7a039SJC Kuo usb2-1 { 1068fab7a039SJC Kuo status = "disabled"; 1069fab7a039SJC Kuo }; 1070fab7a039SJC Kuo 1071fab7a039SJC Kuo usb2-2 { 1072fab7a039SJC Kuo status = "disabled"; 1073fab7a039SJC Kuo }; 1074fab7a039SJC Kuo 1075fab7a039SJC Kuo usb2-3 { 1076fab7a039SJC Kuo status = "disabled"; 1077fab7a039SJC Kuo }; 1078fab7a039SJC Kuo 1079fab7a039SJC Kuo usb3-0 { 1080fab7a039SJC Kuo status = "disabled"; 1081fab7a039SJC Kuo }; 1082fab7a039SJC Kuo 1083fab7a039SJC Kuo usb3-1 { 1084fab7a039SJC Kuo status = "disabled"; 1085fab7a039SJC Kuo }; 1086fab7a039SJC Kuo 1087fab7a039SJC Kuo usb3-2 { 1088fab7a039SJC Kuo status = "disabled"; 1089fab7a039SJC Kuo }; 1090fab7a039SJC Kuo 1091fab7a039SJC Kuo usb3-3 { 1092fab7a039SJC Kuo status = "disabled"; 1093fab7a039SJC Kuo }; 1094fab7a039SJC Kuo }; 1095fab7a039SJC Kuo }; 1096fab7a039SJC Kuo 1097bc8788b2SNagarjuna Kristam usb@3550000 { 1098bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 1099bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 1100bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 1101bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1102bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1103bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1104bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1105bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1106bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1107bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1108c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1109c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1110c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1111c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1112bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1113bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1114bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1115bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1116bc8788b2SNagarjuna Kristam status = "disabled"; 1117bc8788b2SNagarjuna Kristam }; 1118bc8788b2SNagarjuna Kristam 1119fab7a039SJC Kuo usb@3610000 { 1120fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1121fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1122fab7a039SJC Kuo <0x03600000 0x10000>; 1123fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1124fab7a039SJC Kuo 1125fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1126a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1127fab7a039SJC Kuo 1128fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1129fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1130fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1131fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1132fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1133fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1134fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1135fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1136fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1137fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1138fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1139fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1140fab7a039SJC Kuo "pll_e"; 1141c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1142c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1143c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1144c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1145fab7a039SJC Kuo 1146fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1147fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1148fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1149fab7a039SJC Kuo 1150fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1151fab7a039SJC Kuo status = "disabled"; 1152fab7a039SJC Kuo }; 1153fab7a039SJC Kuo 115409903c5eSJC Kuo fuse@3820000 { 115509903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 115609903c5eSJC Kuo reg = <0x03820000 0x10000>; 115709903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 115809903c5eSJC Kuo clock-names = "fuse"; 115909903c5eSJC Kuo }; 116009903c5eSJC Kuo 11615425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 11625425fb15SMikko Perttunen compatible = "arm,gic-400"; 11635425fb15SMikko Perttunen #interrupt-cells = <3>; 11645425fb15SMikko Perttunen interrupt-controller; 11655425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 11665425fb15SMikko Perttunen <0x03882000 0x2000>, 11675425fb15SMikko Perttunen <0x03884000 0x2000>, 11685425fb15SMikko Perttunen <0x03886000 0x2000>; 11695425fb15SMikko Perttunen interrupts = <GIC_PPI 9 11705425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 11715425fb15SMikko Perttunen interrupt-parent = <&gic>; 11725425fb15SMikko Perttunen }; 11735425fb15SMikko Perttunen 1174badb80beSThierry Reding cec@3960000 { 1175badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1176badb80beSThierry Reding reg = <0x03960000 0x10000>; 1177badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1178badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1179badb80beSThierry Reding clock-names = "cec"; 1180badb80beSThierry Reding status = "disabled"; 1181badb80beSThierry Reding }; 1182badb80beSThierry Reding 11835425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1184a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 11855425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1186a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1187a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1188a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1189a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1190a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1191a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1192a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1193a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1194a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1195a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1196a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1197a38570c2SMikko Perttunen "shared7"; 1198a38570c2SMikko Perttunen #mbox-cells = <2>; 1199a38570c2SMikko Perttunen }; 1200a38570c2SMikko Perttunen 12012602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 12022602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12032602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 12042602c32fSVidya Sagar reg-names = "ctl"; 12052602c32fSVidya Sagar 12062602c32fSVidya Sagar #phy-cells = <0>; 12072602c32fSVidya Sagar }; 12082602c32fSVidya Sagar 12092602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 12102602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12112602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 12122602c32fSVidya Sagar reg-names = "ctl"; 12132602c32fSVidya Sagar 12142602c32fSVidya Sagar #phy-cells = <0>; 12152602c32fSVidya Sagar }; 12162602c32fSVidya Sagar 12172602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 12182602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12192602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 12202602c32fSVidya Sagar reg-names = "ctl"; 12212602c32fSVidya Sagar 12222602c32fSVidya Sagar #phy-cells = <0>; 12232602c32fSVidya Sagar }; 12242602c32fSVidya Sagar 12252602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 12262602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12272602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 12282602c32fSVidya Sagar reg-names = "ctl"; 12292602c32fSVidya Sagar 12302602c32fSVidya Sagar #phy-cells = <0>; 12312602c32fSVidya Sagar }; 12322602c32fSVidya Sagar 12332602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 12342602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12352602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 12362602c32fSVidya Sagar reg-names = "ctl"; 12372602c32fSVidya Sagar 12382602c32fSVidya Sagar #phy-cells = <0>; 12392602c32fSVidya Sagar }; 12402602c32fSVidya Sagar 12412602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 12422602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12432602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 12442602c32fSVidya Sagar reg-names = "ctl"; 12452602c32fSVidya Sagar 12462602c32fSVidya Sagar #phy-cells = <0>; 12472602c32fSVidya Sagar }; 12482602c32fSVidya Sagar 12492602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 12502602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12512602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 12522602c32fSVidya Sagar reg-names = "ctl"; 12532602c32fSVidya Sagar 12542602c32fSVidya Sagar #phy-cells = <0>; 12552602c32fSVidya Sagar }; 12562602c32fSVidya Sagar 12572602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 12582602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12592602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 12602602c32fSVidya Sagar reg-names = "ctl"; 12612602c32fSVidya Sagar 12622602c32fSVidya Sagar #phy-cells = <0>; 12632602c32fSVidya Sagar }; 12642602c32fSVidya Sagar 12652602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 12662602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12672602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 12682602c32fSVidya Sagar reg-names = "ctl"; 12692602c32fSVidya Sagar 12702602c32fSVidya Sagar #phy-cells = <0>; 12712602c32fSVidya Sagar }; 12722602c32fSVidya Sagar 12732602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 12742602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12752602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 12762602c32fSVidya Sagar reg-names = "ctl"; 12772602c32fSVidya Sagar 12782602c32fSVidya Sagar #phy-cells = <0>; 12792602c32fSVidya Sagar }; 12802602c32fSVidya Sagar 12812602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 12822602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12832602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 12842602c32fSVidya Sagar reg-names = "ctl"; 12852602c32fSVidya Sagar 12862602c32fSVidya Sagar #phy-cells = <0>; 12872602c32fSVidya Sagar }; 12882602c32fSVidya Sagar 12892602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 12902602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12912602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 12922602c32fSVidya Sagar reg-names = "ctl"; 12932602c32fSVidya Sagar 12942602c32fSVidya Sagar #phy-cells = <0>; 12952602c32fSVidya Sagar }; 12962602c32fSVidya Sagar 12972602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 12982602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12992602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 13002602c32fSVidya Sagar reg-names = "ctl"; 13012602c32fSVidya Sagar 13022602c32fSVidya Sagar #phy-cells = <0>; 13032602c32fSVidya Sagar }; 13042602c32fSVidya Sagar 13052602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 13062602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13072602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 13082602c32fSVidya Sagar reg-names = "ctl"; 13092602c32fSVidya Sagar 13102602c32fSVidya Sagar #phy-cells = <0>; 13112602c32fSVidya Sagar }; 13122602c32fSVidya Sagar 13132602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 13142602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13152602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 13162602c32fSVidya Sagar reg-names = "ctl"; 13172602c32fSVidya Sagar 13182602c32fSVidya Sagar #phy-cells = <0>; 13192602c32fSVidya Sagar }; 13202602c32fSVidya Sagar 13212602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 13222602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13232602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 13242602c32fSVidya Sagar reg-names = "ctl"; 13252602c32fSVidya Sagar 13262602c32fSVidya Sagar #phy-cells = <0>; 13272602c32fSVidya Sagar }; 13282602c32fSVidya Sagar 13292602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 13302602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13312602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 13322602c32fSVidya Sagar reg-names = "ctl"; 13332602c32fSVidya Sagar 13342602c32fSVidya Sagar #phy-cells = <0>; 13352602c32fSVidya Sagar }; 13362602c32fSVidya Sagar 13372602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 13382602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13392602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 13402602c32fSVidya Sagar reg-names = "ctl"; 13412602c32fSVidya Sagar 13422602c32fSVidya Sagar #phy-cells = <0>; 13432602c32fSVidya Sagar }; 13442602c32fSVidya Sagar 13452602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 13462602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13472602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 13482602c32fSVidya Sagar reg-names = "ctl"; 13492602c32fSVidya Sagar 13502602c32fSVidya Sagar #phy-cells = <0>; 13512602c32fSVidya Sagar }; 13522602c32fSVidya Sagar 13532602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 13542602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13552602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 13562602c32fSVidya Sagar reg-names = "ctl"; 13572602c32fSVidya Sagar 13582602c32fSVidya Sagar #phy-cells = <0>; 13592602c32fSVidya Sagar }; 13602602c32fSVidya Sagar 1361a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1362a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 13631741e187SDipen Patel reg = <0x0c150000 0x90000>; 1364a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1365a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1366a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1367a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1368a38570c2SMikko Perttunen /* 1369a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1370a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1371a38570c2SMikko Perttunen */ 1372a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 13735425fb15SMikko Perttunen #mbox-cells = <2>; 13745425fb15SMikko Perttunen }; 13755425fb15SMikko Perttunen 13765425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1377d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 13785425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 13795425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 13805425fb15SMikko Perttunen #address-cells = <1>; 13815425fb15SMikko Perttunen #size-cells = <0>; 13825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 13835425fb15SMikko Perttunen clock-names = "div-clk"; 13845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 13855425fb15SMikko Perttunen reset-names = "i2c"; 13865425fb15SMikko Perttunen status = "disabled"; 13875425fb15SMikko Perttunen }; 13885425fb15SMikko Perttunen 13895425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1390d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 13915425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 13925425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 13935425fb15SMikko Perttunen #address-cells = <1>; 13945425fb15SMikko Perttunen #size-cells = <0>; 13955425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 13965425fb15SMikko Perttunen clock-names = "div-clk"; 13975425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 13985425fb15SMikko Perttunen reset-names = "i2c"; 13995425fb15SMikko Perttunen status = "disabled"; 14005425fb15SMikko Perttunen }; 14015425fb15SMikko Perttunen 14025425fb15SMikko Perttunen uartc: serial@c280000 { 14035425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14045425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 14055425fb15SMikko Perttunen reg-shift = <2>; 14065425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 14075425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 14085425fb15SMikko Perttunen clock-names = "serial"; 14095425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 14105425fb15SMikko Perttunen reset-names = "serial"; 14115425fb15SMikko Perttunen status = "disabled"; 14125425fb15SMikko Perttunen }; 14135425fb15SMikko Perttunen 14145425fb15SMikko Perttunen uartg: serial@c290000 { 14155425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 14165425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 14175425fb15SMikko Perttunen reg-shift = <2>; 14185425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 14195425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 14205425fb15SMikko Perttunen clock-names = "serial"; 14215425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 14225425fb15SMikko Perttunen reset-names = "serial"; 14235425fb15SMikko Perttunen status = "disabled"; 14245425fb15SMikko Perttunen }; 14255425fb15SMikko Perttunen 142637e5a31dSThierry Reding rtc: rtc@c2a0000 { 142737e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 142837e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 142937e5a31dSThierry Reding interrupt-parent = <&pmc>; 143037e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 143137e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 143237e5a31dSThierry Reding clock-names = "rtc"; 143337e5a31dSThierry Reding status = "disabled"; 143437e5a31dSThierry Reding }; 143537e5a31dSThierry Reding 14364d286331SThierry Reding gpio_aon: gpio@c2f0000 { 14374d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 14384d286331SThierry Reding reg-names = "security", "gpio"; 14394d286331SThierry Reding reg = <0xc2f0000 0x1000>, 14404d286331SThierry Reding <0xc2f1000 0x1000>; 14410a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 14420a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 14430a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 14440a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 14454d286331SThierry Reding gpio-controller; 14464d286331SThierry Reding #gpio-cells = <2>; 14474d286331SThierry Reding interrupt-controller; 14484d286331SThierry Reding #interrupt-cells = <2>; 14494d286331SThierry Reding }; 14504d286331SThierry Reding 14516a574ec7SThierry Reding pwm4: pwm@c340000 { 14526a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 14536a574ec7SThierry Reding "nvidia,tegra186-pwm"; 14546a574ec7SThierry Reding reg = <0xc340000 0x10000>; 14556a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 14566a574ec7SThierry Reding clock-names = "pwm"; 14576a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 14586a574ec7SThierry Reding reset-names = "pwm"; 14596a574ec7SThierry Reding status = "disabled"; 14606a574ec7SThierry Reding #pwm-cells = <2>; 14616a574ec7SThierry Reding }; 14626a574ec7SThierry Reding 146338ecf1e5SThierry Reding pmc: pmc@c360000 { 14645425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 14655425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 14665425fb15SMikko Perttunen <0x0c370000 0x10000>, 14675425fb15SMikko Perttunen <0x0c380000 0x10000>, 14685425fb15SMikko Perttunen <0x0c390000 0x10000>, 14695425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 14705425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 147138ecf1e5SThierry Reding 147238ecf1e5SThierry Reding #interrupt-cells = <2>; 147338ecf1e5SThierry Reding interrupt-controller; 14745425fb15SMikko Perttunen }; 14753db6d3baSThierry Reding 1476c7289b1cSThierry Reding smmu: iommu@12000000 { 1477c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1478c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1479c7289b1cSThierry Reding <0x11000000 0x800000>; 1480c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1482c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1509c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1510c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1511c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1512c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1513c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1514c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1515c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1516c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1517c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1518c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1519c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1520c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1521c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1522c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1523c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1524c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1525c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1526c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1527c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1528c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1529c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1530c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1531c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1532c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1533c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1534c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1535c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1536c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1537c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1538c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1539c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1540c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1541c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1542c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1543c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1544c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1545c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1546c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1547c7289b1cSThierry Reding #global-interrupts = <2>; 1548c7289b1cSThierry Reding #iommu-cells = <1>; 1549c7289b1cSThierry Reding 1550c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1551c7289b1cSThierry Reding status = "okay"; 1552c7289b1cSThierry Reding }; 1553c7289b1cSThierry Reding 15543db6d3baSThierry Reding host1x@13e00000 { 1555ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 15563db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 15573db6d3baSThierry Reding <0x13e10000 0x10000>; 15583db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 15593db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 15603db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1561052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 15623db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 15633db6d3baSThierry Reding clock-names = "host1x"; 15643db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 15653db6d3baSThierry Reding reset-names = "host1x"; 15663db6d3baSThierry Reding 15673db6d3baSThierry Reding #address-cells = <1>; 15683db6d3baSThierry Reding #size-cells = <1>; 15693db6d3baSThierry Reding 15703db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1571d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1572d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1573c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 15743db6d3baSThierry Reding 157578a05873SMikko Perttunen nvdec@15140000 { 157678a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 157778a05873SMikko Perttunen reg = <0x15140000 0x00040000>; 157878a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 157978a05873SMikko Perttunen clock-names = "nvdec"; 158078a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 158178a05873SMikko Perttunen reset-names = "nvdec"; 158278a05873SMikko Perttunen 158378a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 158478a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 158578a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 158678a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 158778a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 158878a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 158978a05873SMikko Perttunen dma-coherent; 159078a05873SMikko Perttunen 159178a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 159278a05873SMikko Perttunen }; 159378a05873SMikko Perttunen 15943db6d3baSThierry Reding display-hub@15200000 { 1595aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1596611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 15973db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 15983db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 15993db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 16003db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 16013db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 16023db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 16033db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 16043db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 16053db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 16063db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 16073db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 16083db6d3baSThierry Reding clock-names = "disp", "hub"; 16093db6d3baSThierry Reding status = "disabled"; 16103db6d3baSThierry Reding 16113db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16123db6d3baSThierry Reding 16133db6d3baSThierry Reding #address-cells = <1>; 16143db6d3baSThierry Reding #size-cells = <1>; 16153db6d3baSThierry Reding 16163db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 16173db6d3baSThierry Reding 16183db6d3baSThierry Reding display@15200000 { 16193db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 16203db6d3baSThierry Reding reg = <0x15200000 0x10000>; 16213db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 16223db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 16233db6d3baSThierry Reding clock-names = "dc"; 16243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 16253db6d3baSThierry Reding reset-names = "dc"; 16263db6d3baSThierry Reding 16273db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1628d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1629d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1630d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 16313db6d3baSThierry Reding 16323db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 16333db6d3baSThierry Reding nvidia,head = <0>; 16343db6d3baSThierry Reding }; 16353db6d3baSThierry Reding 16363db6d3baSThierry Reding display@15210000 { 16373db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 16383db6d3baSThierry Reding reg = <0x15210000 0x10000>; 16393db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 16403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 16413db6d3baSThierry Reding clock-names = "dc"; 16423db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 16433db6d3baSThierry Reding reset-names = "dc"; 16443db6d3baSThierry Reding 16453db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1646d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1647d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1648d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 16493db6d3baSThierry Reding 16503db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 16513db6d3baSThierry Reding nvidia,head = <1>; 16523db6d3baSThierry Reding }; 16533db6d3baSThierry Reding 16543db6d3baSThierry Reding display@15220000 { 16553db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 16563db6d3baSThierry Reding reg = <0x15220000 0x10000>; 16573db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 16583db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 16593db6d3baSThierry Reding clock-names = "dc"; 16603db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 16613db6d3baSThierry Reding reset-names = "dc"; 16623db6d3baSThierry Reding 16633db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1664d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1665d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1666d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 16673db6d3baSThierry Reding 16683db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 16693db6d3baSThierry Reding nvidia,head = <2>; 16703db6d3baSThierry Reding }; 16713db6d3baSThierry Reding 16723db6d3baSThierry Reding display@15230000 { 16733db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 16743db6d3baSThierry Reding reg = <0x15230000 0x10000>; 16753db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 16763db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 16773db6d3baSThierry Reding clock-names = "dc"; 16783db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 16793db6d3baSThierry Reding reset-names = "dc"; 16803db6d3baSThierry Reding 16813db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1682d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1683d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1684d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 16853db6d3baSThierry Reding 16863db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 16873db6d3baSThierry Reding nvidia,head = <3>; 16883db6d3baSThierry Reding }; 16893db6d3baSThierry Reding }; 16903db6d3baSThierry Reding 16918d424ec2SThierry Reding vic@15340000 { 16928d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 16938d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 16948d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 16958d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 16968d424ec2SThierry Reding clock-names = "vic"; 16978d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 16988d424ec2SThierry Reding reset-names = "vic"; 16998d424ec2SThierry Reding 17008d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1701d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1702d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1703d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1704c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 17058d424ec2SThierry Reding }; 17068d424ec2SThierry Reding 170778a05873SMikko Perttunen nvdec@15480000 { 170878a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 170978a05873SMikko Perttunen reg = <0x15480000 0x00040000>; 171078a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 171178a05873SMikko Perttunen clock-names = "nvdec"; 171278a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 171378a05873SMikko Perttunen reset-names = "nvdec"; 171478a05873SMikko Perttunen 171578a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 171678a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 171778a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 171878a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 171978a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 172078a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 172178a05873SMikko Perttunen dma-coherent; 172278a05873SMikko Perttunen 172378a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 172478a05873SMikko Perttunen }; 172578a05873SMikko Perttunen 17263db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 17273db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 17283db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 17293db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 17303db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 17313db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 17323db6d3baSThierry Reding clock-names = "dpaux", "parent"; 17333db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 17343db6d3baSThierry Reding reset-names = "dpaux"; 17353db6d3baSThierry Reding status = "disabled"; 17363db6d3baSThierry Reding 17373db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17383db6d3baSThierry Reding 17393db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 17403db6d3baSThierry Reding groups = "dpaux-io"; 17413db6d3baSThierry Reding function = "aux"; 17423db6d3baSThierry Reding }; 17433db6d3baSThierry Reding 17443db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 17453db6d3baSThierry Reding groups = "dpaux-io"; 17463db6d3baSThierry Reding function = "i2c"; 17473db6d3baSThierry Reding }; 17483db6d3baSThierry Reding 17493db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 17503db6d3baSThierry Reding groups = "dpaux-io"; 17513db6d3baSThierry Reding function = "off"; 17523db6d3baSThierry Reding }; 17533db6d3baSThierry Reding 17543db6d3baSThierry Reding i2c-bus { 17553db6d3baSThierry Reding #address-cells = <1>; 17563db6d3baSThierry Reding #size-cells = <0>; 17573db6d3baSThierry Reding }; 17583db6d3baSThierry Reding }; 17593db6d3baSThierry Reding 17603db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 17613db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 17623db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 17633db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 17643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 17653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 17663db6d3baSThierry Reding clock-names = "dpaux", "parent"; 17673db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 17683db6d3baSThierry Reding reset-names = "dpaux"; 17693db6d3baSThierry Reding status = "disabled"; 17703db6d3baSThierry Reding 17713db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17723db6d3baSThierry Reding 17733db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 17743db6d3baSThierry Reding groups = "dpaux-io"; 17753db6d3baSThierry Reding function = "aux"; 17763db6d3baSThierry Reding }; 17773db6d3baSThierry Reding 17783db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 17793db6d3baSThierry Reding groups = "dpaux-io"; 17803db6d3baSThierry Reding function = "i2c"; 17813db6d3baSThierry Reding }; 17823db6d3baSThierry Reding 17833db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 17843db6d3baSThierry Reding groups = "dpaux-io"; 17853db6d3baSThierry Reding function = "off"; 17863db6d3baSThierry Reding }; 17873db6d3baSThierry Reding 17883db6d3baSThierry Reding i2c-bus { 17893db6d3baSThierry Reding #address-cells = <1>; 17903db6d3baSThierry Reding #size-cells = <0>; 17913db6d3baSThierry Reding }; 17923db6d3baSThierry Reding }; 17933db6d3baSThierry Reding 17943db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 17953db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 17963db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 17973db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 17983db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 17993db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 18003db6d3baSThierry Reding clock-names = "dpaux", "parent"; 18013db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 18023db6d3baSThierry Reding reset-names = "dpaux"; 18033db6d3baSThierry Reding status = "disabled"; 18043db6d3baSThierry Reding 18053db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18063db6d3baSThierry Reding 18073db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 18083db6d3baSThierry Reding groups = "dpaux-io"; 18093db6d3baSThierry Reding function = "aux"; 18103db6d3baSThierry Reding }; 18113db6d3baSThierry Reding 18123db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 18133db6d3baSThierry Reding groups = "dpaux-io"; 18143db6d3baSThierry Reding function = "i2c"; 18153db6d3baSThierry Reding }; 18163db6d3baSThierry Reding 18173db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 18183db6d3baSThierry Reding groups = "dpaux-io"; 18193db6d3baSThierry Reding function = "off"; 18203db6d3baSThierry Reding }; 18213db6d3baSThierry Reding 18223db6d3baSThierry Reding i2c-bus { 18233db6d3baSThierry Reding #address-cells = <1>; 18243db6d3baSThierry Reding #size-cells = <0>; 18253db6d3baSThierry Reding }; 18263db6d3baSThierry Reding }; 18273db6d3baSThierry Reding 18283db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 18293db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 18303db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 18313db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 18323db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 18333db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 18343db6d3baSThierry Reding clock-names = "dpaux", "parent"; 18353db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 18363db6d3baSThierry Reding reset-names = "dpaux"; 18373db6d3baSThierry Reding status = "disabled"; 18383db6d3baSThierry Reding 18393db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18403db6d3baSThierry Reding 18413db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 18423db6d3baSThierry Reding groups = "dpaux-io"; 18433db6d3baSThierry Reding function = "aux"; 18443db6d3baSThierry Reding }; 18453db6d3baSThierry Reding 18463db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 18473db6d3baSThierry Reding groups = "dpaux-io"; 18483db6d3baSThierry Reding function = "i2c"; 18493db6d3baSThierry Reding }; 18503db6d3baSThierry Reding 18513db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 18523db6d3baSThierry Reding groups = "dpaux-io"; 18533db6d3baSThierry Reding function = "off"; 18543db6d3baSThierry Reding }; 18553db6d3baSThierry Reding 18563db6d3baSThierry Reding i2c-bus { 18573db6d3baSThierry Reding #address-cells = <1>; 18583db6d3baSThierry Reding #size-cells = <0>; 18593db6d3baSThierry Reding }; 18603db6d3baSThierry Reding }; 18613db6d3baSThierry Reding 18623db6d3baSThierry Reding sor0: sor@15b00000 { 18633db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 18643db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 18653db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 18663db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 18673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 18683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 18693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 18703db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 18713db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 18723db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 18733db6d3baSThierry Reding "pad"; 18743db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 18753db6d3baSThierry Reding reset-names = "sor"; 18763db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 18773db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 18783db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 18793db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 18803db6d3baSThierry Reding status = "disabled"; 18813db6d3baSThierry Reding 18823db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18833db6d3baSThierry Reding nvidia,interface = <0>; 18843db6d3baSThierry Reding }; 18853db6d3baSThierry Reding 18863db6d3baSThierry Reding sor1: sor@15b40000 { 18873db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1888939e7430SThierry Reding reg = <0x15b40000 0x40000>; 18893db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 18903db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 18913db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 18923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 18933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 18943db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 18953db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 18963db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 18973db6d3baSThierry Reding "pad"; 18983db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 18993db6d3baSThierry Reding reset-names = "sor"; 19003db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 19013db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 19023db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 19033db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 19043db6d3baSThierry Reding status = "disabled"; 19053db6d3baSThierry Reding 19063db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19073db6d3baSThierry Reding nvidia,interface = <1>; 19083db6d3baSThierry Reding }; 19093db6d3baSThierry Reding 19103db6d3baSThierry Reding sor2: sor@15b80000 { 19113db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 19123db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 19133db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 19143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 19153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 19163db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 19173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 19183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 19193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 19203db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 19213db6d3baSThierry Reding "pad"; 19223db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 19233db6d3baSThierry Reding reset-names = "sor"; 19243db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 19253db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 19263db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 19273db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 19283db6d3baSThierry Reding status = "disabled"; 19293db6d3baSThierry Reding 19303db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19313db6d3baSThierry Reding nvidia,interface = <2>; 19323db6d3baSThierry Reding }; 19333db6d3baSThierry Reding 19343db6d3baSThierry Reding sor3: sor@15bc0000 { 19353db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 19363db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 19373db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 19383db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 19393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 19403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 19413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 19423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 19433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 19443db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 19453db6d3baSThierry Reding "pad"; 19463db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 19473db6d3baSThierry Reding reset-names = "sor"; 19483db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 19493db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 19503db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 19513db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 19523db6d3baSThierry Reding status = "disabled"; 19533db6d3baSThierry Reding 19543db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19553db6d3baSThierry Reding nvidia,interface = <3>; 19563db6d3baSThierry Reding }; 19573db6d3baSThierry Reding }; 19580f134e39SThierry Reding 19590f134e39SThierry Reding gpu@17000000 { 19600f134e39SThierry Reding compatible = "nvidia,gv11b"; 1961818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1962818ae79aSThierry Reding <0x18000000 0x1000000>; 19630f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 19640f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 19650f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 19660f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 19670f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 19680f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 19690f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 19700f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 19710f134e39SThierry Reding reset-names = "gpu"; 19720f134e39SThierry Reding dma-coherent; 19730f134e39SThierry Reding 19740f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 19750f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 19760f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 19770f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 19780f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 19790f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 19800f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 19810f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 19820f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 19830f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 19840f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 19850f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 19860f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 19870f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 19880f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 19890f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 19900f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 19910f134e39SThierry Reding }; 19925425fb15SMikko Perttunen }; 19935425fb15SMikko Perttunen 19942602c32fSVidya Sagar pcie@14100000 { 1995f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19962602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1997644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1998644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1999644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2000644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20012602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20022602c32fSVidya Sagar 20032602c32fSVidya Sagar status = "disabled"; 20042602c32fSVidya Sagar 20052602c32fSVidya Sagar #address-cells = <3>; 20062602c32fSVidya Sagar #size-cells = <2>; 20072602c32fSVidya Sagar device_type = "pci"; 20082602c32fSVidya Sagar num-lanes = <1>; 20092602c32fSVidya Sagar num-viewport = <8>; 20102602c32fSVidya Sagar linux,pci-domain = <1>; 20112602c32fSVidya Sagar 20122602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 20132602c32fSVidya Sagar clock-names = "core"; 20142602c32fSVidya Sagar 20152602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 20162602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 20172602c32fSVidya Sagar reset-names = "apb", "core"; 20182602c32fSVidya Sagar 20192602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20202602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20212602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20222602c32fSVidya Sagar 20232602c32fSVidya Sagar #interrupt-cells = <1>; 20242602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 20252602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 20262602c32fSVidya Sagar 20272602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 20282602c32fSVidya Sagar 20292602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 20302602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20312602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20322602c32fSVidya Sagar 20332602c32fSVidya Sagar bus-range = <0x0 0xff>; 2034d5237c7cSThierry Reding 20358a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 20368a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 20378a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2038d5237c7cSThierry Reding 2039d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2040d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2041ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2042ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE1>; 2043ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2044ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2045ba02920cSVidya Sagar dma-coherent; 20462602c32fSVidya Sagar }; 20472602c32fSVidya Sagar 20482602c32fSVidya Sagar pcie@14120000 { 2049f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 20502602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2051644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2052644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2053644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2054644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20552602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20562602c32fSVidya Sagar 20572602c32fSVidya Sagar status = "disabled"; 20582602c32fSVidya Sagar 20592602c32fSVidya Sagar #address-cells = <3>; 20602602c32fSVidya Sagar #size-cells = <2>; 20612602c32fSVidya Sagar device_type = "pci"; 20622602c32fSVidya Sagar num-lanes = <1>; 20632602c32fSVidya Sagar num-viewport = <8>; 20642602c32fSVidya Sagar linux,pci-domain = <2>; 20652602c32fSVidya Sagar 20662602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 20672602c32fSVidya Sagar clock-names = "core"; 20682602c32fSVidya Sagar 20692602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 20702602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 20712602c32fSVidya Sagar reset-names = "apb", "core"; 20722602c32fSVidya Sagar 20732602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20742602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20752602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20762602c32fSVidya Sagar 20772602c32fSVidya Sagar #interrupt-cells = <1>; 20782602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 20792602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 20802602c32fSVidya Sagar 20812602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 20822602c32fSVidya Sagar 20832602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 20842602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20852602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20862602c32fSVidya Sagar 20872602c32fSVidya Sagar bus-range = <0x0 0xff>; 2088d5237c7cSThierry Reding 20898a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 20908a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 20918a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2092d5237c7cSThierry Reding 2093d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2094d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2095ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2096ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE2>; 2097ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2098ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2099ba02920cSVidya Sagar dma-coherent; 21002602c32fSVidya Sagar }; 21012602c32fSVidya Sagar 21022602c32fSVidya Sagar pcie@14140000 { 2103f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 21042602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2105644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2106644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2107644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2108644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 21092602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 21102602c32fSVidya Sagar 21112602c32fSVidya Sagar status = "disabled"; 21122602c32fSVidya Sagar 21132602c32fSVidya Sagar #address-cells = <3>; 21142602c32fSVidya Sagar #size-cells = <2>; 21152602c32fSVidya Sagar device_type = "pci"; 21162602c32fSVidya Sagar num-lanes = <1>; 21172602c32fSVidya Sagar num-viewport = <8>; 21182602c32fSVidya Sagar linux,pci-domain = <3>; 21192602c32fSVidya Sagar 21202602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 21212602c32fSVidya Sagar clock-names = "core"; 21222602c32fSVidya Sagar 21232602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 21242602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 21252602c32fSVidya Sagar reset-names = "apb", "core"; 21262602c32fSVidya Sagar 21272602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21282602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 21292602c32fSVidya Sagar interrupt-names = "intr", "msi"; 21302602c32fSVidya Sagar 21312602c32fSVidya Sagar #interrupt-cells = <1>; 21322602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21332602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 21342602c32fSVidya Sagar 21352602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 21362602c32fSVidya Sagar 21372602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21382602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21392602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21402602c32fSVidya Sagar 21412602c32fSVidya Sagar bus-range = <0x0 0xff>; 2142d5237c7cSThierry Reding 21438a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 21448a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 21458a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2146d5237c7cSThierry Reding 2147d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2148d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2149ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2150ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE3>; 2151ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2152ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2153ba02920cSVidya Sagar dma-coherent; 21542602c32fSVidya Sagar }; 21552602c32fSVidya Sagar 21562602c32fSVidya Sagar pcie@14160000 { 2157f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 21582602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2159644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2160644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2161644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2162644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 21632602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 21642602c32fSVidya Sagar 21652602c32fSVidya Sagar status = "disabled"; 21662602c32fSVidya Sagar 21672602c32fSVidya Sagar #address-cells = <3>; 21682602c32fSVidya Sagar #size-cells = <2>; 21692602c32fSVidya Sagar device_type = "pci"; 21702602c32fSVidya Sagar num-lanes = <4>; 21712602c32fSVidya Sagar num-viewport = <8>; 21722602c32fSVidya Sagar linux,pci-domain = <4>; 21732602c32fSVidya Sagar 21742602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 21752602c32fSVidya Sagar clock-names = "core"; 21762602c32fSVidya Sagar 21772602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 21782602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 21792602c32fSVidya Sagar reset-names = "apb", "core"; 21802602c32fSVidya Sagar 21812602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21822602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 21832602c32fSVidya Sagar interrupt-names = "intr", "msi"; 21842602c32fSVidya Sagar 21852602c32fSVidya Sagar #interrupt-cells = <1>; 21862602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21872602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 21882602c32fSVidya Sagar 21892602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 21902602c32fSVidya Sagar 21912602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21922602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21932602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21942602c32fSVidya Sagar 21952602c32fSVidya Sagar bus-range = <0x0 0xff>; 2196d5237c7cSThierry Reding 21978a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 21988a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 21998a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2200d5237c7cSThierry Reding 2201d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2202d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2203ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2204ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2205ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2206ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2207ba02920cSVidya Sagar dma-coherent; 22082602c32fSVidya Sagar }; 22092602c32fSVidya Sagar 22102602c32fSVidya Sagar pcie@14180000 { 2211f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22122602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2213644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2214644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2215644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2216644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22172602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22182602c32fSVidya Sagar 22192602c32fSVidya Sagar status = "disabled"; 22202602c32fSVidya Sagar 22212602c32fSVidya Sagar #address-cells = <3>; 22222602c32fSVidya Sagar #size-cells = <2>; 22232602c32fSVidya Sagar device_type = "pci"; 22242602c32fSVidya Sagar num-lanes = <8>; 22252602c32fSVidya Sagar num-viewport = <8>; 22262602c32fSVidya Sagar linux,pci-domain = <0>; 22272602c32fSVidya Sagar 22282602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 22292602c32fSVidya Sagar clock-names = "core"; 22302602c32fSVidya Sagar 22312602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 22322602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 22332602c32fSVidya Sagar reset-names = "apb", "core"; 22342602c32fSVidya Sagar 22352602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22362602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22372602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22382602c32fSVidya Sagar 22392602c32fSVidya Sagar #interrupt-cells = <1>; 22402602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 22412602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 22422602c32fSVidya Sagar 22432602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 22442602c32fSVidya Sagar 22452602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 22462602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22472602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 22482602c32fSVidya Sagar 22492602c32fSVidya Sagar bus-range = <0x0 0xff>; 2250d5237c7cSThierry Reding 22518a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 22528a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 22538a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2254d5237c7cSThierry Reding 2255d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2256d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2257ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2258ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2259ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2260ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2261ba02920cSVidya Sagar dma-coherent; 22622602c32fSVidya Sagar }; 22632602c32fSVidya Sagar 22642602c32fSVidya Sagar pcie@141a0000 { 2265f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 22662602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2267644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2268644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2269644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2270644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 22712602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 22722602c32fSVidya Sagar 22732602c32fSVidya Sagar status = "disabled"; 22742602c32fSVidya Sagar 22752602c32fSVidya Sagar #address-cells = <3>; 22762602c32fSVidya Sagar #size-cells = <2>; 22772602c32fSVidya Sagar device_type = "pci"; 22782602c32fSVidya Sagar num-lanes = <8>; 22792602c32fSVidya Sagar num-viewport = <8>; 22802602c32fSVidya Sagar linux,pci-domain = <5>; 22812602c32fSVidya Sagar 2282dbb72e2cSVidya Sagar pinctrl-names = "default"; 2283dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2284dbb72e2cSVidya Sagar 22852602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 22862602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 22872602c32fSVidya Sagar clock-names = "core", "core_m"; 22882602c32fSVidya Sagar 22892602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 22902602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 22912602c32fSVidya Sagar reset-names = "apb", "core"; 22922602c32fSVidya Sagar 22932602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22942602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 22952602c32fSVidya Sagar interrupt-names = "intr", "msi"; 22962602c32fSVidya Sagar 22972602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 22982602c32fSVidya Sagar 22992602c32fSVidya Sagar #interrupt-cells = <1>; 23002602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23012602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 23022602c32fSVidya Sagar 23032602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23042602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23052602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23062602c32fSVidya Sagar 23072602c32fSVidya Sagar bus-range = <0x0 0xff>; 2308d5237c7cSThierry Reding 23098a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 23108a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 23118a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2312d5237c7cSThierry Reding 2313d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2314d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2315ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2316ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2317ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2318ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2319ba02920cSVidya Sagar dma-coherent; 23202602c32fSVidya Sagar }; 23212602c32fSVidya Sagar 2322b9e2404cSMauro Carvalho Chehab pcie-ep@14160000 { 2323bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 23240c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2325644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2326644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2328644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 23290c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 23300c988b73SVidya Sagar 23310c988b73SVidya Sagar status = "disabled"; 23320c988b73SVidya Sagar 23330c988b73SVidya Sagar num-lanes = <4>; 23340c988b73SVidya Sagar num-ib-windows = <2>; 23350c988b73SVidya Sagar num-ob-windows = <8>; 23360c988b73SVidya Sagar 23370c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 23380c988b73SVidya Sagar clock-names = "core"; 23390c988b73SVidya Sagar 23400c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 23410c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 23420c988b73SVidya Sagar reset-names = "apb", "core"; 23430c988b73SVidya Sagar 23440c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 23450c988b73SVidya Sagar interrupt-names = "intr"; 23460c988b73SVidya Sagar 23470c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 23480c988b73SVidya Sagar 23490c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 23500c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23510c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2352ba02920cSVidya Sagar 2353ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2354ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2355ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2356ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2357ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2358ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2359ba02920cSVidya Sagar dma-coherent; 23600c988b73SVidya Sagar }; 23610c988b73SVidya Sagar 2362b9e2404cSMauro Carvalho Chehab pcie-ep@14180000 { 2363bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 23640c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2365644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2366644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2367644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2368644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 23690c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 23700c988b73SVidya Sagar 23710c988b73SVidya Sagar status = "disabled"; 23720c988b73SVidya Sagar 23730c988b73SVidya Sagar num-lanes = <8>; 23740c988b73SVidya Sagar num-ib-windows = <2>; 23750c988b73SVidya Sagar num-ob-windows = <8>; 23760c988b73SVidya Sagar 23770c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 23780c988b73SVidya Sagar clock-names = "core"; 23790c988b73SVidya Sagar 23800c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 23810c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 23820c988b73SVidya Sagar reset-names = "apb", "core"; 23830c988b73SVidya Sagar 23840c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 23850c988b73SVidya Sagar interrupt-names = "intr"; 23860c988b73SVidya Sagar 23870c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 23880c988b73SVidya Sagar 23890c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 23900c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23910c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2392ba02920cSVidya Sagar 2393ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2394ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2395ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2396ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2397ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2398ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2399ba02920cSVidya Sagar dma-coherent; 24000c988b73SVidya Sagar }; 24010c988b73SVidya Sagar 2402b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2403bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 24040c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2405644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2406644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2407644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2408644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 24090c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 24100c988b73SVidya Sagar 24110c988b73SVidya Sagar status = "disabled"; 24120c988b73SVidya Sagar 24130c988b73SVidya Sagar num-lanes = <8>; 24140c988b73SVidya Sagar num-ib-windows = <2>; 24150c988b73SVidya Sagar num-ob-windows = <8>; 24160c988b73SVidya Sagar 24170c988b73SVidya Sagar pinctrl-names = "default"; 24180c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 24190c988b73SVidya Sagar 24200c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 24210c988b73SVidya Sagar clock-names = "core"; 24220c988b73SVidya Sagar 24230c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 24240c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 24250c988b73SVidya Sagar reset-names = "apb", "core"; 24260c988b73SVidya Sagar 24270c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 24280c988b73SVidya Sagar interrupt-names = "intr"; 24290c988b73SVidya Sagar 24300c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 24310c988b73SVidya Sagar 24320c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 24330c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24340c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2435ba02920cSVidya Sagar 2436ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2437ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2438ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2439ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2440ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2441ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2442ba02920cSVidya Sagar dma-coherent; 24430c988b73SVidya Sagar }; 24440c988b73SVidya Sagar 2445e867fe41SThierry Reding sram@40000000 { 24465425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 24475425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 24485425fb15SMikko Perttunen #address-cells = <1>; 24495425fb15SMikko Perttunen #size-cells = <1>; 24505425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 24515425fb15SMikko Perttunen 2452e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 24535425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 24545425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 24555425fb15SMikko Perttunen pool; 24565425fb15SMikko Perttunen }; 24575425fb15SMikko Perttunen 2458e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 24595425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 24605425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 24615425fb15SMikko Perttunen pool; 24625425fb15SMikko Perttunen }; 24635425fb15SMikko Perttunen }; 24645425fb15SMikko Perttunen 24655425fb15SMikko Perttunen bpmp: bpmp { 24665425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 24675425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 24685425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 24695425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 24705425fb15SMikko Perttunen #clock-cells = <1>; 24715425fb15SMikko Perttunen #reset-cells = <1>; 24725425fb15SMikko Perttunen #power-domain-cells = <1>; 2473d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2474d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2475d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2476d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2477d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2478c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 24795425fb15SMikko Perttunen 24805425fb15SMikko Perttunen bpmp_i2c: i2c { 24815425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 24825425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 24835425fb15SMikko Perttunen #address-cells = <1>; 24845425fb15SMikko Perttunen #size-cells = <0>; 24855425fb15SMikko Perttunen }; 24865425fb15SMikko Perttunen 24875425fb15SMikko Perttunen bpmp_thermal: thermal { 24885425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 24895425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 24905425fb15SMikko Perttunen }; 24915425fb15SMikko Perttunen }; 24925425fb15SMikko Perttunen 24937780a034SMikko Perttunen cpus { 2494d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2495d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 24967780a034SMikko Perttunen #address-cells = <1>; 24977780a034SMikko Perttunen #size-cells = <0>; 24987780a034SMikko Perttunen 2499b45d322cSThierry Reding cpu0_0: cpu@0 { 250031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25017780a034SMikko Perttunen device_type = "cpu"; 2502b45d322cSThierry Reding reg = <0x000>; 25037780a034SMikko Perttunen enable-method = "psci"; 2504b45d322cSThierry Reding i-cache-size = <131072>; 2505b45d322cSThierry Reding i-cache-line-size = <64>; 2506b45d322cSThierry Reding i-cache-sets = <512>; 2507b45d322cSThierry Reding d-cache-size = <65536>; 2508b45d322cSThierry Reding d-cache-line-size = <64>; 2509b45d322cSThierry Reding d-cache-sets = <256>; 2510b45d322cSThierry Reding next-level-cache = <&l2c_0>; 25117780a034SMikko Perttunen }; 25127780a034SMikko Perttunen 2513b45d322cSThierry Reding cpu0_1: cpu@1 { 251431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25157780a034SMikko Perttunen device_type = "cpu"; 2516b45d322cSThierry Reding reg = <0x001>; 25177780a034SMikko Perttunen enable-method = "psci"; 2518b45d322cSThierry Reding i-cache-size = <131072>; 2519b45d322cSThierry Reding i-cache-line-size = <64>; 2520b45d322cSThierry Reding i-cache-sets = <512>; 2521b45d322cSThierry Reding d-cache-size = <65536>; 2522b45d322cSThierry Reding d-cache-line-size = <64>; 2523b45d322cSThierry Reding d-cache-sets = <256>; 2524b45d322cSThierry Reding next-level-cache = <&l2c_0>; 25257780a034SMikko Perttunen }; 25267780a034SMikko Perttunen 2527b45d322cSThierry Reding cpu1_0: cpu@100 { 252831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25297780a034SMikko Perttunen device_type = "cpu"; 25307780a034SMikko Perttunen reg = <0x100>; 25317780a034SMikko Perttunen enable-method = "psci"; 2532b45d322cSThierry Reding i-cache-size = <131072>; 2533b45d322cSThierry Reding i-cache-line-size = <64>; 2534b45d322cSThierry Reding i-cache-sets = <512>; 2535b45d322cSThierry Reding d-cache-size = <65536>; 2536b45d322cSThierry Reding d-cache-line-size = <64>; 2537b45d322cSThierry Reding d-cache-sets = <256>; 2538b45d322cSThierry Reding next-level-cache = <&l2c_1>; 25397780a034SMikko Perttunen }; 25407780a034SMikko Perttunen 2541b45d322cSThierry Reding cpu1_1: cpu@101 { 254231af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25437780a034SMikko Perttunen device_type = "cpu"; 25447780a034SMikko Perttunen reg = <0x101>; 25457780a034SMikko Perttunen enable-method = "psci"; 2546b45d322cSThierry Reding i-cache-size = <131072>; 2547b45d322cSThierry Reding i-cache-line-size = <64>; 2548b45d322cSThierry Reding i-cache-sets = <512>; 2549b45d322cSThierry Reding d-cache-size = <65536>; 2550b45d322cSThierry Reding d-cache-line-size = <64>; 2551b45d322cSThierry Reding d-cache-sets = <256>; 2552b45d322cSThierry Reding next-level-cache = <&l2c_1>; 25537780a034SMikko Perttunen }; 25547780a034SMikko Perttunen 2555b45d322cSThierry Reding cpu2_0: cpu@200 { 255631af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25577780a034SMikko Perttunen device_type = "cpu"; 25587780a034SMikko Perttunen reg = <0x200>; 25597780a034SMikko Perttunen enable-method = "psci"; 2560b45d322cSThierry Reding i-cache-size = <131072>; 2561b45d322cSThierry Reding i-cache-line-size = <64>; 2562b45d322cSThierry Reding i-cache-sets = <512>; 2563b45d322cSThierry Reding d-cache-size = <65536>; 2564b45d322cSThierry Reding d-cache-line-size = <64>; 2565b45d322cSThierry Reding d-cache-sets = <256>; 2566b45d322cSThierry Reding next-level-cache = <&l2c_2>; 25677780a034SMikko Perttunen }; 25687780a034SMikko Perttunen 2569b45d322cSThierry Reding cpu2_1: cpu@201 { 257031af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25717780a034SMikko Perttunen device_type = "cpu"; 25727780a034SMikko Perttunen reg = <0x201>; 25737780a034SMikko Perttunen enable-method = "psci"; 2574b45d322cSThierry Reding i-cache-size = <131072>; 2575b45d322cSThierry Reding i-cache-line-size = <64>; 2576b45d322cSThierry Reding i-cache-sets = <512>; 2577b45d322cSThierry Reding d-cache-size = <65536>; 2578b45d322cSThierry Reding d-cache-line-size = <64>; 2579b45d322cSThierry Reding d-cache-sets = <256>; 2580b45d322cSThierry Reding next-level-cache = <&l2c_2>; 25817780a034SMikko Perttunen }; 25827780a034SMikko Perttunen 2583b45d322cSThierry Reding cpu3_0: cpu@300 { 258431af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25857780a034SMikko Perttunen device_type = "cpu"; 2586b45d322cSThierry Reding reg = <0x300>; 25877780a034SMikko Perttunen enable-method = "psci"; 2588b45d322cSThierry Reding i-cache-size = <131072>; 2589b45d322cSThierry Reding i-cache-line-size = <64>; 2590b45d322cSThierry Reding i-cache-sets = <512>; 2591b45d322cSThierry Reding d-cache-size = <65536>; 2592b45d322cSThierry Reding d-cache-line-size = <64>; 2593b45d322cSThierry Reding d-cache-sets = <256>; 2594b45d322cSThierry Reding next-level-cache = <&l2c_3>; 25957780a034SMikko Perttunen }; 25967780a034SMikko Perttunen 2597b45d322cSThierry Reding cpu3_1: cpu@301 { 259831af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 25997780a034SMikko Perttunen device_type = "cpu"; 2600b45d322cSThierry Reding reg = <0x301>; 26017780a034SMikko Perttunen enable-method = "psci"; 2602b45d322cSThierry Reding i-cache-size = <131072>; 2603b45d322cSThierry Reding i-cache-line-size = <64>; 2604b45d322cSThierry Reding i-cache-sets = <512>; 2605b45d322cSThierry Reding d-cache-size = <65536>; 2606b45d322cSThierry Reding d-cache-line-size = <64>; 2607b45d322cSThierry Reding d-cache-sets = <256>; 2608b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2609b45d322cSThierry Reding }; 2610b45d322cSThierry Reding 2611b45d322cSThierry Reding cpu-map { 2612b45d322cSThierry Reding cluster0 { 2613b45d322cSThierry Reding core0 { 2614b45d322cSThierry Reding cpu = <&cpu0_0>; 2615b45d322cSThierry Reding }; 2616b45d322cSThierry Reding 2617b45d322cSThierry Reding core1 { 2618b45d322cSThierry Reding cpu = <&cpu0_1>; 2619b45d322cSThierry Reding }; 2620b45d322cSThierry Reding }; 2621b45d322cSThierry Reding 2622b45d322cSThierry Reding cluster1 { 2623b45d322cSThierry Reding core0 { 2624b45d322cSThierry Reding cpu = <&cpu1_0>; 2625b45d322cSThierry Reding }; 2626b45d322cSThierry Reding 2627b45d322cSThierry Reding core1 { 2628b45d322cSThierry Reding cpu = <&cpu1_1>; 2629b45d322cSThierry Reding }; 2630b45d322cSThierry Reding }; 2631b45d322cSThierry Reding 2632b45d322cSThierry Reding cluster2 { 2633b45d322cSThierry Reding core0 { 2634b45d322cSThierry Reding cpu = <&cpu2_0>; 2635b45d322cSThierry Reding }; 2636b45d322cSThierry Reding 2637b45d322cSThierry Reding core1 { 2638b45d322cSThierry Reding cpu = <&cpu2_1>; 2639b45d322cSThierry Reding }; 2640b45d322cSThierry Reding }; 2641b45d322cSThierry Reding 2642b45d322cSThierry Reding cluster3 { 2643b45d322cSThierry Reding core0 { 2644b45d322cSThierry Reding cpu = <&cpu3_0>; 2645b45d322cSThierry Reding }; 2646b45d322cSThierry Reding 2647b45d322cSThierry Reding core1 { 2648b45d322cSThierry Reding cpu = <&cpu3_1>; 2649b45d322cSThierry Reding }; 2650b45d322cSThierry Reding }; 2651b45d322cSThierry Reding }; 2652b45d322cSThierry Reding 2653b45d322cSThierry Reding l2c_0: l2-cache0 { 2654b45d322cSThierry Reding cache-size = <2097152>; 2655b45d322cSThierry Reding cache-line-size = <64>; 2656b45d322cSThierry Reding cache-sets = <2048>; 2657b45d322cSThierry Reding next-level-cache = <&l3c>; 2658b45d322cSThierry Reding }; 2659b45d322cSThierry Reding 2660b45d322cSThierry Reding l2c_1: l2-cache1 { 2661b45d322cSThierry Reding cache-size = <2097152>; 2662b45d322cSThierry Reding cache-line-size = <64>; 2663b45d322cSThierry Reding cache-sets = <2048>; 2664b45d322cSThierry Reding next-level-cache = <&l3c>; 2665b45d322cSThierry Reding }; 2666b45d322cSThierry Reding 2667b45d322cSThierry Reding l2c_2: l2-cache2 { 2668b45d322cSThierry Reding cache-size = <2097152>; 2669b45d322cSThierry Reding cache-line-size = <64>; 2670b45d322cSThierry Reding cache-sets = <2048>; 2671b45d322cSThierry Reding next-level-cache = <&l3c>; 2672b45d322cSThierry Reding }; 2673b45d322cSThierry Reding 2674b45d322cSThierry Reding l2c_3: l2-cache3 { 2675b45d322cSThierry Reding cache-size = <2097152>; 2676b45d322cSThierry Reding cache-line-size = <64>; 2677b45d322cSThierry Reding cache-sets = <2048>; 2678b45d322cSThierry Reding next-level-cache = <&l3c>; 2679b45d322cSThierry Reding }; 2680b45d322cSThierry Reding 2681b45d322cSThierry Reding l3c: l3-cache { 2682b45d322cSThierry Reding cache-size = <4194304>; 2683b45d322cSThierry Reding cache-line-size = <64>; 2684b45d322cSThierry Reding cache-sets = <4096>; 26857780a034SMikko Perttunen }; 26867780a034SMikko Perttunen }; 26877780a034SMikko Perttunen 26889e79e58fSJon Hunter pmu { 26899e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 26909e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 26919e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 26929e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 26939e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 26949e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 26959e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 26969e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 26979e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 26989e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 26999e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 27009e79e58fSJon Hunter }; 27019e79e58fSJon Hunter 27027780a034SMikko Perttunen psci { 27037780a034SMikko Perttunen compatible = "arm,psci-1.0"; 27047780a034SMikko Perttunen status = "okay"; 27057780a034SMikko Perttunen method = "smc"; 27067780a034SMikko Perttunen }; 27077780a034SMikko Perttunen 27085b4f6323SSameer Pujar sound { 27095b4f6323SSameer Pujar status = "disabled"; 27105b4f6323SSameer Pujar 27115b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 27125b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 27135b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 27145b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 27155b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 27165b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 27175b4f6323SSameer Pujar assigned-clock-parents = <0>, 27185b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 27195b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 27205b4f6323SSameer Pujar /* 27215b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 27225b4f6323SSameer Pujar * for this to work and oscillate between base rates required 27235b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 27245b4f6323SSameer Pujar */ 27255b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 272634e0fc34SThierry Reding 272734e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 272834e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 272934e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 273034e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 27315b4f6323SSameer Pujar }; 27325b4f6323SSameer Pujar 2733a38570c2SMikko Perttunen tcu: tcu { 2734a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2735a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2736a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2737a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2738a38570c2SMikko Perttunen }; 2739a38570c2SMikko Perttunen 2740686ba009SThierry Reding thermal-zones { 2741686ba009SThierry Reding cpu { 2742686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2743686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2744686ba009SThierry Reding status = "disabled"; 2745686ba009SThierry Reding }; 2746686ba009SThierry Reding 2747686ba009SThierry Reding gpu { 2748686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2749686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2750686ba009SThierry Reding status = "disabled"; 2751686ba009SThierry Reding }; 2752686ba009SThierry Reding 2753686ba009SThierry Reding aux { 2754686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2755686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2756686ba009SThierry Reding status = "disabled"; 2757686ba009SThierry Reding }; 2758686ba009SThierry Reding 2759686ba009SThierry Reding pllx { 2760686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2761686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2762686ba009SThierry Reding status = "disabled"; 2763686ba009SThierry Reding }; 2764686ba009SThierry Reding 2765686ba009SThierry Reding ao { 2766686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2767686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2768686ba009SThierry Reding status = "disabled"; 2769686ba009SThierry Reding }; 2770686ba009SThierry Reding 2771686ba009SThierry Reding tj { 2772686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2773686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2774686ba009SThierry Reding status = "disabled"; 2775686ba009SThierry Reding }; 2776686ba009SThierry Reding }; 2777686ba009SThierry Reding 27785425fb15SMikko Perttunen timer { 27795425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 27805425fb15SMikko Perttunen interrupts = <GIC_PPI 13 27815425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 27825425fb15SMikko Perttunen <GIC_PPI 14 27835425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 27845425fb15SMikko Perttunen <GIC_PPI 11 27855425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 27865425fb15SMikko Perttunen <GIC_PPI 10 27875425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 27885425fb15SMikko Perttunen interrupt-parent = <&gic>; 2789b30be673SThierry Reding always-on; 27905425fb15SMikko Perttunen }; 27915425fb15SMikko Perttunen}; 2792