15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 198b3aee8fSThierry Reding bus@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37*0a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 38*0a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 39*0a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 40*0a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 41*0a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 42*0a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 43*0a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 44f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 45*0a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 46*0a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 47*0a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 48*0a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 49*0a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 50*0a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 51*0a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 52f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 53*0a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 54*0a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 55*0a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 56*0a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 57*0a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 58*0a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 59*0a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 60f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 61*0a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 62*0a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 63*0a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 64*0a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 65*0a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 66*0a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 67*0a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 68f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 69*0a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 70*0a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 71*0a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 72*0a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 73*0a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 74*0a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 75*0a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 76*0a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 77*0a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 78*0a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 79*0a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 80*0a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 81*0a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 82*0a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 83*0a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 84f69ce393SMikko Perttunen #interrupt-cells = <2>; 85f69ce393SMikko Perttunen interrupt-controller; 86f69ce393SMikko Perttunen #gpio-cells = <2>; 87f69ce393SMikko Perttunen gpio-controller; 88f69ce393SMikko Perttunen }; 89f69ce393SMikko Perttunen 90f89b58ceSMikko Perttunen ethernet@2490000 { 9119dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 9219dc772aSThierry Reding "nvidia,tegra186-eqos", 93f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 94f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 95f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 96f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 97f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 98f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 99f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 100f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 101f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 102f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 103f89b58ceSMikko Perttunen reset-names = "eqos"; 104d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 105d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 106d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 107c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 108f89b58ceSMikko Perttunen status = "disabled"; 109f89b58ceSMikko Perttunen 110f89b58ceSMikko Perttunen snps,write-requests = <1>; 111f89b58ceSMikko Perttunen snps,read-requests = <3>; 112f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 113f89b58ceSMikko Perttunen snps,txpbl = <16>; 114f89b58ceSMikko Perttunen snps,rxpbl = <8>; 115f89b58ceSMikko Perttunen }; 116f89b58ceSMikko Perttunen 1171aaa7698SThierry Reding aconnect@2900000 { 1185d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 1195d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1205d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 1215d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 1225d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1235d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 1245d2249ddSSameer Pujar #address-cells = <1>; 1255d2249ddSSameer Pujar #size-cells = <1>; 1265d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar 129177208f7SSameer Pujar adma: dma-controller@2930000 { 1305d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 1315d2249ddSSameer Pujar "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1815d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1825d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1835d2249ddSSameer Pujar clock-names = "clk"; 1845d2249ddSSameer Pujar status = "disabled"; 1855d2249ddSSameer Pujar }; 186177208f7SSameer Pujar 187177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 188177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 189177208f7SSameer Pujar "nvidia,tegra186-ahub"; 190177208f7SSameer Pujar reg = <0x02900800 0x800>; 191177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 192177208f7SSameer Pujar clock-names = "ahub"; 193177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 194177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 195177208f7SSameer Pujar #address-cells = <1>; 196177208f7SSameer Pujar #size-cells = <1>; 197177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 198177208f7SSameer Pujar status = "disabled"; 199177208f7SSameer Pujar 200177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 201177208f7SSameer Pujar compatible = "nvidia,tegra194-admaif", 202177208f7SSameer Pujar "nvidia,tegra186-admaif"; 203177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 204177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 205177208f7SSameer Pujar <&adma 2>, <&adma 2>, 206177208f7SSameer Pujar <&adma 3>, <&adma 3>, 207177208f7SSameer Pujar <&adma 4>, <&adma 4>, 208177208f7SSameer Pujar <&adma 5>, <&adma 5>, 209177208f7SSameer Pujar <&adma 6>, <&adma 6>, 210177208f7SSameer Pujar <&adma 7>, <&adma 7>, 211177208f7SSameer Pujar <&adma 8>, <&adma 8>, 212177208f7SSameer Pujar <&adma 9>, <&adma 9>, 213177208f7SSameer Pujar <&adma 10>, <&adma 10>, 214177208f7SSameer Pujar <&adma 11>, <&adma 11>, 215177208f7SSameer Pujar <&adma 12>, <&adma 12>, 216177208f7SSameer Pujar <&adma 13>, <&adma 13>, 217177208f7SSameer Pujar <&adma 14>, <&adma 14>, 218177208f7SSameer Pujar <&adma 15>, <&adma 15>, 219177208f7SSameer Pujar <&adma 16>, <&adma 16>, 220177208f7SSameer Pujar <&adma 17>, <&adma 17>, 221177208f7SSameer Pujar <&adma 18>, <&adma 18>, 222177208f7SSameer Pujar <&adma 19>, <&adma 19>, 223177208f7SSameer Pujar <&adma 20>, <&adma 20>; 224177208f7SSameer Pujar dma-names = "rx1", "tx1", 225177208f7SSameer Pujar "rx2", "tx2", 226177208f7SSameer Pujar "rx3", "tx3", 227177208f7SSameer Pujar "rx4", "tx4", 228177208f7SSameer Pujar "rx5", "tx5", 229177208f7SSameer Pujar "rx6", "tx6", 230177208f7SSameer Pujar "rx7", "tx7", 231177208f7SSameer Pujar "rx8", "tx8", 232177208f7SSameer Pujar "rx9", "tx9", 233177208f7SSameer Pujar "rx10", "tx10", 234177208f7SSameer Pujar "rx11", "tx11", 235177208f7SSameer Pujar "rx12", "tx12", 236177208f7SSameer Pujar "rx13", "tx13", 237177208f7SSameer Pujar "rx14", "tx14", 238177208f7SSameer Pujar "rx15", "tx15", 239177208f7SSameer Pujar "rx16", "tx16", 240177208f7SSameer Pujar "rx17", "tx17", 241177208f7SSameer Pujar "rx18", "tx18", 242177208f7SSameer Pujar "rx19", "tx19", 243177208f7SSameer Pujar "rx20", "tx20"; 244177208f7SSameer Pujar status = "disabled"; 245177208f7SSameer Pujar }; 246177208f7SSameer Pujar 247177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 248177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 249177208f7SSameer Pujar "nvidia,tegra210-i2s"; 250177208f7SSameer Pujar reg = <0x2901000 0x100>; 251177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 252177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 253177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 254177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 255177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 256177208f7SSameer Pujar assigned-clock-rates = <1536000>; 257177208f7SSameer Pujar sound-name-prefix = "I2S1"; 258177208f7SSameer Pujar status = "disabled"; 259177208f7SSameer Pujar }; 260177208f7SSameer Pujar 261177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 262177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 263177208f7SSameer Pujar "nvidia,tegra210-i2s"; 264177208f7SSameer Pujar reg = <0x2901100 0x100>; 265177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 266177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 267177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 268177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 269177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 270177208f7SSameer Pujar assigned-clock-rates = <1536000>; 271177208f7SSameer Pujar sound-name-prefix = "I2S2"; 272177208f7SSameer Pujar status = "disabled"; 273177208f7SSameer Pujar }; 274177208f7SSameer Pujar 275177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 276177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 277177208f7SSameer Pujar "nvidia,tegra210-i2s"; 278177208f7SSameer Pujar reg = <0x2901200 0x100>; 279177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 280177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 281177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 282177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 283177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 284177208f7SSameer Pujar assigned-clock-rates = <1536000>; 285177208f7SSameer Pujar sound-name-prefix = "I2S3"; 286177208f7SSameer Pujar status = "disabled"; 287177208f7SSameer Pujar }; 288177208f7SSameer Pujar 289177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 290177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 291177208f7SSameer Pujar "nvidia,tegra210-i2s"; 292177208f7SSameer Pujar reg = <0x2901300 0x100>; 293177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 294177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 295177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 296177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 297177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 298177208f7SSameer Pujar assigned-clock-rates = <1536000>; 299177208f7SSameer Pujar sound-name-prefix = "I2S4"; 300177208f7SSameer Pujar status = "disabled"; 301177208f7SSameer Pujar }; 302177208f7SSameer Pujar 303177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 304177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 305177208f7SSameer Pujar "nvidia,tegra210-i2s"; 306177208f7SSameer Pujar reg = <0x2901400 0x100>; 307177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 308177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 309177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 310177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 311177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 312177208f7SSameer Pujar assigned-clock-rates = <1536000>; 313177208f7SSameer Pujar sound-name-prefix = "I2S5"; 314177208f7SSameer Pujar status = "disabled"; 315177208f7SSameer Pujar }; 316177208f7SSameer Pujar 317177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 318177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 319177208f7SSameer Pujar "nvidia,tegra210-i2s"; 320177208f7SSameer Pujar reg = <0x2901500 0x100>; 321177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 322177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 323177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 324177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 325177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 326177208f7SSameer Pujar assigned-clock-rates = <1536000>; 327177208f7SSameer Pujar sound-name-prefix = "I2S6"; 328177208f7SSameer Pujar status = "disabled"; 329177208f7SSameer Pujar }; 330177208f7SSameer Pujar 331177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 332177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 333177208f7SSameer Pujar "nvidia,tegra210-dmic"; 334177208f7SSameer Pujar reg = <0x2904000 0x100>; 335177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 336177208f7SSameer Pujar clock-names = "dmic"; 337177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 338177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339177208f7SSameer Pujar assigned-clock-rates = <3072000>; 340177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 341177208f7SSameer Pujar status = "disabled"; 342177208f7SSameer Pujar }; 343177208f7SSameer Pujar 344177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 345177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 346177208f7SSameer Pujar "nvidia,tegra210-dmic"; 347177208f7SSameer Pujar reg = <0x2904100 0x100>; 348177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 349177208f7SSameer Pujar clock-names = "dmic"; 350177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 351177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 352177208f7SSameer Pujar assigned-clock-rates = <3072000>; 353177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 354177208f7SSameer Pujar status = "disabled"; 355177208f7SSameer Pujar }; 356177208f7SSameer Pujar 357177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 358177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 359177208f7SSameer Pujar "nvidia,tegra210-dmic"; 360177208f7SSameer Pujar reg = <0x2904200 0x100>; 361177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 362177208f7SSameer Pujar clock-names = "dmic"; 363177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 364177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 365177208f7SSameer Pujar assigned-clock-rates = <3072000>; 366177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 367177208f7SSameer Pujar status = "disabled"; 368177208f7SSameer Pujar }; 369177208f7SSameer Pujar 370177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 371177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 372177208f7SSameer Pujar "nvidia,tegra210-dmic"; 373177208f7SSameer Pujar reg = <0x2904300 0x100>; 374177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 375177208f7SSameer Pujar clock-names = "dmic"; 376177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 377177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 378177208f7SSameer Pujar assigned-clock-rates = <3072000>; 379177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 380177208f7SSameer Pujar status = "disabled"; 381177208f7SSameer Pujar }; 382177208f7SSameer Pujar 383177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 384177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 385177208f7SSameer Pujar "nvidia,tegra186-dspk"; 386177208f7SSameer Pujar reg = <0x2905000 0x100>; 387177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 388177208f7SSameer Pujar clock-names = "dspk"; 389177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 390177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 391177208f7SSameer Pujar assigned-clock-rates = <12288000>; 392177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 393177208f7SSameer Pujar status = "disabled"; 394177208f7SSameer Pujar }; 395177208f7SSameer Pujar 396177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 397177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 398177208f7SSameer Pujar "nvidia,tegra186-dspk"; 399177208f7SSameer Pujar reg = <0x2905100 0x100>; 400177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 401177208f7SSameer Pujar clock-names = "dspk"; 402177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 403177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 404177208f7SSameer Pujar assigned-clock-rates = <12288000>; 405177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 406177208f7SSameer Pujar status = "disabled"; 407177208f7SSameer Pujar }; 408177208f7SSameer Pujar }; 4095d2249ddSSameer Pujar }; 4105d2249ddSSameer Pujar 411dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 412dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 413644c569dSThierry Reding reg = <0x2430000 0x17000>, 414644c569dSThierry Reding <0xc300000 0x4000>; 415dbb72e2cSVidya Sagar 416dbb72e2cSVidya Sagar status = "okay"; 417dbb72e2cSVidya Sagar 418dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 419dbb72e2cSVidya Sagar pex_rst { 420dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 421dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 422dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 423dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4246b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 425dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 426dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427dbb72e2cSVidya Sagar }; 428dbb72e2cSVidya Sagar }; 429dbb72e2cSVidya Sagar 430dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 431dbb72e2cSVidya Sagar clkreq { 432dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 433dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 434dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 435dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 4366b26c1a0SVidya Sagar nvidia,io-hv = <TEGRA_PIN_ENABLE>; 437dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 438dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 439dbb72e2cSVidya Sagar }; 440dbb72e2cSVidya Sagar }; 441dbb72e2cSVidya Sagar }; 442dbb72e2cSVidya Sagar 443be9b887fSThierry Reding mc: memory-controller@2c00000 { 444be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 445be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 446be9b887fSThierry Reding <0x02b80000 0x040000>, 447be9b887fSThierry Reding <0x01700000 0x100000>; 4488613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 449d5237c7cSThierry Reding #interconnect-cells = <1>; 450be9b887fSThierry Reding status = "disabled"; 451be9b887fSThierry Reding 452be9b887fSThierry Reding #address-cells = <2>; 453be9b887fSThierry Reding #size-cells = <2>; 454be9b887fSThierry Reding 455be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 456be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 457be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 458be9b887fSThierry Reding 459be9b887fSThierry Reding /* 460be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 461be9b887fSThierry Reding * controller selects the XBAR format used when memory 462be9b887fSThierry Reding * is accessed. This is used to transparently access 463be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 464be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 465be9b887fSThierry Reding * 466be9b887fSThierry Reding * As a consequence, the operating system must ensure 467be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 468be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 469be9b887fSThierry Reding * devices require access to the XBAR switch, their 470be9b887fSThierry Reding * drivers must set this bit explicitly. 471be9b887fSThierry Reding * 472be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 473be9b887fSThierry Reding */ 474be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 475be9b887fSThierry Reding 476be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 477be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 478be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 479be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 480be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 481be9b887fSThierry Reding clock-names = "emc"; 482be9b887fSThierry Reding 483d5237c7cSThierry Reding #interconnect-cells = <0>; 484d5237c7cSThierry Reding 485be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 486be9b887fSThierry Reding }; 487be9b887fSThierry Reding }; 488be9b887fSThierry Reding 4895425fb15SMikko Perttunen uarta: serial@3100000 { 4905425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 4915425fb15SMikko Perttunen reg = <0x03100000 0x40>; 4925425fb15SMikko Perttunen reg-shift = <2>; 4935425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 4945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 4955425fb15SMikko Perttunen clock-names = "serial"; 4965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 4975425fb15SMikko Perttunen reset-names = "serial"; 4985425fb15SMikko Perttunen status = "disabled"; 4995425fb15SMikko Perttunen }; 5005425fb15SMikko Perttunen 5015425fb15SMikko Perttunen uartb: serial@3110000 { 5025425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5035425fb15SMikko Perttunen reg = <0x03110000 0x40>; 5045425fb15SMikko Perttunen reg-shift = <2>; 5055425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 5065425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 5075425fb15SMikko Perttunen clock-names = "serial"; 5085425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 5095425fb15SMikko Perttunen reset-names = "serial"; 5105425fb15SMikko Perttunen status = "disabled"; 5115425fb15SMikko Perttunen }; 5125425fb15SMikko Perttunen 5135425fb15SMikko Perttunen uartd: serial@3130000 { 5145425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5155425fb15SMikko Perttunen reg = <0x03130000 0x40>; 5165425fb15SMikko Perttunen reg-shift = <2>; 5175425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 5185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 5195425fb15SMikko Perttunen clock-names = "serial"; 5205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 5215425fb15SMikko Perttunen reset-names = "serial"; 5225425fb15SMikko Perttunen status = "disabled"; 5235425fb15SMikko Perttunen }; 5245425fb15SMikko Perttunen 5255425fb15SMikko Perttunen uarte: serial@3140000 { 5265425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5275425fb15SMikko Perttunen reg = <0x03140000 0x40>; 5285425fb15SMikko Perttunen reg-shift = <2>; 5295425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 5305425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 5315425fb15SMikko Perttunen clock-names = "serial"; 5325425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 5335425fb15SMikko Perttunen reset-names = "serial"; 5345425fb15SMikko Perttunen status = "disabled"; 5355425fb15SMikko Perttunen }; 5365425fb15SMikko Perttunen 5375425fb15SMikko Perttunen uartf: serial@3150000 { 5385425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5395425fb15SMikko Perttunen reg = <0x03150000 0x40>; 5405425fb15SMikko Perttunen reg-shift = <2>; 5415425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 5425425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 5435425fb15SMikko Perttunen clock-names = "serial"; 5445425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 5455425fb15SMikko Perttunen reset-names = "serial"; 5465425fb15SMikko Perttunen status = "disabled"; 5475425fb15SMikko Perttunen }; 5485425fb15SMikko Perttunen 5495425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 550d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5515425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 5525425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 5535425fb15SMikko Perttunen #address-cells = <1>; 5545425fb15SMikko Perttunen #size-cells = <0>; 5555425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 5565425fb15SMikko Perttunen clock-names = "div-clk"; 5575425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 5585425fb15SMikko Perttunen reset-names = "i2c"; 5595425fb15SMikko Perttunen status = "disabled"; 5605425fb15SMikko Perttunen }; 5615425fb15SMikko Perttunen 5625425fb15SMikko Perttunen uarth: serial@3170000 { 5635425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 5645425fb15SMikko Perttunen reg = <0x03170000 0x40>; 5655425fb15SMikko Perttunen reg-shift = <2>; 5665425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 5675425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 5685425fb15SMikko Perttunen clock-names = "serial"; 5695425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 5705425fb15SMikko Perttunen reset-names = "serial"; 5715425fb15SMikko Perttunen status = "disabled"; 5725425fb15SMikko Perttunen }; 5735425fb15SMikko Perttunen 5745425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 575d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5765425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 5775425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5785425fb15SMikko Perttunen #address-cells = <1>; 5795425fb15SMikko Perttunen #size-cells = <0>; 5805425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 5815425fb15SMikko Perttunen clock-names = "div-clk"; 5825425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 5835425fb15SMikko Perttunen reset-names = "i2c"; 5845425fb15SMikko Perttunen status = "disabled"; 5855425fb15SMikko Perttunen }; 5865425fb15SMikko Perttunen 5875425fb15SMikko Perttunen /* shares pads with dpaux1 */ 5885425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 589d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 5905425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 5915425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 5925425fb15SMikko Perttunen #address-cells = <1>; 5935425fb15SMikko Perttunen #size-cells = <0>; 5945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 5955425fb15SMikko Perttunen clock-names = "div-clk"; 5965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 5975425fb15SMikko Perttunen reset-names = "i2c"; 598a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 599a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 600a4131561SThierry Reding pinctrl-names = "default", "idle"; 6015425fb15SMikko Perttunen status = "disabled"; 6025425fb15SMikko Perttunen }; 6035425fb15SMikko Perttunen 6045425fb15SMikko Perttunen /* shares pads with dpaux0 */ 6055425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 606d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6075425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 6085425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 6095425fb15SMikko Perttunen #address-cells = <1>; 6105425fb15SMikko Perttunen #size-cells = <0>; 6115425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 6125425fb15SMikko Perttunen clock-names = "div-clk"; 6135425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 6145425fb15SMikko Perttunen reset-names = "i2c"; 615a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 616a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 617a4131561SThierry Reding pinctrl-names = "default", "idle"; 6185425fb15SMikko Perttunen status = "disabled"; 6195425fb15SMikko Perttunen }; 6205425fb15SMikko Perttunen 621a4131561SThierry Reding /* shares pads with dpaux2 */ 622a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 623d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6245425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 6255425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 6265425fb15SMikko Perttunen #address-cells = <1>; 6275425fb15SMikko Perttunen #size-cells = <0>; 6285425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 6295425fb15SMikko Perttunen clock-names = "div-clk"; 6305425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 6315425fb15SMikko Perttunen reset-names = "i2c"; 632a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 633a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 634a4131561SThierry Reding pinctrl-names = "default", "idle"; 6355425fb15SMikko Perttunen status = "disabled"; 6365425fb15SMikko Perttunen }; 6375425fb15SMikko Perttunen 638a4131561SThierry Reding /* shares pads with dpaux3 */ 639a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 640d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 6415425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 6425425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 6435425fb15SMikko Perttunen #address-cells = <1>; 6445425fb15SMikko Perttunen #size-cells = <0>; 6455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 6465425fb15SMikko Perttunen clock-names = "div-clk"; 6475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 6485425fb15SMikko Perttunen reset-names = "i2c"; 649a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 650a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 651a4131561SThierry Reding pinctrl-names = "default", "idle"; 6525425fb15SMikko Perttunen status = "disabled"; 6535425fb15SMikko Perttunen }; 6545425fb15SMikko Perttunen 65596ded827SSowjanya Komatineni spi@3270000 { 65696ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 65796ded827SSowjanya Komatineni reg = <0x3270000 0x1000>; 65896ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 65996ded827SSowjanya Komatineni #address-cells = <1>; 66096ded827SSowjanya Komatineni #size-cells = <0>; 66196ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 66296ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 66396ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 66496ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 66596ded827SSowjanya Komatineni reset-names = "qspi"; 66696ded827SSowjanya Komatineni status = "disabled"; 66796ded827SSowjanya Komatineni }; 66896ded827SSowjanya Komatineni 66996ded827SSowjanya Komatineni spi@3300000 { 67096ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 67196ded827SSowjanya Komatineni reg = <0x3300000 0x1000>; 67296ded827SSowjanya Komatineni interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 67396ded827SSowjanya Komatineni #address-cells = <1>; 67496ded827SSowjanya Komatineni #size-cells = <0>; 67596ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI1>, 67696ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI1_PM>; 67796ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 67896ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI1>; 67996ded827SSowjanya Komatineni reset-names = "qspi"; 68096ded827SSowjanya Komatineni status = "disabled"; 68196ded827SSowjanya Komatineni }; 68296ded827SSowjanya Komatineni 6836a574ec7SThierry Reding pwm1: pwm@3280000 { 6846a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6856a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6866a574ec7SThierry Reding reg = <0x3280000 0x10000>; 6876a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 6886a574ec7SThierry Reding clock-names = "pwm"; 6896a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 6906a574ec7SThierry Reding reset-names = "pwm"; 6916a574ec7SThierry Reding status = "disabled"; 6926a574ec7SThierry Reding #pwm-cells = <2>; 6936a574ec7SThierry Reding }; 6946a574ec7SThierry Reding 6956a574ec7SThierry Reding pwm2: pwm@3290000 { 6966a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 6976a574ec7SThierry Reding "nvidia,tegra186-pwm"; 6986a574ec7SThierry Reding reg = <0x3290000 0x10000>; 6996a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 7006a574ec7SThierry Reding clock-names = "pwm"; 7016a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 7026a574ec7SThierry Reding reset-names = "pwm"; 7036a574ec7SThierry Reding status = "disabled"; 7046a574ec7SThierry Reding #pwm-cells = <2>; 7056a574ec7SThierry Reding }; 7066a574ec7SThierry Reding 7076a574ec7SThierry Reding pwm3: pwm@32a0000 { 7086a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7096a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7106a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 7116a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 7126a574ec7SThierry Reding clock-names = "pwm"; 7136a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 7146a574ec7SThierry Reding reset-names = "pwm"; 7156a574ec7SThierry Reding status = "disabled"; 7166a574ec7SThierry Reding #pwm-cells = <2>; 7176a574ec7SThierry Reding }; 7186a574ec7SThierry Reding 7196a574ec7SThierry Reding pwm5: pwm@32c0000 { 7206a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7216a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7226a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 7236a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 7246a574ec7SThierry Reding clock-names = "pwm"; 7256a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 7266a574ec7SThierry Reding reset-names = "pwm"; 7276a574ec7SThierry Reding status = "disabled"; 7286a574ec7SThierry Reding #pwm-cells = <2>; 7296a574ec7SThierry Reding }; 7306a574ec7SThierry Reding 7316a574ec7SThierry Reding pwm6: pwm@32d0000 { 7326a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7336a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7346a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 7356a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 7366a574ec7SThierry Reding clock-names = "pwm"; 7376a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 7386a574ec7SThierry Reding reset-names = "pwm"; 7396a574ec7SThierry Reding status = "disabled"; 7406a574ec7SThierry Reding #pwm-cells = <2>; 7416a574ec7SThierry Reding }; 7426a574ec7SThierry Reding 7436a574ec7SThierry Reding pwm7: pwm@32e0000 { 7446a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7456a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7466a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 7476a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 7486a574ec7SThierry Reding clock-names = "pwm"; 7496a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 7506a574ec7SThierry Reding reset-names = "pwm"; 7516a574ec7SThierry Reding status = "disabled"; 7526a574ec7SThierry Reding #pwm-cells = <2>; 7536a574ec7SThierry Reding }; 7546a574ec7SThierry Reding 7556a574ec7SThierry Reding pwm8: pwm@32f0000 { 7566a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 7576a574ec7SThierry Reding "nvidia,tegra186-pwm"; 7586a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 7596a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 7606a574ec7SThierry Reding clock-names = "pwm"; 7616a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 7626a574ec7SThierry Reding reset-names = "pwm"; 7636a574ec7SThierry Reding status = "disabled"; 7646a574ec7SThierry Reding #pwm-cells = <2>; 7656a574ec7SThierry Reding }; 7666a574ec7SThierry Reding 76767bb17f6SThierry Reding sdmmc1: mmc@3400000 { 7682c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7695425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 7705425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 771c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 772c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 773c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7745425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 7755425fb15SMikko Perttunen reset-names = "sdhci"; 776d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 777d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 778d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 779c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 7804e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 7814e0f1229SSowjanya Komatineni <0x07>; 7824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 7834e0f1229SSowjanya Komatineni <0x07>; 7844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 7854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 7864e0f1229SSowjanya Komatineni <0x07>; 7874e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 7884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 7894e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 7904e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 7915425fb15SMikko Perttunen status = "disabled"; 7925425fb15SMikko Perttunen }; 7935425fb15SMikko Perttunen 79467bb17f6SThierry Reding sdmmc3: mmc@3440000 { 7952c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 7965425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 7975425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 798c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 799c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 800c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8015425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 8025425fb15SMikko Perttunen reset-names = "sdhci"; 803d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 804d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 805d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 806c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 8074e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 8084e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 8094e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 8104e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 8114e0f1229SSowjanya Komatineni <0x07>; 8124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 8134e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 8144e0f1229SSowjanya Komatineni <0x07>; 8154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 8164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 8174e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 8184e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 8195425fb15SMikko Perttunen status = "disabled"; 8205425fb15SMikko Perttunen }; 8215425fb15SMikko Perttunen 82267bb17f6SThierry Reding sdmmc4: mmc@3460000 { 8232c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 8245425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 8255425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 826c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 827c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 828c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 829351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 830351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 831351648d0SSowjanya Komatineni assigned-clock-parents = 832351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 8335425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 8345425fb15SMikko Perttunen reset-names = "sdhci"; 835d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 836d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 837d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 838c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 8394e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 8404e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 8414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 8424e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 8434e0f1229SSowjanya Komatineni <0x0a>; 8444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 8454e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 8464e0f1229SSowjanya Komatineni <0x0a>; 8474e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 8484e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 8494e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 850dfd3cb6fSSowjanya Komatineni supports-cqe; 8515425fb15SMikko Perttunen status = "disabled"; 8525425fb15SMikko Perttunen }; 8535425fb15SMikko Perttunen 8544878cc0cSSameer Pujar hda@3510000 { 8554878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 8564878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 8574878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 8584878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 85948f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 86048f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 86148f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 8624878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 86348f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, 86448f6e195SSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; 86548f6e195SSameer Pujar reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 8664878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 867d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 868d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 869d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 870c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 8714878cc0cSSameer Pujar status = "disabled"; 8724878cc0cSSameer Pujar }; 8734878cc0cSSameer Pujar 874fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 875fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 876fab7a039SJC Kuo reg = <0x03520000 0x1000>, 877fab7a039SJC Kuo <0x03540000 0x1000>; 878fab7a039SJC Kuo reg-names = "padctl", "ao"; 8796450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 880fab7a039SJC Kuo 881fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 882fab7a039SJC Kuo reset-names = "padctl"; 883fab7a039SJC Kuo 884fab7a039SJC Kuo status = "disabled"; 885fab7a039SJC Kuo 886fab7a039SJC Kuo pads { 887fab7a039SJC Kuo usb2 { 888fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 889fab7a039SJC Kuo clock-names = "trk"; 890fab7a039SJC Kuo 891fab7a039SJC Kuo lanes { 892fab7a039SJC Kuo usb2-0 { 893fab7a039SJC Kuo nvidia,function = "xusb"; 894fab7a039SJC Kuo status = "disabled"; 895fab7a039SJC Kuo #phy-cells = <0>; 896fab7a039SJC Kuo }; 897fab7a039SJC Kuo 898fab7a039SJC Kuo usb2-1 { 899fab7a039SJC Kuo nvidia,function = "xusb"; 900fab7a039SJC Kuo status = "disabled"; 901fab7a039SJC Kuo #phy-cells = <0>; 902fab7a039SJC Kuo }; 903fab7a039SJC Kuo 904fab7a039SJC Kuo usb2-2 { 905fab7a039SJC Kuo nvidia,function = "xusb"; 906fab7a039SJC Kuo status = "disabled"; 907fab7a039SJC Kuo #phy-cells = <0>; 908fab7a039SJC Kuo }; 909fab7a039SJC Kuo 910fab7a039SJC Kuo usb2-3 { 911fab7a039SJC Kuo nvidia,function = "xusb"; 912fab7a039SJC Kuo status = "disabled"; 913fab7a039SJC Kuo #phy-cells = <0>; 914fab7a039SJC Kuo }; 915fab7a039SJC Kuo }; 916fab7a039SJC Kuo }; 917fab7a039SJC Kuo 918fab7a039SJC Kuo usb3 { 919fab7a039SJC Kuo lanes { 920fab7a039SJC Kuo usb3-0 { 921fab7a039SJC Kuo nvidia,function = "xusb"; 922fab7a039SJC Kuo status = "disabled"; 923fab7a039SJC Kuo #phy-cells = <0>; 924fab7a039SJC Kuo }; 925fab7a039SJC Kuo 926fab7a039SJC Kuo usb3-1 { 927fab7a039SJC Kuo nvidia,function = "xusb"; 928fab7a039SJC Kuo status = "disabled"; 929fab7a039SJC Kuo #phy-cells = <0>; 930fab7a039SJC Kuo }; 931fab7a039SJC Kuo 932fab7a039SJC Kuo usb3-2 { 933fab7a039SJC Kuo nvidia,function = "xusb"; 934fab7a039SJC Kuo status = "disabled"; 935fab7a039SJC Kuo #phy-cells = <0>; 936fab7a039SJC Kuo }; 937fab7a039SJC Kuo 938fab7a039SJC Kuo usb3-3 { 939fab7a039SJC Kuo nvidia,function = "xusb"; 940fab7a039SJC Kuo status = "disabled"; 941fab7a039SJC Kuo #phy-cells = <0>; 942fab7a039SJC Kuo }; 943fab7a039SJC Kuo }; 944fab7a039SJC Kuo }; 945fab7a039SJC Kuo }; 946fab7a039SJC Kuo 947fab7a039SJC Kuo ports { 948fab7a039SJC Kuo usb2-0 { 949fab7a039SJC Kuo status = "disabled"; 950fab7a039SJC Kuo }; 951fab7a039SJC Kuo 952fab7a039SJC Kuo usb2-1 { 953fab7a039SJC Kuo status = "disabled"; 954fab7a039SJC Kuo }; 955fab7a039SJC Kuo 956fab7a039SJC Kuo usb2-2 { 957fab7a039SJC Kuo status = "disabled"; 958fab7a039SJC Kuo }; 959fab7a039SJC Kuo 960fab7a039SJC Kuo usb2-3 { 961fab7a039SJC Kuo status = "disabled"; 962fab7a039SJC Kuo }; 963fab7a039SJC Kuo 964fab7a039SJC Kuo usb3-0 { 965fab7a039SJC Kuo status = "disabled"; 966fab7a039SJC Kuo }; 967fab7a039SJC Kuo 968fab7a039SJC Kuo usb3-1 { 969fab7a039SJC Kuo status = "disabled"; 970fab7a039SJC Kuo }; 971fab7a039SJC Kuo 972fab7a039SJC Kuo usb3-2 { 973fab7a039SJC Kuo status = "disabled"; 974fab7a039SJC Kuo }; 975fab7a039SJC Kuo 976fab7a039SJC Kuo usb3-3 { 977fab7a039SJC Kuo status = "disabled"; 978fab7a039SJC Kuo }; 979fab7a039SJC Kuo }; 980fab7a039SJC Kuo }; 981fab7a039SJC Kuo 982bc8788b2SNagarjuna Kristam usb@3550000 { 983bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 984bc8788b2SNagarjuna Kristam reg = <0x03550000 0x8000>, 985bc8788b2SNagarjuna Kristam <0x03558000 0x1000>; 986bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 987bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 988bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 989bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 990bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 991bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 992bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 993c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 994c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 995c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 996c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 997bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 998bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 999bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1000bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1001bc8788b2SNagarjuna Kristam status = "disabled"; 1002bc8788b2SNagarjuna Kristam }; 1003bc8788b2SNagarjuna Kristam 1004fab7a039SJC Kuo usb@3610000 { 1005fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 1006fab7a039SJC Kuo reg = <0x03610000 0x40000>, 1007fab7a039SJC Kuo <0x03600000 0x10000>; 1008fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1009fab7a039SJC Kuo 1010fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1011a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1012fab7a039SJC Kuo 1013fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1014fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1015fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1016fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1017fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1018fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1019fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1020fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1021fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1022fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1023fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1024fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1025fab7a039SJC Kuo "pll_e"; 1026c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1027c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1028c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1029c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1030fab7a039SJC Kuo 1031fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1032fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1033fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1034fab7a039SJC Kuo 1035fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1036fab7a039SJC Kuo status = "disabled"; 1037fab7a039SJC Kuo }; 1038fab7a039SJC Kuo 103909903c5eSJC Kuo fuse@3820000 { 104009903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 104109903c5eSJC Kuo reg = <0x03820000 0x10000>; 104209903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 104309903c5eSJC Kuo clock-names = "fuse"; 104409903c5eSJC Kuo }; 104509903c5eSJC Kuo 10465425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 10475425fb15SMikko Perttunen compatible = "arm,gic-400"; 10485425fb15SMikko Perttunen #interrupt-cells = <3>; 10495425fb15SMikko Perttunen interrupt-controller; 10505425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 10515425fb15SMikko Perttunen <0x03882000 0x2000>, 10525425fb15SMikko Perttunen <0x03884000 0x2000>, 10535425fb15SMikko Perttunen <0x03886000 0x2000>; 10545425fb15SMikko Perttunen interrupts = <GIC_PPI 9 10555425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 10565425fb15SMikko Perttunen interrupt-parent = <&gic>; 10575425fb15SMikko Perttunen }; 10585425fb15SMikko Perttunen 1059badb80beSThierry Reding cec@3960000 { 1060badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 1061badb80beSThierry Reding reg = <0x03960000 0x10000>; 1062badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1063badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1064badb80beSThierry Reding clock-names = "cec"; 1065badb80beSThierry Reding status = "disabled"; 1066badb80beSThierry Reding }; 1067badb80beSThierry Reding 10685425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1069a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 10705425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 1071a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1072a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1073a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1074a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1075a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1076a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1077a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1078a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1079a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1080a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1081a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1082a38570c2SMikko Perttunen "shared7"; 1083a38570c2SMikko Perttunen #mbox-cells = <2>; 1084a38570c2SMikko Perttunen }; 1085a38570c2SMikko Perttunen 10862602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 10872602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10882602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 10892602c32fSVidya Sagar reg-names = "ctl"; 10902602c32fSVidya Sagar 10912602c32fSVidya Sagar #phy-cells = <0>; 10922602c32fSVidya Sagar }; 10932602c32fSVidya Sagar 10942602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 10952602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 10962602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 10972602c32fSVidya Sagar reg-names = "ctl"; 10982602c32fSVidya Sagar 10992602c32fSVidya Sagar #phy-cells = <0>; 11002602c32fSVidya Sagar }; 11012602c32fSVidya Sagar 11022602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 11032602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11042602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 11052602c32fSVidya Sagar reg-names = "ctl"; 11062602c32fSVidya Sagar 11072602c32fSVidya Sagar #phy-cells = <0>; 11082602c32fSVidya Sagar }; 11092602c32fSVidya Sagar 11102602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 11112602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11122602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 11132602c32fSVidya Sagar reg-names = "ctl"; 11142602c32fSVidya Sagar 11152602c32fSVidya Sagar #phy-cells = <0>; 11162602c32fSVidya Sagar }; 11172602c32fSVidya Sagar 11182602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 11192602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11202602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 11212602c32fSVidya Sagar reg-names = "ctl"; 11222602c32fSVidya Sagar 11232602c32fSVidya Sagar #phy-cells = <0>; 11242602c32fSVidya Sagar }; 11252602c32fSVidya Sagar 11262602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 11272602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11282602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 11292602c32fSVidya Sagar reg-names = "ctl"; 11302602c32fSVidya Sagar 11312602c32fSVidya Sagar #phy-cells = <0>; 11322602c32fSVidya Sagar }; 11332602c32fSVidya Sagar 11342602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 11352602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11362602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 11372602c32fSVidya Sagar reg-names = "ctl"; 11382602c32fSVidya Sagar 11392602c32fSVidya Sagar #phy-cells = <0>; 11402602c32fSVidya Sagar }; 11412602c32fSVidya Sagar 11422602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 11432602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11442602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 11452602c32fSVidya Sagar reg-names = "ctl"; 11462602c32fSVidya Sagar 11472602c32fSVidya Sagar #phy-cells = <0>; 11482602c32fSVidya Sagar }; 11492602c32fSVidya Sagar 11502602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 11512602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11522602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 11532602c32fSVidya Sagar reg-names = "ctl"; 11542602c32fSVidya Sagar 11552602c32fSVidya Sagar #phy-cells = <0>; 11562602c32fSVidya Sagar }; 11572602c32fSVidya Sagar 11582602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 11592602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11602602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 11612602c32fSVidya Sagar reg-names = "ctl"; 11622602c32fSVidya Sagar 11632602c32fSVidya Sagar #phy-cells = <0>; 11642602c32fSVidya Sagar }; 11652602c32fSVidya Sagar 11662602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 11672602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11682602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 11692602c32fSVidya Sagar reg-names = "ctl"; 11702602c32fSVidya Sagar 11712602c32fSVidya Sagar #phy-cells = <0>; 11722602c32fSVidya Sagar }; 11732602c32fSVidya Sagar 11742602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 11752602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11762602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 11772602c32fSVidya Sagar reg-names = "ctl"; 11782602c32fSVidya Sagar 11792602c32fSVidya Sagar #phy-cells = <0>; 11802602c32fSVidya Sagar }; 11812602c32fSVidya Sagar 11822602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 11832602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11842602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 11852602c32fSVidya Sagar reg-names = "ctl"; 11862602c32fSVidya Sagar 11872602c32fSVidya Sagar #phy-cells = <0>; 11882602c32fSVidya Sagar }; 11892602c32fSVidya Sagar 11902602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 11912602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 11922602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 11932602c32fSVidya Sagar reg-names = "ctl"; 11942602c32fSVidya Sagar 11952602c32fSVidya Sagar #phy-cells = <0>; 11962602c32fSVidya Sagar }; 11972602c32fSVidya Sagar 11982602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 11992602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12002602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 12012602c32fSVidya Sagar reg-names = "ctl"; 12022602c32fSVidya Sagar 12032602c32fSVidya Sagar #phy-cells = <0>; 12042602c32fSVidya Sagar }; 12052602c32fSVidya Sagar 12062602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 12072602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12082602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 12092602c32fSVidya Sagar reg-names = "ctl"; 12102602c32fSVidya Sagar 12112602c32fSVidya Sagar #phy-cells = <0>; 12122602c32fSVidya Sagar }; 12132602c32fSVidya Sagar 12142602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 12152602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12162602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 12172602c32fSVidya Sagar reg-names = "ctl"; 12182602c32fSVidya Sagar 12192602c32fSVidya Sagar #phy-cells = <0>; 12202602c32fSVidya Sagar }; 12212602c32fSVidya Sagar 12222602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 12232602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12242602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 12252602c32fSVidya Sagar reg-names = "ctl"; 12262602c32fSVidya Sagar 12272602c32fSVidya Sagar #phy-cells = <0>; 12282602c32fSVidya Sagar }; 12292602c32fSVidya Sagar 12302602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 12312602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12322602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 12332602c32fSVidya Sagar reg-names = "ctl"; 12342602c32fSVidya Sagar 12352602c32fSVidya Sagar #phy-cells = <0>; 12362602c32fSVidya Sagar }; 12372602c32fSVidya Sagar 12382602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 12392602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 12402602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 12412602c32fSVidya Sagar reg-names = "ctl"; 12422602c32fSVidya Sagar 12432602c32fSVidya Sagar #phy-cells = <0>; 12442602c32fSVidya Sagar }; 12452602c32fSVidya Sagar 1246a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1247a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 12481741e187SDipen Patel reg = <0x0c150000 0x90000>; 1249a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1250a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1251a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1252a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1253a38570c2SMikko Perttunen /* 1254a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1255a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1256a38570c2SMikko Perttunen */ 1257a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 12585425fb15SMikko Perttunen #mbox-cells = <2>; 12595425fb15SMikko Perttunen }; 12605425fb15SMikko Perttunen 12615425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1262d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12635425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 12645425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 12655425fb15SMikko Perttunen #address-cells = <1>; 12665425fb15SMikko Perttunen #size-cells = <0>; 12675425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 12685425fb15SMikko Perttunen clock-names = "div-clk"; 12695425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 12705425fb15SMikko Perttunen reset-names = "i2c"; 12715425fb15SMikko Perttunen status = "disabled"; 12725425fb15SMikko Perttunen }; 12735425fb15SMikko Perttunen 12745425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1275d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 12765425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 12775425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 12785425fb15SMikko Perttunen #address-cells = <1>; 12795425fb15SMikko Perttunen #size-cells = <0>; 12805425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 12815425fb15SMikko Perttunen clock-names = "div-clk"; 12825425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 12835425fb15SMikko Perttunen reset-names = "i2c"; 12845425fb15SMikko Perttunen status = "disabled"; 12855425fb15SMikko Perttunen }; 12865425fb15SMikko Perttunen 12875425fb15SMikko Perttunen uartc: serial@c280000 { 12885425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 12895425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 12905425fb15SMikko Perttunen reg-shift = <2>; 12915425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 12925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 12935425fb15SMikko Perttunen clock-names = "serial"; 12945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 12955425fb15SMikko Perttunen reset-names = "serial"; 12965425fb15SMikko Perttunen status = "disabled"; 12975425fb15SMikko Perttunen }; 12985425fb15SMikko Perttunen 12995425fb15SMikko Perttunen uartg: serial@c290000 { 13005425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 13015425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 13025425fb15SMikko Perttunen reg-shift = <2>; 13035425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 13045425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 13055425fb15SMikko Perttunen clock-names = "serial"; 13065425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 13075425fb15SMikko Perttunen reset-names = "serial"; 13085425fb15SMikko Perttunen status = "disabled"; 13095425fb15SMikko Perttunen }; 13105425fb15SMikko Perttunen 131137e5a31dSThierry Reding rtc: rtc@c2a0000 { 131237e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 131337e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 131437e5a31dSThierry Reding interrupt-parent = <&pmc>; 131537e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 131637e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 131737e5a31dSThierry Reding clock-names = "rtc"; 131837e5a31dSThierry Reding status = "disabled"; 131937e5a31dSThierry Reding }; 132037e5a31dSThierry Reding 13214d286331SThierry Reding gpio_aon: gpio@c2f0000 { 13224d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 13234d286331SThierry Reding reg-names = "security", "gpio"; 13244d286331SThierry Reding reg = <0xc2f0000 0x1000>, 13254d286331SThierry Reding <0xc2f1000 0x1000>; 1326*0a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1327*0a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1328*0a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1329*0a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 13304d286331SThierry Reding gpio-controller; 13314d286331SThierry Reding #gpio-cells = <2>; 13324d286331SThierry Reding interrupt-controller; 13334d286331SThierry Reding #interrupt-cells = <2>; 13344d286331SThierry Reding }; 13354d286331SThierry Reding 13366a574ec7SThierry Reding pwm4: pwm@c340000 { 13376a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 13386a574ec7SThierry Reding "nvidia,tegra186-pwm"; 13396a574ec7SThierry Reding reg = <0xc340000 0x10000>; 13406a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 13416a574ec7SThierry Reding clock-names = "pwm"; 13426a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 13436a574ec7SThierry Reding reset-names = "pwm"; 13446a574ec7SThierry Reding status = "disabled"; 13456a574ec7SThierry Reding #pwm-cells = <2>; 13466a574ec7SThierry Reding }; 13476a574ec7SThierry Reding 134838ecf1e5SThierry Reding pmc: pmc@c360000 { 13495425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 13505425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 13515425fb15SMikko Perttunen <0x0c370000 0x10000>, 13525425fb15SMikko Perttunen <0x0c380000 0x10000>, 13535425fb15SMikko Perttunen <0x0c390000 0x10000>, 13545425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 13555425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 135638ecf1e5SThierry Reding 135738ecf1e5SThierry Reding #interrupt-cells = <2>; 135838ecf1e5SThierry Reding interrupt-controller; 13595425fb15SMikko Perttunen }; 13603db6d3baSThierry Reding 1361c7289b1cSThierry Reding smmu: iommu@12000000 { 1362c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1363c7289b1cSThierry Reding reg = <0x12000000 0x800000>, 1364c7289b1cSThierry Reding <0x11000000 0x800000>; 1365c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1367c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1431c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1432c7289b1cSThierry Reding #global-interrupts = <2>; 1433c7289b1cSThierry Reding #iommu-cells = <1>; 1434c7289b1cSThierry Reding 1435c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1436c7289b1cSThierry Reding status = "okay"; 1437c7289b1cSThierry Reding }; 1438c7289b1cSThierry Reding 14393db6d3baSThierry Reding host1x@13e00000 { 1440ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 14413db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 14423db6d3baSThierry Reding <0x13e10000 0x10000>; 14433db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 14443db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 14453db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1446052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 14473db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 14483db6d3baSThierry Reding clock-names = "host1x"; 14493db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 14503db6d3baSThierry Reding reset-names = "host1x"; 14513db6d3baSThierry Reding 14523db6d3baSThierry Reding #address-cells = <1>; 14533db6d3baSThierry Reding #size-cells = <1>; 14543db6d3baSThierry Reding 14553db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 1456d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1457d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1458c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 14593db6d3baSThierry Reding 14603db6d3baSThierry Reding display-hub@15200000 { 1461aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 1462611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 14633db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 14643db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 14653db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 14663db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 14673db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 14683db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 14693db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 14703db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 14713db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 14723db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 14733db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 14743db6d3baSThierry Reding clock-names = "disp", "hub"; 14753db6d3baSThierry Reding status = "disabled"; 14763db6d3baSThierry Reding 14773db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 14783db6d3baSThierry Reding 14793db6d3baSThierry Reding #address-cells = <1>; 14803db6d3baSThierry Reding #size-cells = <1>; 14813db6d3baSThierry Reding 14823db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 14833db6d3baSThierry Reding 14843db6d3baSThierry Reding display@15200000 { 14853db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 14863db6d3baSThierry Reding reg = <0x15200000 0x10000>; 14873db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 14883db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 14893db6d3baSThierry Reding clock-names = "dc"; 14903db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 14913db6d3baSThierry Reding reset-names = "dc"; 14923db6d3baSThierry Reding 14933db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1494d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1495d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1496d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 14973db6d3baSThierry Reding 14983db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 14993db6d3baSThierry Reding nvidia,head = <0>; 15003db6d3baSThierry Reding }; 15013db6d3baSThierry Reding 15023db6d3baSThierry Reding display@15210000 { 15033db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 15043db6d3baSThierry Reding reg = <0x15210000 0x10000>; 15053db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 15063db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 15073db6d3baSThierry Reding clock-names = "dc"; 15083db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 15093db6d3baSThierry Reding reset-names = "dc"; 15103db6d3baSThierry Reding 15113db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1512d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1513d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1514d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 15153db6d3baSThierry Reding 15163db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 15173db6d3baSThierry Reding nvidia,head = <1>; 15183db6d3baSThierry Reding }; 15193db6d3baSThierry Reding 15203db6d3baSThierry Reding display@15220000 { 15213db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 15223db6d3baSThierry Reding reg = <0x15220000 0x10000>; 15233db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 15243db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 15253db6d3baSThierry Reding clock-names = "dc"; 15263db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 15273db6d3baSThierry Reding reset-names = "dc"; 15283db6d3baSThierry Reding 15293db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1530d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1531d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1532d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 15333db6d3baSThierry Reding 15343db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 15353db6d3baSThierry Reding nvidia,head = <2>; 15363db6d3baSThierry Reding }; 15373db6d3baSThierry Reding 15383db6d3baSThierry Reding display@15230000 { 15393db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 15403db6d3baSThierry Reding reg = <0x15230000 0x10000>; 15413db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 15423db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 15433db6d3baSThierry Reding clock-names = "dc"; 15443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 15453db6d3baSThierry Reding reset-names = "dc"; 15463db6d3baSThierry Reding 15473db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1548d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1549d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1550d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 15513db6d3baSThierry Reding 15523db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 15533db6d3baSThierry Reding nvidia,head = <3>; 15543db6d3baSThierry Reding }; 15553db6d3baSThierry Reding }; 15563db6d3baSThierry Reding 15578d424ec2SThierry Reding vic@15340000 { 15588d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 15598d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 15608d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 15618d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 15628d424ec2SThierry Reding clock-names = "vic"; 15638d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 15648d424ec2SThierry Reding reset-names = "vic"; 15658d424ec2SThierry Reding 15668d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1567d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1568d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1569d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1570c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 15718d424ec2SThierry Reding }; 15728d424ec2SThierry Reding 15733db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 15743db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 15753db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 15763db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 15773db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 15783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 15793db6d3baSThierry Reding clock-names = "dpaux", "parent"; 15803db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 15813db6d3baSThierry Reding reset-names = "dpaux"; 15823db6d3baSThierry Reding status = "disabled"; 15833db6d3baSThierry Reding 15843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 15853db6d3baSThierry Reding 15863db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 15873db6d3baSThierry Reding groups = "dpaux-io"; 15883db6d3baSThierry Reding function = "aux"; 15893db6d3baSThierry Reding }; 15903db6d3baSThierry Reding 15913db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 15923db6d3baSThierry Reding groups = "dpaux-io"; 15933db6d3baSThierry Reding function = "i2c"; 15943db6d3baSThierry Reding }; 15953db6d3baSThierry Reding 15963db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 15973db6d3baSThierry Reding groups = "dpaux-io"; 15983db6d3baSThierry Reding function = "off"; 15993db6d3baSThierry Reding }; 16003db6d3baSThierry Reding 16013db6d3baSThierry Reding i2c-bus { 16023db6d3baSThierry Reding #address-cells = <1>; 16033db6d3baSThierry Reding #size-cells = <0>; 16043db6d3baSThierry Reding }; 16053db6d3baSThierry Reding }; 16063db6d3baSThierry Reding 16073db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 16083db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 16093db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 16103db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 16113db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 16123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 16133db6d3baSThierry Reding clock-names = "dpaux", "parent"; 16143db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 16153db6d3baSThierry Reding reset-names = "dpaux"; 16163db6d3baSThierry Reding status = "disabled"; 16173db6d3baSThierry Reding 16183db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16193db6d3baSThierry Reding 16203db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 16213db6d3baSThierry Reding groups = "dpaux-io"; 16223db6d3baSThierry Reding function = "aux"; 16233db6d3baSThierry Reding }; 16243db6d3baSThierry Reding 16253db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 16263db6d3baSThierry Reding groups = "dpaux-io"; 16273db6d3baSThierry Reding function = "i2c"; 16283db6d3baSThierry Reding }; 16293db6d3baSThierry Reding 16303db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 16313db6d3baSThierry Reding groups = "dpaux-io"; 16323db6d3baSThierry Reding function = "off"; 16333db6d3baSThierry Reding }; 16343db6d3baSThierry Reding 16353db6d3baSThierry Reding i2c-bus { 16363db6d3baSThierry Reding #address-cells = <1>; 16373db6d3baSThierry Reding #size-cells = <0>; 16383db6d3baSThierry Reding }; 16393db6d3baSThierry Reding }; 16403db6d3baSThierry Reding 16413db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 16423db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 16433db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 16443db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 16453db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 16463db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 16473db6d3baSThierry Reding clock-names = "dpaux", "parent"; 16483db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 16493db6d3baSThierry Reding reset-names = "dpaux"; 16503db6d3baSThierry Reding status = "disabled"; 16513db6d3baSThierry Reding 16523db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16533db6d3baSThierry Reding 16543db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 16553db6d3baSThierry Reding groups = "dpaux-io"; 16563db6d3baSThierry Reding function = "aux"; 16573db6d3baSThierry Reding }; 16583db6d3baSThierry Reding 16593db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 16603db6d3baSThierry Reding groups = "dpaux-io"; 16613db6d3baSThierry Reding function = "i2c"; 16623db6d3baSThierry Reding }; 16633db6d3baSThierry Reding 16643db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 16653db6d3baSThierry Reding groups = "dpaux-io"; 16663db6d3baSThierry Reding function = "off"; 16673db6d3baSThierry Reding }; 16683db6d3baSThierry Reding 16693db6d3baSThierry Reding i2c-bus { 16703db6d3baSThierry Reding #address-cells = <1>; 16713db6d3baSThierry Reding #size-cells = <0>; 16723db6d3baSThierry Reding }; 16733db6d3baSThierry Reding }; 16743db6d3baSThierry Reding 16753db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 16763db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 16773db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 16783db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 16793db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 16803db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 16813db6d3baSThierry Reding clock-names = "dpaux", "parent"; 16823db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 16833db6d3baSThierry Reding reset-names = "dpaux"; 16843db6d3baSThierry Reding status = "disabled"; 16853db6d3baSThierry Reding 16863db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 16873db6d3baSThierry Reding 16883db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 16893db6d3baSThierry Reding groups = "dpaux-io"; 16903db6d3baSThierry Reding function = "aux"; 16913db6d3baSThierry Reding }; 16923db6d3baSThierry Reding 16933db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 16943db6d3baSThierry Reding groups = "dpaux-io"; 16953db6d3baSThierry Reding function = "i2c"; 16963db6d3baSThierry Reding }; 16973db6d3baSThierry Reding 16983db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 16993db6d3baSThierry Reding groups = "dpaux-io"; 17003db6d3baSThierry Reding function = "off"; 17013db6d3baSThierry Reding }; 17023db6d3baSThierry Reding 17033db6d3baSThierry Reding i2c-bus { 17043db6d3baSThierry Reding #address-cells = <1>; 17053db6d3baSThierry Reding #size-cells = <0>; 17063db6d3baSThierry Reding }; 17073db6d3baSThierry Reding }; 17083db6d3baSThierry Reding 17093db6d3baSThierry Reding sor0: sor@15b00000 { 17103db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 17113db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 17123db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 17133db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 17143db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 17153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 17163db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 17193db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17203db6d3baSThierry Reding "pad"; 17213db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 17223db6d3baSThierry Reding reset-names = "sor"; 17233db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 17243db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 17253db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 17263db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17273db6d3baSThierry Reding status = "disabled"; 17283db6d3baSThierry Reding 17293db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17303db6d3baSThierry Reding nvidia,interface = <0>; 17313db6d3baSThierry Reding }; 17323db6d3baSThierry Reding 17333db6d3baSThierry Reding sor1: sor@15b40000 { 17343db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1735939e7430SThierry Reding reg = <0x15b40000 0x40000>; 17363db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 17373db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 17383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 17393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 17403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 17433db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17443db6d3baSThierry Reding "pad"; 17453db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 17463db6d3baSThierry Reding reset-names = "sor"; 17473db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 17483db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 17493db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 17503db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17513db6d3baSThierry Reding status = "disabled"; 17523db6d3baSThierry Reding 17533db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17543db6d3baSThierry Reding nvidia,interface = <1>; 17553db6d3baSThierry Reding }; 17563db6d3baSThierry Reding 17573db6d3baSThierry Reding sor2: sor@15b80000 { 17583db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 17593db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 17603db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 17613db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 17623db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 17633db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 17643db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17663db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 17673db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17683db6d3baSThierry Reding "pad"; 17693db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 17703db6d3baSThierry Reding reset-names = "sor"; 17713db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 17723db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 17733db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 17743db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17753db6d3baSThierry Reding status = "disabled"; 17763db6d3baSThierry Reding 17773db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 17783db6d3baSThierry Reding nvidia,interface = <2>; 17793db6d3baSThierry Reding }; 17803db6d3baSThierry Reding 17813db6d3baSThierry Reding sor3: sor@15bc0000 { 17823db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 17833db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 17843db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 17853db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 17863db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 17873db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 17883db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 17893db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 17903db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 17913db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 17923db6d3baSThierry Reding "pad"; 17933db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 17943db6d3baSThierry Reding reset-names = "sor"; 17953db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 17963db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 17973db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 17983db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 17993db6d3baSThierry Reding status = "disabled"; 18003db6d3baSThierry Reding 18013db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 18023db6d3baSThierry Reding nvidia,interface = <3>; 18033db6d3baSThierry Reding }; 18043db6d3baSThierry Reding }; 18050f134e39SThierry Reding 18060f134e39SThierry Reding gpu@17000000 { 18070f134e39SThierry Reding compatible = "nvidia,gv11b"; 1808818ae79aSThierry Reding reg = <0x17000000 0x1000000>, 1809818ae79aSThierry Reding <0x18000000 0x1000000>; 18100f134e39SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 18110f134e39SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 18120f134e39SThierry Reding interrupt-names = "stall", "nonstall"; 18130f134e39SThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 18140f134e39SThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 18150f134e39SThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 18160f134e39SThierry Reding clock-names = "gpu", "pwr", "fuse"; 18170f134e39SThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 18180f134e39SThierry Reding reset-names = "gpu"; 18190f134e39SThierry Reding dma-coherent; 18200f134e39SThierry Reding 18210f134e39SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 18220f134e39SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 18230f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 18240f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 18250f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 18260f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 18270f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 18280f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 18290f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 18300f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 18310f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 18320f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 18330f134e39SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 18340f134e39SThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 18350f134e39SThierry Reding "read-1", "read-1-hp", "write-1", 18360f134e39SThierry Reding "read-2", "read-2-hp", "write-2", 18370f134e39SThierry Reding "read-3", "read-3-hp", "write-3"; 18380f134e39SThierry Reding }; 18395425fb15SMikko Perttunen }; 18405425fb15SMikko Perttunen 18412602c32fSVidya Sagar pcie@14100000 { 1842f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18432602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1844644c569dSThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 1845644c569dSThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 1846644c569dSThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1847644c569dSThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 18482602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 18492602c32fSVidya Sagar 18502602c32fSVidya Sagar status = "disabled"; 18512602c32fSVidya Sagar 18522602c32fSVidya Sagar #address-cells = <3>; 18532602c32fSVidya Sagar #size-cells = <2>; 18542602c32fSVidya Sagar device_type = "pci"; 18552602c32fSVidya Sagar num-lanes = <1>; 18562602c32fSVidya Sagar num-viewport = <8>; 18572602c32fSVidya Sagar linux,pci-domain = <1>; 18582602c32fSVidya Sagar 18592602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 18602602c32fSVidya Sagar clock-names = "core"; 18612602c32fSVidya Sagar 18622602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 18632602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 18642602c32fSVidya Sagar reset-names = "apb", "core"; 18652602c32fSVidya Sagar 18662602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 18672602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 18682602c32fSVidya Sagar interrupt-names = "intr", "msi"; 18692602c32fSVidya Sagar 18702602c32fSVidya Sagar #interrupt-cells = <1>; 18712602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 18722602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 18732602c32fSVidya Sagar 18742602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 18752602c32fSVidya Sagar 18762602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 18772602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 18782602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 18792602c32fSVidya Sagar 18802602c32fSVidya Sagar bus-range = <0x0 0xff>; 1881d5237c7cSThierry Reding 18828a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 18838a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 18848a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1885d5237c7cSThierry Reding 1886d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 1887d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 1888ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1889ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE1>; 1890ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 1891ba02920cSVidya Sagar iommu-map-mask = <0x0>; 1892ba02920cSVidya Sagar dma-coherent; 18932602c32fSVidya Sagar }; 18942602c32fSVidya Sagar 18952602c32fSVidya Sagar pcie@14120000 { 1896f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 18972602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1898644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 1899644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 1900644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1901644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19022602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19032602c32fSVidya Sagar 19042602c32fSVidya Sagar status = "disabled"; 19052602c32fSVidya Sagar 19062602c32fSVidya Sagar #address-cells = <3>; 19072602c32fSVidya Sagar #size-cells = <2>; 19082602c32fSVidya Sagar device_type = "pci"; 19092602c32fSVidya Sagar num-lanes = <1>; 19102602c32fSVidya Sagar num-viewport = <8>; 19112602c32fSVidya Sagar linux,pci-domain = <2>; 19122602c32fSVidya Sagar 19132602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 19142602c32fSVidya Sagar clock-names = "core"; 19152602c32fSVidya Sagar 19162602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 19172602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 19182602c32fSVidya Sagar reset-names = "apb", "core"; 19192602c32fSVidya Sagar 19202602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19212602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19222602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19232602c32fSVidya Sagar 19242602c32fSVidya Sagar #interrupt-cells = <1>; 19252602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19262602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 19272602c32fSVidya Sagar 19282602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 19292602c32fSVidya Sagar 19302602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19312602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19322602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19332602c32fSVidya Sagar 19342602c32fSVidya Sagar bus-range = <0x0 0xff>; 1935d5237c7cSThierry Reding 19368a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 19378a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 19388a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1939d5237c7cSThierry Reding 1940d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 1941d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 1942ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1943ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE2>; 1944ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 1945ba02920cSVidya Sagar iommu-map-mask = <0x0>; 1946ba02920cSVidya Sagar dma-coherent; 19472602c32fSVidya Sagar }; 19482602c32fSVidya Sagar 19492602c32fSVidya Sagar pcie@14140000 { 1950f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 19512602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1952644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 1953644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 1954644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 1955644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 19562602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 19572602c32fSVidya Sagar 19582602c32fSVidya Sagar status = "disabled"; 19592602c32fSVidya Sagar 19602602c32fSVidya Sagar #address-cells = <3>; 19612602c32fSVidya Sagar #size-cells = <2>; 19622602c32fSVidya Sagar device_type = "pci"; 19632602c32fSVidya Sagar num-lanes = <1>; 19642602c32fSVidya Sagar num-viewport = <8>; 19652602c32fSVidya Sagar linux,pci-domain = <3>; 19662602c32fSVidya Sagar 19672602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 19682602c32fSVidya Sagar clock-names = "core"; 19692602c32fSVidya Sagar 19702602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 19712602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 19722602c32fSVidya Sagar reset-names = "apb", "core"; 19732602c32fSVidya Sagar 19742602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 19752602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 19762602c32fSVidya Sagar interrupt-names = "intr", "msi"; 19772602c32fSVidya Sagar 19782602c32fSVidya Sagar #interrupt-cells = <1>; 19792602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 19802602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 19812602c32fSVidya Sagar 19822602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 19832602c32fSVidya Sagar 19842602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 19852602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 19862602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 19872602c32fSVidya Sagar 19882602c32fSVidya Sagar bus-range = <0x0 0xff>; 1989d5237c7cSThierry Reding 19908a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 19918a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 19928a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 1993d5237c7cSThierry Reding 1994d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 1995d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 1996ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 1997ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE3>; 1998ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 1999ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2000ba02920cSVidya Sagar dma-coherent; 20012602c32fSVidya Sagar }; 20022602c32fSVidya Sagar 20032602c32fSVidya Sagar pcie@14160000 { 2004f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 20052602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2006644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2007644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2008644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2009644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20102602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20112602c32fSVidya Sagar 20122602c32fSVidya Sagar status = "disabled"; 20132602c32fSVidya Sagar 20142602c32fSVidya Sagar #address-cells = <3>; 20152602c32fSVidya Sagar #size-cells = <2>; 20162602c32fSVidya Sagar device_type = "pci"; 20172602c32fSVidya Sagar num-lanes = <4>; 20182602c32fSVidya Sagar num-viewport = <8>; 20192602c32fSVidya Sagar linux,pci-domain = <4>; 20202602c32fSVidya Sagar 20212602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 20222602c32fSVidya Sagar clock-names = "core"; 20232602c32fSVidya Sagar 20242602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 20252602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 20262602c32fSVidya Sagar reset-names = "apb", "core"; 20272602c32fSVidya Sagar 20282602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20292602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20302602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20312602c32fSVidya Sagar 20322602c32fSVidya Sagar #interrupt-cells = <1>; 20332602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 20342602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 20352602c32fSVidya Sagar 20362602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 20372602c32fSVidya Sagar 20382602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 20392602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20402602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20412602c32fSVidya Sagar 20422602c32fSVidya Sagar bus-range = <0x0 0xff>; 2043d5237c7cSThierry Reding 20448a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 20458a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 20468a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2047d5237c7cSThierry Reding 2048d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2049d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2050ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2051ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2052ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2053ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2054ba02920cSVidya Sagar dma-coherent; 20552602c32fSVidya Sagar }; 20562602c32fSVidya Sagar 20572602c32fSVidya Sagar pcie@14180000 { 2058f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 20592602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2060644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2061644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2062644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2063644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 20642602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 20652602c32fSVidya Sagar 20662602c32fSVidya Sagar status = "disabled"; 20672602c32fSVidya Sagar 20682602c32fSVidya Sagar #address-cells = <3>; 20692602c32fSVidya Sagar #size-cells = <2>; 20702602c32fSVidya Sagar device_type = "pci"; 20712602c32fSVidya Sagar num-lanes = <8>; 20722602c32fSVidya Sagar num-viewport = <8>; 20732602c32fSVidya Sagar linux,pci-domain = <0>; 20742602c32fSVidya Sagar 20752602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 20762602c32fSVidya Sagar clock-names = "core"; 20772602c32fSVidya Sagar 20782602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 20792602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 20802602c32fSVidya Sagar reset-names = "apb", "core"; 20812602c32fSVidya Sagar 20822602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 20832602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 20842602c32fSVidya Sagar interrupt-names = "intr", "msi"; 20852602c32fSVidya Sagar 20862602c32fSVidya Sagar #interrupt-cells = <1>; 20872602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 20882602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 20892602c32fSVidya Sagar 20902602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 20912602c32fSVidya Sagar 20922602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 20932602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 20942602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 20952602c32fSVidya Sagar 20962602c32fSVidya Sagar bus-range = <0x0 0xff>; 2097d5237c7cSThierry Reding 20988a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 20998a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 21008a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2101d5237c7cSThierry Reding 2102d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2103d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2104ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2105ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2106ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2107ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2108ba02920cSVidya Sagar dma-coherent; 21092602c32fSVidya Sagar }; 21102602c32fSVidya Sagar 21112602c32fSVidya Sagar pcie@141a0000 { 2112f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 21132602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2114644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2115644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2116644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2117644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 21182602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 21192602c32fSVidya Sagar 21202602c32fSVidya Sagar status = "disabled"; 21212602c32fSVidya Sagar 21222602c32fSVidya Sagar #address-cells = <3>; 21232602c32fSVidya Sagar #size-cells = <2>; 21242602c32fSVidya Sagar device_type = "pci"; 21252602c32fSVidya Sagar num-lanes = <8>; 21262602c32fSVidya Sagar num-viewport = <8>; 21272602c32fSVidya Sagar linux,pci-domain = <5>; 21282602c32fSVidya Sagar 2129dbb72e2cSVidya Sagar pinctrl-names = "default"; 2130dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2131dbb72e2cSVidya Sagar 21322602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 21332602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 21342602c32fSVidya Sagar clock-names = "core", "core_m"; 21352602c32fSVidya Sagar 21362602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 21372602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 21382602c32fSVidya Sagar reset-names = "apb", "core"; 21392602c32fSVidya Sagar 21402602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 21412602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 21422602c32fSVidya Sagar interrupt-names = "intr", "msi"; 21432602c32fSVidya Sagar 21442602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 21452602c32fSVidya Sagar 21462602c32fSVidya Sagar #interrupt-cells = <1>; 21472602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 21482602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 21492602c32fSVidya Sagar 21502602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 21512602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21522602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 21532602c32fSVidya Sagar 21542602c32fSVidya Sagar bus-range = <0x0 0xff>; 2155d5237c7cSThierry Reding 21568a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 21578a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 21588a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2159d5237c7cSThierry Reding 2160d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2161d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2162ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2163ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2164ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2165ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2166ba02920cSVidya Sagar dma-coherent; 21672602c32fSVidya Sagar }; 21682602c32fSVidya Sagar 21690c988b73SVidya Sagar pcie_ep@14160000 { 2170bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 21710c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2172644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2173644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2174644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2175644c569dSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 21760c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 21770c988b73SVidya Sagar 21780c988b73SVidya Sagar status = "disabled"; 21790c988b73SVidya Sagar 21800c988b73SVidya Sagar num-lanes = <4>; 21810c988b73SVidya Sagar num-ib-windows = <2>; 21820c988b73SVidya Sagar num-ob-windows = <8>; 21830c988b73SVidya Sagar 21840c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 21850c988b73SVidya Sagar clock-names = "core"; 21860c988b73SVidya Sagar 21870c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 21880c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 21890c988b73SVidya Sagar reset-names = "apb", "core"; 21900c988b73SVidya Sagar 21910c988b73SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 21920c988b73SVidya Sagar interrupt-names = "intr"; 21930c988b73SVidya Sagar 21940c988b73SVidya Sagar nvidia,bpmp = <&bpmp 4>; 21950c988b73SVidya Sagar 21960c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 21970c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 21980c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2199ba02920cSVidya Sagar 2200ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2201ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2202ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2203ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE4>; 2204ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2205ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2206ba02920cSVidya Sagar dma-coherent; 22070c988b73SVidya Sagar }; 22080c988b73SVidya Sagar 22090c988b73SVidya Sagar pcie_ep@14180000 { 2210bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 22110c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2212644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2213644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2214644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2215644c569dSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 22160c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 22170c988b73SVidya Sagar 22180c988b73SVidya Sagar status = "disabled"; 22190c988b73SVidya Sagar 22200c988b73SVidya Sagar num-lanes = <8>; 22210c988b73SVidya Sagar num-ib-windows = <2>; 22220c988b73SVidya Sagar num-ob-windows = <8>; 22230c988b73SVidya Sagar 22240c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 22250c988b73SVidya Sagar clock-names = "core"; 22260c988b73SVidya Sagar 22270c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 22280c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 22290c988b73SVidya Sagar reset-names = "apb", "core"; 22300c988b73SVidya Sagar 22310c988b73SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 22320c988b73SVidya Sagar interrupt-names = "intr"; 22330c988b73SVidya Sagar 22340c988b73SVidya Sagar nvidia,bpmp = <&bpmp 0>; 22350c988b73SVidya Sagar 22360c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 22370c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22380c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2239ba02920cSVidya Sagar 2240ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2241ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2242ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2243ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE0>; 2244ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2245ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2246ba02920cSVidya Sagar dma-coherent; 22470c988b73SVidya Sagar }; 22480c988b73SVidya Sagar 22490c988b73SVidya Sagar pcie_ep@141a0000 { 2250bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 22510c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2252644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2253644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2254644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2255644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 22560c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 22570c988b73SVidya Sagar 22580c988b73SVidya Sagar status = "disabled"; 22590c988b73SVidya Sagar 22600c988b73SVidya Sagar num-lanes = <8>; 22610c988b73SVidya Sagar num-ib-windows = <2>; 22620c988b73SVidya Sagar num-ob-windows = <8>; 22630c988b73SVidya Sagar 22640c988b73SVidya Sagar pinctrl-names = "default"; 22650c988b73SVidya Sagar pinctrl-0 = <&clkreq_c5_bi_dir_state>; 22660c988b73SVidya Sagar 22670c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 22680c988b73SVidya Sagar clock-names = "core"; 22690c988b73SVidya Sagar 22700c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 22710c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 22720c988b73SVidya Sagar reset-names = "apb", "core"; 22730c988b73SVidya Sagar 22740c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 22750c988b73SVidya Sagar interrupt-names = "intr"; 22760c988b73SVidya Sagar 22770c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 22780c988b73SVidya Sagar 22790c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 22800c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 22810c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2282ba02920cSVidya Sagar 2283ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2284ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2285ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2286ba02920cSVidya Sagar iommus = <&smmu TEGRA194_SID_PCIE5>; 2287ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2288ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2289ba02920cSVidya Sagar dma-coherent; 22900c988b73SVidya Sagar }; 22910c988b73SVidya Sagar 2292e867fe41SThierry Reding sram@40000000 { 22935425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 22945425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 22955425fb15SMikko Perttunen #address-cells = <1>; 22965425fb15SMikko Perttunen #size-cells = <1>; 22975425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 22985425fb15SMikko Perttunen 2299e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 23005425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 23015425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 23025425fb15SMikko Perttunen pool; 23035425fb15SMikko Perttunen }; 23045425fb15SMikko Perttunen 2305e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 23065425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 23075425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 23085425fb15SMikko Perttunen pool; 23095425fb15SMikko Perttunen }; 23105425fb15SMikko Perttunen }; 23115425fb15SMikko Perttunen 23125425fb15SMikko Perttunen bpmp: bpmp { 23135425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 23145425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 23155425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 23165425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 23175425fb15SMikko Perttunen #clock-cells = <1>; 23185425fb15SMikko Perttunen #reset-cells = <1>; 23195425fb15SMikko Perttunen #power-domain-cells = <1>; 2320d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2321d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2322d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2323d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2324d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2325c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 23265425fb15SMikko Perttunen 23275425fb15SMikko Perttunen bpmp_i2c: i2c { 23285425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 23295425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 23305425fb15SMikko Perttunen #address-cells = <1>; 23315425fb15SMikko Perttunen #size-cells = <0>; 23325425fb15SMikko Perttunen }; 23335425fb15SMikko Perttunen 23345425fb15SMikko Perttunen bpmp_thermal: thermal { 23355425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 23365425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 23375425fb15SMikko Perttunen }; 23385425fb15SMikko Perttunen }; 23395425fb15SMikko Perttunen 23407780a034SMikko Perttunen cpus { 2341d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2342d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 23437780a034SMikko Perttunen #address-cells = <1>; 23447780a034SMikko Perttunen #size-cells = <0>; 23457780a034SMikko Perttunen 2346b45d322cSThierry Reding cpu0_0: cpu@0 { 234731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23487780a034SMikko Perttunen device_type = "cpu"; 2349b45d322cSThierry Reding reg = <0x000>; 23507780a034SMikko Perttunen enable-method = "psci"; 2351b45d322cSThierry Reding i-cache-size = <131072>; 2352b45d322cSThierry Reding i-cache-line-size = <64>; 2353b45d322cSThierry Reding i-cache-sets = <512>; 2354b45d322cSThierry Reding d-cache-size = <65536>; 2355b45d322cSThierry Reding d-cache-line-size = <64>; 2356b45d322cSThierry Reding d-cache-sets = <256>; 2357b45d322cSThierry Reding next-level-cache = <&l2c_0>; 23587780a034SMikko Perttunen }; 23597780a034SMikko Perttunen 2360b45d322cSThierry Reding cpu0_1: cpu@1 { 236131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23627780a034SMikko Perttunen device_type = "cpu"; 2363b45d322cSThierry Reding reg = <0x001>; 23647780a034SMikko Perttunen enable-method = "psci"; 2365b45d322cSThierry Reding i-cache-size = <131072>; 2366b45d322cSThierry Reding i-cache-line-size = <64>; 2367b45d322cSThierry Reding i-cache-sets = <512>; 2368b45d322cSThierry Reding d-cache-size = <65536>; 2369b45d322cSThierry Reding d-cache-line-size = <64>; 2370b45d322cSThierry Reding d-cache-sets = <256>; 2371b45d322cSThierry Reding next-level-cache = <&l2c_0>; 23727780a034SMikko Perttunen }; 23737780a034SMikko Perttunen 2374b45d322cSThierry Reding cpu1_0: cpu@100 { 237531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23767780a034SMikko Perttunen device_type = "cpu"; 23777780a034SMikko Perttunen reg = <0x100>; 23787780a034SMikko Perttunen enable-method = "psci"; 2379b45d322cSThierry Reding i-cache-size = <131072>; 2380b45d322cSThierry Reding i-cache-line-size = <64>; 2381b45d322cSThierry Reding i-cache-sets = <512>; 2382b45d322cSThierry Reding d-cache-size = <65536>; 2383b45d322cSThierry Reding d-cache-line-size = <64>; 2384b45d322cSThierry Reding d-cache-sets = <256>; 2385b45d322cSThierry Reding next-level-cache = <&l2c_1>; 23867780a034SMikko Perttunen }; 23877780a034SMikko Perttunen 2388b45d322cSThierry Reding cpu1_1: cpu@101 { 238931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 23907780a034SMikko Perttunen device_type = "cpu"; 23917780a034SMikko Perttunen reg = <0x101>; 23927780a034SMikko Perttunen enable-method = "psci"; 2393b45d322cSThierry Reding i-cache-size = <131072>; 2394b45d322cSThierry Reding i-cache-line-size = <64>; 2395b45d322cSThierry Reding i-cache-sets = <512>; 2396b45d322cSThierry Reding d-cache-size = <65536>; 2397b45d322cSThierry Reding d-cache-line-size = <64>; 2398b45d322cSThierry Reding d-cache-sets = <256>; 2399b45d322cSThierry Reding next-level-cache = <&l2c_1>; 24007780a034SMikko Perttunen }; 24017780a034SMikko Perttunen 2402b45d322cSThierry Reding cpu2_0: cpu@200 { 240331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 24047780a034SMikko Perttunen device_type = "cpu"; 24057780a034SMikko Perttunen reg = <0x200>; 24067780a034SMikko Perttunen enable-method = "psci"; 2407b45d322cSThierry Reding i-cache-size = <131072>; 2408b45d322cSThierry Reding i-cache-line-size = <64>; 2409b45d322cSThierry Reding i-cache-sets = <512>; 2410b45d322cSThierry Reding d-cache-size = <65536>; 2411b45d322cSThierry Reding d-cache-line-size = <64>; 2412b45d322cSThierry Reding d-cache-sets = <256>; 2413b45d322cSThierry Reding next-level-cache = <&l2c_2>; 24147780a034SMikko Perttunen }; 24157780a034SMikko Perttunen 2416b45d322cSThierry Reding cpu2_1: cpu@201 { 241731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 24187780a034SMikko Perttunen device_type = "cpu"; 24197780a034SMikko Perttunen reg = <0x201>; 24207780a034SMikko Perttunen enable-method = "psci"; 2421b45d322cSThierry Reding i-cache-size = <131072>; 2422b45d322cSThierry Reding i-cache-line-size = <64>; 2423b45d322cSThierry Reding i-cache-sets = <512>; 2424b45d322cSThierry Reding d-cache-size = <65536>; 2425b45d322cSThierry Reding d-cache-line-size = <64>; 2426b45d322cSThierry Reding d-cache-sets = <256>; 2427b45d322cSThierry Reding next-level-cache = <&l2c_2>; 24287780a034SMikko Perttunen }; 24297780a034SMikko Perttunen 2430b45d322cSThierry Reding cpu3_0: cpu@300 { 243131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 24327780a034SMikko Perttunen device_type = "cpu"; 2433b45d322cSThierry Reding reg = <0x300>; 24347780a034SMikko Perttunen enable-method = "psci"; 2435b45d322cSThierry Reding i-cache-size = <131072>; 2436b45d322cSThierry Reding i-cache-line-size = <64>; 2437b45d322cSThierry Reding i-cache-sets = <512>; 2438b45d322cSThierry Reding d-cache-size = <65536>; 2439b45d322cSThierry Reding d-cache-line-size = <64>; 2440b45d322cSThierry Reding d-cache-sets = <256>; 2441b45d322cSThierry Reding next-level-cache = <&l2c_3>; 24427780a034SMikko Perttunen }; 24437780a034SMikko Perttunen 2444b45d322cSThierry Reding cpu3_1: cpu@301 { 244531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 24467780a034SMikko Perttunen device_type = "cpu"; 2447b45d322cSThierry Reding reg = <0x301>; 24487780a034SMikko Perttunen enable-method = "psci"; 2449b45d322cSThierry Reding i-cache-size = <131072>; 2450b45d322cSThierry Reding i-cache-line-size = <64>; 2451b45d322cSThierry Reding i-cache-sets = <512>; 2452b45d322cSThierry Reding d-cache-size = <65536>; 2453b45d322cSThierry Reding d-cache-line-size = <64>; 2454b45d322cSThierry Reding d-cache-sets = <256>; 2455b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2456b45d322cSThierry Reding }; 2457b45d322cSThierry Reding 2458b45d322cSThierry Reding cpu-map { 2459b45d322cSThierry Reding cluster0 { 2460b45d322cSThierry Reding core0 { 2461b45d322cSThierry Reding cpu = <&cpu0_0>; 2462b45d322cSThierry Reding }; 2463b45d322cSThierry Reding 2464b45d322cSThierry Reding core1 { 2465b45d322cSThierry Reding cpu = <&cpu0_1>; 2466b45d322cSThierry Reding }; 2467b45d322cSThierry Reding }; 2468b45d322cSThierry Reding 2469b45d322cSThierry Reding cluster1 { 2470b45d322cSThierry Reding core0 { 2471b45d322cSThierry Reding cpu = <&cpu1_0>; 2472b45d322cSThierry Reding }; 2473b45d322cSThierry Reding 2474b45d322cSThierry Reding core1 { 2475b45d322cSThierry Reding cpu = <&cpu1_1>; 2476b45d322cSThierry Reding }; 2477b45d322cSThierry Reding }; 2478b45d322cSThierry Reding 2479b45d322cSThierry Reding cluster2 { 2480b45d322cSThierry Reding core0 { 2481b45d322cSThierry Reding cpu = <&cpu2_0>; 2482b45d322cSThierry Reding }; 2483b45d322cSThierry Reding 2484b45d322cSThierry Reding core1 { 2485b45d322cSThierry Reding cpu = <&cpu2_1>; 2486b45d322cSThierry Reding }; 2487b45d322cSThierry Reding }; 2488b45d322cSThierry Reding 2489b45d322cSThierry Reding cluster3 { 2490b45d322cSThierry Reding core0 { 2491b45d322cSThierry Reding cpu = <&cpu3_0>; 2492b45d322cSThierry Reding }; 2493b45d322cSThierry Reding 2494b45d322cSThierry Reding core1 { 2495b45d322cSThierry Reding cpu = <&cpu3_1>; 2496b45d322cSThierry Reding }; 2497b45d322cSThierry Reding }; 2498b45d322cSThierry Reding }; 2499b45d322cSThierry Reding 2500b45d322cSThierry Reding l2c_0: l2-cache0 { 2501b45d322cSThierry Reding cache-size = <2097152>; 2502b45d322cSThierry Reding cache-line-size = <64>; 2503b45d322cSThierry Reding cache-sets = <2048>; 2504b45d322cSThierry Reding next-level-cache = <&l3c>; 2505b45d322cSThierry Reding }; 2506b45d322cSThierry Reding 2507b45d322cSThierry Reding l2c_1: l2-cache1 { 2508b45d322cSThierry Reding cache-size = <2097152>; 2509b45d322cSThierry Reding cache-line-size = <64>; 2510b45d322cSThierry Reding cache-sets = <2048>; 2511b45d322cSThierry Reding next-level-cache = <&l3c>; 2512b45d322cSThierry Reding }; 2513b45d322cSThierry Reding 2514b45d322cSThierry Reding l2c_2: l2-cache2 { 2515b45d322cSThierry Reding cache-size = <2097152>; 2516b45d322cSThierry Reding cache-line-size = <64>; 2517b45d322cSThierry Reding cache-sets = <2048>; 2518b45d322cSThierry Reding next-level-cache = <&l3c>; 2519b45d322cSThierry Reding }; 2520b45d322cSThierry Reding 2521b45d322cSThierry Reding l2c_3: l2-cache3 { 2522b45d322cSThierry Reding cache-size = <2097152>; 2523b45d322cSThierry Reding cache-line-size = <64>; 2524b45d322cSThierry Reding cache-sets = <2048>; 2525b45d322cSThierry Reding next-level-cache = <&l3c>; 2526b45d322cSThierry Reding }; 2527b45d322cSThierry Reding 2528b45d322cSThierry Reding l3c: l3-cache { 2529b45d322cSThierry Reding cache-size = <4194304>; 2530b45d322cSThierry Reding cache-line-size = <64>; 2531b45d322cSThierry Reding cache-sets = <4096>; 25327780a034SMikko Perttunen }; 25337780a034SMikko Perttunen }; 25347780a034SMikko Perttunen 25359e79e58fSJon Hunter pmu { 25369e79e58fSJon Hunter compatible = "arm,armv8-pmuv3"; 25379e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 25389e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 25399e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 25409e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 25419e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 25429e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 25439e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 25449e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 25459e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 25469e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 25479e79e58fSJon Hunter }; 25489e79e58fSJon Hunter 25497780a034SMikko Perttunen psci { 25507780a034SMikko Perttunen compatible = "arm,psci-1.0"; 25517780a034SMikko Perttunen status = "okay"; 25527780a034SMikko Perttunen method = "smc"; 25537780a034SMikko Perttunen }; 25547780a034SMikko Perttunen 25555b4f6323SSameer Pujar sound { 25565b4f6323SSameer Pujar status = "disabled"; 25575b4f6323SSameer Pujar 25585b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 25595b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 25605b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 25615b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 25625b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 25635b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 25645b4f6323SSameer Pujar assigned-clock-parents = <0>, 25655b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 25665b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 25675b4f6323SSameer Pujar /* 25685b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 25695b4f6323SSameer Pujar * for this to work and oscillate between base rates required 25705b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 25715b4f6323SSameer Pujar */ 25725b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 257334e0fc34SThierry Reding 257434e0fc34SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 257534e0fc34SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 257634e0fc34SThierry Reding interconnect-names = "dma-mem", "write"; 257734e0fc34SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 25785b4f6323SSameer Pujar }; 25795b4f6323SSameer Pujar 2580a38570c2SMikko Perttunen tcu: tcu { 2581a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 2582a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2583a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2584a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 2585a38570c2SMikko Perttunen }; 2586a38570c2SMikko Perttunen 2587686ba009SThierry Reding thermal-zones { 2588686ba009SThierry Reding cpu { 2589686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2590686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2591686ba009SThierry Reding status = "disabled"; 2592686ba009SThierry Reding }; 2593686ba009SThierry Reding 2594686ba009SThierry Reding gpu { 2595686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2596686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 2597686ba009SThierry Reding status = "disabled"; 2598686ba009SThierry Reding }; 2599686ba009SThierry Reding 2600686ba009SThierry Reding aux { 2601686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2602686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 2603686ba009SThierry Reding status = "disabled"; 2604686ba009SThierry Reding }; 2605686ba009SThierry Reding 2606686ba009SThierry Reding pllx { 2607686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2608686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 2609686ba009SThierry Reding status = "disabled"; 2610686ba009SThierry Reding }; 2611686ba009SThierry Reding 2612686ba009SThierry Reding ao { 2613686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2614686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 2615686ba009SThierry Reding status = "disabled"; 2616686ba009SThierry Reding }; 2617686ba009SThierry Reding 2618686ba009SThierry Reding tj { 2619686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 2620686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 2621686ba009SThierry Reding status = "disabled"; 2622686ba009SThierry Reding }; 2623686ba009SThierry Reding }; 2624686ba009SThierry Reding 26255425fb15SMikko Perttunen timer { 26265425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 26275425fb15SMikko Perttunen interrupts = <GIC_PPI 13 26285425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 26295425fb15SMikko Perttunen <GIC_PPI 14 26305425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 26315425fb15SMikko Perttunen <GIC_PPI 11 26325425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 26335425fb15SMikko Perttunen <GIC_PPI 10 26345425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 26355425fb15SMikko Perttunen interrupt-parent = <&gic>; 2636b30be673SThierry Reding always-on; 26375425fb15SMikko Perttunen }; 26385425fb15SMikko Perttunen}; 2639