15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 73db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 8dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 9686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 115425fb15SMikko Perttunen 125425fb15SMikko Perttunen/ { 135425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 145425fb15SMikko Perttunen interrupt-parent = <&gic>; 155425fb15SMikko Perttunen #address-cells = <2>; 165425fb15SMikko Perttunen #size-cells = <2>; 175425fb15SMikko Perttunen 185425fb15SMikko Perttunen /* control backbone */ 19eef97c2aSThierry Reding cbb@0 { 205425fb15SMikko Perttunen compatible = "simple-bus"; 215425fb15SMikko Perttunen #address-cells = <1>; 225425fb15SMikko Perttunen #size-cells = <1>; 235425fb15SMikko Perttunen ranges = <0x0 0x0 0x0 0x40000000>; 245425fb15SMikko Perttunen 2509903c5eSJC Kuo misc@100000 { 2609903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 2709903c5eSJC Kuo reg = <0x00100000 0xf000>, 2809903c5eSJC Kuo <0x0010f000 0x1000>; 2909903c5eSJC Kuo }; 3009903c5eSJC Kuo 31f69ce393SMikko Perttunen gpio: gpio@2200000 { 32f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 33f69ce393SMikko Perttunen reg-names = "security", "gpio"; 34f69ce393SMikko Perttunen reg = <0x2200000 0x10000>, 35f69ce393SMikko Perttunen <0x2210000 0x10000>; 36f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 37f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 38f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 39f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 40f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 41f69ce393SMikko Perttunen <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 42f69ce393SMikko Perttunen #interrupt-cells = <2>; 43f69ce393SMikko Perttunen interrupt-controller; 44f69ce393SMikko Perttunen #gpio-cells = <2>; 45f69ce393SMikko Perttunen gpio-controller; 46f69ce393SMikko Perttunen }; 47f69ce393SMikko Perttunen 48f89b58ceSMikko Perttunen ethernet@2490000 { 4919dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 5019dc772aSThierry Reding "nvidia,tegra186-eqos", 51f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 52f89b58ceSMikko Perttunen reg = <0x02490000 0x10000>; 53f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 54f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 55f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 56f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 57f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 58f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 59f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 61f89b58ceSMikko Perttunen reset-names = "eqos"; 62f89b58ceSMikko Perttunen status = "disabled"; 63f89b58ceSMikko Perttunen 64f89b58ceSMikko Perttunen snps,write-requests = <1>; 65f89b58ceSMikko Perttunen snps,read-requests = <3>; 66f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 67f89b58ceSMikko Perttunen snps,txpbl = <16>; 68f89b58ceSMikko Perttunen snps,rxpbl = <8>; 69f89b58ceSMikko Perttunen }; 70f89b58ceSMikko Perttunen 711aaa7698SThierry Reding aconnect@2900000 { 725d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 735d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 745d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 755d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 765d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 775d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 785d2249ddSSameer Pujar #address-cells = <1>; 795d2249ddSSameer Pujar #size-cells = <1>; 805d2249ddSSameer Pujar ranges = <0x02900000 0x02900000 0x200000>; 815d2249ddSSameer Pujar status = "disabled"; 825d2249ddSSameer Pujar 835d2249ddSSameer Pujar dma-controller@2930000 { 845d2249ddSSameer Pujar compatible = "nvidia,tegra194-adma", 855d2249ddSSameer Pujar "nvidia,tegra186-adma"; 865d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 875d2249ddSSameer Pujar interrupt-parent = <&agic>; 885d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 895d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1205d2249ddSSameer Pujar #dma-cells = <1>; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 1225d2249ddSSameer Pujar clock-names = "d_audio"; 1235d2249ddSSameer Pujar status = "disabled"; 1245d2249ddSSameer Pujar }; 1255d2249ddSSameer Pujar 1265d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1275d2249ddSSameer Pujar compatible = "nvidia,tegra194-agic", 1285d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1295d2249ddSSameer Pujar #interrupt-cells = <3>; 1305d2249ddSSameer Pujar interrupt-controller; 1315d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1325d2249ddSSameer Pujar <0x02a42000 0x2000>; 1335d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1345d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | 1355d2249ddSSameer Pujar IRQ_TYPE_LEVEL_HIGH)>; 1365d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>; 1375d2249ddSSameer Pujar clock-names = "clk"; 1385d2249ddSSameer Pujar status = "disabled"; 1395d2249ddSSameer Pujar }; 1405d2249ddSSameer Pujar }; 1415d2249ddSSameer Pujar 142dbb72e2cSVidya Sagar pinmux: pinmux@2430000 { 143dbb72e2cSVidya Sagar compatible = "nvidia,tegra194-pinmux"; 144dbb72e2cSVidya Sagar reg = <0x2430000 0x17000 145dbb72e2cSVidya Sagar 0xc300000 0x4000>; 146dbb72e2cSVidya Sagar 147dbb72e2cSVidya Sagar status = "okay"; 148dbb72e2cSVidya Sagar 149dbb72e2cSVidya Sagar pex_rst_c5_out_state: pex_rst_c5_out { 150dbb72e2cSVidya Sagar pex_rst { 151dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_rst_n_pgg1"; 152dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 153dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 154dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_DISABLE>; 155dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 156dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 157dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 158dbb72e2cSVidya Sagar }; 159dbb72e2cSVidya Sagar }; 160dbb72e2cSVidya Sagar 161dbb72e2cSVidya Sagar clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 162dbb72e2cSVidya Sagar clkreq { 163dbb72e2cSVidya Sagar nvidia,pins = "pex_l5_clkreq_n_pgg0"; 164dbb72e2cSVidya Sagar nvidia,schmitt = <TEGRA_PIN_DISABLE>; 165dbb72e2cSVidya Sagar nvidia,lpdr = <TEGRA_PIN_ENABLE>; 166dbb72e2cSVidya Sagar nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167dbb72e2cSVidya Sagar nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 168dbb72e2cSVidya Sagar nvidia,tristate = <TEGRA_PIN_DISABLE>; 169dbb72e2cSVidya Sagar nvidia,pull = <TEGRA_PIN_PULL_NONE>; 170dbb72e2cSVidya Sagar }; 171dbb72e2cSVidya Sagar }; 172dbb72e2cSVidya Sagar }; 173dbb72e2cSVidya Sagar 174be9b887fSThierry Reding mc: memory-controller@2c00000 { 175be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 176be9b887fSThierry Reding reg = <0x02c00000 0x100000>, 177be9b887fSThierry Reding <0x02b80000 0x040000>, 178be9b887fSThierry Reding <0x01700000 0x100000>; 179be9b887fSThierry Reding status = "disabled"; 180be9b887fSThierry Reding 181be9b887fSThierry Reding #address-cells = <2>; 182be9b887fSThierry Reding #size-cells = <2>; 183be9b887fSThierry Reding 184be9b887fSThierry Reding ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 185be9b887fSThierry Reding <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 186be9b887fSThierry Reding <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 187be9b887fSThierry Reding 188be9b887fSThierry Reding /* 189be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 190be9b887fSThierry Reding * controller selects the XBAR format used when memory 191be9b887fSThierry Reding * is accessed. This is used to transparently access 192be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 193be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 194be9b887fSThierry Reding * 195be9b887fSThierry Reding * As a consequence, the operating system must ensure 196be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 197be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 198be9b887fSThierry Reding * devices require access to the XBAR switch, their 199be9b887fSThierry Reding * drivers must set this bit explicitly. 200be9b887fSThierry Reding * 201be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 202be9b887fSThierry Reding */ 203be9b887fSThierry Reding dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 204be9b887fSThierry Reding 205be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 206be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 207be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 208be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 209be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 210be9b887fSThierry Reding clock-names = "emc"; 211be9b887fSThierry Reding 212be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 213be9b887fSThierry Reding }; 214be9b887fSThierry Reding }; 215be9b887fSThierry Reding 2165425fb15SMikko Perttunen uarta: serial@3100000 { 2175425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2185425fb15SMikko Perttunen reg = <0x03100000 0x40>; 2195425fb15SMikko Perttunen reg-shift = <2>; 2205425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 2225425fb15SMikko Perttunen clock-names = "serial"; 2235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 2245425fb15SMikko Perttunen reset-names = "serial"; 2255425fb15SMikko Perttunen status = "disabled"; 2265425fb15SMikko Perttunen }; 2275425fb15SMikko Perttunen 2285425fb15SMikko Perttunen uartb: serial@3110000 { 2295425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2305425fb15SMikko Perttunen reg = <0x03110000 0x40>; 2315425fb15SMikko Perttunen reg-shift = <2>; 2325425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2335425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 2345425fb15SMikko Perttunen clock-names = "serial"; 2355425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 2365425fb15SMikko Perttunen reset-names = "serial"; 2375425fb15SMikko Perttunen status = "disabled"; 2385425fb15SMikko Perttunen }; 2395425fb15SMikko Perttunen 2405425fb15SMikko Perttunen uartd: serial@3130000 { 2415425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2425425fb15SMikko Perttunen reg = <0x03130000 0x40>; 2435425fb15SMikko Perttunen reg-shift = <2>; 2445425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 2455425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 2465425fb15SMikko Perttunen clock-names = "serial"; 2475425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 2485425fb15SMikko Perttunen reset-names = "serial"; 2495425fb15SMikko Perttunen status = "disabled"; 2505425fb15SMikko Perttunen }; 2515425fb15SMikko Perttunen 2525425fb15SMikko Perttunen uarte: serial@3140000 { 2535425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2545425fb15SMikko Perttunen reg = <0x03140000 0x40>; 2555425fb15SMikko Perttunen reg-shift = <2>; 2565425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2575425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 2585425fb15SMikko Perttunen clock-names = "serial"; 2595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 2605425fb15SMikko Perttunen reset-names = "serial"; 2615425fb15SMikko Perttunen status = "disabled"; 2625425fb15SMikko Perttunen }; 2635425fb15SMikko Perttunen 2645425fb15SMikko Perttunen uartf: serial@3150000 { 2655425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2665425fb15SMikko Perttunen reg = <0x03150000 0x40>; 2675425fb15SMikko Perttunen reg-shift = <2>; 2685425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 2695425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 2705425fb15SMikko Perttunen clock-names = "serial"; 2715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 2725425fb15SMikko Perttunen reset-names = "serial"; 2735425fb15SMikko Perttunen status = "disabled"; 2745425fb15SMikko Perttunen }; 2755425fb15SMikko Perttunen 2765425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 277d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 2785425fb15SMikko Perttunen reg = <0x03160000 0x10000>; 2795425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2805425fb15SMikko Perttunen #address-cells = <1>; 2815425fb15SMikko Perttunen #size-cells = <0>; 2825425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 2835425fb15SMikko Perttunen clock-names = "div-clk"; 2845425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 2855425fb15SMikko Perttunen reset-names = "i2c"; 2865425fb15SMikko Perttunen status = "disabled"; 2875425fb15SMikko Perttunen }; 2885425fb15SMikko Perttunen 2895425fb15SMikko Perttunen uarth: serial@3170000 { 2905425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 2915425fb15SMikko Perttunen reg = <0x03170000 0x40>; 2925425fb15SMikko Perttunen reg-shift = <2>; 2935425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 2945425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 2955425fb15SMikko Perttunen clock-names = "serial"; 2965425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 2975425fb15SMikko Perttunen reset-names = "serial"; 2985425fb15SMikko Perttunen status = "disabled"; 2995425fb15SMikko Perttunen }; 3005425fb15SMikko Perttunen 3015425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 302d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3035425fb15SMikko Perttunen reg = <0x03180000 0x10000>; 3045425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 3055425fb15SMikko Perttunen #address-cells = <1>; 3065425fb15SMikko Perttunen #size-cells = <0>; 3075425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 3085425fb15SMikko Perttunen clock-names = "div-clk"; 3095425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 3105425fb15SMikko Perttunen reset-names = "i2c"; 3115425fb15SMikko Perttunen status = "disabled"; 3125425fb15SMikko Perttunen }; 3135425fb15SMikko Perttunen 3145425fb15SMikko Perttunen /* shares pads with dpaux1 */ 3155425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 316d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3175425fb15SMikko Perttunen reg = <0x03190000 0x10000>; 3185425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 3195425fb15SMikko Perttunen #address-cells = <1>; 3205425fb15SMikko Perttunen #size-cells = <0>; 3215425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 3225425fb15SMikko Perttunen clock-names = "div-clk"; 3235425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 3245425fb15SMikko Perttunen reset-names = "i2c"; 3255425fb15SMikko Perttunen status = "disabled"; 3265425fb15SMikko Perttunen }; 3275425fb15SMikko Perttunen 3285425fb15SMikko Perttunen /* shares pads with dpaux0 */ 3295425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 330d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3315425fb15SMikko Perttunen reg = <0x031b0000 0x10000>; 3325425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3335425fb15SMikko Perttunen #address-cells = <1>; 3345425fb15SMikko Perttunen #size-cells = <0>; 3355425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 3365425fb15SMikko Perttunen clock-names = "div-clk"; 3375425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 3385425fb15SMikko Perttunen reset-names = "i2c"; 3395425fb15SMikko Perttunen status = "disabled"; 3405425fb15SMikko Perttunen }; 3415425fb15SMikko Perttunen 3425425fb15SMikko Perttunen gen7_i2c: i2c@31c0000 { 343d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3445425fb15SMikko Perttunen reg = <0x031c0000 0x10000>; 3455425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 3465425fb15SMikko Perttunen #address-cells = <1>; 3475425fb15SMikko Perttunen #size-cells = <0>; 3485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 3495425fb15SMikko Perttunen clock-names = "div-clk"; 3505425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 3515425fb15SMikko Perttunen reset-names = "i2c"; 3525425fb15SMikko Perttunen status = "disabled"; 3535425fb15SMikko Perttunen }; 3545425fb15SMikko Perttunen 3555425fb15SMikko Perttunen gen9_i2c: i2c@31e0000 { 356d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 3575425fb15SMikko Perttunen reg = <0x031e0000 0x10000>; 3585425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3595425fb15SMikko Perttunen #address-cells = <1>; 3605425fb15SMikko Perttunen #size-cells = <0>; 3615425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 3625425fb15SMikko Perttunen clock-names = "div-clk"; 3635425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 3645425fb15SMikko Perttunen reset-names = "i2c"; 3655425fb15SMikko Perttunen status = "disabled"; 3665425fb15SMikko Perttunen }; 3675425fb15SMikko Perttunen 3686a574ec7SThierry Reding pwm1: pwm@3280000 { 3696a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3706a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3716a574ec7SThierry Reding reg = <0x3280000 0x10000>; 3726a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 3736a574ec7SThierry Reding clock-names = "pwm"; 3746a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 3756a574ec7SThierry Reding reset-names = "pwm"; 3766a574ec7SThierry Reding status = "disabled"; 3776a574ec7SThierry Reding #pwm-cells = <2>; 3786a574ec7SThierry Reding }; 3796a574ec7SThierry Reding 3806a574ec7SThierry Reding pwm2: pwm@3290000 { 3816a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3826a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3836a574ec7SThierry Reding reg = <0x3290000 0x10000>; 3846a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 3856a574ec7SThierry Reding clock-names = "pwm"; 3866a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 3876a574ec7SThierry Reding reset-names = "pwm"; 3886a574ec7SThierry Reding status = "disabled"; 3896a574ec7SThierry Reding #pwm-cells = <2>; 3906a574ec7SThierry Reding }; 3916a574ec7SThierry Reding 3926a574ec7SThierry Reding pwm3: pwm@32a0000 { 3936a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 3946a574ec7SThierry Reding "nvidia,tegra186-pwm"; 3956a574ec7SThierry Reding reg = <0x32a0000 0x10000>; 3966a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 3976a574ec7SThierry Reding clock-names = "pwm"; 3986a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 3996a574ec7SThierry Reding reset-names = "pwm"; 4006a574ec7SThierry Reding status = "disabled"; 4016a574ec7SThierry Reding #pwm-cells = <2>; 4026a574ec7SThierry Reding }; 4036a574ec7SThierry Reding 4046a574ec7SThierry Reding pwm5: pwm@32c0000 { 4056a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4066a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4076a574ec7SThierry Reding reg = <0x32c0000 0x10000>; 4086a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 4096a574ec7SThierry Reding clock-names = "pwm"; 4106a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 4116a574ec7SThierry Reding reset-names = "pwm"; 4126a574ec7SThierry Reding status = "disabled"; 4136a574ec7SThierry Reding #pwm-cells = <2>; 4146a574ec7SThierry Reding }; 4156a574ec7SThierry Reding 4166a574ec7SThierry Reding pwm6: pwm@32d0000 { 4176a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4186a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4196a574ec7SThierry Reding reg = <0x32d0000 0x10000>; 4206a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 4216a574ec7SThierry Reding clock-names = "pwm"; 4226a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 4236a574ec7SThierry Reding reset-names = "pwm"; 4246a574ec7SThierry Reding status = "disabled"; 4256a574ec7SThierry Reding #pwm-cells = <2>; 4266a574ec7SThierry Reding }; 4276a574ec7SThierry Reding 4286a574ec7SThierry Reding pwm7: pwm@32e0000 { 4296a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4306a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4316a574ec7SThierry Reding reg = <0x32e0000 0x10000>; 4326a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 4336a574ec7SThierry Reding clock-names = "pwm"; 4346a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 4356a574ec7SThierry Reding reset-names = "pwm"; 4366a574ec7SThierry Reding status = "disabled"; 4376a574ec7SThierry Reding #pwm-cells = <2>; 4386a574ec7SThierry Reding }; 4396a574ec7SThierry Reding 4406a574ec7SThierry Reding pwm8: pwm@32f0000 { 4416a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 4426a574ec7SThierry Reding "nvidia,tegra186-pwm"; 4436a574ec7SThierry Reding reg = <0x32f0000 0x10000>; 4446a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 4456a574ec7SThierry Reding clock-names = "pwm"; 4466a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 4476a574ec7SThierry Reding reset-names = "pwm"; 4486a574ec7SThierry Reding status = "disabled"; 4496a574ec7SThierry Reding #pwm-cells = <2>; 4506a574ec7SThierry Reding }; 4516a574ec7SThierry Reding 4525425fb15SMikko Perttunen sdmmc1: sdhci@3400000 { 4535425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4545425fb15SMikko Perttunen reg = <0x03400000 0x10000>; 4555425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 4565425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 4575425fb15SMikko Perttunen clock-names = "sdhci"; 4585425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 4595425fb15SMikko Perttunen reset-names = "sdhci"; 4604e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 4614e0f1229SSowjanya Komatineni <0x07>; 4624e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4634e0f1229SSowjanya Komatineni <0x07>; 4644e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4654e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4664e0f1229SSowjanya Komatineni <0x07>; 4674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4694e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4704e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4715425fb15SMikko Perttunen status = "disabled"; 4725425fb15SMikko Perttunen }; 4735425fb15SMikko Perttunen 4745425fb15SMikko Perttunen sdmmc3: sdhci@3440000 { 4755425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4765425fb15SMikko Perttunen reg = <0x03440000 0x10000>; 4775425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 4785425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 4795425fb15SMikko Perttunen clock-names = "sdhci"; 4805425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 4815425fb15SMikko Perttunen reset-names = "sdhci"; 4824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 4834e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 4844e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 4854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 4864e0f1229SSowjanya Komatineni <0x07>; 4874e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 4884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 4894e0f1229SSowjanya Komatineni <0x07>; 4904e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 4914e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 4924e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 4934e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 4945425fb15SMikko Perttunen status = "disabled"; 4955425fb15SMikko Perttunen }; 4965425fb15SMikko Perttunen 4975425fb15SMikko Perttunen sdmmc4: sdhci@3460000 { 4985425fb15SMikko Perttunen compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 4995425fb15SMikko Perttunen reg = <0x03460000 0x10000>; 5005425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 5015425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 5025425fb15SMikko Perttunen clock-names = "sdhci"; 503351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 504351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 505351648d0SSowjanya Komatineni assigned-clock-parents = 506351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 5075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 5085425fb15SMikko Perttunen reset-names = "sdhci"; 5094e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 5104e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 5114e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 5124e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 5134e0f1229SSowjanya Komatineni <0x0a>; 5144e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 5154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 5164e0f1229SSowjanya Komatineni <0x0a>; 5174e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 5184e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 5194e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 520dfd3cb6fSSowjanya Komatineni supports-cqe; 5215425fb15SMikko Perttunen status = "disabled"; 5225425fb15SMikko Perttunen }; 5235425fb15SMikko Perttunen 5244878cc0cSSameer Pujar hda@3510000 { 5254878cc0cSSameer Pujar compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 5264878cc0cSSameer Pujar reg = <0x3510000 0x10000>; 5274878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 5284878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 5294878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 5304878cc0cSSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 5314878cc0cSSameer Pujar clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 5324878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 5334878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 5344878cc0cSSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 5354878cc0cSSameer Pujar reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 5364878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 5374878cc0cSSameer Pujar status = "disabled"; 5384878cc0cSSameer Pujar }; 5394878cc0cSSameer Pujar 54009903c5eSJC Kuo fuse@3820000 { 54109903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 54209903c5eSJC Kuo reg = <0x03820000 0x10000>; 54309903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 54409903c5eSJC Kuo clock-names = "fuse"; 54509903c5eSJC Kuo }; 54609903c5eSJC Kuo 5475425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 5485425fb15SMikko Perttunen compatible = "arm,gic-400"; 5495425fb15SMikko Perttunen #interrupt-cells = <3>; 5505425fb15SMikko Perttunen interrupt-controller; 5515425fb15SMikko Perttunen reg = <0x03881000 0x1000>, 5525425fb15SMikko Perttunen <0x03882000 0x2000>, 5535425fb15SMikko Perttunen <0x03884000 0x2000>, 5545425fb15SMikko Perttunen <0x03886000 0x2000>; 5555425fb15SMikko Perttunen interrupts = <GIC_PPI 9 5565425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 5575425fb15SMikko Perttunen interrupt-parent = <&gic>; 5585425fb15SMikko Perttunen }; 5595425fb15SMikko Perttunen 560badb80beSThierry Reding cec@3960000 { 561badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 562badb80beSThierry Reding reg = <0x03960000 0x10000>; 563badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 564badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 565badb80beSThierry Reding clock-names = "cec"; 566badb80beSThierry Reding status = "disabled"; 567badb80beSThierry Reding }; 568badb80beSThierry Reding 5695425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 570a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 5715425fb15SMikko Perttunen reg = <0x03c00000 0xa0000>; 572a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 573a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 574a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 575a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 576a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 577a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 578a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 579a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 580a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 581a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 582a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 583a38570c2SMikko Perttunen "shared7"; 584a38570c2SMikko Perttunen #mbox-cells = <2>; 585a38570c2SMikko Perttunen }; 586a38570c2SMikko Perttunen 5872602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 5882602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5892602c32fSVidya Sagar reg = <0x03e10000 0x10000>; 5902602c32fSVidya Sagar reg-names = "ctl"; 5912602c32fSVidya Sagar 5922602c32fSVidya Sagar #phy-cells = <0>; 5932602c32fSVidya Sagar }; 5942602c32fSVidya Sagar 5952602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 5962602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 5972602c32fSVidya Sagar reg = <0x03e20000 0x10000>; 5982602c32fSVidya Sagar reg-names = "ctl"; 5992602c32fSVidya Sagar 6002602c32fSVidya Sagar #phy-cells = <0>; 6012602c32fSVidya Sagar }; 6022602c32fSVidya Sagar 6032602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 6042602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6052602c32fSVidya Sagar reg = <0x03e30000 0x10000>; 6062602c32fSVidya Sagar reg-names = "ctl"; 6072602c32fSVidya Sagar 6082602c32fSVidya Sagar #phy-cells = <0>; 6092602c32fSVidya Sagar }; 6102602c32fSVidya Sagar 6112602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 6122602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6132602c32fSVidya Sagar reg = <0x03e40000 0x10000>; 6142602c32fSVidya Sagar reg-names = "ctl"; 6152602c32fSVidya Sagar 6162602c32fSVidya Sagar #phy-cells = <0>; 6172602c32fSVidya Sagar }; 6182602c32fSVidya Sagar 6192602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 6202602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6212602c32fSVidya Sagar reg = <0x03e50000 0x10000>; 6222602c32fSVidya Sagar reg-names = "ctl"; 6232602c32fSVidya Sagar 6242602c32fSVidya Sagar #phy-cells = <0>; 6252602c32fSVidya Sagar }; 6262602c32fSVidya Sagar 6272602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 6282602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6292602c32fSVidya Sagar reg = <0x03e60000 0x10000>; 6302602c32fSVidya Sagar reg-names = "ctl"; 6312602c32fSVidya Sagar 6322602c32fSVidya Sagar #phy-cells = <0>; 6332602c32fSVidya Sagar }; 6342602c32fSVidya Sagar 6352602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 6362602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6372602c32fSVidya Sagar reg = <0x03e70000 0x10000>; 6382602c32fSVidya Sagar reg-names = "ctl"; 6392602c32fSVidya Sagar 6402602c32fSVidya Sagar #phy-cells = <0>; 6412602c32fSVidya Sagar }; 6422602c32fSVidya Sagar 6432602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 6442602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6452602c32fSVidya Sagar reg = <0x03e80000 0x10000>; 6462602c32fSVidya Sagar reg-names = "ctl"; 6472602c32fSVidya Sagar 6482602c32fSVidya Sagar #phy-cells = <0>; 6492602c32fSVidya Sagar }; 6502602c32fSVidya Sagar 6512602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 6522602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6532602c32fSVidya Sagar reg = <0x03e90000 0x10000>; 6542602c32fSVidya Sagar reg-names = "ctl"; 6552602c32fSVidya Sagar 6562602c32fSVidya Sagar #phy-cells = <0>; 6572602c32fSVidya Sagar }; 6582602c32fSVidya Sagar 6592602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 6602602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6612602c32fSVidya Sagar reg = <0x03ea0000 0x10000>; 6622602c32fSVidya Sagar reg-names = "ctl"; 6632602c32fSVidya Sagar 6642602c32fSVidya Sagar #phy-cells = <0>; 6652602c32fSVidya Sagar }; 6662602c32fSVidya Sagar 6672602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 6682602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6692602c32fSVidya Sagar reg = <0x03eb0000 0x10000>; 6702602c32fSVidya Sagar reg-names = "ctl"; 6712602c32fSVidya Sagar 6722602c32fSVidya Sagar #phy-cells = <0>; 6732602c32fSVidya Sagar }; 6742602c32fSVidya Sagar 6752602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 6762602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6772602c32fSVidya Sagar reg = <0x03ec0000 0x10000>; 6782602c32fSVidya Sagar reg-names = "ctl"; 6792602c32fSVidya Sagar 6802602c32fSVidya Sagar #phy-cells = <0>; 6812602c32fSVidya Sagar }; 6822602c32fSVidya Sagar 6832602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 6842602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6852602c32fSVidya Sagar reg = <0x03ed0000 0x10000>; 6862602c32fSVidya Sagar reg-names = "ctl"; 6872602c32fSVidya Sagar 6882602c32fSVidya Sagar #phy-cells = <0>; 6892602c32fSVidya Sagar }; 6902602c32fSVidya Sagar 6912602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 6922602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 6932602c32fSVidya Sagar reg = <0x03ee0000 0x10000>; 6942602c32fSVidya Sagar reg-names = "ctl"; 6952602c32fSVidya Sagar 6962602c32fSVidya Sagar #phy-cells = <0>; 6972602c32fSVidya Sagar }; 6982602c32fSVidya Sagar 6992602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 7002602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7012602c32fSVidya Sagar reg = <0x03ef0000 0x10000>; 7022602c32fSVidya Sagar reg-names = "ctl"; 7032602c32fSVidya Sagar 7042602c32fSVidya Sagar #phy-cells = <0>; 7052602c32fSVidya Sagar }; 7062602c32fSVidya Sagar 7072602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 7082602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7092602c32fSVidya Sagar reg = <0x03f00000 0x10000>; 7102602c32fSVidya Sagar reg-names = "ctl"; 7112602c32fSVidya Sagar 7122602c32fSVidya Sagar #phy-cells = <0>; 7132602c32fSVidya Sagar }; 7142602c32fSVidya Sagar 7152602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 7162602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7172602c32fSVidya Sagar reg = <0x03f10000 0x10000>; 7182602c32fSVidya Sagar reg-names = "ctl"; 7192602c32fSVidya Sagar 7202602c32fSVidya Sagar #phy-cells = <0>; 7212602c32fSVidya Sagar }; 7222602c32fSVidya Sagar 7232602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 7242602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7252602c32fSVidya Sagar reg = <0x03f20000 0x10000>; 7262602c32fSVidya Sagar reg-names = "ctl"; 7272602c32fSVidya Sagar 7282602c32fSVidya Sagar #phy-cells = <0>; 7292602c32fSVidya Sagar }; 7302602c32fSVidya Sagar 7312602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 7322602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7332602c32fSVidya Sagar reg = <0x03f30000 0x10000>; 7342602c32fSVidya Sagar reg-names = "ctl"; 7352602c32fSVidya Sagar 7362602c32fSVidya Sagar #phy-cells = <0>; 7372602c32fSVidya Sagar }; 7382602c32fSVidya Sagar 7392602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 7402602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 7412602c32fSVidya Sagar reg = <0x03f40000 0x10000>; 7422602c32fSVidya Sagar reg-names = "ctl"; 7432602c32fSVidya Sagar 7442602c32fSVidya Sagar #phy-cells = <0>; 7452602c32fSVidya Sagar }; 7462602c32fSVidya Sagar 747a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 748a38570c2SMikko Perttunen compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 749a38570c2SMikko Perttunen reg = <0x0c150000 0xa0000>; 750a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 751a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 752a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 753a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 754a38570c2SMikko Perttunen /* 755a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 756a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 757a38570c2SMikko Perttunen */ 758a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 7595425fb15SMikko Perttunen #mbox-cells = <2>; 7605425fb15SMikko Perttunen }; 7615425fb15SMikko Perttunen 7625425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 763d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7645425fb15SMikko Perttunen reg = <0x0c240000 0x10000>; 7655425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 7665425fb15SMikko Perttunen #address-cells = <1>; 7675425fb15SMikko Perttunen #size-cells = <0>; 7685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 7695425fb15SMikko Perttunen clock-names = "div-clk"; 7705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 7715425fb15SMikko Perttunen reset-names = "i2c"; 7725425fb15SMikko Perttunen status = "disabled"; 7735425fb15SMikko Perttunen }; 7745425fb15SMikko Perttunen 7755425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 776d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 7775425fb15SMikko Perttunen reg = <0x0c250000 0x10000>; 7785425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 7795425fb15SMikko Perttunen #address-cells = <1>; 7805425fb15SMikko Perttunen #size-cells = <0>; 7815425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 7825425fb15SMikko Perttunen clock-names = "div-clk"; 7835425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 7845425fb15SMikko Perttunen reset-names = "i2c"; 7855425fb15SMikko Perttunen status = "disabled"; 7865425fb15SMikko Perttunen }; 7875425fb15SMikko Perttunen 7885425fb15SMikko Perttunen uartc: serial@c280000 { 7895425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7905425fb15SMikko Perttunen reg = <0x0c280000 0x40>; 7915425fb15SMikko Perttunen reg-shift = <2>; 7925425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 7935425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 7945425fb15SMikko Perttunen clock-names = "serial"; 7955425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 7965425fb15SMikko Perttunen reset-names = "serial"; 7975425fb15SMikko Perttunen status = "disabled"; 7985425fb15SMikko Perttunen }; 7995425fb15SMikko Perttunen 8005425fb15SMikko Perttunen uartg: serial@c290000 { 8015425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8025425fb15SMikko Perttunen reg = <0x0c290000 0x40>; 8035425fb15SMikko Perttunen reg-shift = <2>; 8045425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 8055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 8065425fb15SMikko Perttunen clock-names = "serial"; 8075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 8085425fb15SMikko Perttunen reset-names = "serial"; 8095425fb15SMikko Perttunen status = "disabled"; 8105425fb15SMikko Perttunen }; 8115425fb15SMikko Perttunen 81237e5a31dSThierry Reding rtc: rtc@c2a0000 { 81337e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 81437e5a31dSThierry Reding reg = <0x0c2a0000 0x10000>; 81537e5a31dSThierry Reding interrupt-parent = <&pmc>; 81637e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 81737e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 81837e5a31dSThierry Reding clock-names = "rtc"; 81937e5a31dSThierry Reding status = "disabled"; 82037e5a31dSThierry Reding }; 82137e5a31dSThierry Reding 8224d286331SThierry Reding gpio_aon: gpio@c2f0000 { 8234d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 8244d286331SThierry Reding reg-names = "security", "gpio"; 8254d286331SThierry Reding reg = <0xc2f0000 0x1000>, 8264d286331SThierry Reding <0xc2f1000 0x1000>; 8274d286331SThierry Reding interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 8284d286331SThierry Reding <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 8294d286331SThierry Reding <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 8304d286331SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 8314d286331SThierry Reding gpio-controller; 8324d286331SThierry Reding #gpio-cells = <2>; 8334d286331SThierry Reding interrupt-controller; 8344d286331SThierry Reding #interrupt-cells = <2>; 8354d286331SThierry Reding }; 8364d286331SThierry Reding 8376a574ec7SThierry Reding pwm4: pwm@c340000 { 8386a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 8396a574ec7SThierry Reding "nvidia,tegra186-pwm"; 8406a574ec7SThierry Reding reg = <0xc340000 0x10000>; 8416a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 8426a574ec7SThierry Reding clock-names = "pwm"; 8436a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 8446a574ec7SThierry Reding reset-names = "pwm"; 8456a574ec7SThierry Reding status = "disabled"; 8466a574ec7SThierry Reding #pwm-cells = <2>; 8476a574ec7SThierry Reding }; 8486a574ec7SThierry Reding 84938ecf1e5SThierry Reding pmc: pmc@c360000 { 8505425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 8515425fb15SMikko Perttunen reg = <0x0c360000 0x10000>, 8525425fb15SMikko Perttunen <0x0c370000 0x10000>, 8535425fb15SMikko Perttunen <0x0c380000 0x10000>, 8545425fb15SMikko Perttunen <0x0c390000 0x10000>, 8555425fb15SMikko Perttunen <0x0c3a0000 0x10000>; 8565425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 85738ecf1e5SThierry Reding 85838ecf1e5SThierry Reding #interrupt-cells = <2>; 85938ecf1e5SThierry Reding interrupt-controller; 8605425fb15SMikko Perttunen }; 8613db6d3baSThierry Reding 8623db6d3baSThierry Reding host1x@13e00000 { 8633db6d3baSThierry Reding compatible = "nvidia,tegra194-host1x", "simple-bus"; 8643db6d3baSThierry Reding reg = <0x13e00000 0x10000>, 8653db6d3baSThierry Reding <0x13e10000 0x10000>; 8663db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 8673db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 8683db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 8693db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 8703db6d3baSThierry Reding clock-names = "host1x"; 8713db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 8723db6d3baSThierry Reding reset-names = "host1x"; 8733db6d3baSThierry Reding 8743db6d3baSThierry Reding #address-cells = <1>; 8753db6d3baSThierry Reding #size-cells = <1>; 8763db6d3baSThierry Reding 8773db6d3baSThierry Reding ranges = <0x15000000 0x15000000 0x01000000>; 8783db6d3baSThierry Reding 8793db6d3baSThierry Reding display-hub@15200000 { 8803db6d3baSThierry Reding compatible = "nvidia,tegra194-display", "simple-bus"; 881611a1c69SThierry Reding reg = <0x15200000 0x00040000>; 8823db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 8833db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 8843db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 8853db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 8863db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 8873db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 8883db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 8893db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 8903db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 8913db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 8923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 8933db6d3baSThierry Reding clock-names = "disp", "hub"; 8943db6d3baSThierry Reding status = "disabled"; 8953db6d3baSThierry Reding 8963db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 8973db6d3baSThierry Reding 8983db6d3baSThierry Reding #address-cells = <1>; 8993db6d3baSThierry Reding #size-cells = <1>; 9003db6d3baSThierry Reding 9013db6d3baSThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 9023db6d3baSThierry Reding 9033db6d3baSThierry Reding display@15200000 { 9043db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 9053db6d3baSThierry Reding reg = <0x15200000 0x10000>; 9063db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 9073db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 9083db6d3baSThierry Reding clock-names = "dc"; 9093db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 9103db6d3baSThierry Reding reset-names = "dc"; 9113db6d3baSThierry Reding 9123db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9133db6d3baSThierry Reding 9143db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 9153db6d3baSThierry Reding nvidia,head = <0>; 9163db6d3baSThierry Reding }; 9173db6d3baSThierry Reding 9183db6d3baSThierry Reding display@15210000 { 9193db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 9203db6d3baSThierry Reding reg = <0x15210000 0x10000>; 9213db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 9223db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 9233db6d3baSThierry Reding clock-names = "dc"; 9243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 9253db6d3baSThierry Reding reset-names = "dc"; 9263db6d3baSThierry Reding 9273db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 9283db6d3baSThierry Reding 9293db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 9303db6d3baSThierry Reding nvidia,head = <1>; 9313db6d3baSThierry Reding }; 9323db6d3baSThierry Reding 9333db6d3baSThierry Reding display@15220000 { 9343db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 9353db6d3baSThierry Reding reg = <0x15220000 0x10000>; 9363db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 9373db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 9383db6d3baSThierry Reding clock-names = "dc"; 9393db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 9403db6d3baSThierry Reding reset-names = "dc"; 9413db6d3baSThierry Reding 9423db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 9433db6d3baSThierry Reding 9443db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 9453db6d3baSThierry Reding nvidia,head = <2>; 9463db6d3baSThierry Reding }; 9473db6d3baSThierry Reding 9483db6d3baSThierry Reding display@15230000 { 9493db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 9503db6d3baSThierry Reding reg = <0x15230000 0x10000>; 9513db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 9523db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 9533db6d3baSThierry Reding clock-names = "dc"; 9543db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 9553db6d3baSThierry Reding reset-names = "dc"; 9563db6d3baSThierry Reding 9573db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 9583db6d3baSThierry Reding 9593db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 9603db6d3baSThierry Reding nvidia,head = <3>; 9613db6d3baSThierry Reding }; 9623db6d3baSThierry Reding }; 9633db6d3baSThierry Reding 9648d424ec2SThierry Reding vic@15340000 { 9658d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 9668d424ec2SThierry Reding reg = <0x15340000 0x00040000>; 9678d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 9688d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 9698d424ec2SThierry Reding clock-names = "vic"; 9708d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 9718d424ec2SThierry Reding reset-names = "vic"; 9728d424ec2SThierry Reding 9738d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 9748d424ec2SThierry Reding }; 9758d424ec2SThierry Reding 9763db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 9773db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 9783db6d3baSThierry Reding reg = <0x155c0000 0x10000>; 9793db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 9803db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 9813db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 9823db6d3baSThierry Reding clock-names = "dpaux", "parent"; 9833db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 9843db6d3baSThierry Reding reset-names = "dpaux"; 9853db6d3baSThierry Reding status = "disabled"; 9863db6d3baSThierry Reding 9873db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 9883db6d3baSThierry Reding 9893db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 9903db6d3baSThierry Reding groups = "dpaux-io"; 9913db6d3baSThierry Reding function = "aux"; 9923db6d3baSThierry Reding }; 9933db6d3baSThierry Reding 9943db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 9953db6d3baSThierry Reding groups = "dpaux-io"; 9963db6d3baSThierry Reding function = "i2c"; 9973db6d3baSThierry Reding }; 9983db6d3baSThierry Reding 9993db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 10003db6d3baSThierry Reding groups = "dpaux-io"; 10013db6d3baSThierry Reding function = "off"; 10023db6d3baSThierry Reding }; 10033db6d3baSThierry Reding 10043db6d3baSThierry Reding i2c-bus { 10053db6d3baSThierry Reding #address-cells = <1>; 10063db6d3baSThierry Reding #size-cells = <0>; 10073db6d3baSThierry Reding }; 10083db6d3baSThierry Reding }; 10093db6d3baSThierry Reding 10103db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 10113db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 10123db6d3baSThierry Reding reg = <0x155d0000 0x10000>; 10133db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 10143db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 10153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 10163db6d3baSThierry Reding clock-names = "dpaux", "parent"; 10173db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 10183db6d3baSThierry Reding reset-names = "dpaux"; 10193db6d3baSThierry Reding status = "disabled"; 10203db6d3baSThierry Reding 10213db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10223db6d3baSThierry Reding 10233db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 10243db6d3baSThierry Reding groups = "dpaux-io"; 10253db6d3baSThierry Reding function = "aux"; 10263db6d3baSThierry Reding }; 10273db6d3baSThierry Reding 10283db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 10293db6d3baSThierry Reding groups = "dpaux-io"; 10303db6d3baSThierry Reding function = "i2c"; 10313db6d3baSThierry Reding }; 10323db6d3baSThierry Reding 10333db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 10343db6d3baSThierry Reding groups = "dpaux-io"; 10353db6d3baSThierry Reding function = "off"; 10363db6d3baSThierry Reding }; 10373db6d3baSThierry Reding 10383db6d3baSThierry Reding i2c-bus { 10393db6d3baSThierry Reding #address-cells = <1>; 10403db6d3baSThierry Reding #size-cells = <0>; 10413db6d3baSThierry Reding }; 10423db6d3baSThierry Reding }; 10433db6d3baSThierry Reding 10443db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 10453db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 10463db6d3baSThierry Reding reg = <0x155e0000 0x10000>; 10473db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 10483db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 10493db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 10503db6d3baSThierry Reding clock-names = "dpaux", "parent"; 10513db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 10523db6d3baSThierry Reding reset-names = "dpaux"; 10533db6d3baSThierry Reding status = "disabled"; 10543db6d3baSThierry Reding 10553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10563db6d3baSThierry Reding 10573db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 10583db6d3baSThierry Reding groups = "dpaux-io"; 10593db6d3baSThierry Reding function = "aux"; 10603db6d3baSThierry Reding }; 10613db6d3baSThierry Reding 10623db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 10633db6d3baSThierry Reding groups = "dpaux-io"; 10643db6d3baSThierry Reding function = "i2c"; 10653db6d3baSThierry Reding }; 10663db6d3baSThierry Reding 10673db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 10683db6d3baSThierry Reding groups = "dpaux-io"; 10693db6d3baSThierry Reding function = "off"; 10703db6d3baSThierry Reding }; 10713db6d3baSThierry Reding 10723db6d3baSThierry Reding i2c-bus { 10733db6d3baSThierry Reding #address-cells = <1>; 10743db6d3baSThierry Reding #size-cells = <0>; 10753db6d3baSThierry Reding }; 10763db6d3baSThierry Reding }; 10773db6d3baSThierry Reding 10783db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 10793db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 10803db6d3baSThierry Reding reg = <0x155f0000 0x10000>; 10813db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 10823db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 10833db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 10843db6d3baSThierry Reding clock-names = "dpaux", "parent"; 10853db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 10863db6d3baSThierry Reding reset-names = "dpaux"; 10873db6d3baSThierry Reding status = "disabled"; 10883db6d3baSThierry Reding 10893db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 10903db6d3baSThierry Reding 10913db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 10923db6d3baSThierry Reding groups = "dpaux-io"; 10933db6d3baSThierry Reding function = "aux"; 10943db6d3baSThierry Reding }; 10953db6d3baSThierry Reding 10963db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 10973db6d3baSThierry Reding groups = "dpaux-io"; 10983db6d3baSThierry Reding function = "i2c"; 10993db6d3baSThierry Reding }; 11003db6d3baSThierry Reding 11013db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 11023db6d3baSThierry Reding groups = "dpaux-io"; 11033db6d3baSThierry Reding function = "off"; 11043db6d3baSThierry Reding }; 11053db6d3baSThierry Reding 11063db6d3baSThierry Reding i2c-bus { 11073db6d3baSThierry Reding #address-cells = <1>; 11083db6d3baSThierry Reding #size-cells = <0>; 11093db6d3baSThierry Reding }; 11103db6d3baSThierry Reding }; 11113db6d3baSThierry Reding 11123db6d3baSThierry Reding sor0: sor@15b00000 { 11133db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 11143db6d3baSThierry Reding reg = <0x15b00000 0x40000>; 11153db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 11163db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 11173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 11183db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 11193db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11203db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11213db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 11223db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11233db6d3baSThierry Reding "pad"; 11243db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 11253db6d3baSThierry Reding reset-names = "sor"; 11263db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 11273db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 11283db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 11293db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11303db6d3baSThierry Reding status = "disabled"; 11313db6d3baSThierry Reding 11323db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11333db6d3baSThierry Reding nvidia,interface = <0>; 11343db6d3baSThierry Reding }; 11353db6d3baSThierry Reding 11363db6d3baSThierry Reding sor1: sor@15b40000 { 11373db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 1138939e7430SThierry Reding reg = <0x15b40000 0x40000>; 11393db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 11403db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 11413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 11423db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 11433db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11443db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11453db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 11463db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11473db6d3baSThierry Reding "pad"; 11483db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 11493db6d3baSThierry Reding reset-names = "sor"; 11503db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 11513db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 11523db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 11533db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11543db6d3baSThierry Reding status = "disabled"; 11553db6d3baSThierry Reding 11563db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11573db6d3baSThierry Reding nvidia,interface = <1>; 11583db6d3baSThierry Reding }; 11593db6d3baSThierry Reding 11603db6d3baSThierry Reding sor2: sor@15b80000 { 11613db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 11623db6d3baSThierry Reding reg = <0x15b80000 0x40000>; 11633db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 11643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 11653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 11663db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 11673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 11703db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11713db6d3baSThierry Reding "pad"; 11723db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 11733db6d3baSThierry Reding reset-names = "sor"; 11743db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 11753db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 11763db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 11773db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 11783db6d3baSThierry Reding status = "disabled"; 11793db6d3baSThierry Reding 11803db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 11813db6d3baSThierry Reding nvidia,interface = <2>; 11823db6d3baSThierry Reding }; 11833db6d3baSThierry Reding 11843db6d3baSThierry Reding sor3: sor@15bc0000 { 11853db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 11863db6d3baSThierry Reding reg = <0x15bc0000 0x40000>; 11873db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 11883db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 11893db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 11903db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 11913db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 11923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 11933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 11943db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 11953db6d3baSThierry Reding "pad"; 11963db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 11973db6d3baSThierry Reding reset-names = "sor"; 11983db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 11993db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 12003db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 12013db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 12023db6d3baSThierry Reding status = "disabled"; 12033db6d3baSThierry Reding 12043db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 12053db6d3baSThierry Reding nvidia,interface = <3>; 12063db6d3baSThierry Reding }; 12073db6d3baSThierry Reding }; 12085425fb15SMikko Perttunen }; 12095425fb15SMikko Perttunen 12102602c32fSVidya Sagar pcie@14100000 { 12112602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12122602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 12132602c32fSVidya Sagar reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 12142602c32fSVidya Sagar 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 12152602c32fSVidya Sagar 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12162602c32fSVidya Sagar 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12172602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12182602c32fSVidya Sagar 12192602c32fSVidya Sagar status = "disabled"; 12202602c32fSVidya Sagar 12212602c32fSVidya Sagar #address-cells = <3>; 12222602c32fSVidya Sagar #size-cells = <2>; 12232602c32fSVidya Sagar device_type = "pci"; 12242602c32fSVidya Sagar num-lanes = <1>; 12252602c32fSVidya Sagar num-viewport = <8>; 12262602c32fSVidya Sagar linux,pci-domain = <1>; 12272602c32fSVidya Sagar 12282602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 12292602c32fSVidya Sagar clock-names = "core"; 12302602c32fSVidya Sagar 12312602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 12322602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 12332602c32fSVidya Sagar reset-names = "apb", "core"; 12342602c32fSVidya Sagar 12352602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12362602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12372602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12382602c32fSVidya Sagar 12392602c32fSVidya Sagar #interrupt-cells = <1>; 12402602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12412602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 12422602c32fSVidya Sagar 12432602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 12442602c32fSVidya Sagar 12452602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12462602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12472602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12482602c32fSVidya Sagar 12492602c32fSVidya Sagar bus-range = <0x0 0xff>; 12502602c32fSVidya Sagar ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12512602c32fSVidya Sagar 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12522602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12532602c32fSVidya Sagar }; 12542602c32fSVidya Sagar 12552602c32fSVidya Sagar pcie@14120000 { 12562602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 12572602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 12582602c32fSVidya Sagar reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 12592602c32fSVidya Sagar 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 12602602c32fSVidya Sagar 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 12612602c32fSVidya Sagar 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 12622602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 12632602c32fSVidya Sagar 12642602c32fSVidya Sagar status = "disabled"; 12652602c32fSVidya Sagar 12662602c32fSVidya Sagar #address-cells = <3>; 12672602c32fSVidya Sagar #size-cells = <2>; 12682602c32fSVidya Sagar device_type = "pci"; 12692602c32fSVidya Sagar num-lanes = <1>; 12702602c32fSVidya Sagar num-viewport = <8>; 12712602c32fSVidya Sagar linux,pci-domain = <2>; 12722602c32fSVidya Sagar 12732602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 12742602c32fSVidya Sagar clock-names = "core"; 12752602c32fSVidya Sagar 12762602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 12772602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 12782602c32fSVidya Sagar reset-names = "apb", "core"; 12792602c32fSVidya Sagar 12802602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 12812602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 12822602c32fSVidya Sagar interrupt-names = "intr", "msi"; 12832602c32fSVidya Sagar 12842602c32fSVidya Sagar #interrupt-cells = <1>; 12852602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 12862602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 12872602c32fSVidya Sagar 12882602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 12892602c32fSVidya Sagar 12902602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 12912602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 12922602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 12932602c32fSVidya Sagar 12942602c32fSVidya Sagar bus-range = <0x0 0xff>; 12952602c32fSVidya Sagar ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 12962602c32fSVidya Sagar 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 12972602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 12982602c32fSVidya Sagar }; 12992602c32fSVidya Sagar 13002602c32fSVidya Sagar pcie@14140000 { 13012602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13022602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 13032602c32fSVidya Sagar reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 13042602c32fSVidya Sagar 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 13052602c32fSVidya Sagar 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13062602c32fSVidya Sagar 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13072602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13082602c32fSVidya Sagar 13092602c32fSVidya Sagar status = "disabled"; 13102602c32fSVidya Sagar 13112602c32fSVidya Sagar #address-cells = <3>; 13122602c32fSVidya Sagar #size-cells = <2>; 13132602c32fSVidya Sagar device_type = "pci"; 13142602c32fSVidya Sagar num-lanes = <1>; 13152602c32fSVidya Sagar num-viewport = <8>; 13162602c32fSVidya Sagar linux,pci-domain = <3>; 13172602c32fSVidya Sagar 13182602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 13192602c32fSVidya Sagar clock-names = "core"; 13202602c32fSVidya Sagar 13212602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 13222602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 13232602c32fSVidya Sagar reset-names = "apb", "core"; 13242602c32fSVidya Sagar 13252602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13262602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13272602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13282602c32fSVidya Sagar 13292602c32fSVidya Sagar #interrupt-cells = <1>; 13302602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13312602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 13322602c32fSVidya Sagar 13332602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 13342602c32fSVidya Sagar 13352602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13362602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13372602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13382602c32fSVidya Sagar 13392602c32fSVidya Sagar bus-range = <0x0 0xff>; 13402602c32fSVidya Sagar ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13412602c32fSVidya Sagar 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 13422602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 13432602c32fSVidya Sagar }; 13442602c32fSVidya Sagar 13452602c32fSVidya Sagar pcie@14160000 { 13462602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13472602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 13482602c32fSVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 13492602c32fSVidya Sagar 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 13502602c32fSVidya Sagar 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13512602c32fSVidya Sagar 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13522602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13532602c32fSVidya Sagar 13542602c32fSVidya Sagar status = "disabled"; 13552602c32fSVidya Sagar 13562602c32fSVidya Sagar #address-cells = <3>; 13572602c32fSVidya Sagar #size-cells = <2>; 13582602c32fSVidya Sagar device_type = "pci"; 13592602c32fSVidya Sagar num-lanes = <4>; 13602602c32fSVidya Sagar num-viewport = <8>; 13612602c32fSVidya Sagar linux,pci-domain = <4>; 13622602c32fSVidya Sagar 13632602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 13642602c32fSVidya Sagar clock-names = "core"; 13652602c32fSVidya Sagar 13662602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 13672602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 13682602c32fSVidya Sagar reset-names = "apb", "core"; 13692602c32fSVidya Sagar 13702602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 13712602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 13722602c32fSVidya Sagar interrupt-names = "intr", "msi"; 13732602c32fSVidya Sagar 13742602c32fSVidya Sagar #interrupt-cells = <1>; 13752602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 13762602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 13772602c32fSVidya Sagar 13782602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 13792602c32fSVidya Sagar 13802602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 13812602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 13822602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 13832602c32fSVidya Sagar 13842602c32fSVidya Sagar bus-range = <0x0 0xff>; 13852602c32fSVidya Sagar ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 13862602c32fSVidya Sagar 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 13872602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 13882602c32fSVidya Sagar }; 13892602c32fSVidya Sagar 13902602c32fSVidya Sagar pcie@14180000 { 13912602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 13922602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 13932602c32fSVidya Sagar reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 13942602c32fSVidya Sagar 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 13952602c32fSVidya Sagar 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 13962602c32fSVidya Sagar 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 13972602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 13982602c32fSVidya Sagar 13992602c32fSVidya Sagar status = "disabled"; 14002602c32fSVidya Sagar 14012602c32fSVidya Sagar #address-cells = <3>; 14022602c32fSVidya Sagar #size-cells = <2>; 14032602c32fSVidya Sagar device_type = "pci"; 14042602c32fSVidya Sagar num-lanes = <8>; 14052602c32fSVidya Sagar num-viewport = <8>; 14062602c32fSVidya Sagar linux,pci-domain = <0>; 14072602c32fSVidya Sagar 14082602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 14092602c32fSVidya Sagar clock-names = "core"; 14102602c32fSVidya Sagar 14112602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 14122602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 14132602c32fSVidya Sagar reset-names = "apb", "core"; 14142602c32fSVidya Sagar 14152602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14162602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14172602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14182602c32fSVidya Sagar 14192602c32fSVidya Sagar #interrupt-cells = <1>; 14202602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14212602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 14222602c32fSVidya Sagar 14232602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 14242602c32fSVidya Sagar 14252602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14262602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14272602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14282602c32fSVidya Sagar 14292602c32fSVidya Sagar bus-range = <0x0 0xff>; 14302602c32fSVidya Sagar ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14312602c32fSVidya Sagar 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 14322602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 14332602c32fSVidya Sagar }; 14342602c32fSVidya Sagar 14352602c32fSVidya Sagar pcie@141a0000 { 14362602c32fSVidya Sagar compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 14372602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 14382602c32fSVidya Sagar reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 14392602c32fSVidya Sagar 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 14402602c32fSVidya Sagar 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 14412602c32fSVidya Sagar 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 14422602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 14432602c32fSVidya Sagar 14442602c32fSVidya Sagar status = "disabled"; 14452602c32fSVidya Sagar 14462602c32fSVidya Sagar #address-cells = <3>; 14472602c32fSVidya Sagar #size-cells = <2>; 14482602c32fSVidya Sagar device_type = "pci"; 14492602c32fSVidya Sagar num-lanes = <8>; 14502602c32fSVidya Sagar num-viewport = <8>; 14512602c32fSVidya Sagar linux,pci-domain = <5>; 14522602c32fSVidya Sagar 1453dbb72e2cSVidya Sagar pinctrl-names = "default"; 1454dbb72e2cSVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1455dbb72e2cSVidya Sagar 14562602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 14572602c32fSVidya Sagar <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 14582602c32fSVidya Sagar clock-names = "core", "core_m"; 14592602c32fSVidya Sagar 14602602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 14612602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 14622602c32fSVidya Sagar reset-names = "apb", "core"; 14632602c32fSVidya Sagar 14642602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 14652602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 14662602c32fSVidya Sagar interrupt-names = "intr", "msi"; 14672602c32fSVidya Sagar 14682602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 14692602c32fSVidya Sagar 14702602c32fSVidya Sagar #interrupt-cells = <1>; 14712602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 14722602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 14732602c32fSVidya Sagar 14742602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 14752602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 14762602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 14772602c32fSVidya Sagar 14782602c32fSVidya Sagar bus-range = <0x0 0xff>; 14792602c32fSVidya Sagar ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 14802602c32fSVidya Sagar 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 14812602c32fSVidya Sagar 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 14822602c32fSVidya Sagar }; 14832602c32fSVidya Sagar 14845425fb15SMikko Perttunen sysram@40000000 { 14855425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 14865425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 14875425fb15SMikko Perttunen #address-cells = <1>; 14885425fb15SMikko Perttunen #size-cells = <1>; 14895425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 14905425fb15SMikko Perttunen 14915425fb15SMikko Perttunen cpu_bpmp_tx: shmem@4e000 { 14925425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 14935425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 14945425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 14955425fb15SMikko Perttunen pool; 14965425fb15SMikko Perttunen }; 14975425fb15SMikko Perttunen 14985425fb15SMikko Perttunen cpu_bpmp_rx: shmem@4f000 { 14995425fb15SMikko Perttunen compatible = "nvidia,tegra194-bpmp-shmem"; 15005425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 15015425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 15025425fb15SMikko Perttunen pool; 15035425fb15SMikko Perttunen }; 15045425fb15SMikko Perttunen }; 15055425fb15SMikko Perttunen 15065425fb15SMikko Perttunen bpmp: bpmp { 15075425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 15085425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 15095425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 15105425fb15SMikko Perttunen shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 15115425fb15SMikko Perttunen #clock-cells = <1>; 15125425fb15SMikko Perttunen #reset-cells = <1>; 15135425fb15SMikko Perttunen #power-domain-cells = <1>; 15145425fb15SMikko Perttunen 15155425fb15SMikko Perttunen bpmp_i2c: i2c { 15165425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 15175425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 15185425fb15SMikko Perttunen #address-cells = <1>; 15195425fb15SMikko Perttunen #size-cells = <0>; 15205425fb15SMikko Perttunen }; 15215425fb15SMikko Perttunen 15225425fb15SMikko Perttunen bpmp_thermal: thermal { 15235425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 15245425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 15255425fb15SMikko Perttunen }; 15265425fb15SMikko Perttunen }; 15275425fb15SMikko Perttunen 15287780a034SMikko Perttunen cpus { 15297780a034SMikko Perttunen #address-cells = <1>; 15307780a034SMikko Perttunen #size-cells = <0>; 15317780a034SMikko Perttunen 1532b45d322cSThierry Reding cpu0_0: cpu@0 { 153331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15347780a034SMikko Perttunen device_type = "cpu"; 1535b45d322cSThierry Reding reg = <0x000>; 15367780a034SMikko Perttunen enable-method = "psci"; 1537b45d322cSThierry Reding i-cache-size = <131072>; 1538b45d322cSThierry Reding i-cache-line-size = <64>; 1539b45d322cSThierry Reding i-cache-sets = <512>; 1540b45d322cSThierry Reding d-cache-size = <65536>; 1541b45d322cSThierry Reding d-cache-line-size = <64>; 1542b45d322cSThierry Reding d-cache-sets = <256>; 1543b45d322cSThierry Reding next-level-cache = <&l2c_0>; 15447780a034SMikko Perttunen }; 15457780a034SMikko Perttunen 1546b45d322cSThierry Reding cpu0_1: cpu@1 { 154731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15487780a034SMikko Perttunen device_type = "cpu"; 1549b45d322cSThierry Reding reg = <0x001>; 15507780a034SMikko Perttunen enable-method = "psci"; 1551b45d322cSThierry Reding i-cache-size = <131072>; 1552b45d322cSThierry Reding i-cache-line-size = <64>; 1553b45d322cSThierry Reding i-cache-sets = <512>; 1554b45d322cSThierry Reding d-cache-size = <65536>; 1555b45d322cSThierry Reding d-cache-line-size = <64>; 1556b45d322cSThierry Reding d-cache-sets = <256>; 1557b45d322cSThierry Reding next-level-cache = <&l2c_0>; 15587780a034SMikko Perttunen }; 15597780a034SMikko Perttunen 1560b45d322cSThierry Reding cpu1_0: cpu@100 { 156131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15627780a034SMikko Perttunen device_type = "cpu"; 15637780a034SMikko Perttunen reg = <0x100>; 15647780a034SMikko Perttunen enable-method = "psci"; 1565b45d322cSThierry Reding i-cache-size = <131072>; 1566b45d322cSThierry Reding i-cache-line-size = <64>; 1567b45d322cSThierry Reding i-cache-sets = <512>; 1568b45d322cSThierry Reding d-cache-size = <65536>; 1569b45d322cSThierry Reding d-cache-line-size = <64>; 1570b45d322cSThierry Reding d-cache-sets = <256>; 1571b45d322cSThierry Reding next-level-cache = <&l2c_1>; 15727780a034SMikko Perttunen }; 15737780a034SMikko Perttunen 1574b45d322cSThierry Reding cpu1_1: cpu@101 { 157531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15767780a034SMikko Perttunen device_type = "cpu"; 15777780a034SMikko Perttunen reg = <0x101>; 15787780a034SMikko Perttunen enable-method = "psci"; 1579b45d322cSThierry Reding i-cache-size = <131072>; 1580b45d322cSThierry Reding i-cache-line-size = <64>; 1581b45d322cSThierry Reding i-cache-sets = <512>; 1582b45d322cSThierry Reding d-cache-size = <65536>; 1583b45d322cSThierry Reding d-cache-line-size = <64>; 1584b45d322cSThierry Reding d-cache-sets = <256>; 1585b45d322cSThierry Reding next-level-cache = <&l2c_1>; 15867780a034SMikko Perttunen }; 15877780a034SMikko Perttunen 1588b45d322cSThierry Reding cpu2_0: cpu@200 { 158931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 15907780a034SMikko Perttunen device_type = "cpu"; 15917780a034SMikko Perttunen reg = <0x200>; 15927780a034SMikko Perttunen enable-method = "psci"; 1593b45d322cSThierry Reding i-cache-size = <131072>; 1594b45d322cSThierry Reding i-cache-line-size = <64>; 1595b45d322cSThierry Reding i-cache-sets = <512>; 1596b45d322cSThierry Reding d-cache-size = <65536>; 1597b45d322cSThierry Reding d-cache-line-size = <64>; 1598b45d322cSThierry Reding d-cache-sets = <256>; 1599b45d322cSThierry Reding next-level-cache = <&l2c_2>; 16007780a034SMikko Perttunen }; 16017780a034SMikko Perttunen 1602b45d322cSThierry Reding cpu2_1: cpu@201 { 160331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 16047780a034SMikko Perttunen device_type = "cpu"; 16057780a034SMikko Perttunen reg = <0x201>; 16067780a034SMikko Perttunen enable-method = "psci"; 1607b45d322cSThierry Reding i-cache-size = <131072>; 1608b45d322cSThierry Reding i-cache-line-size = <64>; 1609b45d322cSThierry Reding i-cache-sets = <512>; 1610b45d322cSThierry Reding d-cache-size = <65536>; 1611b45d322cSThierry Reding d-cache-line-size = <64>; 1612b45d322cSThierry Reding d-cache-sets = <256>; 1613b45d322cSThierry Reding next-level-cache = <&l2c_2>; 16147780a034SMikko Perttunen }; 16157780a034SMikko Perttunen 1616b45d322cSThierry Reding cpu3_0: cpu@300 { 161731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 16187780a034SMikko Perttunen device_type = "cpu"; 1619b45d322cSThierry Reding reg = <0x300>; 16207780a034SMikko Perttunen enable-method = "psci"; 1621b45d322cSThierry Reding i-cache-size = <131072>; 1622b45d322cSThierry Reding i-cache-line-size = <64>; 1623b45d322cSThierry Reding i-cache-sets = <512>; 1624b45d322cSThierry Reding d-cache-size = <65536>; 1625b45d322cSThierry Reding d-cache-line-size = <64>; 1626b45d322cSThierry Reding d-cache-sets = <256>; 1627b45d322cSThierry Reding next-level-cache = <&l2c_3>; 16287780a034SMikko Perttunen }; 16297780a034SMikko Perttunen 1630b45d322cSThierry Reding cpu3_1: cpu@301 { 163131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 16327780a034SMikko Perttunen device_type = "cpu"; 1633b45d322cSThierry Reding reg = <0x301>; 16347780a034SMikko Perttunen enable-method = "psci"; 1635b45d322cSThierry Reding i-cache-size = <131072>; 1636b45d322cSThierry Reding i-cache-line-size = <64>; 1637b45d322cSThierry Reding i-cache-sets = <512>; 1638b45d322cSThierry Reding d-cache-size = <65536>; 1639b45d322cSThierry Reding d-cache-line-size = <64>; 1640b45d322cSThierry Reding d-cache-sets = <256>; 1641b45d322cSThierry Reding next-level-cache = <&l2c_3>; 1642b45d322cSThierry Reding }; 1643b45d322cSThierry Reding 1644b45d322cSThierry Reding cpu-map { 1645b45d322cSThierry Reding cluster0 { 1646b45d322cSThierry Reding core0 { 1647b45d322cSThierry Reding cpu = <&cpu0_0>; 1648b45d322cSThierry Reding }; 1649b45d322cSThierry Reding 1650b45d322cSThierry Reding core1 { 1651b45d322cSThierry Reding cpu = <&cpu0_1>; 1652b45d322cSThierry Reding }; 1653b45d322cSThierry Reding }; 1654b45d322cSThierry Reding 1655b45d322cSThierry Reding cluster1 { 1656b45d322cSThierry Reding core0 { 1657b45d322cSThierry Reding cpu = <&cpu1_0>; 1658b45d322cSThierry Reding }; 1659b45d322cSThierry Reding 1660b45d322cSThierry Reding core1 { 1661b45d322cSThierry Reding cpu = <&cpu1_1>; 1662b45d322cSThierry Reding }; 1663b45d322cSThierry Reding }; 1664b45d322cSThierry Reding 1665b45d322cSThierry Reding cluster2 { 1666b45d322cSThierry Reding core0 { 1667b45d322cSThierry Reding cpu = <&cpu2_0>; 1668b45d322cSThierry Reding }; 1669b45d322cSThierry Reding 1670b45d322cSThierry Reding core1 { 1671b45d322cSThierry Reding cpu = <&cpu2_1>; 1672b45d322cSThierry Reding }; 1673b45d322cSThierry Reding }; 1674b45d322cSThierry Reding 1675b45d322cSThierry Reding cluster3 { 1676b45d322cSThierry Reding core0 { 1677b45d322cSThierry Reding cpu = <&cpu3_0>; 1678b45d322cSThierry Reding }; 1679b45d322cSThierry Reding 1680b45d322cSThierry Reding core1 { 1681b45d322cSThierry Reding cpu = <&cpu3_1>; 1682b45d322cSThierry Reding }; 1683b45d322cSThierry Reding }; 1684b45d322cSThierry Reding }; 1685b45d322cSThierry Reding 1686b45d322cSThierry Reding l2c_0: l2-cache0 { 1687b45d322cSThierry Reding cache-size = <2097152>; 1688b45d322cSThierry Reding cache-line-size = <64>; 1689b45d322cSThierry Reding cache-sets = <2048>; 1690b45d322cSThierry Reding next-level-cache = <&l3c>; 1691b45d322cSThierry Reding }; 1692b45d322cSThierry Reding 1693b45d322cSThierry Reding l2c_1: l2-cache1 { 1694b45d322cSThierry Reding cache-size = <2097152>; 1695b45d322cSThierry Reding cache-line-size = <64>; 1696b45d322cSThierry Reding cache-sets = <2048>; 1697b45d322cSThierry Reding next-level-cache = <&l3c>; 1698b45d322cSThierry Reding }; 1699b45d322cSThierry Reding 1700b45d322cSThierry Reding l2c_2: l2-cache2 { 1701b45d322cSThierry Reding cache-size = <2097152>; 1702b45d322cSThierry Reding cache-line-size = <64>; 1703b45d322cSThierry Reding cache-sets = <2048>; 1704b45d322cSThierry Reding next-level-cache = <&l3c>; 1705b45d322cSThierry Reding }; 1706b45d322cSThierry Reding 1707b45d322cSThierry Reding l2c_3: l2-cache3 { 1708b45d322cSThierry Reding cache-size = <2097152>; 1709b45d322cSThierry Reding cache-line-size = <64>; 1710b45d322cSThierry Reding cache-sets = <2048>; 1711b45d322cSThierry Reding next-level-cache = <&l3c>; 1712b45d322cSThierry Reding }; 1713b45d322cSThierry Reding 1714b45d322cSThierry Reding l3c: l3-cache { 1715b45d322cSThierry Reding cache-size = <4194304>; 1716b45d322cSThierry Reding cache-line-size = <64>; 1717b45d322cSThierry Reding cache-sets = <4096>; 17187780a034SMikko Perttunen }; 17197780a034SMikko Perttunen }; 17207780a034SMikko Perttunen 17217780a034SMikko Perttunen psci { 17227780a034SMikko Perttunen compatible = "arm,psci-1.0"; 17237780a034SMikko Perttunen status = "okay"; 17247780a034SMikko Perttunen method = "smc"; 17257780a034SMikko Perttunen }; 17267780a034SMikko Perttunen 1727a38570c2SMikko Perttunen tcu: tcu { 1728a38570c2SMikko Perttunen compatible = "nvidia,tegra194-tcu"; 1729a38570c2SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1730a38570c2SMikko Perttunen <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1731a38570c2SMikko Perttunen mbox-names = "rx", "tx"; 1732a38570c2SMikko Perttunen }; 1733a38570c2SMikko Perttunen 1734686ba009SThierry Reding thermal-zones { 1735686ba009SThierry Reding cpu { 1736686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1737686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1738686ba009SThierry Reding status = "disabled"; 1739686ba009SThierry Reding }; 1740686ba009SThierry Reding 1741686ba009SThierry Reding gpu { 1742686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1743686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1744686ba009SThierry Reding status = "disabled"; 1745686ba009SThierry Reding }; 1746686ba009SThierry Reding 1747686ba009SThierry Reding aux { 1748686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1749686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1750686ba009SThierry Reding status = "disabled"; 1751686ba009SThierry Reding }; 1752686ba009SThierry Reding 1753686ba009SThierry Reding pllx { 1754686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1755686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1756686ba009SThierry Reding status = "disabled"; 1757686ba009SThierry Reding }; 1758686ba009SThierry Reding 1759686ba009SThierry Reding ao { 1760686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1761686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_AO>; 1762686ba009SThierry Reding status = "disabled"; 1763686ba009SThierry Reding }; 1764686ba009SThierry Reding 1765686ba009SThierry Reding tj { 1766686ba009SThierry Reding thermal-sensors = <&{/bpmp/thermal} 1767686ba009SThierry Reding TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1768686ba009SThierry Reding status = "disabled"; 1769686ba009SThierry Reding }; 1770686ba009SThierry Reding }; 1771686ba009SThierry Reding 17725425fb15SMikko Perttunen timer { 17735425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 17745425fb15SMikko Perttunen interrupts = <GIC_PPI 13 17755425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17765425fb15SMikko Perttunen <GIC_PPI 14 17775425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17785425fb15SMikko Perttunen <GIC_PPI 11 17795425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 17805425fb15SMikko Perttunen <GIC_PPI 10 17815425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 17825425fb15SMikko Perttunen interrupt-parent = <&gic>; 1783b30be673SThierry Reding always-on; 17845425fb15SMikko Perttunen }; 17855425fb15SMikko Perttunen}; 1786