15425fb15SMikko Perttunen// SPDX-License-Identifier: GPL-2.0 25425fb15SMikko Perttunen#include <dt-bindings/clock/tegra194-clock.h> 35425fb15SMikko Perttunen#include <dt-bindings/gpio/tegra194-gpio.h> 45425fb15SMikko Perttunen#include <dt-bindings/interrupt-controller/arm-gic.h> 55425fb15SMikko Perttunen#include <dt-bindings/mailbox/tegra186-hsp.h> 6ff21087eSPrathamesh Shete#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7dbb72e2cSVidya Sagar#include <dt-bindings/pinctrl/pinctrl-tegra.h> 83db6d3baSThierry Reding#include <dt-bindings/power/tegra194-powergate.h> 9dbb72e2cSVidya Sagar#include <dt-bindings/reset/tegra194-reset.h> 10686ba009SThierry Reding#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11be9b887fSThierry Reding#include <dt-bindings/memory/tegra194-mc.h> 125425fb15SMikko Perttunen 135425fb15SMikko Perttunen/ { 145425fb15SMikko Perttunen compatible = "nvidia,tegra194"; 155425fb15SMikko Perttunen interrupt-parent = <&gic>; 165425fb15SMikko Perttunen #address-cells = <2>; 175425fb15SMikko Perttunen #size-cells = <2>; 185425fb15SMikko Perttunen 195425fb15SMikko Perttunen /* control backbone */ 208b3aee8fSThierry Reding bus@0 { 215425fb15SMikko Perttunen compatible = "simple-bus"; 222838cfddSThierry Reding 232838cfddSThierry Reding #address-cells = <2>; 242838cfddSThierry Reding #size-cells = <2>; 254bb54c2cSThierry Reding ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 265425fb15SMikko Perttunen 27a47e173eSSumit Gupta apbmisc: misc@100000 { 2809903c5eSJC Kuo compatible = "nvidia,tegra194-misc"; 292838cfddSThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 302838cfddSThierry Reding <0x0 0x0010f000 0x0 0x1000>; 3109903c5eSJC Kuo }; 3209903c5eSJC Kuo 33f69ce393SMikko Perttunen gpio: gpio@2200000 { 34f69ce393SMikko Perttunen compatible = "nvidia,tegra194-gpio"; 35f69ce393SMikko Perttunen reg-names = "security", "gpio"; 362838cfddSThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 372838cfddSThierry Reding <0x0 0x2210000 0x0 0x10000>; 38f69ce393SMikko Perttunen interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 390a85cf28Spshete <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 400a85cf28Spshete <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 410a85cf28Spshete <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 420a85cf28Spshete <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 430a85cf28Spshete <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 440a85cf28Spshete <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 450a85cf28Spshete <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46f69ce393SMikko Perttunen <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 470a85cf28Spshete <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 480a85cf28Spshete <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 490a85cf28Spshete <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 500a85cf28Spshete <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 510a85cf28Spshete <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 520a85cf28Spshete <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 530a85cf28Spshete <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54f69ce393SMikko Perttunen <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 550a85cf28Spshete <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 560a85cf28Spshete <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 570a85cf28Spshete <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 580a85cf28Spshete <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 590a85cf28Spshete <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 600a85cf28Spshete <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 610a85cf28Spshete <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62f69ce393SMikko Perttunen <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 630a85cf28Spshete <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 640a85cf28Spshete <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 650a85cf28Spshete <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 660a85cf28Spshete <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 670a85cf28Spshete <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 680a85cf28Spshete <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 690a85cf28Spshete <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70f69ce393SMikko Perttunen <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 710a85cf28Spshete <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 720a85cf28Spshete <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 730a85cf28Spshete <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 740a85cf28Spshete <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 750a85cf28Spshete <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 760a85cf28Spshete <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 770a85cf28Spshete <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 780a85cf28Spshete <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 790a85cf28Spshete <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 800a85cf28Spshete <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 810a85cf28Spshete <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 820a85cf28Spshete <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 830a85cf28Spshete <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 840a85cf28Spshete <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 850a85cf28Spshete <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86f69ce393SMikko Perttunen #interrupt-cells = <2>; 87f69ce393SMikko Perttunen interrupt-controller; 88f69ce393SMikko Perttunen #gpio-cells = <2>; 89f69ce393SMikko Perttunen gpio-controller; 906f380a4eSThierry Reding gpio-ranges = <&pinmux 0 0 169>; 91f69ce393SMikko Perttunen }; 92f69ce393SMikko Perttunen 93a47e173eSSumit Gupta cbb-noc@2300000 { 94a47e173eSSumit Gupta compatible = "nvidia,tegra194-cbb-noc"; 952838cfddSThierry Reding reg = <0x0 0x02300000 0x0 0x1000>; 96a47e173eSSumit Gupta interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97a47e173eSSumit Gupta <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 99a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 100a47e173eSSumit Gupta status = "okay"; 101a47e173eSSumit Gupta }; 102a47e173eSSumit Gupta 103a47e173eSSumit Gupta axi2apb: axi2apb@2390000 { 104a47e173eSSumit Gupta compatible = "nvidia,tegra194-axi2apb"; 1052838cfddSThierry Reding reg = <0x0 0x2390000 0x0 0x1000>, 1062838cfddSThierry Reding <0x0 0x23a0000 0x0 0x1000>, 1072838cfddSThierry Reding <0x0 0x23b0000 0x0 0x1000>, 1082838cfddSThierry Reding <0x0 0x23c0000 0x0 0x1000>, 1092838cfddSThierry Reding <0x0 0x23d0000 0x0 0x1000>, 1102838cfddSThierry Reding <0x0 0x23e0000 0x0 0x1000>; 111a47e173eSSumit Gupta status = "okay"; 112a47e173eSSumit Gupta }; 113a47e173eSSumit Gupta 11479ed18d9SThierry Reding pinmux: pinmux@2430000 { 11579ed18d9SThierry Reding compatible = "nvidia,tegra194-pinmux"; 11679ed18d9SThierry Reding reg = <0x0 0x2430000 0x0 0x17000>; 11779ed18d9SThierry Reding status = "okay"; 11879ed18d9SThierry Reding 11979ed18d9SThierry Reding pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 12079ed18d9SThierry Reding clkreq { 12179ed18d9SThierry Reding nvidia,pins = "pex_l5_clkreq_n_pgg0"; 12279ed18d9SThierry Reding nvidia,schmitt = <TEGRA_PIN_DISABLE>; 12379ed18d9SThierry Reding nvidia,enable-input = <TEGRA_PIN_ENABLE>; 12479ed18d9SThierry Reding nvidia,io-hv = <TEGRA_PIN_ENABLE>; 12579ed18d9SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 12679ed18d9SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 12779ed18d9SThierry Reding }; 12879ed18d9SThierry Reding }; 12979ed18d9SThierry Reding 13079ed18d9SThierry Reding pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 13179ed18d9SThierry Reding pex_rst { 13279ed18d9SThierry Reding nvidia,pins = "pex_l5_rst_n_pgg1"; 13379ed18d9SThierry Reding nvidia,schmitt = <TEGRA_PIN_DISABLE>; 13479ed18d9SThierry Reding nvidia,enable-input = <TEGRA_PIN_DISABLE>; 13579ed18d9SThierry Reding nvidia,io-hv = <TEGRA_PIN_ENABLE>; 13679ed18d9SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 13779ed18d9SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 13879ed18d9SThierry Reding }; 13979ed18d9SThierry Reding }; 14079ed18d9SThierry Reding }; 14179ed18d9SThierry Reding 142f89b58ceSMikko Perttunen ethernet@2490000 { 14319dc772aSThierry Reding compatible = "nvidia,tegra194-eqos", 14419dc772aSThierry Reding "nvidia,tegra186-eqos", 145f89b58ceSMikko Perttunen "snps,dwc-qos-ethernet-4.10"; 1462838cfddSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 147f89b58ceSMikko Perttunen interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148f89b58ceSMikko Perttunen clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_AXI>, 150f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_RX>, 151f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_TX>, 152f89b58ceSMikko Perttunen <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153f89b58ceSMikko Perttunen clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154f89b58ceSMikko Perttunen resets = <&bpmp TEGRA194_RESET_EQOS>; 155f89b58ceSMikko Perttunen reset-names = "eqos"; 156d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 159c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_EQOS>; 160f89b58ceSMikko Perttunen status = "disabled"; 161f89b58ceSMikko Perttunen 162f89b58ceSMikko Perttunen snps,write-requests = <1>; 163f89b58ceSMikko Perttunen snps,read-requests = <3>; 164f89b58ceSMikko Perttunen snps,burst-map = <0x7>; 165f89b58ceSMikko Perttunen snps,txpbl = <16>; 166f89b58ceSMikko Perttunen snps,rxpbl = <8>; 167f89b58ceSMikko Perttunen }; 168f89b58ceSMikko Perttunen 169835553b3SAkhil R gpcdma: dma-controller@2600000 { 170835553b3SAkhil R compatible = "nvidia,tegra194-gpcdma", 171835553b3SAkhil R "nvidia,tegra186-gpcdma"; 1722838cfddSThierry Reding reg = <0x0 0x2600000 0x0 0x210000>; 173835553b3SAkhil R resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174835553b3SAkhil R reset-names = "gpcdma"; 175dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207835553b3SAkhil R #dma-cells = <1>; 208835553b3SAkhil R iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209835553b3SAkhil R dma-coherent; 210dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 211835553b3SAkhil R status = "okay"; 212835553b3SAkhil R }; 213835553b3SAkhil R 2141aaa7698SThierry Reding aconnect@2900000 { 2155d2249ddSSameer Pujar compatible = "nvidia,tegra194-aconnect", 2165d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 2175d2249ddSSameer Pujar clocks = <&bpmp TEGRA194_CLK_APE>, 2185d2249ddSSameer Pujar <&bpmp TEGRA194_CLK_APB2APE>; 2195d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 2205d2249ddSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 2215d2249ddSSameer Pujar status = "disabled"; 2225d2249ddSSameer Pujar 2232838cfddSThierry Reding #address-cells = <2>; 2242838cfddSThierry Reding #size-cells = <2>; 2252838cfddSThierry Reding ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 2262838cfddSThierry Reding 227177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 228177208f7SSameer Pujar compatible = "nvidia,tegra194-ahub", 229177208f7SSameer Pujar "nvidia,tegra186-ahub"; 2302838cfddSThierry Reding reg = <0x0 0x02900800 0x0 0x800>; 231177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_AHUB>; 232177208f7SSameer Pujar clock-names = "ahub"; 233177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234*dc6d5d85SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>; 235*dc6d5d85SSameer Pujar assigned-clock-rates = <81600000>; 236177208f7SSameer Pujar status = "disabled"; 237177208f7SSameer Pujar 2382838cfddSThierry Reding #address-cells = <2>; 2392838cfddSThierry Reding #size-cells = <2>; 2402838cfddSThierry Reding ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 2412838cfddSThierry Reding 242177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 243177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 244177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2452838cfddSThierry Reding reg = <0x0 0x2901000 0x0 0x100>; 246177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S1>, 247177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 248177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 249177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 250177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 251177208f7SSameer Pujar assigned-clock-rates = <1536000>; 252177208f7SSameer Pujar sound-name-prefix = "I2S1"; 253177208f7SSameer Pujar status = "disabled"; 254177208f7SSameer Pujar }; 255177208f7SSameer Pujar 256177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 257177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 258177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2592838cfddSThierry Reding reg = <0x0 0x2901100 0x0 0x100>; 260177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S2>, 261177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 262177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 263177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 264177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 265177208f7SSameer Pujar assigned-clock-rates = <1536000>; 266177208f7SSameer Pujar sound-name-prefix = "I2S2"; 267177208f7SSameer Pujar status = "disabled"; 268177208f7SSameer Pujar }; 269177208f7SSameer Pujar 270177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 271177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 272177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2732838cfddSThierry Reding reg = <0x0 0x2901200 0x0 0x100>; 274177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S3>, 275177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 276177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 277177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 278177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 279177208f7SSameer Pujar assigned-clock-rates = <1536000>; 280177208f7SSameer Pujar sound-name-prefix = "I2S3"; 281177208f7SSameer Pujar status = "disabled"; 282177208f7SSameer Pujar }; 283177208f7SSameer Pujar 284177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 285177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 286177208f7SSameer Pujar "nvidia,tegra210-i2s"; 2872838cfddSThierry Reding reg = <0x0 0x2901300 0x0 0x100>; 288177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S4>, 289177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 290177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 291177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 292177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 293177208f7SSameer Pujar assigned-clock-rates = <1536000>; 294177208f7SSameer Pujar sound-name-prefix = "I2S4"; 295177208f7SSameer Pujar status = "disabled"; 296177208f7SSameer Pujar }; 297177208f7SSameer Pujar 298177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 299177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 300177208f7SSameer Pujar "nvidia,tegra210-i2s"; 3012838cfddSThierry Reding reg = <0x0 0x2901400 0x0 0x100>; 302177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S5>, 303177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 304177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 305177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 306177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 307177208f7SSameer Pujar assigned-clock-rates = <1536000>; 308177208f7SSameer Pujar sound-name-prefix = "I2S5"; 309177208f7SSameer Pujar status = "disabled"; 310177208f7SSameer Pujar }; 311177208f7SSameer Pujar 312177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 313177208f7SSameer Pujar compatible = "nvidia,tegra194-i2s", 314177208f7SSameer Pujar "nvidia,tegra210-i2s"; 3152838cfddSThierry Reding reg = <0x0 0x2901500 0x0 0x100>; 316177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_I2S6>, 317177208f7SSameer Pujar <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 318177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 319177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 320177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 321177208f7SSameer Pujar assigned-clock-rates = <1536000>; 322177208f7SSameer Pujar sound-name-prefix = "I2S6"; 323177208f7SSameer Pujar status = "disabled"; 324177208f7SSameer Pujar }; 325177208f7SSameer Pujar 32679ed18d9SThierry Reding tegra_sfc1: sfc@2902000 { 32779ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 32879ed18d9SThierry Reding "nvidia,tegra210-sfc"; 32979ed18d9SThierry Reding reg = <0x0 0x2902000 0x0 0x200>; 33079ed18d9SThierry Reding sound-name-prefix = "SFC1"; 33179ed18d9SThierry Reding status = "disabled"; 33279ed18d9SThierry Reding }; 33379ed18d9SThierry Reding 33479ed18d9SThierry Reding tegra_sfc2: sfc@2902200 { 33579ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 33679ed18d9SThierry Reding "nvidia,tegra210-sfc"; 33779ed18d9SThierry Reding reg = <0x0 0x2902200 0x0 0x200>; 33879ed18d9SThierry Reding sound-name-prefix = "SFC2"; 33979ed18d9SThierry Reding status = "disabled"; 34079ed18d9SThierry Reding }; 34179ed18d9SThierry Reding 34279ed18d9SThierry Reding tegra_sfc3: sfc@2902400 { 34379ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 34479ed18d9SThierry Reding "nvidia,tegra210-sfc"; 34579ed18d9SThierry Reding reg = <0x0 0x2902400 0x0 0x200>; 34679ed18d9SThierry Reding sound-name-prefix = "SFC3"; 34779ed18d9SThierry Reding status = "disabled"; 34879ed18d9SThierry Reding }; 34979ed18d9SThierry Reding 35079ed18d9SThierry Reding tegra_sfc4: sfc@2902600 { 35179ed18d9SThierry Reding compatible = "nvidia,tegra194-sfc", 35279ed18d9SThierry Reding "nvidia,tegra210-sfc"; 35379ed18d9SThierry Reding reg = <0x0 0x2902600 0x0 0x200>; 35479ed18d9SThierry Reding sound-name-prefix = "SFC4"; 35579ed18d9SThierry Reding status = "disabled"; 35679ed18d9SThierry Reding }; 35779ed18d9SThierry Reding 35879ed18d9SThierry Reding tegra_amx1: amx@2903000 { 35979ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 36079ed18d9SThierry Reding reg = <0x0 0x2903000 0x0 0x100>; 36179ed18d9SThierry Reding sound-name-prefix = "AMX1"; 36279ed18d9SThierry Reding status = "disabled"; 36379ed18d9SThierry Reding }; 36479ed18d9SThierry Reding 36579ed18d9SThierry Reding tegra_amx2: amx@2903100 { 36679ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 36779ed18d9SThierry Reding reg = <0x0 0x2903100 0x0 0x100>; 36879ed18d9SThierry Reding sound-name-prefix = "AMX2"; 36979ed18d9SThierry Reding status = "disabled"; 37079ed18d9SThierry Reding }; 37179ed18d9SThierry Reding 37279ed18d9SThierry Reding tegra_amx3: amx@2903200 { 37379ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 37479ed18d9SThierry Reding reg = <0x0 0x2903200 0x0 0x100>; 37579ed18d9SThierry Reding sound-name-prefix = "AMX3"; 37679ed18d9SThierry Reding status = "disabled"; 37779ed18d9SThierry Reding }; 37879ed18d9SThierry Reding 37979ed18d9SThierry Reding tegra_amx4: amx@2903300 { 38079ed18d9SThierry Reding compatible = "nvidia,tegra194-amx"; 38179ed18d9SThierry Reding reg = <0x0 0x2903300 0x0 0x100>; 38279ed18d9SThierry Reding sound-name-prefix = "AMX4"; 38379ed18d9SThierry Reding status = "disabled"; 38479ed18d9SThierry Reding }; 38579ed18d9SThierry Reding 38679ed18d9SThierry Reding tegra_adx1: adx@2903800 { 38779ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 38879ed18d9SThierry Reding "nvidia,tegra210-adx"; 38979ed18d9SThierry Reding reg = <0x0 0x2903800 0x0 0x100>; 39079ed18d9SThierry Reding sound-name-prefix = "ADX1"; 39179ed18d9SThierry Reding status = "disabled"; 39279ed18d9SThierry Reding }; 39379ed18d9SThierry Reding 39479ed18d9SThierry Reding tegra_adx2: adx@2903900 { 39579ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 39679ed18d9SThierry Reding "nvidia,tegra210-adx"; 39779ed18d9SThierry Reding reg = <0x0 0x2903900 0x0 0x100>; 39879ed18d9SThierry Reding sound-name-prefix = "ADX2"; 39979ed18d9SThierry Reding status = "disabled"; 40079ed18d9SThierry Reding }; 40179ed18d9SThierry Reding 40279ed18d9SThierry Reding tegra_adx3: adx@2903a00 { 40379ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 40479ed18d9SThierry Reding "nvidia,tegra210-adx"; 40579ed18d9SThierry Reding reg = <0x0 0x2903a00 0x0 0x100>; 40679ed18d9SThierry Reding sound-name-prefix = "ADX3"; 40779ed18d9SThierry Reding status = "disabled"; 40879ed18d9SThierry Reding }; 40979ed18d9SThierry Reding 41079ed18d9SThierry Reding tegra_adx4: adx@2903b00 { 41179ed18d9SThierry Reding compatible = "nvidia,tegra194-adx", 41279ed18d9SThierry Reding "nvidia,tegra210-adx"; 41379ed18d9SThierry Reding reg = <0x0 0x2903b00 0x0 0x100>; 41479ed18d9SThierry Reding sound-name-prefix = "ADX4"; 41579ed18d9SThierry Reding status = "disabled"; 41679ed18d9SThierry Reding }; 41779ed18d9SThierry Reding 418177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 419177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 420177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4212838cfddSThierry Reding reg = <0x0 0x2904000 0x0 0x100>; 422177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC1>; 423177208f7SSameer Pujar clock-names = "dmic"; 424177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 425177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426177208f7SSameer Pujar assigned-clock-rates = <3072000>; 427177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 428177208f7SSameer Pujar status = "disabled"; 429177208f7SSameer Pujar }; 430177208f7SSameer Pujar 431177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 432177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 433177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4342838cfddSThierry Reding reg = <0x0 0x2904100 0x0 0x100>; 435177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC2>; 436177208f7SSameer Pujar clock-names = "dmic"; 437177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 438177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439177208f7SSameer Pujar assigned-clock-rates = <3072000>; 440177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 441177208f7SSameer Pujar status = "disabled"; 442177208f7SSameer Pujar }; 443177208f7SSameer Pujar 444177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 445177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 446177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4472838cfddSThierry Reding reg = <0x0 0x2904200 0x0 0x100>; 448177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC3>; 449177208f7SSameer Pujar clock-names = "dmic"; 450177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 451177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452177208f7SSameer Pujar assigned-clock-rates = <3072000>; 453177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 454177208f7SSameer Pujar status = "disabled"; 455177208f7SSameer Pujar }; 456177208f7SSameer Pujar 457177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 458177208f7SSameer Pujar compatible = "nvidia,tegra194-dmic", 459177208f7SSameer Pujar "nvidia,tegra210-dmic"; 4602838cfddSThierry Reding reg = <0x0 0x2904300 0x0 0x100>; 461177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DMIC4>; 462177208f7SSameer Pujar clock-names = "dmic"; 463177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 464177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 465177208f7SSameer Pujar assigned-clock-rates = <3072000>; 466177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 467177208f7SSameer Pujar status = "disabled"; 468177208f7SSameer Pujar }; 469177208f7SSameer Pujar 470177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 471177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 472177208f7SSameer Pujar "nvidia,tegra186-dspk"; 4732838cfddSThierry Reding reg = <0x0 0x2905000 0x0 0x100>; 474177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK1>; 475177208f7SSameer Pujar clock-names = "dspk"; 476177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 477177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 478177208f7SSameer Pujar assigned-clock-rates = <12288000>; 479177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 480177208f7SSameer Pujar status = "disabled"; 481177208f7SSameer Pujar }; 482177208f7SSameer Pujar 483177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 484177208f7SSameer Pujar compatible = "nvidia,tegra194-dspk", 485177208f7SSameer Pujar "nvidia,tegra186-dspk"; 4862838cfddSThierry Reding reg = <0x0 0x2905100 0x0 0x100>; 487177208f7SSameer Pujar clocks = <&bpmp TEGRA194_CLK_DSPK2>; 488177208f7SSameer Pujar clock-names = "dspk"; 489177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 490177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 491177208f7SSameer Pujar assigned-clock-rates = <12288000>; 492177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 493177208f7SSameer Pujar status = "disabled"; 494177208f7SSameer Pujar }; 495848f3290SSameer Pujar 4964b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 4974b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-ope", 4984b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4992838cfddSThierry Reding reg = <0x0 0x2908000 0x0 0x100>; 5004b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5014b6a1b7cSSameer Pujar status = "disabled"; 5024b6a1b7cSSameer Pujar 5032838cfddSThierry Reding #address-cells = <2>; 5042838cfddSThierry Reding #size-cells = <2>; 5052838cfddSThierry Reding ranges; 5062838cfddSThierry Reding 5074b6a1b7cSSameer Pujar equalizer@2908100 { 5084b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-peq", 5094b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5102838cfddSThierry Reding reg = <0x0 0x2908100 0x0 0x100>; 5114b6a1b7cSSameer Pujar }; 5124b6a1b7cSSameer Pujar 5134b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 5144b6a1b7cSSameer Pujar compatible = "nvidia,tegra194-mbdrc", 5154b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 5162838cfddSThierry Reding reg = <0x0 0x2908200 0x0 0x200>; 5174b6a1b7cSSameer Pujar }; 5184b6a1b7cSSameer Pujar }; 5194b6a1b7cSSameer Pujar 52079ed18d9SThierry Reding tegra_mvc1: mvc@290a000 { 52179ed18d9SThierry Reding compatible = "nvidia,tegra194-mvc", 52279ed18d9SThierry Reding "nvidia,tegra210-mvc"; 52379ed18d9SThierry Reding reg = <0x0 0x290a000 0x0 0x200>; 52479ed18d9SThierry Reding sound-name-prefix = "MVC1"; 52579ed18d9SThierry Reding status = "disabled"; 52679ed18d9SThierry Reding }; 52779ed18d9SThierry Reding 52879ed18d9SThierry Reding tegra_mvc2: mvc@290a200 { 52979ed18d9SThierry Reding compatible = "nvidia,tegra194-mvc", 53079ed18d9SThierry Reding "nvidia,tegra210-mvc"; 53179ed18d9SThierry Reding reg = <0x0 0x290a200 0x0 0x200>; 53279ed18d9SThierry Reding sound-name-prefix = "MVC2"; 53379ed18d9SThierry Reding status = "disabled"; 53479ed18d9SThierry Reding }; 53579ed18d9SThierry Reding 536848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 537848f3290SSameer Pujar compatible = "nvidia,tegra194-amixer", 538848f3290SSameer Pujar "nvidia,tegra210-amixer"; 5392838cfddSThierry Reding reg = <0x0 0x290bb00 0x0 0x800>; 540848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 541848f3290SSameer Pujar status = "disabled"; 542848f3290SSameer Pujar }; 54347a08153SSameer Pujar 54479ed18d9SThierry Reding tegra_admaif: admaif@290f000 { 54579ed18d9SThierry Reding compatible = "nvidia,tegra194-admaif", 54679ed18d9SThierry Reding "nvidia,tegra186-admaif"; 54779ed18d9SThierry Reding reg = <0x0 0x0290f000 0x0 0x1000>; 54879ed18d9SThierry Reding dmas = <&adma 1>, <&adma 1>, 54979ed18d9SThierry Reding <&adma 2>, <&adma 2>, 55079ed18d9SThierry Reding <&adma 3>, <&adma 3>, 55179ed18d9SThierry Reding <&adma 4>, <&adma 4>, 55279ed18d9SThierry Reding <&adma 5>, <&adma 5>, 55379ed18d9SThierry Reding <&adma 6>, <&adma 6>, 55479ed18d9SThierry Reding <&adma 7>, <&adma 7>, 55579ed18d9SThierry Reding <&adma 8>, <&adma 8>, 55679ed18d9SThierry Reding <&adma 9>, <&adma 9>, 55779ed18d9SThierry Reding <&adma 10>, <&adma 10>, 55879ed18d9SThierry Reding <&adma 11>, <&adma 11>, 55979ed18d9SThierry Reding <&adma 12>, <&adma 12>, 56079ed18d9SThierry Reding <&adma 13>, <&adma 13>, 56179ed18d9SThierry Reding <&adma 14>, <&adma 14>, 56279ed18d9SThierry Reding <&adma 15>, <&adma 15>, 56379ed18d9SThierry Reding <&adma 16>, <&adma 16>, 56479ed18d9SThierry Reding <&adma 17>, <&adma 17>, 56579ed18d9SThierry Reding <&adma 18>, <&adma 18>, 56679ed18d9SThierry Reding <&adma 19>, <&adma 19>, 56779ed18d9SThierry Reding <&adma 20>, <&adma 20>; 56879ed18d9SThierry Reding dma-names = "rx1", "tx1", 56979ed18d9SThierry Reding "rx2", "tx2", 57079ed18d9SThierry Reding "rx3", "tx3", 57179ed18d9SThierry Reding "rx4", "tx4", 57279ed18d9SThierry Reding "rx5", "tx5", 57379ed18d9SThierry Reding "rx6", "tx6", 57479ed18d9SThierry Reding "rx7", "tx7", 57579ed18d9SThierry Reding "rx8", "tx8", 57679ed18d9SThierry Reding "rx9", "tx9", 57779ed18d9SThierry Reding "rx10", "tx10", 57879ed18d9SThierry Reding "rx11", "tx11", 57979ed18d9SThierry Reding "rx12", "tx12", 58079ed18d9SThierry Reding "rx13", "tx13", 58179ed18d9SThierry Reding "rx14", "tx14", 58279ed18d9SThierry Reding "rx15", "tx15", 58379ed18d9SThierry Reding "rx16", "tx16", 58479ed18d9SThierry Reding "rx17", "tx17", 58579ed18d9SThierry Reding "rx18", "tx18", 58679ed18d9SThierry Reding "rx19", "tx19", 58779ed18d9SThierry Reding "rx20", "tx20"; 58879ed18d9SThierry Reding status = "disabled"; 58979ed18d9SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 59079ed18d9SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 59179ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 59279ed18d9SThierry Reding iommus = <&smmu TEGRA194_SID_APE>; 59379ed18d9SThierry Reding }; 59479ed18d9SThierry Reding 59547a08153SSameer Pujar tegra_asrc: asrc@2910000 { 59647a08153SSameer Pujar compatible = "nvidia,tegra194-asrc", 59747a08153SSameer Pujar "nvidia,tegra186-asrc"; 5982838cfddSThierry Reding reg = <0x0 0x2910000 0x0 0x2000>; 59947a08153SSameer Pujar sound-name-prefix = "ASRC1"; 60047a08153SSameer Pujar status = "disabled"; 60147a08153SSameer Pujar }; 602177208f7SSameer Pujar }; 60379ed18d9SThierry Reding 60479ed18d9SThierry Reding adma: dma-controller@2930000 { 60579ed18d9SThierry Reding compatible = "nvidia,tegra194-adma", 60679ed18d9SThierry Reding "nvidia,tegra186-adma"; 60779ed18d9SThierry Reding reg = <0x0 0x02930000 0x0 0x20000>; 60879ed18d9SThierry Reding interrupt-parent = <&agic>; 60979ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 61079ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 61179ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 61279ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 61379ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 61479ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 61579ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 61679ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 61779ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 61879ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 61979ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 62079ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 62179ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 62279ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 62379ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 62479ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 62579ed18d9SThierry Reding <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 62679ed18d9SThierry Reding <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 62779ed18d9SThierry Reding <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 62879ed18d9SThierry Reding <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 62979ed18d9SThierry Reding <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 63079ed18d9SThierry Reding <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 63179ed18d9SThierry Reding <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 63279ed18d9SThierry Reding <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 63379ed18d9SThierry Reding <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 63479ed18d9SThierry Reding <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 63579ed18d9SThierry Reding <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 63679ed18d9SThierry Reding <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 63779ed18d9SThierry Reding <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 63879ed18d9SThierry Reding <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 63979ed18d9SThierry Reding <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 64079ed18d9SThierry Reding <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 64179ed18d9SThierry Reding #dma-cells = <1>; 64279ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_AHUB>; 64379ed18d9SThierry Reding clock-names = "d_audio"; 64479ed18d9SThierry Reding status = "disabled"; 6455d2249ddSSameer Pujar }; 6465d2249ddSSameer Pujar 64779ed18d9SThierry Reding agic: interrupt-controller@2a40000 { 64879ed18d9SThierry Reding compatible = "nvidia,tegra194-agic", 64979ed18d9SThierry Reding "nvidia,tegra210-agic"; 65079ed18d9SThierry Reding #interrupt-cells = <3>; 65179ed18d9SThierry Reding interrupt-controller; 65279ed18d9SThierry Reding reg = <0x0 0x02a41000 0x0 0x1000>, 65379ed18d9SThierry Reding <0x0 0x02a42000 0x0 0x2000>; 65479ed18d9SThierry Reding interrupts = <GIC_SPI 145 65579ed18d9SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | 65679ed18d9SThierry Reding IRQ_TYPE_LEVEL_HIGH)>; 65779ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_APE>; 65879ed18d9SThierry Reding clock-names = "clk"; 65979ed18d9SThierry Reding status = "disabled"; 660dbb72e2cSVidya Sagar }; 661dbb72e2cSVidya Sagar }; 662dbb72e2cSVidya Sagar 663be9b887fSThierry Reding mc: memory-controller@2c00000 { 664be9b887fSThierry Reding compatible = "nvidia,tegra194-mc"; 6652838cfddSThierry Reding reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 6662838cfddSThierry Reding <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 6672838cfddSThierry Reding <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 6682838cfddSThierry Reding <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 6692838cfddSThierry Reding <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 6702838cfddSThierry Reding <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 6712838cfddSThierry Reding <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 6722838cfddSThierry Reding <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 6732838cfddSThierry Reding <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 6742838cfddSThierry Reding <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 6752838cfddSThierry Reding <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 6762838cfddSThierry Reding <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 6772838cfddSThierry Reding <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 6782838cfddSThierry Reding <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 6792838cfddSThierry Reding <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 6802838cfddSThierry Reding <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 6812838cfddSThierry Reding <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 6822838cfddSThierry Reding <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 683000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 684000b99e5SAshish Mhetre "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 685000b99e5SAshish Mhetre "ch11", "ch12", "ch13", "ch14", "ch15"; 6868613b4c8SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 687d5237c7cSThierry Reding #interconnect-cells = <1>; 688be9b887fSThierry Reding status = "disabled"; 689be9b887fSThierry Reding 690be9b887fSThierry Reding #address-cells = <2>; 691be9b887fSThierry Reding #size-cells = <2>; 6922838cfddSThierry Reding ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 6932838cfddSThierry Reding <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 6942838cfddSThierry Reding <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 695be9b887fSThierry Reding 696be9b887fSThierry Reding /* 697be9b887fSThierry Reding * Bit 39 of addresses passing through the memory 698be9b887fSThierry Reding * controller selects the XBAR format used when memory 699be9b887fSThierry Reding * is accessed. This is used to transparently access 700be9b887fSThierry Reding * memory in the XBAR format used by the discrete GPU 701be9b887fSThierry Reding * (bit 39 set) or Tegra (bit 39 clear). 702be9b887fSThierry Reding * 703be9b887fSThierry Reding * As a consequence, the operating system must ensure 704be9b887fSThierry Reding * that bit 39 is never used implicitly, for example 705be9b887fSThierry Reding * via an I/O virtual address mapping of an IOMMU. If 706be9b887fSThierry Reding * devices require access to the XBAR switch, their 707be9b887fSThierry Reding * drivers must set this bit explicitly. 708be9b887fSThierry Reding * 709be9b887fSThierry Reding * Limit the DMA range for memory clients to [38:0]. 710be9b887fSThierry Reding */ 7112838cfddSThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 712be9b887fSThierry Reding 713be9b887fSThierry Reding emc: external-memory-controller@2c60000 { 714be9b887fSThierry Reding compatible = "nvidia,tegra194-emc"; 715be9b887fSThierry Reding reg = <0x0 0x02c60000 0x0 0x90000>, 716be9b887fSThierry Reding <0x0 0x01780000 0x0 0x80000>; 717cc939667SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 718be9b887fSThierry Reding clocks = <&bpmp TEGRA194_CLK_EMC>; 719be9b887fSThierry Reding clock-names = "emc"; 720be9b887fSThierry Reding 721d5237c7cSThierry Reding #interconnect-cells = <0>; 722d5237c7cSThierry Reding 723be9b887fSThierry Reding nvidia,bpmp = <&bpmp>; 724be9b887fSThierry Reding }; 725be9b887fSThierry Reding }; 726be9b887fSThierry Reding 7275aa9083eSThierry Reding timer@3010000 { 7285aa9083eSThierry Reding compatible = "nvidia,tegra186-timer"; 7292838cfddSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 7305aa9083eSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 7315aa9083eSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7325aa9083eSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 7335aa9083eSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7345aa9083eSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7355aa9083eSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 7365aa9083eSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 7375aa9083eSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 7385aa9083eSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7395aa9083eSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7405aa9083eSThierry Reding status = "okay"; 7415aa9083eSThierry Reding }; 7425aa9083eSThierry Reding 7435425fb15SMikko Perttunen uarta: serial@3100000 { 7445425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7452838cfddSThierry Reding reg = <0x0 0x03100000 0x0 0x40>; 7465425fb15SMikko Perttunen reg-shift = <2>; 7475425fb15SMikko Perttunen interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 7485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTA>; 7495425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTA>; 7505425fb15SMikko Perttunen status = "disabled"; 7515425fb15SMikko Perttunen }; 7525425fb15SMikko Perttunen 7535425fb15SMikko Perttunen uartb: serial@3110000 { 7545425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7552838cfddSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 7565425fb15SMikko Perttunen reg-shift = <2>; 7575425fb15SMikko Perttunen interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 7585425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTB>; 7595425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTB>; 7605425fb15SMikko Perttunen status = "disabled"; 7615425fb15SMikko Perttunen }; 7625425fb15SMikko Perttunen 7635425fb15SMikko Perttunen uartd: serial@3130000 { 7645425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7652838cfddSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 7665425fb15SMikko Perttunen reg-shift = <2>; 7675425fb15SMikko Perttunen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 7685425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTD>; 7695425fb15SMikko Perttunen clock-names = "serial"; 7705425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTD>; 7715425fb15SMikko Perttunen reset-names = "serial"; 7725425fb15SMikko Perttunen status = "disabled"; 7735425fb15SMikko Perttunen }; 7745425fb15SMikko Perttunen 7755425fb15SMikko Perttunen uarte: serial@3140000 { 7765425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7772838cfddSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 7785425fb15SMikko Perttunen reg-shift = <2>; 7795425fb15SMikko Perttunen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 7805425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTE>; 7815425fb15SMikko Perttunen clock-names = "serial"; 7825425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTE>; 7835425fb15SMikko Perttunen reset-names = "serial"; 7845425fb15SMikko Perttunen status = "disabled"; 7855425fb15SMikko Perttunen }; 7865425fb15SMikko Perttunen 7875425fb15SMikko Perttunen uartf: serial@3150000 { 7885425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 7892838cfddSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 7905425fb15SMikko Perttunen reg-shift = <2>; 7915425fb15SMikko Perttunen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7925425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTF>; 7935425fb15SMikko Perttunen clock-names = "serial"; 7945425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTF>; 7955425fb15SMikko Perttunen reset-names = "serial"; 7965425fb15SMikko Perttunen status = "disabled"; 7975425fb15SMikko Perttunen }; 7985425fb15SMikko Perttunen 7995425fb15SMikko Perttunen gen1_i2c: i2c@3160000 { 800d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8012838cfddSThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 8025425fb15SMikko Perttunen interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 8035425fb15SMikko Perttunen #address-cells = <1>; 8045425fb15SMikko Perttunen #size-cells = <0>; 8055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C1>; 8065425fb15SMikko Perttunen clock-names = "div-clk"; 8075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C1>; 8085425fb15SMikko Perttunen reset-names = "i2c"; 8098e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 8108e442805SAkhil R dma-names = "rx", "tx"; 8115425fb15SMikko Perttunen status = "disabled"; 8125425fb15SMikko Perttunen }; 8135425fb15SMikko Perttunen 8145425fb15SMikko Perttunen uarth: serial@3170000 { 8155425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 8162838cfddSThierry Reding reg = <0x0 0x03170000 0x0 0x40>; 8175425fb15SMikko Perttunen reg-shift = <2>; 8185425fb15SMikko Perttunen interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 8195425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTH>; 8205425fb15SMikko Perttunen clock-names = "serial"; 8215425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTH>; 8225425fb15SMikko Perttunen reset-names = "serial"; 8235425fb15SMikko Perttunen status = "disabled"; 8245425fb15SMikko Perttunen }; 8255425fb15SMikko Perttunen 8265425fb15SMikko Perttunen cam_i2c: i2c@3180000 { 827d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8282838cfddSThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 8295425fb15SMikko Perttunen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8305425fb15SMikko Perttunen #address-cells = <1>; 8315425fb15SMikko Perttunen #size-cells = <0>; 8325425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C3>; 8335425fb15SMikko Perttunen clock-names = "div-clk"; 8345425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C3>; 8355425fb15SMikko Perttunen reset-names = "i2c"; 8368e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 8378e442805SAkhil R dma-names = "rx", "tx"; 8385425fb15SMikko Perttunen status = "disabled"; 8395425fb15SMikko Perttunen }; 8405425fb15SMikko Perttunen 8415425fb15SMikko Perttunen /* shares pads with dpaux1 */ 8425425fb15SMikko Perttunen dp_aux_ch1_i2c: i2c@3190000 { 843d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8442838cfddSThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 8455425fb15SMikko Perttunen interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8465425fb15SMikko Perttunen #address-cells = <1>; 8475425fb15SMikko Perttunen #size-cells = <0>; 8485425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C4>; 8495425fb15SMikko Perttunen clock-names = "div-clk"; 8505425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C4>; 8515425fb15SMikko Perttunen reset-names = "i2c"; 852a4131561SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 853a4131561SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 854a4131561SThierry Reding pinctrl-names = "default", "idle"; 8558e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 8568e442805SAkhil R dma-names = "rx", "tx"; 8575425fb15SMikko Perttunen status = "disabled"; 8585425fb15SMikko Perttunen }; 8595425fb15SMikko Perttunen 8605425fb15SMikko Perttunen /* shares pads with dpaux0 */ 8615425fb15SMikko Perttunen dp_aux_ch0_i2c: i2c@31b0000 { 862d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8632838cfddSThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 8645425fb15SMikko Perttunen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 8655425fb15SMikko Perttunen #address-cells = <1>; 8665425fb15SMikko Perttunen #size-cells = <0>; 8675425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C6>; 8685425fb15SMikko Perttunen clock-names = "div-clk"; 8695425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C6>; 8705425fb15SMikko Perttunen reset-names = "i2c"; 871a4131561SThierry Reding pinctrl-0 = <&state_dpaux0_i2c>; 872a4131561SThierry Reding pinctrl-1 = <&state_dpaux0_off>; 873a4131561SThierry Reding pinctrl-names = "default", "idle"; 8748e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 8758e442805SAkhil R dma-names = "rx", "tx"; 8765425fb15SMikko Perttunen status = "disabled"; 8775425fb15SMikko Perttunen }; 8785425fb15SMikko Perttunen 879a4131561SThierry Reding /* shares pads with dpaux2 */ 880a4131561SThierry Reding dp_aux_ch2_i2c: i2c@31c0000 { 881d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 8822838cfddSThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 8835425fb15SMikko Perttunen interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 8845425fb15SMikko Perttunen #address-cells = <1>; 8855425fb15SMikko Perttunen #size-cells = <0>; 8865425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C7>; 8875425fb15SMikko Perttunen clock-names = "div-clk"; 8885425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C7>; 8895425fb15SMikko Perttunen reset-names = "i2c"; 890a4131561SThierry Reding pinctrl-0 = <&state_dpaux2_i2c>; 891a4131561SThierry Reding pinctrl-1 = <&state_dpaux2_off>; 892a4131561SThierry Reding pinctrl-names = "default", "idle"; 8938e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 8948e442805SAkhil R dma-names = "rx", "tx"; 8955425fb15SMikko Perttunen status = "disabled"; 8965425fb15SMikko Perttunen }; 8975425fb15SMikko Perttunen 898a4131561SThierry Reding /* shares pads with dpaux3 */ 899a4131561SThierry Reding dp_aux_ch3_i2c: i2c@31e0000 { 900d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 9012838cfddSThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 9025425fb15SMikko Perttunen interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 9035425fb15SMikko Perttunen #address-cells = <1>; 9045425fb15SMikko Perttunen #size-cells = <0>; 9055425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C9>; 9065425fb15SMikko Perttunen clock-names = "div-clk"; 9075425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C9>; 9085425fb15SMikko Perttunen reset-names = "i2c"; 909a4131561SThierry Reding pinctrl-0 = <&state_dpaux3_i2c>; 910a4131561SThierry Reding pinctrl-1 = <&state_dpaux3_off>; 911a4131561SThierry Reding pinctrl-names = "default", "idle"; 9128e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 9138e442805SAkhil R dma-names = "rx", "tx"; 9145425fb15SMikko Perttunen status = "disabled"; 9155425fb15SMikko Perttunen }; 9165425fb15SMikko Perttunen 91796ded827SSowjanya Komatineni spi@3270000 { 91896ded827SSowjanya Komatineni compatible = "nvidia,tegra194-qspi"; 9192838cfddSThierry Reding reg = <0x0 0x3270000 0x0 0x1000>; 92096ded827SSowjanya Komatineni interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 92196ded827SSowjanya Komatineni #address-cells = <1>; 92296ded827SSowjanya Komatineni #size-cells = <0>; 92396ded827SSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_QSPI0>, 92496ded827SSowjanya Komatineni <&bpmp TEGRA194_CLK_QSPI0_PM>; 92596ded827SSowjanya Komatineni clock-names = "qspi", "qspi_out"; 92696ded827SSowjanya Komatineni resets = <&bpmp TEGRA194_RESET_QSPI0>; 92796ded827SSowjanya Komatineni status = "disabled"; 92896ded827SSowjanya Komatineni }; 92996ded827SSowjanya Komatineni 9306a574ec7SThierry Reding pwm1: pwm@3280000 { 9316a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9326a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9332838cfddSThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 9346a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM1>; 9356a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM1>; 9366a574ec7SThierry Reding reset-names = "pwm"; 9376a574ec7SThierry Reding status = "disabled"; 9386a574ec7SThierry Reding #pwm-cells = <2>; 9396a574ec7SThierry Reding }; 9406a574ec7SThierry Reding 9416a574ec7SThierry Reding pwm2: pwm@3290000 { 9426a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9436a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9442838cfddSThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 9456a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM2>; 9466a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM2>; 9476a574ec7SThierry Reding reset-names = "pwm"; 9486a574ec7SThierry Reding status = "disabled"; 9496a574ec7SThierry Reding #pwm-cells = <2>; 9506a574ec7SThierry Reding }; 9516a574ec7SThierry Reding 9526a574ec7SThierry Reding pwm3: pwm@32a0000 { 9536a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9546a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9552838cfddSThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 9566a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM3>; 9576a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM3>; 9586a574ec7SThierry Reding reset-names = "pwm"; 9596a574ec7SThierry Reding status = "disabled"; 9606a574ec7SThierry Reding #pwm-cells = <2>; 9616a574ec7SThierry Reding }; 9626a574ec7SThierry Reding 9636a574ec7SThierry Reding pwm5: pwm@32c0000 { 9646a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9656a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9662838cfddSThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 9676a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM5>; 9686a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM5>; 9696a574ec7SThierry Reding reset-names = "pwm"; 9706a574ec7SThierry Reding status = "disabled"; 9716a574ec7SThierry Reding #pwm-cells = <2>; 9726a574ec7SThierry Reding }; 9736a574ec7SThierry Reding 9746a574ec7SThierry Reding pwm6: pwm@32d0000 { 9756a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9766a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9772838cfddSThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 9786a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM6>; 9796a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM6>; 9806a574ec7SThierry Reding reset-names = "pwm"; 9816a574ec7SThierry Reding status = "disabled"; 9826a574ec7SThierry Reding #pwm-cells = <2>; 9836a574ec7SThierry Reding }; 9846a574ec7SThierry Reding 9856a574ec7SThierry Reding pwm7: pwm@32e0000 { 9866a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9876a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9882838cfddSThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 9896a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM7>; 9906a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM7>; 9916a574ec7SThierry Reding reset-names = "pwm"; 9926a574ec7SThierry Reding status = "disabled"; 9936a574ec7SThierry Reding #pwm-cells = <2>; 9946a574ec7SThierry Reding }; 9956a574ec7SThierry Reding 9966a574ec7SThierry Reding pwm8: pwm@32f0000 { 9976a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 9986a574ec7SThierry Reding "nvidia,tegra186-pwm"; 9992838cfddSThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 10006a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM8>; 10016a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM8>; 10026a574ec7SThierry Reding reset-names = "pwm"; 10036a574ec7SThierry Reding status = "disabled"; 10046a574ec7SThierry Reding #pwm-cells = <2>; 10056a574ec7SThierry Reding }; 10066a574ec7SThierry Reding 100779ed18d9SThierry Reding spi@3300000 { 100879ed18d9SThierry Reding compatible = "nvidia,tegra194-qspi"; 100979ed18d9SThierry Reding reg = <0x0 0x3300000 0x0 0x1000>; 101079ed18d9SThierry Reding interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 101179ed18d9SThierry Reding #address-cells = <1>; 101279ed18d9SThierry Reding #size-cells = <0>; 101379ed18d9SThierry Reding clocks = <&bpmp TEGRA194_CLK_QSPI1>, 101479ed18d9SThierry Reding <&bpmp TEGRA194_CLK_QSPI1_PM>; 101579ed18d9SThierry Reding clock-names = "qspi", "qspi_out"; 101679ed18d9SThierry Reding resets = <&bpmp TEGRA194_RESET_QSPI1>; 101779ed18d9SThierry Reding status = "disabled"; 101879ed18d9SThierry Reding }; 101979ed18d9SThierry Reding 102067bb17f6SThierry Reding sdmmc1: mmc@3400000 { 10212c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10222838cfddSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 10235425fb15SMikko Perttunen interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1024c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1025c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1026c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10277ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 10287ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10297ac853baSAniruddha Rao assigned-clock-parents = 10307ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10317ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10325425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC1>; 10335425fb15SMikko Perttunen reset-names = "sdhci"; 1034d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1035d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1036d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1037c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC1>; 1038ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1039ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc1_3v3>; 1040ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc1_1v8>; 10414e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = 10424e0f1229SSowjanya Komatineni <0x07>; 10434e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10444e0f1229SSowjanya Komatineni <0x07>; 10454e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10464e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10474e0f1229SSowjanya Komatineni <0x07>; 10484e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10494e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10504e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10514e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1052ff21087eSPrathamesh Shete sd-uhs-sdr25; 1053ff21087eSPrathamesh Shete sd-uhs-sdr50; 1054ff21087eSPrathamesh Shete sd-uhs-ddr50; 1055ff21087eSPrathamesh Shete sd-uhs-sdr104; 10565425fb15SMikko Perttunen status = "disabled"; 10575425fb15SMikko Perttunen }; 10585425fb15SMikko Perttunen 105967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 10602c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 10612838cfddSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 10625425fb15SMikko Perttunen interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1063c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1064c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1065c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 10667ac853baSAniruddha Rao assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 10677ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 10687ac853baSAniruddha Rao assigned-clock-parents = 10697ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 10707ac853baSAniruddha Rao <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 10715425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC3>; 10725425fb15SMikko Perttunen reset-names = "sdhci"; 1073d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1074d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1075d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1076c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC3>; 1077ff21087eSPrathamesh Shete pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1078ff21087eSPrathamesh Shete pinctrl-0 = <&sdmmc3_3v3>; 1079ff21087eSPrathamesh Shete pinctrl-1 = <&sdmmc3_1v8>; 10804e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 10814e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 10824e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 10834e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 10844e0f1229SSowjanya Komatineni <0x07>; 10854e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 10864e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 10874e0f1229SSowjanya Komatineni <0x07>; 10884e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 10894e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 10904e0f1229SSowjanya Komatineni nvidia,default-tap = <0x9>; 10914e0f1229SSowjanya Komatineni nvidia,default-trim = <0x5>; 1092ff21087eSPrathamesh Shete sd-uhs-sdr25; 1093ff21087eSPrathamesh Shete sd-uhs-sdr50; 1094ff21087eSPrathamesh Shete sd-uhs-ddr50; 1095ff21087eSPrathamesh Shete sd-uhs-sdr104; 10965425fb15SMikko Perttunen status = "disabled"; 10975425fb15SMikko Perttunen }; 10985425fb15SMikko Perttunen 109967bb17f6SThierry Reding sdmmc4: mmc@3460000 { 11002c3578b3SThierry Reding compatible = "nvidia,tegra194-sdhci"; 11012838cfddSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 11025425fb15SMikko Perttunen interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1103c956c0cdSSowjanya Komatineni clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1104c956c0cdSSowjanya Komatineni <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1105c956c0cdSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 1106351648d0SSowjanya Komatineni assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1107351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 1108351648d0SSowjanya Komatineni assigned-clock-parents = 1109351648d0SSowjanya Komatineni <&bpmp TEGRA194_CLK_PLLC4>; 11105425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_SDMMC4>; 11115425fb15SMikko Perttunen reset-names = "sdhci"; 1112d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1113d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1114d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1115c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_SDMMC4>; 11164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 11174e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 11184e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 11194e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-1v8-timeout = 11204e0f1229SSowjanya Komatineni <0x0a>; 11214e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 11224e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = 11234e0f1229SSowjanya Komatineni <0x0a>; 11244e0f1229SSowjanya Komatineni nvidia,default-tap = <0x8>; 11254e0f1229SSowjanya Komatineni nvidia,default-trim = <0x14>; 11264e0f1229SSowjanya Komatineni nvidia,dqs-trim = <40>; 1127c2fee443SPrathamesh Shete cap-mmc-highspeed; 1128c2fee443SPrathamesh Shete mmc-ddr-1_8v; 1129c2fee443SPrathamesh Shete mmc-hs200-1_8v; 1130c2fee443SPrathamesh Shete mmc-hs400-1_8v; 1131c2fee443SPrathamesh Shete mmc-hs400-enhanced-strobe; 1132dfd3cb6fSSowjanya Komatineni supports-cqe; 11335425fb15SMikko Perttunen status = "disabled"; 11345425fb15SMikko Perttunen }; 11355425fb15SMikko Perttunen 11364878cc0cSSameer Pujar hda@3510000 { 11377f0ea5acSThierry Reding compatible = "nvidia,tegra194-hda"; 11382838cfddSThierry Reding reg = <0x0 0x3510000 0x0 0x10000>; 11394878cc0cSSameer Pujar interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 11404878cc0cSSameer Pujar clocks = <&bpmp TEGRA194_CLK_HDA>, 114148f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 114248f6e195SSameer Pujar <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 114348f6e195SSameer Pujar clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 11444878cc0cSSameer Pujar resets = <&bpmp TEGRA194_RESET_HDA>, 1145146b3a77SSameer Pujar <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1146146b3a77SSameer Pujar reset-names = "hda", "hda2hdmi"; 11474878cc0cSSameer Pujar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1148d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1149d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1150d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 1151c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HDA>; 11524878cc0cSSameer Pujar status = "disabled"; 11534878cc0cSSameer Pujar }; 11544878cc0cSSameer Pujar 1155fab7a039SJC Kuo xusb_padctl: padctl@3520000 { 1156fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb-padctl"; 11572838cfddSThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 11582838cfddSThierry Reding <0x0 0x03540000 0x0 0x1000>; 1159fab7a039SJC Kuo reg-names = "padctl", "ao"; 11606450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1161fab7a039SJC Kuo 1162fab7a039SJC Kuo resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1163fab7a039SJC Kuo reset-names = "padctl"; 1164fab7a039SJC Kuo 1165fab7a039SJC Kuo status = "disabled"; 1166fab7a039SJC Kuo 1167fab7a039SJC Kuo pads { 1168fab7a039SJC Kuo usb2 { 1169fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1170fab7a039SJC Kuo clock-names = "trk"; 1171fab7a039SJC Kuo 1172fab7a039SJC Kuo lanes { 1173fab7a039SJC Kuo usb2-0 { 1174fab7a039SJC Kuo nvidia,function = "xusb"; 1175fab7a039SJC Kuo status = "disabled"; 1176fab7a039SJC Kuo #phy-cells = <0>; 1177fab7a039SJC Kuo }; 1178fab7a039SJC Kuo 1179fab7a039SJC Kuo usb2-1 { 1180fab7a039SJC Kuo nvidia,function = "xusb"; 1181fab7a039SJC Kuo status = "disabled"; 1182fab7a039SJC Kuo #phy-cells = <0>; 1183fab7a039SJC Kuo }; 1184fab7a039SJC Kuo 1185fab7a039SJC Kuo usb2-2 { 1186fab7a039SJC Kuo nvidia,function = "xusb"; 1187fab7a039SJC Kuo status = "disabled"; 1188fab7a039SJC Kuo #phy-cells = <0>; 1189fab7a039SJC Kuo }; 1190fab7a039SJC Kuo 1191fab7a039SJC Kuo usb2-3 { 1192fab7a039SJC Kuo nvidia,function = "xusb"; 1193fab7a039SJC Kuo status = "disabled"; 1194fab7a039SJC Kuo #phy-cells = <0>; 1195fab7a039SJC Kuo }; 1196fab7a039SJC Kuo }; 1197fab7a039SJC Kuo }; 1198fab7a039SJC Kuo 1199fab7a039SJC Kuo usb3 { 1200fab7a039SJC Kuo lanes { 1201fab7a039SJC Kuo usb3-0 { 1202fab7a039SJC Kuo nvidia,function = "xusb"; 1203fab7a039SJC Kuo status = "disabled"; 1204fab7a039SJC Kuo #phy-cells = <0>; 1205fab7a039SJC Kuo }; 1206fab7a039SJC Kuo 1207fab7a039SJC Kuo usb3-1 { 1208fab7a039SJC Kuo nvidia,function = "xusb"; 1209fab7a039SJC Kuo status = "disabled"; 1210fab7a039SJC Kuo #phy-cells = <0>; 1211fab7a039SJC Kuo }; 1212fab7a039SJC Kuo 1213fab7a039SJC Kuo usb3-2 { 1214fab7a039SJC Kuo nvidia,function = "xusb"; 1215fab7a039SJC Kuo status = "disabled"; 1216fab7a039SJC Kuo #phy-cells = <0>; 1217fab7a039SJC Kuo }; 1218fab7a039SJC Kuo 1219fab7a039SJC Kuo usb3-3 { 1220fab7a039SJC Kuo nvidia,function = "xusb"; 1221fab7a039SJC Kuo status = "disabled"; 1222fab7a039SJC Kuo #phy-cells = <0>; 1223fab7a039SJC Kuo }; 1224fab7a039SJC Kuo }; 1225fab7a039SJC Kuo }; 1226fab7a039SJC Kuo }; 1227fab7a039SJC Kuo 1228fab7a039SJC Kuo ports { 1229fab7a039SJC Kuo usb2-0 { 1230fab7a039SJC Kuo status = "disabled"; 1231fab7a039SJC Kuo }; 1232fab7a039SJC Kuo 1233fab7a039SJC Kuo usb2-1 { 1234fab7a039SJC Kuo status = "disabled"; 1235fab7a039SJC Kuo }; 1236fab7a039SJC Kuo 1237fab7a039SJC Kuo usb2-2 { 1238fab7a039SJC Kuo status = "disabled"; 1239fab7a039SJC Kuo }; 1240fab7a039SJC Kuo 1241fab7a039SJC Kuo usb2-3 { 1242fab7a039SJC Kuo status = "disabled"; 1243fab7a039SJC Kuo }; 1244fab7a039SJC Kuo 1245fab7a039SJC Kuo usb3-0 { 1246fab7a039SJC Kuo status = "disabled"; 1247fab7a039SJC Kuo }; 1248fab7a039SJC Kuo 1249fab7a039SJC Kuo usb3-1 { 1250fab7a039SJC Kuo status = "disabled"; 1251fab7a039SJC Kuo }; 1252fab7a039SJC Kuo 1253fab7a039SJC Kuo usb3-2 { 1254fab7a039SJC Kuo status = "disabled"; 1255fab7a039SJC Kuo }; 1256fab7a039SJC Kuo 1257fab7a039SJC Kuo usb3-3 { 1258fab7a039SJC Kuo status = "disabled"; 1259fab7a039SJC Kuo }; 1260fab7a039SJC Kuo }; 1261fab7a039SJC Kuo }; 1262fab7a039SJC Kuo 1263bc8788b2SNagarjuna Kristam usb@3550000 { 1264bc8788b2SNagarjuna Kristam compatible = "nvidia,tegra194-xudc"; 12652838cfddSThierry Reding reg = <0x0 0x03550000 0x0 0x8000>, 12662838cfddSThierry Reding <0x0 0x03558000 0x0 0x1000>; 1267bc8788b2SNagarjuna Kristam reg-names = "base", "fpci"; 1268bc8788b2SNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1269bc8788b2SNagarjuna Kristam clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1270bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1271bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_SS>, 1272bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_CLK_XUSB_FS>; 1273bc8788b2SNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1274c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1275c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1276c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1277c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1278bc8788b2SNagarjuna Kristam power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1279bc8788b2SNagarjuna Kristam <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1280bc8788b2SNagarjuna Kristam power-domain-names = "dev", "ss"; 1281bc8788b2SNagarjuna Kristam nvidia,xusb-padctl = <&xusb_padctl>; 1282f19bb95dSJon Hunter dma-coherent; 1283bc8788b2SNagarjuna Kristam status = "disabled"; 1284bc8788b2SNagarjuna Kristam }; 1285bc8788b2SNagarjuna Kristam 1286fab7a039SJC Kuo usb@3610000 { 1287fab7a039SJC Kuo compatible = "nvidia,tegra194-xusb"; 12882838cfddSThierry Reding reg = <0x0 0x03610000 0x0 0x40000>, 12892838cfddSThierry Reding <0x0 0x03600000 0x0 0x10000>; 1290fab7a039SJC Kuo reg-names = "hcd", "fpci"; 1291fab7a039SJC Kuo 1292fab7a039SJC Kuo interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1293a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1294fab7a039SJC Kuo 1295fab7a039SJC Kuo clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1296fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1297fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1298fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_SS>, 1299fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1300fab7a039SJC Kuo <&bpmp TEGRA194_CLK_XUSB_FS>, 1301fab7a039SJC Kuo <&bpmp TEGRA194_CLK_UTMIPLL>, 1302fab7a039SJC Kuo <&bpmp TEGRA194_CLK_CLK_M>, 1303fab7a039SJC Kuo <&bpmp TEGRA194_CLK_PLLE>; 1304fab7a039SJC Kuo clock-names = "xusb_host", "xusb_falcon_src", 1305fab7a039SJC Kuo "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1306fab7a039SJC Kuo "xusb_fs_src", "pll_u_480m", "clk_m", 1307fab7a039SJC Kuo "pll_e"; 1308c667dcd4SThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1309c667dcd4SThierry Reding <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1310c667dcd4SThierry Reding interconnect-names = "dma-mem", "write"; 1311c667dcd4SThierry Reding iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1312fab7a039SJC Kuo 1313fab7a039SJC Kuo power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1314fab7a039SJC Kuo <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1315fab7a039SJC Kuo power-domain-names = "xusb_host", "xusb_ss"; 1316fab7a039SJC Kuo 1317fab7a039SJC Kuo nvidia,xusb-padctl = <&xusb_padctl>; 1318fab7a039SJC Kuo status = "disabled"; 1319fab7a039SJC Kuo }; 1320fab7a039SJC Kuo 132109903c5eSJC Kuo fuse@3820000 { 132209903c5eSJC Kuo compatible = "nvidia,tegra194-efuse"; 13232838cfddSThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 132409903c5eSJC Kuo clocks = <&bpmp TEGRA194_CLK_FUSE>; 132509903c5eSJC Kuo clock-names = "fuse"; 132609903c5eSJC Kuo }; 132709903c5eSJC Kuo 13285425fb15SMikko Perttunen gic: interrupt-controller@3881000 { 13295425fb15SMikko Perttunen compatible = "arm,gic-400"; 13305425fb15SMikko Perttunen #interrupt-cells = <3>; 13315425fb15SMikko Perttunen interrupt-controller; 13322838cfddSThierry Reding reg = <0x0 0x03881000 0x0 0x1000>, 13332838cfddSThierry Reding <0x0 0x03882000 0x0 0x2000>, 13342838cfddSThierry Reding <0x0 0x03884000 0x0 0x2000>, 13352838cfddSThierry Reding <0x0 0x03886000 0x0 0x2000>; 13365425fb15SMikko Perttunen interrupts = <GIC_PPI 9 13375425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 13385425fb15SMikko Perttunen interrupt-parent = <&gic>; 13395425fb15SMikko Perttunen }; 13405425fb15SMikko Perttunen 1341badb80beSThierry Reding cec@3960000 { 1342badb80beSThierry Reding compatible = "nvidia,tegra194-cec"; 13432838cfddSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 1344badb80beSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1345badb80beSThierry Reding clocks = <&bpmp TEGRA194_CLK_CEC>; 1346badb80beSThierry Reding clock-names = "cec"; 1347badb80beSThierry Reding status = "disabled"; 1348badb80beSThierry Reding }; 1349badb80beSThierry Reding 13508fbd2d11SDipen Patel hte_lic: hardware-timestamp@3aa0000 { 13518fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-lic"; 13522838cfddSThierry Reding reg = <0x0 0x3aa0000 0x0 0x10000>; 13538fbd2d11SDipen Patel interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 13548fbd2d11SDipen Patel nvidia,int-threshold = <1>; 13558fbd2d11SDipen Patel nvidia,slices = <11>; 13568fbd2d11SDipen Patel #timestamp-cells = <1>; 13578fbd2d11SDipen Patel status = "okay"; 13588fbd2d11SDipen Patel }; 13598fbd2d11SDipen Patel 13605425fb15SMikko Perttunen hsp_top0: hsp@3c00000 { 1361cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 13622838cfddSThierry Reding reg = <0x0 0x03c00000 0x0 0xa0000>; 1363a38570c2SMikko Perttunen interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1364a38570c2SMikko Perttunen <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1365a38570c2SMikko Perttunen <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1366a38570c2SMikko Perttunen <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1367a38570c2SMikko Perttunen <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1368a38570c2SMikko Perttunen <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1369a38570c2SMikko Perttunen <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1370a38570c2SMikko Perttunen <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1371a38570c2SMikko Perttunen <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1372a38570c2SMikko Perttunen interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1373a38570c2SMikko Perttunen "shared3", "shared4", "shared5", "shared6", 1374a38570c2SMikko Perttunen "shared7"; 1375a38570c2SMikko Perttunen #mbox-cells = <2>; 1376a38570c2SMikko Perttunen }; 1377a38570c2SMikko Perttunen 13782602c32fSVidya Sagar p2u_hsio_0: phy@3e10000 { 13792602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13802838cfddSThierry Reding reg = <0x0 0x03e10000 0x0 0x10000>; 13812602c32fSVidya Sagar reg-names = "ctl"; 13822602c32fSVidya Sagar 13832602c32fSVidya Sagar #phy-cells = <0>; 13842602c32fSVidya Sagar }; 13852602c32fSVidya Sagar 13862602c32fSVidya Sagar p2u_hsio_1: phy@3e20000 { 13872602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13882838cfddSThierry Reding reg = <0x0 0x03e20000 0x0 0x10000>; 13892602c32fSVidya Sagar reg-names = "ctl"; 13902602c32fSVidya Sagar 13912602c32fSVidya Sagar #phy-cells = <0>; 13922602c32fSVidya Sagar }; 13932602c32fSVidya Sagar 13942602c32fSVidya Sagar p2u_hsio_2: phy@3e30000 { 13952602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 13962838cfddSThierry Reding reg = <0x0 0x03e30000 0x0 0x10000>; 13972602c32fSVidya Sagar reg-names = "ctl"; 13982602c32fSVidya Sagar 13992602c32fSVidya Sagar #phy-cells = <0>; 14002602c32fSVidya Sagar }; 14012602c32fSVidya Sagar 14022602c32fSVidya Sagar p2u_hsio_3: phy@3e40000 { 14032602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14042838cfddSThierry Reding reg = <0x0 0x03e40000 0x0 0x10000>; 14052602c32fSVidya Sagar reg-names = "ctl"; 14062602c32fSVidya Sagar 14072602c32fSVidya Sagar #phy-cells = <0>; 14082602c32fSVidya Sagar }; 14092602c32fSVidya Sagar 14102602c32fSVidya Sagar p2u_hsio_4: phy@3e50000 { 14112602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14122838cfddSThierry Reding reg = <0x0 0x03e50000 0x0 0x10000>; 14132602c32fSVidya Sagar reg-names = "ctl"; 14142602c32fSVidya Sagar 14152602c32fSVidya Sagar #phy-cells = <0>; 14162602c32fSVidya Sagar }; 14172602c32fSVidya Sagar 14182602c32fSVidya Sagar p2u_hsio_5: phy@3e60000 { 14192602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14202838cfddSThierry Reding reg = <0x0 0x03e60000 0x0 0x10000>; 14212602c32fSVidya Sagar reg-names = "ctl"; 14222602c32fSVidya Sagar 14232602c32fSVidya Sagar #phy-cells = <0>; 14242602c32fSVidya Sagar }; 14252602c32fSVidya Sagar 14262602c32fSVidya Sagar p2u_hsio_6: phy@3e70000 { 14272602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14282838cfddSThierry Reding reg = <0x0 0x03e70000 0x0 0x10000>; 14292602c32fSVidya Sagar reg-names = "ctl"; 14302602c32fSVidya Sagar 14312602c32fSVidya Sagar #phy-cells = <0>; 14322602c32fSVidya Sagar }; 14332602c32fSVidya Sagar 14342602c32fSVidya Sagar p2u_hsio_7: phy@3e80000 { 14352602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14362838cfddSThierry Reding reg = <0x0 0x03e80000 0x0 0x10000>; 14372602c32fSVidya Sagar reg-names = "ctl"; 14382602c32fSVidya Sagar 14392602c32fSVidya Sagar #phy-cells = <0>; 14402602c32fSVidya Sagar }; 14412602c32fSVidya Sagar 14422602c32fSVidya Sagar p2u_hsio_8: phy@3e90000 { 14432602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14442838cfddSThierry Reding reg = <0x0 0x03e90000 0x0 0x10000>; 14452602c32fSVidya Sagar reg-names = "ctl"; 14462602c32fSVidya Sagar 14472602c32fSVidya Sagar #phy-cells = <0>; 14482602c32fSVidya Sagar }; 14492602c32fSVidya Sagar 14502602c32fSVidya Sagar p2u_hsio_9: phy@3ea0000 { 14512602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14522838cfddSThierry Reding reg = <0x0 0x03ea0000 0x0 0x10000>; 14532602c32fSVidya Sagar reg-names = "ctl"; 14542602c32fSVidya Sagar 14552602c32fSVidya Sagar #phy-cells = <0>; 14562602c32fSVidya Sagar }; 14572602c32fSVidya Sagar 14582602c32fSVidya Sagar p2u_nvhs_0: phy@3eb0000 { 14592602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14602838cfddSThierry Reding reg = <0x0 0x03eb0000 0x0 0x10000>; 14612602c32fSVidya Sagar reg-names = "ctl"; 14622602c32fSVidya Sagar 14632602c32fSVidya Sagar #phy-cells = <0>; 14642602c32fSVidya Sagar }; 14652602c32fSVidya Sagar 14662602c32fSVidya Sagar p2u_nvhs_1: phy@3ec0000 { 14672602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14682838cfddSThierry Reding reg = <0x0 0x03ec0000 0x0 0x10000>; 14692602c32fSVidya Sagar reg-names = "ctl"; 14702602c32fSVidya Sagar 14712602c32fSVidya Sagar #phy-cells = <0>; 14722602c32fSVidya Sagar }; 14732602c32fSVidya Sagar 14742602c32fSVidya Sagar p2u_nvhs_2: phy@3ed0000 { 14752602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14762838cfddSThierry Reding reg = <0x0 0x03ed0000 0x0 0x10000>; 14772602c32fSVidya Sagar reg-names = "ctl"; 14782602c32fSVidya Sagar 14792602c32fSVidya Sagar #phy-cells = <0>; 14802602c32fSVidya Sagar }; 14812602c32fSVidya Sagar 14822602c32fSVidya Sagar p2u_nvhs_3: phy@3ee0000 { 14832602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14842838cfddSThierry Reding reg = <0x0 0x03ee0000 0x0 0x10000>; 14852602c32fSVidya Sagar reg-names = "ctl"; 14862602c32fSVidya Sagar 14872602c32fSVidya Sagar #phy-cells = <0>; 14882602c32fSVidya Sagar }; 14892602c32fSVidya Sagar 14902602c32fSVidya Sagar p2u_nvhs_4: phy@3ef0000 { 14912602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 14922838cfddSThierry Reding reg = <0x0 0x03ef0000 0x0 0x10000>; 14932602c32fSVidya Sagar reg-names = "ctl"; 14942602c32fSVidya Sagar 14952602c32fSVidya Sagar #phy-cells = <0>; 14962602c32fSVidya Sagar }; 14972602c32fSVidya Sagar 14982602c32fSVidya Sagar p2u_nvhs_5: phy@3f00000 { 14992602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15002838cfddSThierry Reding reg = <0x0 0x03f00000 0x0 0x10000>; 15012602c32fSVidya Sagar reg-names = "ctl"; 15022602c32fSVidya Sagar 15032602c32fSVidya Sagar #phy-cells = <0>; 15042602c32fSVidya Sagar }; 15052602c32fSVidya Sagar 15062602c32fSVidya Sagar p2u_nvhs_6: phy@3f10000 { 15072602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15082838cfddSThierry Reding reg = <0x0 0x03f10000 0x0 0x10000>; 15092602c32fSVidya Sagar reg-names = "ctl"; 15102602c32fSVidya Sagar 15112602c32fSVidya Sagar #phy-cells = <0>; 15122602c32fSVidya Sagar }; 15132602c32fSVidya Sagar 15142602c32fSVidya Sagar p2u_nvhs_7: phy@3f20000 { 15152602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15162838cfddSThierry Reding reg = <0x0 0x03f20000 0x0 0x10000>; 15172602c32fSVidya Sagar reg-names = "ctl"; 15182602c32fSVidya Sagar 15192602c32fSVidya Sagar #phy-cells = <0>; 15202602c32fSVidya Sagar }; 15212602c32fSVidya Sagar 15222602c32fSVidya Sagar p2u_hsio_10: phy@3f30000 { 15232602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15242838cfddSThierry Reding reg = <0x0 0x03f30000 0x0 0x10000>; 15252602c32fSVidya Sagar reg-names = "ctl"; 15262602c32fSVidya Sagar 15272602c32fSVidya Sagar #phy-cells = <0>; 15282602c32fSVidya Sagar }; 15292602c32fSVidya Sagar 15302602c32fSVidya Sagar p2u_hsio_11: phy@3f40000 { 15312602c32fSVidya Sagar compatible = "nvidia,tegra194-p2u"; 15322838cfddSThierry Reding reg = <0x0 0x03f40000 0x0 0x10000>; 15332602c32fSVidya Sagar reg-names = "ctl"; 15342602c32fSVidya Sagar 15352602c32fSVidya Sagar #phy-cells = <0>; 15362602c32fSVidya Sagar }; 15372602c32fSVidya Sagar 1538a47e173eSSumit Gupta sce-noc@b600000 { 1539a47e173eSSumit Gupta compatible = "nvidia,tegra194-sce-noc"; 15402838cfddSThierry Reding reg = <0x0 0xb600000 0x0 0x1000>; 1541a47e173eSSumit Gupta interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1542a47e173eSSumit Gupta <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1543a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1544a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1545a47e173eSSumit Gupta status = "okay"; 1546a47e173eSSumit Gupta }; 1547a47e173eSSumit Gupta 1548a47e173eSSumit Gupta rce-noc@be00000 { 1549a47e173eSSumit Gupta compatible = "nvidia,tegra194-rce-noc"; 15502838cfddSThierry Reding reg = <0x0 0xbe00000 0x0 0x1000>; 1551a47e173eSSumit Gupta interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1552a47e173eSSumit Gupta <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1553a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1554a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1555a47e173eSSumit Gupta status = "okay"; 1556a47e173eSSumit Gupta }; 1557a47e173eSSumit Gupta 1558a38570c2SMikko Perttunen hsp_aon: hsp@c150000 { 1559cd6157c1SThierry Reding compatible = "nvidia,tegra194-hsp"; 15602838cfddSThierry Reding reg = <0x0 0x0c150000 0x0 0x90000>; 1561a38570c2SMikko Perttunen interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1562a38570c2SMikko Perttunen <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1563a38570c2SMikko Perttunen <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1564a38570c2SMikko Perttunen <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1565a38570c2SMikko Perttunen /* 1566a38570c2SMikko Perttunen * Shared interrupt 0 is routed only to AON/SPE, so 1567a38570c2SMikko Perttunen * we only have 4 shared interrupts for the CCPLEX. 1568a38570c2SMikko Perttunen */ 1569a38570c2SMikko Perttunen interrupt-names = "shared1", "shared2", "shared3", "shared4"; 15705425fb15SMikko Perttunen #mbox-cells = <2>; 15715425fb15SMikko Perttunen }; 15725425fb15SMikko Perttunen 15738fbd2d11SDipen Patel hte_aon: hardware-timestamp@c1e0000 { 15748fbd2d11SDipen Patel compatible = "nvidia,tegra194-gte-aon"; 15752838cfddSThierry Reding reg = <0x0 0xc1e0000 0x0 0x10000>; 15768fbd2d11SDipen Patel interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 15778fbd2d11SDipen Patel nvidia,int-threshold = <1>; 15788fbd2d11SDipen Patel nvidia,slices = <3>; 15798fbd2d11SDipen Patel #timestamp-cells = <1>; 15808fbd2d11SDipen Patel status = "okay"; 15818fbd2d11SDipen Patel }; 15828fbd2d11SDipen Patel 15835425fb15SMikko Perttunen gen2_i2c: i2c@c240000 { 1584d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 15852838cfddSThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 15865425fb15SMikko Perttunen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 15875425fb15SMikko Perttunen #address-cells = <1>; 15885425fb15SMikko Perttunen #size-cells = <0>; 15895425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C2>; 15905425fb15SMikko Perttunen clock-names = "div-clk"; 15915425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C2>; 15925425fb15SMikko Perttunen reset-names = "i2c"; 15938e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 15948e442805SAkhil R dma-names = "rx", "tx"; 15955425fb15SMikko Perttunen status = "disabled"; 15965425fb15SMikko Perttunen }; 15975425fb15SMikko Perttunen 15985425fb15SMikko Perttunen gen8_i2c: i2c@c250000 { 1599d9fd2244SThierry Reding compatible = "nvidia,tegra194-i2c"; 16002838cfddSThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 16015425fb15SMikko Perttunen interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 16025425fb15SMikko Perttunen #address-cells = <1>; 16035425fb15SMikko Perttunen #size-cells = <0>; 16045425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_I2C8>; 16055425fb15SMikko Perttunen clock-names = "div-clk"; 16065425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_I2C8>; 16075425fb15SMikko Perttunen reset-names = "i2c"; 16088e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 16098e442805SAkhil R dma-names = "rx", "tx"; 16105425fb15SMikko Perttunen status = "disabled"; 16115425fb15SMikko Perttunen }; 16125425fb15SMikko Perttunen 16135425fb15SMikko Perttunen uartc: serial@c280000 { 16145425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16152838cfddSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 16165425fb15SMikko Perttunen reg-shift = <2>; 16175425fb15SMikko Perttunen interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 16185425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTC>; 16195425fb15SMikko Perttunen clock-names = "serial"; 16205425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTC>; 16215425fb15SMikko Perttunen reset-names = "serial"; 16225425fb15SMikko Perttunen status = "disabled"; 16235425fb15SMikko Perttunen }; 16245425fb15SMikko Perttunen 16255425fb15SMikko Perttunen uartg: serial@c290000 { 16265425fb15SMikko Perttunen compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 16272838cfddSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 16285425fb15SMikko Perttunen reg-shift = <2>; 16295425fb15SMikko Perttunen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 16305425fb15SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_UARTG>; 16315425fb15SMikko Perttunen clock-names = "serial"; 16325425fb15SMikko Perttunen resets = <&bpmp TEGRA194_RESET_UARTG>; 16335425fb15SMikko Perttunen reset-names = "serial"; 16345425fb15SMikko Perttunen status = "disabled"; 16355425fb15SMikko Perttunen }; 16365425fb15SMikko Perttunen 163737e5a31dSThierry Reding rtc: rtc@c2a0000 { 163837e5a31dSThierry Reding compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 16392838cfddSThierry Reding reg = <0x0 0x0c2a0000 0x0 0x10000>; 164037e5a31dSThierry Reding interrupt-parent = <&pmc>; 164137e5a31dSThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 164237e5a31dSThierry Reding clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 164337e5a31dSThierry Reding clock-names = "rtc"; 164437e5a31dSThierry Reding status = "disabled"; 164537e5a31dSThierry Reding }; 164637e5a31dSThierry Reding 16474d286331SThierry Reding gpio_aon: gpio@c2f0000 { 16484d286331SThierry Reding compatible = "nvidia,tegra194-gpio-aon"; 16494d286331SThierry Reding reg-names = "security", "gpio"; 16502838cfddSThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 16512838cfddSThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 16520a85cf28Spshete interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 16530a85cf28Spshete <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 16540a85cf28Spshete <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 16550a85cf28Spshete <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 16564d286331SThierry Reding gpio-controller; 16574d286331SThierry Reding #gpio-cells = <2>; 16584d286331SThierry Reding interrupt-controller; 16594d286331SThierry Reding #interrupt-cells = <2>; 1660979ac5efSThierry Reding gpio-ranges = <&pinmux_aon 0 0 30>; 16616f380a4eSThierry Reding }; 16626f380a4eSThierry Reding 16636f380a4eSThierry Reding pinmux_aon: pinmux@c300000 { 16646f380a4eSThierry Reding compatible = "nvidia,tegra194-pinmux-aon"; 16652838cfddSThierry Reding reg = <0x0 0xc300000 0x0 0x4000>; 16666f380a4eSThierry Reding 16676f380a4eSThierry Reding status = "okay"; 16684d286331SThierry Reding }; 16694d286331SThierry Reding 16706a574ec7SThierry Reding pwm4: pwm@c340000 { 16716a574ec7SThierry Reding compatible = "nvidia,tegra194-pwm", 16726a574ec7SThierry Reding "nvidia,tegra186-pwm"; 16732838cfddSThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 16746a574ec7SThierry Reding clocks = <&bpmp TEGRA194_CLK_PWM4>; 16756a574ec7SThierry Reding resets = <&bpmp TEGRA194_RESET_PWM4>; 16766a574ec7SThierry Reding reset-names = "pwm"; 16776a574ec7SThierry Reding status = "disabled"; 16786a574ec7SThierry Reding #pwm-cells = <2>; 16796a574ec7SThierry Reding }; 16806a574ec7SThierry Reding 168138ecf1e5SThierry Reding pmc: pmc@c360000 { 16825425fb15SMikko Perttunen compatible = "nvidia,tegra194-pmc"; 16832838cfddSThierry Reding reg = <0x0 0x0c360000 0x0 0x10000>, 16842838cfddSThierry Reding <0x0 0x0c370000 0x0 0x10000>, 16852838cfddSThierry Reding <0x0 0x0c380000 0x0 0x10000>, 16862838cfddSThierry Reding <0x0 0x0c390000 0x0 0x10000>, 16872838cfddSThierry Reding <0x0 0x0c3a0000 0x0 0x10000>; 16885425fb15SMikko Perttunen reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 168938ecf1e5SThierry Reding 169038ecf1e5SThierry Reding #interrupt-cells = <2>; 169138ecf1e5SThierry Reding interrupt-controller; 1692ff21087eSPrathamesh Shete 1693ff21087eSPrathamesh Shete sdmmc1_1v8: sdmmc1-1v8 { 1694ff21087eSPrathamesh Shete pins = "sdmmc1-hv"; 1695ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1696ff21087eSPrathamesh Shete }; 169779ed18d9SThierry Reding 169879ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 169979ed18d9SThierry Reding pins = "sdmmc1-hv"; 1700ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1701ff21087eSPrathamesh Shete }; 1702ff21087eSPrathamesh Shete 1703ff21087eSPrathamesh Shete sdmmc3_1v8: sdmmc3-1v8 { 1704ff21087eSPrathamesh Shete pins = "sdmmc3-hv"; 1705ff21087eSPrathamesh Shete power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1706ff21087eSPrathamesh Shete }; 1707ff21087eSPrathamesh Shete 170879ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 170979ed18d9SThierry Reding pins = "sdmmc3-hv"; 171079ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 171179ed18d9SThierry Reding }; 17125425fb15SMikko Perttunen }; 17133db6d3baSThierry Reding 1714a47e173eSSumit Gupta aon-noc@c600000 { 1715a47e173eSSumit Gupta compatible = "nvidia,tegra194-aon-noc"; 17162838cfddSThierry Reding reg = <0x0 0xc600000 0x0 0x1000>; 1717a47e173eSSumit Gupta interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1718a47e173eSSumit Gupta <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1719a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1720a47e173eSSumit Gupta status = "okay"; 1721a47e173eSSumit Gupta }; 1722a47e173eSSumit Gupta 1723a47e173eSSumit Gupta bpmp-noc@d600000 { 1724a47e173eSSumit Gupta compatible = "nvidia,tegra194-bpmp-noc"; 17252838cfddSThierry Reding reg = <0x0 0xd600000 0x0 0x1000>; 1726a47e173eSSumit Gupta interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1727a47e173eSSumit Gupta <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1728a47e173eSSumit Gupta nvidia,axi2apb = <&axi2apb>; 1729a47e173eSSumit Gupta nvidia,apbmisc = <&apbmisc>; 1730a47e173eSSumit Gupta status = "okay"; 1731a47e173eSSumit Gupta }; 1732a47e173eSSumit Gupta 1733e762232fSJon Hunter iommu@10000000 { 1734e762232fSJon Hunter compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 17352838cfddSThierry Reding reg = <0x0 0x10000000 0x0 0x800000>; 1736e762232fSJon Hunter interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800e762232fSJon Hunter <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1801e762232fSJon Hunter stream-match-mask = <0x7f80>; 1802e762232fSJon Hunter #global-interrupts = <1>; 1803e762232fSJon Hunter #iommu-cells = <1>; 1804e762232fSJon Hunter 1805e762232fSJon Hunter nvidia,memory-controller = <&mc>; 1806ebea268eSJon Hunter status = "disabled"; 1807e762232fSJon Hunter }; 1808e762232fSJon Hunter 1809c7289b1cSThierry Reding smmu: iommu@12000000 { 1810c7289b1cSThierry Reding compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 18112838cfddSThierry Reding reg = <0x0 0x12000000 0x0 0x800000>, 18122838cfddSThierry Reding <0x0 0x11000000 0x0 0x800000>; 1813c7289b1cSThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814c7289b1cSThierry Reding <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1815c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878c7289b1cSThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1879c7289b1cSThierry Reding stream-match-mask = <0x7f80>; 1880c7289b1cSThierry Reding #global-interrupts = <2>; 1881c7289b1cSThierry Reding #iommu-cells = <1>; 1882c7289b1cSThierry Reding 1883c7289b1cSThierry Reding nvidia,memory-controller = <&mc>; 1884c7289b1cSThierry Reding status = "okay"; 1885c7289b1cSThierry Reding }; 1886c7289b1cSThierry Reding 18873db6d3baSThierry Reding host1x@13e00000 { 1888ef126bc4SThierry Reding compatible = "nvidia,tegra194-host1x"; 18892838cfddSThierry Reding reg = <0x0 0x13e00000 0x0 0x10000>, 18902838cfddSThierry Reding <0x0 0x13e10000 0x0 0x10000>; 18913db6d3baSThierry Reding reg-names = "hypervisor", "vm"; 18923db6d3baSThierry Reding interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 18933db6d3baSThierry Reding <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1894052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 18953db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_HOST1X>; 18963db6d3baSThierry Reding clock-names = "host1x"; 18973db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_HOST1X>; 18983db6d3baSThierry Reding reset-names = "host1x"; 18993db6d3baSThierry Reding 19002838cfddSThierry Reding #address-cells = <2>; 19012838cfddSThierry Reding #size-cells = <2>; 19022838cfddSThierry Reding ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 19033db6d3baSThierry Reding 1904d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1905d5237c7cSThierry Reding interconnect-names = "dma-mem"; 1906c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_HOST1X>; 1907361238cdSMikko Perttunen dma-coherent; 19083db6d3baSThierry Reding 1909e30cf101SMikko Perttunen /* Context isolation domains */ 1910b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1911b0c1a994SThierry Reding <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1912b0c1a994SThierry Reding <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1913b0c1a994SThierry Reding <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1914b0c1a994SThierry Reding <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1915b0c1a994SThierry Reding <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1916b0c1a994SThierry Reding <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1917b0c1a994SThierry Reding <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1918e30cf101SMikko Perttunen 191978a05873SMikko Perttunen nvdec@15140000 { 192078a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 19212838cfddSThierry Reding reg = <0x0 0x15140000 0x0 0x00040000>; 192278a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 192378a05873SMikko Perttunen clock-names = "nvdec"; 192478a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC1>; 192578a05873SMikko Perttunen reset-names = "nvdec"; 192678a05873SMikko Perttunen 192778a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 192878a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 192978a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 193078a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 193178a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 193278a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC1>; 193378a05873SMikko Perttunen dma-coherent; 193478a05873SMikko Perttunen 193578a05873SMikko Perttunen nvidia,host1x-class = <0xf5>; 193678a05873SMikko Perttunen }; 193778a05873SMikko Perttunen 19383db6d3baSThierry Reding display-hub@15200000 { 1939aa342b53SThierry Reding compatible = "nvidia,tegra194-display"; 19402838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x00040000>; 19413db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 19423db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 19433db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 19443db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 19453db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 19463db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 19473db6d3baSThierry Reding <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 19483db6d3baSThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 19493db6d3baSThierry Reding "wgrp3", "wgrp4", "wgrp5"; 19503db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 19513db6d3baSThierry Reding <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 19523db6d3baSThierry Reding clock-names = "disp", "hub"; 19533db6d3baSThierry Reding status = "disabled"; 19543db6d3baSThierry Reding 19553db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 19563db6d3baSThierry Reding 19572838cfddSThierry Reding #address-cells = <2>; 19582838cfddSThierry Reding #size-cells = <2>; 19592838cfddSThierry Reding ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 19603db6d3baSThierry Reding 19613db6d3baSThierry Reding display@15200000 { 19623db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19632838cfddSThierry Reding reg = <0x0 0x15200000 0x0 0x10000>; 19643db6d3baSThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 19653db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 19663db6d3baSThierry Reding clock-names = "dc"; 19673db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 19683db6d3baSThierry Reding reset-names = "dc"; 19693db6d3baSThierry Reding 19703db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1971d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1972d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1973d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19743db6d3baSThierry Reding 19753db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19763db6d3baSThierry Reding nvidia,head = <0>; 19773db6d3baSThierry Reding }; 19783db6d3baSThierry Reding 19793db6d3baSThierry Reding display@15210000 { 19803db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19812838cfddSThierry Reding reg = <0x0 0x15210000 0x0 0x10000>; 19823db6d3baSThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 19833db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 19843db6d3baSThierry Reding clock-names = "dc"; 19853db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 19863db6d3baSThierry Reding reset-names = "dc"; 19873db6d3baSThierry Reding 19883db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1989d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1990d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1991d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 19923db6d3baSThierry Reding 19933db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 19943db6d3baSThierry Reding nvidia,head = <1>; 19953db6d3baSThierry Reding }; 19963db6d3baSThierry Reding 19973db6d3baSThierry Reding display@15220000 { 19983db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 19992838cfddSThierry Reding reg = <0x0 0x15220000 0x0 0x10000>; 20003db6d3baSThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 20013db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 20023db6d3baSThierry Reding clock-names = "dc"; 20033db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 20043db6d3baSThierry Reding reset-names = "dc"; 20053db6d3baSThierry Reding 20063db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2007d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2008d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2009d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20103db6d3baSThierry Reding 20113db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20123db6d3baSThierry Reding nvidia,head = <2>; 20133db6d3baSThierry Reding }; 20143db6d3baSThierry Reding 20153db6d3baSThierry Reding display@15230000 { 20163db6d3baSThierry Reding compatible = "nvidia,tegra194-dc"; 20172838cfddSThierry Reding reg = <0x0 0x15230000 0x0 0x10000>; 20183db6d3baSThierry Reding interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 20193db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 20203db6d3baSThierry Reding clock-names = "dc"; 20213db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 20223db6d3baSThierry Reding reset-names = "dc"; 20233db6d3baSThierry Reding 20243db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2025d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2026d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2027d5237c7cSThierry Reding interconnect-names = "dma-mem", "read-1"; 20283db6d3baSThierry Reding 20293db6d3baSThierry Reding nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 20303db6d3baSThierry Reding nvidia,head = <3>; 20313db6d3baSThierry Reding }; 20323db6d3baSThierry Reding }; 20333db6d3baSThierry Reding 20348d424ec2SThierry Reding vic@15340000 { 20358d424ec2SThierry Reding compatible = "nvidia,tegra194-vic"; 20362838cfddSThierry Reding reg = <0x0 0x15340000 0x0 0x00040000>; 20378d424ec2SThierry Reding interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 20388d424ec2SThierry Reding clocks = <&bpmp TEGRA194_CLK_VIC>; 20398d424ec2SThierry Reding clock-names = "vic"; 20408d424ec2SThierry Reding resets = <&bpmp TEGRA194_RESET_VIC>; 20418d424ec2SThierry Reding reset-names = "vic"; 20428d424ec2SThierry Reding 20438d424ec2SThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2044d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2045d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2046d5237c7cSThierry Reding interconnect-names = "dma-mem", "write"; 2047c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_VIC>; 2048a52280c8SJon Hunter dma-coherent; 20498d424ec2SThierry Reding }; 20508d424ec2SThierry Reding 2051f7eb2785SJon Hunter nvjpg@15380000 { 2052f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvjpg"; 20532838cfddSThierry Reding reg = <0x0 0x15380000 0x0 0x40000>; 2054f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2055f7eb2785SJon Hunter clock-names = "nvjpg"; 2056f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVJPG>; 2057f7eb2785SJon Hunter reset-names = "nvjpg"; 2058f7eb2785SJon Hunter 2059f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2060f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2061f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2062f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 2063f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVJPG>; 2064f7eb2785SJon Hunter dma-coherent; 2065f7eb2785SJon Hunter }; 2066f7eb2785SJon Hunter 206778a05873SMikko Perttunen nvdec@15480000 { 206878a05873SMikko Perttunen compatible = "nvidia,tegra194-nvdec"; 20692838cfddSThierry Reding reg = <0x0 0x15480000 0x0 0x00040000>; 207078a05873SMikko Perttunen clocks = <&bpmp TEGRA194_CLK_NVDEC>; 207178a05873SMikko Perttunen clock-names = "nvdec"; 207278a05873SMikko Perttunen resets = <&bpmp TEGRA194_RESET_NVDEC>; 207378a05873SMikko Perttunen reset-names = "nvdec"; 207478a05873SMikko Perttunen 207578a05873SMikko Perttunen power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 207678a05873SMikko Perttunen interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 207778a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 207878a05873SMikko Perttunen <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 207978a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 208078a05873SMikko Perttunen iommus = <&smmu TEGRA194_SID_NVDEC>; 208178a05873SMikko Perttunen dma-coherent; 208278a05873SMikko Perttunen 208378a05873SMikko Perttunen nvidia,host1x-class = <0xf0>; 208478a05873SMikko Perttunen }; 208578a05873SMikko Perttunen 2086f7eb2785SJon Hunter nvenc@154c0000 { 2087f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 20882838cfddSThierry Reding reg = <0x0 0x154c0000 0x0 0x40000>; 2089f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC>; 2090f7eb2785SJon Hunter clock-names = "nvenc"; 2091f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC>; 2092f7eb2785SJon Hunter reset-names = "nvenc"; 2093f7eb2785SJon Hunter 2094f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2095f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2096f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2097f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2098f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2099f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC>; 2100f7eb2785SJon Hunter dma-coherent; 2101f7eb2785SJon Hunter 2102f7eb2785SJon Hunter nvidia,host1x-class = <0x21>; 2103f7eb2785SJon Hunter }; 2104f7eb2785SJon Hunter 21053db6d3baSThierry Reding dpaux0: dpaux@155c0000 { 21063db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21072838cfddSThierry Reding reg = <0x0 0x155c0000 0x0 0x10000>; 21083db6d3baSThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 21093db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX>, 21103db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21113db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21123db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX>; 21133db6d3baSThierry Reding reset-names = "dpaux"; 21143db6d3baSThierry Reding status = "disabled"; 21153db6d3baSThierry Reding 21163db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21173db6d3baSThierry Reding 21183db6d3baSThierry Reding state_dpaux0_aux: pinmux-aux { 21193db6d3baSThierry Reding groups = "dpaux-io"; 21203db6d3baSThierry Reding function = "aux"; 21213db6d3baSThierry Reding }; 21223db6d3baSThierry Reding 21233db6d3baSThierry Reding state_dpaux0_i2c: pinmux-i2c { 21243db6d3baSThierry Reding groups = "dpaux-io"; 21253db6d3baSThierry Reding function = "i2c"; 21263db6d3baSThierry Reding }; 21273db6d3baSThierry Reding 21283db6d3baSThierry Reding state_dpaux0_off: pinmux-off { 21293db6d3baSThierry Reding groups = "dpaux-io"; 21303db6d3baSThierry Reding function = "off"; 21313db6d3baSThierry Reding }; 21323db6d3baSThierry Reding 21333db6d3baSThierry Reding i2c-bus { 21343db6d3baSThierry Reding #address-cells = <1>; 21353db6d3baSThierry Reding #size-cells = <0>; 21363db6d3baSThierry Reding }; 21373db6d3baSThierry Reding }; 21383db6d3baSThierry Reding 21393db6d3baSThierry Reding dpaux1: dpaux@155d0000 { 21403db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21412838cfddSThierry Reding reg = <0x0 0x155d0000 0x0 0x10000>; 21423db6d3baSThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 21433db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 21443db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21453db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21463db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX1>; 21473db6d3baSThierry Reding reset-names = "dpaux"; 21483db6d3baSThierry Reding status = "disabled"; 21493db6d3baSThierry Reding 21503db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21513db6d3baSThierry Reding 21523db6d3baSThierry Reding state_dpaux1_aux: pinmux-aux { 21533db6d3baSThierry Reding groups = "dpaux-io"; 21543db6d3baSThierry Reding function = "aux"; 21553db6d3baSThierry Reding }; 21563db6d3baSThierry Reding 21573db6d3baSThierry Reding state_dpaux1_i2c: pinmux-i2c { 21583db6d3baSThierry Reding groups = "dpaux-io"; 21593db6d3baSThierry Reding function = "i2c"; 21603db6d3baSThierry Reding }; 21613db6d3baSThierry Reding 21623db6d3baSThierry Reding state_dpaux1_off: pinmux-off { 21633db6d3baSThierry Reding groups = "dpaux-io"; 21643db6d3baSThierry Reding function = "off"; 21653db6d3baSThierry Reding }; 21663db6d3baSThierry Reding 21673db6d3baSThierry Reding i2c-bus { 21683db6d3baSThierry Reding #address-cells = <1>; 21693db6d3baSThierry Reding #size-cells = <0>; 21703db6d3baSThierry Reding }; 21713db6d3baSThierry Reding }; 21723db6d3baSThierry Reding 21733db6d3baSThierry Reding dpaux2: dpaux@155e0000 { 21743db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 21752838cfddSThierry Reding reg = <0x0 0x155e0000 0x0 0x10000>; 21763db6d3baSThierry Reding interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 21773db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 21783db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 21793db6d3baSThierry Reding clock-names = "dpaux", "parent"; 21803db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX2>; 21813db6d3baSThierry Reding reset-names = "dpaux"; 21823db6d3baSThierry Reding status = "disabled"; 21833db6d3baSThierry Reding 21843db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 21853db6d3baSThierry Reding 21863db6d3baSThierry Reding state_dpaux2_aux: pinmux-aux { 21873db6d3baSThierry Reding groups = "dpaux-io"; 21883db6d3baSThierry Reding function = "aux"; 21893db6d3baSThierry Reding }; 21903db6d3baSThierry Reding 21913db6d3baSThierry Reding state_dpaux2_i2c: pinmux-i2c { 21923db6d3baSThierry Reding groups = "dpaux-io"; 21933db6d3baSThierry Reding function = "i2c"; 21943db6d3baSThierry Reding }; 21953db6d3baSThierry Reding 21963db6d3baSThierry Reding state_dpaux2_off: pinmux-off { 21973db6d3baSThierry Reding groups = "dpaux-io"; 21983db6d3baSThierry Reding function = "off"; 21993db6d3baSThierry Reding }; 22003db6d3baSThierry Reding 22013db6d3baSThierry Reding i2c-bus { 22023db6d3baSThierry Reding #address-cells = <1>; 22033db6d3baSThierry Reding #size-cells = <0>; 22043db6d3baSThierry Reding }; 22053db6d3baSThierry Reding }; 22063db6d3baSThierry Reding 22073db6d3baSThierry Reding dpaux3: dpaux@155f0000 { 22083db6d3baSThierry Reding compatible = "nvidia,tegra194-dpaux"; 22092838cfddSThierry Reding reg = <0x0 0x155f0000 0x0 0x10000>; 22103db6d3baSThierry Reding interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 22113db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 22123db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>; 22133db6d3baSThierry Reding clock-names = "dpaux", "parent"; 22143db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_DPAUX3>; 22153db6d3baSThierry Reding reset-names = "dpaux"; 22163db6d3baSThierry Reding status = "disabled"; 22173db6d3baSThierry Reding 22183db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22193db6d3baSThierry Reding 22203db6d3baSThierry Reding state_dpaux3_aux: pinmux-aux { 22213db6d3baSThierry Reding groups = "dpaux-io"; 22223db6d3baSThierry Reding function = "aux"; 22233db6d3baSThierry Reding }; 22243db6d3baSThierry Reding 22253db6d3baSThierry Reding state_dpaux3_i2c: pinmux-i2c { 22263db6d3baSThierry Reding groups = "dpaux-io"; 22273db6d3baSThierry Reding function = "i2c"; 22283db6d3baSThierry Reding }; 22293db6d3baSThierry Reding 22303db6d3baSThierry Reding state_dpaux3_off: pinmux-off { 22313db6d3baSThierry Reding groups = "dpaux-io"; 22323db6d3baSThierry Reding function = "off"; 22333db6d3baSThierry Reding }; 22343db6d3baSThierry Reding 22353db6d3baSThierry Reding i2c-bus { 22363db6d3baSThierry Reding #address-cells = <1>; 22373db6d3baSThierry Reding #size-cells = <0>; 22383db6d3baSThierry Reding }; 22393db6d3baSThierry Reding }; 22403db6d3baSThierry Reding 2241f7eb2785SJon Hunter nvenc@15a80000 { 2242f7eb2785SJon Hunter compatible = "nvidia,tegra194-nvenc"; 22432838cfddSThierry Reding reg = <0x0 0x15a80000 0x0 0x00040000>; 2244f7eb2785SJon Hunter clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2245f7eb2785SJon Hunter clock-names = "nvenc"; 2246f7eb2785SJon Hunter resets = <&bpmp TEGRA194_RESET_NVENC1>; 2247f7eb2785SJon Hunter reset-names = "nvenc"; 2248f7eb2785SJon Hunter 2249f7eb2785SJon Hunter power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2250f7eb2785SJon Hunter interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2251f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2252f7eb2785SJon Hunter <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2253f7eb2785SJon Hunter interconnect-names = "dma-mem", "read-1", "write"; 2254f7eb2785SJon Hunter iommus = <&smmu TEGRA194_SID_NVENC1>; 2255f7eb2785SJon Hunter dma-coherent; 2256f7eb2785SJon Hunter 2257f7eb2785SJon Hunter nvidia,host1x-class = <0x22>; 2258f7eb2785SJon Hunter }; 2259f7eb2785SJon Hunter 22603db6d3baSThierry Reding sor0: sor@15b00000 { 22613db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22622838cfddSThierry Reding reg = <0x0 0x15b00000 0x0 0x40000>; 22633db6d3baSThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 22643db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 22653db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_OUT>, 22663db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD>, 22673db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22683db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22693db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 22703db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22713db6d3baSThierry Reding "pad"; 22723db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR0>; 22733db6d3baSThierry Reding reset-names = "sor"; 22743db6d3baSThierry Reding pinctrl-0 = <&state_dpaux0_aux>; 22753db6d3baSThierry Reding pinctrl-1 = <&state_dpaux0_i2c>; 22763db6d3baSThierry Reding pinctrl-2 = <&state_dpaux0_off>; 22773db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 22783db6d3baSThierry Reding status = "disabled"; 22793db6d3baSThierry Reding 22803db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 22813db6d3baSThierry Reding nvidia,interface = <0>; 22823db6d3baSThierry Reding }; 22833db6d3baSThierry Reding 22843db6d3baSThierry Reding sor1: sor@15b40000 { 22853db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 22862838cfddSThierry Reding reg = <0x0 0x15b40000 0x0 0x40000>; 22873db6d3baSThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 22883db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 22893db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_OUT>, 22903db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD2>, 22913db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 22923db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 22933db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 22943db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 22953db6d3baSThierry Reding "pad"; 22963db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR1>; 22973db6d3baSThierry Reding reset-names = "sor"; 22983db6d3baSThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 22993db6d3baSThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 23003db6d3baSThierry Reding pinctrl-2 = <&state_dpaux1_off>; 23013db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23023db6d3baSThierry Reding status = "disabled"; 23033db6d3baSThierry Reding 23043db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23053db6d3baSThierry Reding nvidia,interface = <1>; 23063db6d3baSThierry Reding }; 23073db6d3baSThierry Reding 23083db6d3baSThierry Reding sor2: sor@15b80000 { 23093db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23102838cfddSThierry Reding reg = <0x0 0x15b80000 0x0 0x40000>; 23113db6d3baSThierry Reding interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 23123db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 23133db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_OUT>, 23143db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD3>, 23153db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23163db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23173db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 23183db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23193db6d3baSThierry Reding "pad"; 23203db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR2>; 23213db6d3baSThierry Reding reset-names = "sor"; 23223db6d3baSThierry Reding pinctrl-0 = <&state_dpaux2_aux>; 23233db6d3baSThierry Reding pinctrl-1 = <&state_dpaux2_i2c>; 23243db6d3baSThierry Reding pinctrl-2 = <&state_dpaux2_off>; 23253db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23263db6d3baSThierry Reding status = "disabled"; 23273db6d3baSThierry Reding 23283db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23293db6d3baSThierry Reding nvidia,interface = <2>; 23303db6d3baSThierry Reding }; 23313db6d3baSThierry Reding 23323db6d3baSThierry Reding sor3: sor@15bc0000 { 23333db6d3baSThierry Reding compatible = "nvidia,tegra194-sor"; 23342838cfddSThierry Reding reg = <0x0 0x15bc0000 0x0 0x40000>; 23353db6d3baSThierry Reding interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 23363db6d3baSThierry Reding clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 23373db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_OUT>, 23383db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLD4>, 23393db6d3baSThierry Reding <&bpmp TEGRA194_CLK_PLLDP>, 23403db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR_SAFE>, 23413db6d3baSThierry Reding <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 23423db6d3baSThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 23433db6d3baSThierry Reding "pad"; 23443db6d3baSThierry Reding resets = <&bpmp TEGRA194_RESET_SOR3>; 23453db6d3baSThierry Reding reset-names = "sor"; 23463db6d3baSThierry Reding pinctrl-0 = <&state_dpaux3_aux>; 23473db6d3baSThierry Reding pinctrl-1 = <&state_dpaux3_i2c>; 23483db6d3baSThierry Reding pinctrl-2 = <&state_dpaux3_off>; 23493db6d3baSThierry Reding pinctrl-names = "aux", "i2c", "off"; 23503db6d3baSThierry Reding status = "disabled"; 23513db6d3baSThierry Reding 23523db6d3baSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 23533db6d3baSThierry Reding nvidia,interface = <3>; 23543db6d3baSThierry Reding }; 23553db6d3baSThierry Reding }; 23560f134e39SThierry Reding 23572602c32fSVidya Sagar pcie@14100000 { 2358f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 23592602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 236079ed18d9SThierry Reding reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 236179ed18d9SThierry Reding <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 236279ed18d9SThierry Reding <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 236379ed18d9SThierry Reding <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 23642602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 23652602c32fSVidya Sagar 23662602c32fSVidya Sagar status = "disabled"; 23672602c32fSVidya Sagar 23682602c32fSVidya Sagar #address-cells = <3>; 23692602c32fSVidya Sagar #size-cells = <2>; 23702602c32fSVidya Sagar device_type = "pci"; 23712602c32fSVidya Sagar num-lanes = <1>; 23722602c32fSVidya Sagar linux,pci-domain = <1>; 23732602c32fSVidya Sagar 23742602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 23752602c32fSVidya Sagar clock-names = "core"; 23762602c32fSVidya Sagar 23772602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 23782602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 23792602c32fSVidya Sagar reset-names = "apb", "core"; 23802602c32fSVidya Sagar 23812602c32fSVidya Sagar interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 23822602c32fSVidya Sagar <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 23832602c32fSVidya Sagar interrupt-names = "intr", "msi"; 23842602c32fSVidya Sagar 23852602c32fSVidya Sagar #interrupt-cells = <1>; 23862602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 23872602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 23882602c32fSVidya Sagar 23892602c32fSVidya Sagar nvidia,bpmp = <&bpmp 1>; 23902602c32fSVidya Sagar 23912602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 23922602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 23932602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 23942602c32fSVidya Sagar 23952602c32fSVidya Sagar bus-range = <0x0 0xff>; 2396d5237c7cSThierry Reding 23978a565952SVidya Sagar ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 23988a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 23998a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2400d5237c7cSThierry Reding 2401d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2402d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2403ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2404ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2405ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2406ba02920cSVidya Sagar dma-coherent; 24072602c32fSVidya Sagar }; 24082602c32fSVidya Sagar 24092602c32fSVidya Sagar pcie@14120000 { 2410f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24112602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2412644c569dSThierry Reding reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2413644c569dSThierry Reding <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2414644c569dSThierry Reding <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2415644c569dSThierry Reding <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24162602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24172602c32fSVidya Sagar 24182602c32fSVidya Sagar status = "disabled"; 24192602c32fSVidya Sagar 24202602c32fSVidya Sagar #address-cells = <3>; 24212602c32fSVidya Sagar #size-cells = <2>; 24222602c32fSVidya Sagar device_type = "pci"; 24232602c32fSVidya Sagar num-lanes = <1>; 24242602c32fSVidya Sagar linux,pci-domain = <2>; 24252602c32fSVidya Sagar 24262602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 24272602c32fSVidya Sagar clock-names = "core"; 24282602c32fSVidya Sagar 24292602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 24302602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 24312602c32fSVidya Sagar reset-names = "apb", "core"; 24322602c32fSVidya Sagar 24332602c32fSVidya Sagar interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24342602c32fSVidya Sagar <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24352602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24362602c32fSVidya Sagar 24372602c32fSVidya Sagar #interrupt-cells = <1>; 24382602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24392602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 24402602c32fSVidya Sagar 24412602c32fSVidya Sagar nvidia,bpmp = <&bpmp 2>; 24422602c32fSVidya Sagar 24432602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24442602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24452602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24462602c32fSVidya Sagar 24472602c32fSVidya Sagar bus-range = <0x0 0xff>; 2448d5237c7cSThierry Reding 24498a565952SVidya Sagar ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 24508a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 24518a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2452d5237c7cSThierry Reding 2453d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2454d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2455ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2456ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2457ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2458ba02920cSVidya Sagar dma-coherent; 24592602c32fSVidya Sagar }; 24602602c32fSVidya Sagar 24612602c32fSVidya Sagar pcie@14140000 { 2462f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 24632602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2464644c569dSThierry Reding reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2465644c569dSThierry Reding <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2466644c569dSThierry Reding <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2467644c569dSThierry Reding <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 24682602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 24692602c32fSVidya Sagar 24702602c32fSVidya Sagar status = "disabled"; 24712602c32fSVidya Sagar 24722602c32fSVidya Sagar #address-cells = <3>; 24732602c32fSVidya Sagar #size-cells = <2>; 24742602c32fSVidya Sagar device_type = "pci"; 24752602c32fSVidya Sagar num-lanes = <1>; 24762602c32fSVidya Sagar linux,pci-domain = <3>; 24772602c32fSVidya Sagar 24782602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 24792602c32fSVidya Sagar clock-names = "core"; 24802602c32fSVidya Sagar 24812602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 24822602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 24832602c32fSVidya Sagar reset-names = "apb", "core"; 24842602c32fSVidya Sagar 24852602c32fSVidya Sagar interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 24862602c32fSVidya Sagar <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 24872602c32fSVidya Sagar interrupt-names = "intr", "msi"; 24882602c32fSVidya Sagar 24892602c32fSVidya Sagar #interrupt-cells = <1>; 24902602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 24912602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 24922602c32fSVidya Sagar 24932602c32fSVidya Sagar nvidia,bpmp = <&bpmp 3>; 24942602c32fSVidya Sagar 24952602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 24962602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 24972602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 24982602c32fSVidya Sagar 24992602c32fSVidya Sagar bus-range = <0x0 0xff>; 2500d5237c7cSThierry Reding 25018a565952SVidya Sagar ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 25028a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 25038a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2504d5237c7cSThierry Reding 2505d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2506d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2507ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2508ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2509ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2510ba02920cSVidya Sagar dma-coherent; 25112602c32fSVidya Sagar }; 25122602c32fSVidya Sagar 25132602c32fSVidya Sagar pcie@14160000 { 2514f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 25152602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2516644c569dSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2517644c569dSThierry Reding <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2518644c569dSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2519644c569dSThierry Reding <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 25202602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 25212602c32fSVidya Sagar 25222602c32fSVidya Sagar status = "disabled"; 25232602c32fSVidya Sagar 25242602c32fSVidya Sagar #address-cells = <3>; 25252602c32fSVidya Sagar #size-cells = <2>; 25262602c32fSVidya Sagar device_type = "pci"; 25272602c32fSVidya Sagar num-lanes = <4>; 25282602c32fSVidya Sagar linux,pci-domain = <4>; 25292602c32fSVidya Sagar 25302602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25312602c32fSVidya Sagar clock-names = "core"; 25322602c32fSVidya Sagar 25332602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25342602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25352602c32fSVidya Sagar reset-names = "apb", "core"; 25362602c32fSVidya Sagar 25372602c32fSVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 25382602c32fSVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 25392602c32fSVidya Sagar interrupt-names = "intr", "msi"; 25402602c32fSVidya Sagar 25412602c32fSVidya Sagar #interrupt-cells = <1>; 25422602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 25432602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 25442602c32fSVidya Sagar 25452602c32fSVidya Sagar nvidia,bpmp = <&bpmp 4>; 25462602c32fSVidya Sagar 25472602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 25482602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 25492602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 25502602c32fSVidya Sagar 25512602c32fSVidya Sagar bus-range = <0x0 0xff>; 2552d5237c7cSThierry Reding 25538a565952SVidya Sagar ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 25548a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 25558a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2556d5237c7cSThierry Reding 2557d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2558d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2559ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2560ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2561ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2562ba02920cSVidya Sagar dma-coherent; 25632602c32fSVidya Sagar }; 25642602c32fSVidya Sagar 25652838cfddSThierry Reding pcie-ep@14160000 { 25662838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 25672838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 25682838cfddSThierry Reding reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 25692838cfddSThierry Reding <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 25702838cfddSThierry Reding <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 25712838cfddSThierry Reding <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 25722838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 25732838cfddSThierry Reding 25742838cfddSThierry Reding status = "disabled"; 25752838cfddSThierry Reding 25762838cfddSThierry Reding num-lanes = <4>; 25772838cfddSThierry Reding num-ib-windows = <2>; 25782838cfddSThierry Reding num-ob-windows = <8>; 25792838cfddSThierry Reding 25802838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 25812838cfddSThierry Reding clock-names = "core"; 25822838cfddSThierry Reding 25832838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 25842838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 25852838cfddSThierry Reding reset-names = "apb", "core"; 25862838cfddSThierry Reding 25872838cfddSThierry Reding interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 25882838cfddSThierry Reding interrupt-names = "intr"; 25892838cfddSThierry Reding 25902838cfddSThierry Reding nvidia,bpmp = <&bpmp 4>; 25912838cfddSThierry Reding 25922838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 25932838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 25942838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 25952838cfddSThierry Reding 25962838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 25972838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 25982838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 25992838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 26002838cfddSThierry Reding iommu-map-mask = <0x0>; 26012838cfddSThierry Reding dma-coherent; 26022838cfddSThierry Reding }; 26032838cfddSThierry Reding 26042602c32fSVidya Sagar pcie@14180000 { 2605f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26062602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2607644c569dSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2608644c569dSThierry Reding <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2609644c569dSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2610644c569dSThierry Reding <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 26112602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 26122602c32fSVidya Sagar 26132602c32fSVidya Sagar status = "disabled"; 26142602c32fSVidya Sagar 26152602c32fSVidya Sagar #address-cells = <3>; 26162602c32fSVidya Sagar #size-cells = <2>; 26172602c32fSVidya Sagar device_type = "pci"; 26182602c32fSVidya Sagar num-lanes = <8>; 26192602c32fSVidya Sagar linux,pci-domain = <0>; 26202602c32fSVidya Sagar 26212602c32fSVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26222602c32fSVidya Sagar clock-names = "core"; 26232602c32fSVidya Sagar 26242602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26252602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26262602c32fSVidya Sagar reset-names = "apb", "core"; 26272602c32fSVidya Sagar 26282602c32fSVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26292602c32fSVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 26302602c32fSVidya Sagar interrupt-names = "intr", "msi"; 26312602c32fSVidya Sagar 26322602c32fSVidya Sagar #interrupt-cells = <1>; 26332602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 26342602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 26352602c32fSVidya Sagar 26362602c32fSVidya Sagar nvidia,bpmp = <&bpmp 0>; 26372602c32fSVidya Sagar 26382602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 26392602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 26402602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 26412602c32fSVidya Sagar 26422602c32fSVidya Sagar bus-range = <0x0 0xff>; 2643d5237c7cSThierry Reding 26448a565952SVidya Sagar ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 26458a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 26468a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2647d5237c7cSThierry Reding 2648d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2649d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2650ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2651ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2652ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2653ba02920cSVidya Sagar dma-coherent; 26542602c32fSVidya Sagar }; 26552602c32fSVidya Sagar 26562838cfddSThierry Reding pcie-ep@14180000 { 26572838cfddSThierry Reding compatible = "nvidia,tegra194-pcie-ep"; 26582838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 26592838cfddSThierry Reding reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 26602838cfddSThierry Reding <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 26612838cfddSThierry Reding <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 26622838cfddSThierry Reding <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 26632838cfddSThierry Reding reg-names = "appl", "atu_dma", "dbi", "addr_space"; 26642838cfddSThierry Reding 26652838cfddSThierry Reding status = "disabled"; 26662838cfddSThierry Reding 26672838cfddSThierry Reding num-lanes = <8>; 26682838cfddSThierry Reding num-ib-windows = <2>; 26692838cfddSThierry Reding num-ob-windows = <8>; 26702838cfddSThierry Reding 26712838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 26722838cfddSThierry Reding clock-names = "core"; 26732838cfddSThierry Reding 26742838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 26752838cfddSThierry Reding <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 26762838cfddSThierry Reding reset-names = "apb", "core"; 26772838cfddSThierry Reding 26782838cfddSThierry Reding interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 26792838cfddSThierry Reding interrupt-names = "intr"; 26802838cfddSThierry Reding 26812838cfddSThierry Reding nvidia,bpmp = <&bpmp 0>; 26822838cfddSThierry Reding 26832838cfddSThierry Reding nvidia,aspm-cmrt-us = <60>; 26842838cfddSThierry Reding nvidia,aspm-pwr-on-t-us = <20>; 26852838cfddSThierry Reding nvidia,aspm-l0s-entrance-latency-us = <3>; 26862838cfddSThierry Reding 26872838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 26882838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 26892838cfddSThierry Reding interconnect-names = "dma-mem", "write"; 26902838cfddSThierry Reding iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 26912838cfddSThierry Reding iommu-map-mask = <0x0>; 26922838cfddSThierry Reding dma-coherent; 26932838cfddSThierry Reding }; 26942838cfddSThierry Reding 26952602c32fSVidya Sagar pcie@141a0000 { 2696f9f711efSJon Hunter compatible = "nvidia,tegra194-pcie"; 26972602c32fSVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2698644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2699644c569dSThierry Reding <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2700644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2701644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 27022602c32fSVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 27032602c32fSVidya Sagar 27042602c32fSVidya Sagar status = "disabled"; 27052602c32fSVidya Sagar 27062602c32fSVidya Sagar #address-cells = <3>; 27072602c32fSVidya Sagar #size-cells = <2>; 27082602c32fSVidya Sagar device_type = "pci"; 27092602c32fSVidya Sagar num-lanes = <8>; 27102602c32fSVidya Sagar linux,pci-domain = <5>; 27112602c32fSVidya Sagar 2712dbb72e2cSVidya Sagar pinctrl-names = "default"; 271379ed18d9SThierry Reding pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2714dbb72e2cSVidya Sagar 2715c453cc9eSThierry Reding clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2716c453cc9eSThierry Reding clock-names = "core"; 27172602c32fSVidya Sagar 27182602c32fSVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27192602c32fSVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27202602c32fSVidya Sagar reset-names = "apb", "core"; 27212602c32fSVidya Sagar 27222602c32fSVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27232602c32fSVidya Sagar <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27242602c32fSVidya Sagar interrupt-names = "intr", "msi"; 27252602c32fSVidya Sagar 27262602c32fSVidya Sagar nvidia,bpmp = <&bpmp 5>; 27272602c32fSVidya Sagar 27282602c32fSVidya Sagar #interrupt-cells = <1>; 27292602c32fSVidya Sagar interrupt-map-mask = <0 0 0 0>; 27302602c32fSVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 27312602c32fSVidya Sagar 27322602c32fSVidya Sagar nvidia,aspm-cmrt-us = <60>; 27332602c32fSVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27342602c32fSVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 27352602c32fSVidya Sagar 27362602c32fSVidya Sagar bus-range = <0x0 0xff>; 2737d5237c7cSThierry Reding 27388a565952SVidya Sagar ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 27398a565952SVidya Sagar <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 27408a565952SVidya Sagar <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2741d5237c7cSThierry Reding 2742d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2743d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2744ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2745ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2746ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2747ba02920cSVidya Sagar dma-coherent; 27482602c32fSVidya Sagar }; 27492602c32fSVidya Sagar 2750b9e2404cSMauro Carvalho Chehab pcie-ep@141a0000 { 2751bf2942a8SVidya Sagar compatible = "nvidia,tegra194-pcie-ep"; 27520c988b73SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2753644c569dSThierry Reding reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2754644c569dSThierry Reding <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2755644c569dSThierry Reding <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2756644c569dSThierry Reding <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 27570c988b73SVidya Sagar reg-names = "appl", "atu_dma", "dbi", "addr_space"; 27580c988b73SVidya Sagar 27590c988b73SVidya Sagar status = "disabled"; 27600c988b73SVidya Sagar 27610c988b73SVidya Sagar num-lanes = <8>; 27620c988b73SVidya Sagar num-ib-windows = <2>; 27630c988b73SVidya Sagar num-ob-windows = <8>; 27640c988b73SVidya Sagar 27650c988b73SVidya Sagar pinctrl-names = "default"; 276679ed18d9SThierry Reding pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 27670c988b73SVidya Sagar 27680c988b73SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 27690c988b73SVidya Sagar clock-names = "core"; 27700c988b73SVidya Sagar 27710c988b73SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 27720c988b73SVidya Sagar <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 27730c988b73SVidya Sagar reset-names = "apb", "core"; 27740c988b73SVidya Sagar 27750c988b73SVidya Sagar interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 27760c988b73SVidya Sagar interrupt-names = "intr"; 27770c988b73SVidya Sagar 27780c988b73SVidya Sagar nvidia,bpmp = <&bpmp 5>; 27790c988b73SVidya Sagar 27800c988b73SVidya Sagar nvidia,aspm-cmrt-us = <60>; 27810c988b73SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 27820c988b73SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 2783ba02920cSVidya Sagar 2784ba02920cSVidya Sagar interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2785ba02920cSVidya Sagar <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2786ba02920cSVidya Sagar interconnect-names = "dma-mem", "write"; 2787ba02920cSVidya Sagar iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2788ba02920cSVidya Sagar iommu-map-mask = <0x0>; 2789ba02920cSVidya Sagar dma-coherent; 27900c988b73SVidya Sagar }; 27910c988b73SVidya Sagar 27922838cfddSThierry Reding gpu@17000000 { 27932838cfddSThierry Reding compatible = "nvidia,gv11b"; 27942838cfddSThierry Reding reg = <0x0 0x17000000 0x0 0x1000000>, 27952838cfddSThierry Reding <0x0 0x18000000 0x0 0x1000000>; 27962838cfddSThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 27972838cfddSThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 27982838cfddSThierry Reding interrupt-names = "stall", "nonstall"; 27992838cfddSThierry Reding clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 28002838cfddSThierry Reding <&bpmp TEGRA194_CLK_GPU_PWR>, 28012838cfddSThierry Reding <&bpmp TEGRA194_CLK_FUSE>; 28022838cfddSThierry Reding clock-names = "gpu", "pwr", "fuse"; 28032838cfddSThierry Reding resets = <&bpmp TEGRA194_RESET_GPU>; 28042838cfddSThierry Reding reset-names = "gpu"; 28052838cfddSThierry Reding dma-coherent; 28062838cfddSThierry Reding 28072838cfddSThierry Reding power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 28082838cfddSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 28092838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 28102838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 28112838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 28122838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 28132838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 28142838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 28152838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 28162838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 28172838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 28182838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 28192838cfddSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 28202838cfddSThierry Reding interconnect-names = "dma-mem", "read-0-hp", "write-0", 28212838cfddSThierry Reding "read-1", "read-1-hp", "write-1", 28222838cfddSThierry Reding "read-2", "read-2-hp", "write-2", 28232838cfddSThierry Reding "read-3", "read-3-hp", "write-3"; 28242838cfddSThierry Reding }; 28252838cfddSThierry Reding }; 28262838cfddSThierry Reding 2827e867fe41SThierry Reding sram@40000000 { 28285425fb15SMikko Perttunen compatible = "nvidia,tegra194-sysram", "mmio-sram"; 28295425fb15SMikko Perttunen reg = <0x0 0x40000000 0x0 0x50000>; 28302838cfddSThierry Reding 28315425fb15SMikko Perttunen #address-cells = <1>; 28325425fb15SMikko Perttunen #size-cells = <1>; 28335425fb15SMikko Perttunen ranges = <0x0 0x0 0x40000000 0x50000>; 28342838cfddSThierry Reding 283561192a9dSMikko Perttunen no-memory-wc; 28365425fb15SMikko Perttunen 2837e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 28385425fb15SMikko Perttunen reg = <0x4e000 0x1000>; 28395425fb15SMikko Perttunen label = "cpu-bpmp-tx"; 28405425fb15SMikko Perttunen pool; 28415425fb15SMikko Perttunen }; 28425425fb15SMikko Perttunen 2843e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 28445425fb15SMikko Perttunen reg = <0x4f000 0x1000>; 28455425fb15SMikko Perttunen label = "cpu-bpmp-rx"; 28465425fb15SMikko Perttunen pool; 28475425fb15SMikko Perttunen }; 28485425fb15SMikko Perttunen }; 28495425fb15SMikko Perttunen 28505425fb15SMikko Perttunen bpmp: bpmp { 28515425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp"; 28525425fb15SMikko Perttunen mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 28535425fb15SMikko Perttunen TEGRA_HSP_DB_MASTER_BPMP>; 28547fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 28555425fb15SMikko Perttunen #clock-cells = <1>; 28565425fb15SMikko Perttunen #reset-cells = <1>; 28575425fb15SMikko Perttunen #power-domain-cells = <1>; 2858d5237c7cSThierry Reding interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2859d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2860d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2861d5237c7cSThierry Reding <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2862d5237c7cSThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 2863c7289b1cSThierry Reding iommus = <&smmu TEGRA194_SID_BPMP>; 28645425fb15SMikko Perttunen 28655425fb15SMikko Perttunen bpmp_i2c: i2c { 28665425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-i2c"; 28675425fb15SMikko Perttunen nvidia,bpmp-bus-id = <5>; 28685425fb15SMikko Perttunen #address-cells = <1>; 28695425fb15SMikko Perttunen #size-cells = <0>; 28705425fb15SMikko Perttunen }; 28715425fb15SMikko Perttunen 28725425fb15SMikko Perttunen bpmp_thermal: thermal { 28735425fb15SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 28745425fb15SMikko Perttunen #thermal-sensor-cells = <1>; 28755425fb15SMikko Perttunen }; 28765425fb15SMikko Perttunen }; 28775425fb15SMikko Perttunen 28787780a034SMikko Perttunen cpus { 2879d4ff18b8SSumit Gupta compatible = "nvidia,tegra194-ccplex"; 2880d4ff18b8SSumit Gupta nvidia,bpmp = <&bpmp>; 28817780a034SMikko Perttunen #address-cells = <1>; 28827780a034SMikko Perttunen #size-cells = <0>; 28837780a034SMikko Perttunen 2884b45d322cSThierry Reding cpu0_0: cpu@0 { 288531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 28867780a034SMikko Perttunen device_type = "cpu"; 2887b45d322cSThierry Reding reg = <0x000>; 28887780a034SMikko Perttunen enable-method = "psci"; 2889b45d322cSThierry Reding i-cache-size = <131072>; 2890b45d322cSThierry Reding i-cache-line-size = <64>; 2891b45d322cSThierry Reding i-cache-sets = <512>; 2892b45d322cSThierry Reding d-cache-size = <65536>; 2893b45d322cSThierry Reding d-cache-line-size = <64>; 2894b45d322cSThierry Reding d-cache-sets = <256>; 2895b45d322cSThierry Reding next-level-cache = <&l2c_0>; 28967780a034SMikko Perttunen }; 28977780a034SMikko Perttunen 2898b45d322cSThierry Reding cpu0_1: cpu@1 { 289931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29007780a034SMikko Perttunen device_type = "cpu"; 2901b45d322cSThierry Reding reg = <0x001>; 29027780a034SMikko Perttunen enable-method = "psci"; 2903b45d322cSThierry Reding i-cache-size = <131072>; 2904b45d322cSThierry Reding i-cache-line-size = <64>; 2905b45d322cSThierry Reding i-cache-sets = <512>; 2906b45d322cSThierry Reding d-cache-size = <65536>; 2907b45d322cSThierry Reding d-cache-line-size = <64>; 2908b45d322cSThierry Reding d-cache-sets = <256>; 2909b45d322cSThierry Reding next-level-cache = <&l2c_0>; 29107780a034SMikko Perttunen }; 29117780a034SMikko Perttunen 2912b45d322cSThierry Reding cpu1_0: cpu@100 { 291331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29147780a034SMikko Perttunen device_type = "cpu"; 29157780a034SMikko Perttunen reg = <0x100>; 29167780a034SMikko Perttunen enable-method = "psci"; 2917b45d322cSThierry Reding i-cache-size = <131072>; 2918b45d322cSThierry Reding i-cache-line-size = <64>; 2919b45d322cSThierry Reding i-cache-sets = <512>; 2920b45d322cSThierry Reding d-cache-size = <65536>; 2921b45d322cSThierry Reding d-cache-line-size = <64>; 2922b45d322cSThierry Reding d-cache-sets = <256>; 2923b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29247780a034SMikko Perttunen }; 29257780a034SMikko Perttunen 2926b45d322cSThierry Reding cpu1_1: cpu@101 { 292731af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29287780a034SMikko Perttunen device_type = "cpu"; 29297780a034SMikko Perttunen reg = <0x101>; 29307780a034SMikko Perttunen enable-method = "psci"; 2931b45d322cSThierry Reding i-cache-size = <131072>; 2932b45d322cSThierry Reding i-cache-line-size = <64>; 2933b45d322cSThierry Reding i-cache-sets = <512>; 2934b45d322cSThierry Reding d-cache-size = <65536>; 2935b45d322cSThierry Reding d-cache-line-size = <64>; 2936b45d322cSThierry Reding d-cache-sets = <256>; 2937b45d322cSThierry Reding next-level-cache = <&l2c_1>; 29387780a034SMikko Perttunen }; 29397780a034SMikko Perttunen 2940b45d322cSThierry Reding cpu2_0: cpu@200 { 294131af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29427780a034SMikko Perttunen device_type = "cpu"; 29437780a034SMikko Perttunen reg = <0x200>; 29447780a034SMikko Perttunen enable-method = "psci"; 2945b45d322cSThierry Reding i-cache-size = <131072>; 2946b45d322cSThierry Reding i-cache-line-size = <64>; 2947b45d322cSThierry Reding i-cache-sets = <512>; 2948b45d322cSThierry Reding d-cache-size = <65536>; 2949b45d322cSThierry Reding d-cache-line-size = <64>; 2950b45d322cSThierry Reding d-cache-sets = <256>; 2951b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29527780a034SMikko Perttunen }; 29537780a034SMikko Perttunen 2954b45d322cSThierry Reding cpu2_1: cpu@201 { 295531af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29567780a034SMikko Perttunen device_type = "cpu"; 29577780a034SMikko Perttunen reg = <0x201>; 29587780a034SMikko Perttunen enable-method = "psci"; 2959b45d322cSThierry Reding i-cache-size = <131072>; 2960b45d322cSThierry Reding i-cache-line-size = <64>; 2961b45d322cSThierry Reding i-cache-sets = <512>; 2962b45d322cSThierry Reding d-cache-size = <65536>; 2963b45d322cSThierry Reding d-cache-line-size = <64>; 2964b45d322cSThierry Reding d-cache-sets = <256>; 2965b45d322cSThierry Reding next-level-cache = <&l2c_2>; 29667780a034SMikko Perttunen }; 29677780a034SMikko Perttunen 2968b45d322cSThierry Reding cpu3_0: cpu@300 { 296931af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29707780a034SMikko Perttunen device_type = "cpu"; 2971b45d322cSThierry Reding reg = <0x300>; 29727780a034SMikko Perttunen enable-method = "psci"; 2973b45d322cSThierry Reding i-cache-size = <131072>; 2974b45d322cSThierry Reding i-cache-line-size = <64>; 2975b45d322cSThierry Reding i-cache-sets = <512>; 2976b45d322cSThierry Reding d-cache-size = <65536>; 2977b45d322cSThierry Reding d-cache-line-size = <64>; 2978b45d322cSThierry Reding d-cache-sets = <256>; 2979b45d322cSThierry Reding next-level-cache = <&l2c_3>; 29807780a034SMikko Perttunen }; 29817780a034SMikko Perttunen 2982b45d322cSThierry Reding cpu3_1: cpu@301 { 298331af04cdSRob Herring compatible = "nvidia,tegra194-carmel"; 29847780a034SMikko Perttunen device_type = "cpu"; 2985b45d322cSThierry Reding reg = <0x301>; 29867780a034SMikko Perttunen enable-method = "psci"; 2987b45d322cSThierry Reding i-cache-size = <131072>; 2988b45d322cSThierry Reding i-cache-line-size = <64>; 2989b45d322cSThierry Reding i-cache-sets = <512>; 2990b45d322cSThierry Reding d-cache-size = <65536>; 2991b45d322cSThierry Reding d-cache-line-size = <64>; 2992b45d322cSThierry Reding d-cache-sets = <256>; 2993b45d322cSThierry Reding next-level-cache = <&l2c_3>; 2994b45d322cSThierry Reding }; 2995b45d322cSThierry Reding 2996b45d322cSThierry Reding cpu-map { 2997b45d322cSThierry Reding cluster0 { 2998b45d322cSThierry Reding core0 { 2999b45d322cSThierry Reding cpu = <&cpu0_0>; 3000b45d322cSThierry Reding }; 3001b45d322cSThierry Reding 3002b45d322cSThierry Reding core1 { 3003b45d322cSThierry Reding cpu = <&cpu0_1>; 3004b45d322cSThierry Reding }; 3005b45d322cSThierry Reding }; 3006b45d322cSThierry Reding 3007b45d322cSThierry Reding cluster1 { 3008b45d322cSThierry Reding core0 { 3009b45d322cSThierry Reding cpu = <&cpu1_0>; 3010b45d322cSThierry Reding }; 3011b45d322cSThierry Reding 3012b45d322cSThierry Reding core1 { 3013b45d322cSThierry Reding cpu = <&cpu1_1>; 3014b45d322cSThierry Reding }; 3015b45d322cSThierry Reding }; 3016b45d322cSThierry Reding 3017b45d322cSThierry Reding cluster2 { 3018b45d322cSThierry Reding core0 { 3019b45d322cSThierry Reding cpu = <&cpu2_0>; 3020b45d322cSThierry Reding }; 3021b45d322cSThierry Reding 3022b45d322cSThierry Reding core1 { 3023b45d322cSThierry Reding cpu = <&cpu2_1>; 3024b45d322cSThierry Reding }; 3025b45d322cSThierry Reding }; 3026b45d322cSThierry Reding 3027b45d322cSThierry Reding cluster3 { 3028b45d322cSThierry Reding core0 { 3029b45d322cSThierry Reding cpu = <&cpu3_0>; 3030b45d322cSThierry Reding }; 3031b45d322cSThierry Reding 3032b45d322cSThierry Reding core1 { 3033b45d322cSThierry Reding cpu = <&cpu3_1>; 3034b45d322cSThierry Reding }; 3035b45d322cSThierry Reding }; 3036b45d322cSThierry Reding }; 3037b45d322cSThierry Reding 3038b45d322cSThierry Reding l2c_0: l2-cache0 { 303927f1568bSPierre Gondois compatible = "cache"; 304027f1568bSPierre Gondois cache-unified; 3041b45d322cSThierry Reding cache-size = <2097152>; 3042b45d322cSThierry Reding cache-line-size = <64>; 3043b45d322cSThierry Reding cache-sets = <2048>; 304427f1568bSPierre Gondois cache-level = <2>; 3045b45d322cSThierry Reding next-level-cache = <&l3c>; 3046b45d322cSThierry Reding }; 3047b45d322cSThierry Reding 3048b45d322cSThierry Reding l2c_1: l2-cache1 { 304927f1568bSPierre Gondois compatible = "cache"; 305027f1568bSPierre Gondois cache-unified; 3051b45d322cSThierry Reding cache-size = <2097152>; 3052b45d322cSThierry Reding cache-line-size = <64>; 3053b45d322cSThierry Reding cache-sets = <2048>; 305427f1568bSPierre Gondois cache-level = <2>; 3055b45d322cSThierry Reding next-level-cache = <&l3c>; 3056b45d322cSThierry Reding }; 3057b45d322cSThierry Reding 3058b45d322cSThierry Reding l2c_2: l2-cache2 { 305927f1568bSPierre Gondois compatible = "cache"; 306027f1568bSPierre Gondois cache-unified; 3061b45d322cSThierry Reding cache-size = <2097152>; 3062b45d322cSThierry Reding cache-line-size = <64>; 3063b45d322cSThierry Reding cache-sets = <2048>; 306427f1568bSPierre Gondois cache-level = <2>; 3065b45d322cSThierry Reding next-level-cache = <&l3c>; 3066b45d322cSThierry Reding }; 3067b45d322cSThierry Reding 3068b45d322cSThierry Reding l2c_3: l2-cache3 { 306927f1568bSPierre Gondois compatible = "cache"; 307027f1568bSPierre Gondois cache-unified; 3071b45d322cSThierry Reding cache-size = <2097152>; 3072b45d322cSThierry Reding cache-line-size = <64>; 3073b45d322cSThierry Reding cache-sets = <2048>; 307427f1568bSPierre Gondois cache-level = <2>; 3075b45d322cSThierry Reding next-level-cache = <&l3c>; 3076b45d322cSThierry Reding }; 3077b45d322cSThierry Reding 3078b45d322cSThierry Reding l3c: l3-cache { 307927f1568bSPierre Gondois compatible = "cache"; 308027f1568bSPierre Gondois cache-unified; 3081b45d322cSThierry Reding cache-size = <4194304>; 3082b45d322cSThierry Reding cache-line-size = <64>; 308327f1568bSPierre Gondois cache-level = <3>; 3084b45d322cSThierry Reding cache-sets = <4096>; 30857780a034SMikko Perttunen }; 30867780a034SMikko Perttunen }; 30877780a034SMikko Perttunen 30889e79e58fSJon Hunter pmu { 3089f0a48120SThierry Reding compatible = "nvidia,carmel-pmu"; 30909e79e58fSJon Hunter interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 30919e79e58fSJon Hunter <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 30929e79e58fSJon Hunter <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 30939e79e58fSJon Hunter <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 30949e79e58fSJon Hunter <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 30959e79e58fSJon Hunter <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 30969e79e58fSJon Hunter <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 30979e79e58fSJon Hunter <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 30989e79e58fSJon Hunter interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 30999e79e58fSJon Hunter &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 31009e79e58fSJon Hunter }; 31019e79e58fSJon Hunter 31027780a034SMikko Perttunen psci { 31037780a034SMikko Perttunen compatible = "arm,psci-1.0"; 31047780a034SMikko Perttunen status = "okay"; 31057780a034SMikko Perttunen method = "smc"; 31067780a034SMikko Perttunen }; 31077780a034SMikko Perttunen 310879ed18d9SThierry Reding tcu: serial { 310979ed18d9SThierry Reding compatible = "nvidia,tegra194-tcu"; 311079ed18d9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 311179ed18d9SThierry Reding <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 311279ed18d9SThierry Reding mbox-names = "rx", "tx"; 311379ed18d9SThierry Reding }; 311479ed18d9SThierry Reding 31155b4f6323SSameer Pujar sound { 31165b4f6323SSameer Pujar status = "disabled"; 31175b4f6323SSameer Pujar 31185b4f6323SSameer Pujar clocks = <&bpmp TEGRA194_CLK_PLLA>, 31195b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31205b4f6323SSameer Pujar clock-names = "pll_a", "plla_out0"; 31215b4f6323SSameer Pujar assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 31225b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>, 31235b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_AUD_MCLK>; 31245b4f6323SSameer Pujar assigned-clock-parents = <0>, 31255b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA>, 31265b4f6323SSameer Pujar <&bpmp TEGRA194_CLK_PLLA_OUT0>; 31275b4f6323SSameer Pujar /* 31285b4f6323SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 31295b4f6323SSameer Pujar * for this to work and oscillate between base rates required 31305b4f6323SSameer Pujar * for 8x and 11.025x sample rate streams. 31315b4f6323SSameer Pujar */ 31325b4f6323SSameer Pujar assigned-clock-rates = <258000000>; 31335b4f6323SSameer Pujar }; 31345b4f6323SSameer Pujar 3135686ba009SThierry Reding thermal-zones { 3136fe57ff53SThierry Reding cpu-thermal { 3137fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3138686ba009SThierry Reding status = "disabled"; 3139686ba009SThierry Reding }; 3140686ba009SThierry Reding 3141fe57ff53SThierry Reding gpu-thermal { 3142fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3143686ba009SThierry Reding status = "disabled"; 3144686ba009SThierry Reding }; 3145686ba009SThierry Reding 3146fe57ff53SThierry Reding aux-thermal { 3147fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3148686ba009SThierry Reding status = "disabled"; 3149686ba009SThierry Reding }; 3150686ba009SThierry Reding 3151fe57ff53SThierry Reding pllx-thermal { 3152fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3153686ba009SThierry Reding status = "disabled"; 3154686ba009SThierry Reding }; 3155686ba009SThierry Reding 3156fe57ff53SThierry Reding ao-thermal { 3157fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3158686ba009SThierry Reding status = "disabled"; 3159686ba009SThierry Reding }; 3160686ba009SThierry Reding 3161fe57ff53SThierry Reding tj-thermal { 3162fe57ff53SThierry Reding thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3163686ba009SThierry Reding status = "disabled"; 3164686ba009SThierry Reding }; 3165686ba009SThierry Reding }; 3166686ba009SThierry Reding 31675425fb15SMikko Perttunen timer { 31685425fb15SMikko Perttunen compatible = "arm,armv8-timer"; 31695425fb15SMikko Perttunen interrupts = <GIC_PPI 13 31705425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31715425fb15SMikko Perttunen <GIC_PPI 14 31725425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31735425fb15SMikko Perttunen <GIC_PPI 11 31745425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 31755425fb15SMikko Perttunen <GIC_PPI 10 31765425fb15SMikko Perttunen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 31775425fb15SMikko Perttunen interrupt-parent = <&gic>; 3178b30be673SThierry Reding always-on; 31795425fb15SMikko Perttunen }; 31805425fb15SMikko Perttunen}; 3181