1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 764b154b94SThierry Reding aconnect@2900000 { 775d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 785d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 795d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 805d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 815d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 825d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 835d2249ddSSameer Pujar #address-cells = <1>; 845d2249ddSSameer Pujar #size-cells = <1>; 855d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 865d2249ddSSameer Pujar status = "disabled"; 875d2249ddSSameer Pujar 88177208f7SSameer Pujar adma: dma-controller@2930000 { 895d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 146177208f7SSameer Pujar reg = <0x02900800 0x800>; 147177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 148177208f7SSameer Pujar clock-names = "ahub"; 149177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151177208f7SSameer Pujar #address-cells = <1>; 152177208f7SSameer Pujar #size-cells = <1>; 153177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 154177208f7SSameer Pujar status = "disabled"; 155177208f7SSameer Pujar 156177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 157177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 158177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 159177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 160177208f7SSameer Pujar <&adma 2>, <&adma 2>, 161177208f7SSameer Pujar <&adma 3>, <&adma 3>, 162177208f7SSameer Pujar <&adma 4>, <&adma 4>, 163177208f7SSameer Pujar <&adma 5>, <&adma 5>, 164177208f7SSameer Pujar <&adma 6>, <&adma 6>, 165177208f7SSameer Pujar <&adma 7>, <&adma 7>, 166177208f7SSameer Pujar <&adma 8>, <&adma 8>, 167177208f7SSameer Pujar <&adma 9>, <&adma 9>, 168177208f7SSameer Pujar <&adma 10>, <&adma 10>, 169177208f7SSameer Pujar <&adma 11>, <&adma 11>, 170177208f7SSameer Pujar <&adma 12>, <&adma 12>, 171177208f7SSameer Pujar <&adma 13>, <&adma 13>, 172177208f7SSameer Pujar <&adma 14>, <&adma 14>, 173177208f7SSameer Pujar <&adma 15>, <&adma 15>, 174177208f7SSameer Pujar <&adma 16>, <&adma 16>, 175177208f7SSameer Pujar <&adma 17>, <&adma 17>, 176177208f7SSameer Pujar <&adma 18>, <&adma 18>, 177177208f7SSameer Pujar <&adma 19>, <&adma 19>, 178177208f7SSameer Pujar <&adma 20>, <&adma 20>; 179177208f7SSameer Pujar dma-names = "rx1", "tx1", 180177208f7SSameer Pujar "rx2", "tx2", 181177208f7SSameer Pujar "rx3", "tx3", 182177208f7SSameer Pujar "rx4", "tx4", 183177208f7SSameer Pujar "rx5", "tx5", 184177208f7SSameer Pujar "rx6", "tx6", 185177208f7SSameer Pujar "rx7", "tx7", 186177208f7SSameer Pujar "rx8", "tx8", 187177208f7SSameer Pujar "rx9", "tx9", 188177208f7SSameer Pujar "rx10", "tx10", 189177208f7SSameer Pujar "rx11", "tx11", 190177208f7SSameer Pujar "rx12", "tx12", 191177208f7SSameer Pujar "rx13", "tx13", 192177208f7SSameer Pujar "rx14", "tx14", 193177208f7SSameer Pujar "rx15", "tx15", 194177208f7SSameer Pujar "rx16", "tx16", 195177208f7SSameer Pujar "rx17", "tx17", 196177208f7SSameer Pujar "rx18", "tx18", 197177208f7SSameer Pujar "rx19", "tx19", 198177208f7SSameer Pujar "rx20", "tx20"; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar }; 201177208f7SSameer Pujar 202177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 203177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 204177208f7SSameer Pujar "nvidia,tegra210-i2s"; 205177208f7SSameer Pujar reg = <0x2901000 0x100>; 206177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 207177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 209177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211177208f7SSameer Pujar assigned-clock-rates = <1536000>; 212177208f7SSameer Pujar sound-name-prefix = "I2S1"; 213177208f7SSameer Pujar status = "disabled"; 214177208f7SSameer Pujar }; 215177208f7SSameer Pujar 216177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 217177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 218177208f7SSameer Pujar "nvidia,tegra210-i2s"; 219177208f7SSameer Pujar reg = <0x2901100 0x100>; 220177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 221177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 223177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225177208f7SSameer Pujar assigned-clock-rates = <1536000>; 226177208f7SSameer Pujar sound-name-prefix = "I2S2"; 227177208f7SSameer Pujar status = "disabled"; 228177208f7SSameer Pujar }; 229177208f7SSameer Pujar 230177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 231177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 232177208f7SSameer Pujar "nvidia,tegra210-i2s"; 233177208f7SSameer Pujar reg = <0x2901200 0x100>; 234177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 235177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239177208f7SSameer Pujar assigned-clock-rates = <1536000>; 240177208f7SSameer Pujar sound-name-prefix = "I2S3"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901300 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S4"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901400 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S5"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901500 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S6"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 287177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 288177208f7SSameer Pujar reg = <0x2904000 0x100>; 289177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290177208f7SSameer Pujar clock-names = "dmic"; 291177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293177208f7SSameer Pujar assigned-clock-rates = <3072000>; 294177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 295177208f7SSameer Pujar status = "disabled"; 296177208f7SSameer Pujar }; 297177208f7SSameer Pujar 298177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 299177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 300177208f7SSameer Pujar reg = <0x2904100 0x100>; 301177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302177208f7SSameer Pujar clock-names = "dmic"; 303177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305177208f7SSameer Pujar assigned-clock-rates = <3072000>; 306177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 307177208f7SSameer Pujar status = "disabled"; 308177208f7SSameer Pujar }; 309177208f7SSameer Pujar 310177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 311177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 312177208f7SSameer Pujar reg = <0x2904200 0x100>; 313177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314177208f7SSameer Pujar clock-names = "dmic"; 315177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317177208f7SSameer Pujar assigned-clock-rates = <3072000>; 318177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 319177208f7SSameer Pujar status = "disabled"; 320177208f7SSameer Pujar }; 321177208f7SSameer Pujar 322177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 323177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 324177208f7SSameer Pujar reg = <0x2904300 0x100>; 325177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326177208f7SSameer Pujar clock-names = "dmic"; 327177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329177208f7SSameer Pujar assigned-clock-rates = <3072000>; 330177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 331177208f7SSameer Pujar status = "disabled"; 332177208f7SSameer Pujar }; 333177208f7SSameer Pujar 334177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 335177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 336177208f7SSameer Pujar reg = <0x2905000 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338177208f7SSameer Pujar clock-names = "dspk"; 339177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341177208f7SSameer Pujar assigned-clock-rates = <12288000>; 342177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 343177208f7SSameer Pujar status = "disabled"; 344177208f7SSameer Pujar }; 345177208f7SSameer Pujar 346177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 347177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 348177208f7SSameer Pujar reg = <0x2905100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350177208f7SSameer Pujar clock-names = "dspk"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <12288000>; 354177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357848f3290SSameer Pujar 358848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 359848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 360848f3290SSameer Pujar "nvidia,tegra210-sfc"; 361848f3290SSameer Pujar reg = <0x2902000 0x200>; 362848f3290SSameer Pujar sound-name-prefix = "SFC1"; 363848f3290SSameer Pujar status = "disabled"; 364848f3290SSameer Pujar }; 365848f3290SSameer Pujar 366848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 367848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 368848f3290SSameer Pujar "nvidia,tegra210-sfc"; 369848f3290SSameer Pujar reg = <0x2902200 0x200>; 370848f3290SSameer Pujar sound-name-prefix = "SFC2"; 371848f3290SSameer Pujar status = "disabled"; 372848f3290SSameer Pujar }; 373848f3290SSameer Pujar 374848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 375848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 376848f3290SSameer Pujar "nvidia,tegra210-sfc"; 377848f3290SSameer Pujar reg = <0x2902400 0x200>; 378848f3290SSameer Pujar sound-name-prefix = "SFC3"; 379848f3290SSameer Pujar status = "disabled"; 380848f3290SSameer Pujar }; 381848f3290SSameer Pujar 382848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 383848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 384848f3290SSameer Pujar "nvidia,tegra210-sfc"; 385848f3290SSameer Pujar reg = <0x2902600 0x200>; 386848f3290SSameer Pujar sound-name-prefix = "SFC4"; 387848f3290SSameer Pujar status = "disabled"; 388848f3290SSameer Pujar }; 389848f3290SSameer Pujar 390848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 391848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 392848f3290SSameer Pujar "nvidia,tegra210-mvc"; 393848f3290SSameer Pujar reg = <0x290a000 0x200>; 394848f3290SSameer Pujar sound-name-prefix = "MVC1"; 395848f3290SSameer Pujar status = "disabled"; 396848f3290SSameer Pujar }; 397848f3290SSameer Pujar 398848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 399848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 400848f3290SSameer Pujar "nvidia,tegra210-mvc"; 401848f3290SSameer Pujar reg = <0x290a200 0x200>; 402848f3290SSameer Pujar sound-name-prefix = "MVC2"; 403848f3290SSameer Pujar status = "disabled"; 404848f3290SSameer Pujar }; 405848f3290SSameer Pujar 406848f3290SSameer Pujar tegra_amx1: amx@2903000 { 407848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 408848f3290SSameer Pujar "nvidia,tegra210-amx"; 409848f3290SSameer Pujar reg = <0x2903000 0x100>; 410848f3290SSameer Pujar sound-name-prefix = "AMX1"; 411848f3290SSameer Pujar status = "disabled"; 412848f3290SSameer Pujar }; 413848f3290SSameer Pujar 414848f3290SSameer Pujar tegra_amx2: amx@2903100 { 415848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 416848f3290SSameer Pujar "nvidia,tegra210-amx"; 417848f3290SSameer Pujar reg = <0x2903100 0x100>; 418848f3290SSameer Pujar sound-name-prefix = "AMX2"; 419848f3290SSameer Pujar status = "disabled"; 420848f3290SSameer Pujar }; 421848f3290SSameer Pujar 422848f3290SSameer Pujar tegra_amx3: amx@2903200 { 423848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 424848f3290SSameer Pujar "nvidia,tegra210-amx"; 425848f3290SSameer Pujar reg = <0x2903200 0x100>; 426848f3290SSameer Pujar sound-name-prefix = "AMX3"; 427848f3290SSameer Pujar status = "disabled"; 428848f3290SSameer Pujar }; 429848f3290SSameer Pujar 430848f3290SSameer Pujar tegra_amx4: amx@2903300 { 431848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 432848f3290SSameer Pujar "nvidia,tegra210-amx"; 433848f3290SSameer Pujar reg = <0x2903300 0x100>; 434848f3290SSameer Pujar sound-name-prefix = "AMX4"; 435848f3290SSameer Pujar status = "disabled"; 436848f3290SSameer Pujar }; 437848f3290SSameer Pujar 438848f3290SSameer Pujar tegra_adx1: adx@2903800 { 439848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 440848f3290SSameer Pujar "nvidia,tegra210-adx"; 441848f3290SSameer Pujar reg = <0x2903800 0x100>; 442848f3290SSameer Pujar sound-name-prefix = "ADX1"; 443848f3290SSameer Pujar status = "disabled"; 444848f3290SSameer Pujar }; 445848f3290SSameer Pujar 446848f3290SSameer Pujar tegra_adx2: adx@2903900 { 447848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 448848f3290SSameer Pujar "nvidia,tegra210-adx"; 449848f3290SSameer Pujar reg = <0x2903900 0x100>; 450848f3290SSameer Pujar sound-name-prefix = "ADX2"; 451848f3290SSameer Pujar status = "disabled"; 452848f3290SSameer Pujar }; 453848f3290SSameer Pujar 454848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 455848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 456848f3290SSameer Pujar "nvidia,tegra210-adx"; 457848f3290SSameer Pujar reg = <0x2903a00 0x100>; 458848f3290SSameer Pujar sound-name-prefix = "ADX3"; 459848f3290SSameer Pujar status = "disabled"; 460848f3290SSameer Pujar }; 461848f3290SSameer Pujar 462848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 463848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 464848f3290SSameer Pujar "nvidia,tegra210-adx"; 465848f3290SSameer Pujar reg = <0x2903b00 0x100>; 466848f3290SSameer Pujar sound-name-prefix = "ADX4"; 467848f3290SSameer Pujar status = "disabled"; 468848f3290SSameer Pujar }; 469848f3290SSameer Pujar 470848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 471848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 472848f3290SSameer Pujar "nvidia,tegra210-amixer"; 473848f3290SSameer Pujar reg = <0x290bb00 0x800>; 474848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 475848f3290SSameer Pujar status = "disabled"; 476848f3290SSameer Pujar }; 477177208f7SSameer Pujar }; 4785d2249ddSSameer Pujar }; 4795d2249ddSSameer Pujar 480954490b3SThierry Reding mc: memory-controller@2c00000 { 481d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 482d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 483b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 484d25a3bf1SThierry Reding status = "disabled"; 4853f6eaef9SThierry Reding 486954490b3SThierry Reding #interconnect-cells = <1>; 4873f6eaef9SThierry Reding #address-cells = <2>; 4883f6eaef9SThierry Reding #size-cells = <2>; 4893f6eaef9SThierry Reding 4903f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 4913f6eaef9SThierry Reding 4923f6eaef9SThierry Reding /* 4933f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 4943f6eaef9SThierry Reding * controller can address. 4953f6eaef9SThierry Reding */ 4963f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 4973f6eaef9SThierry Reding 4983f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 4993f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5003f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5013f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5023f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5033f6eaef9SThierry Reding clock-names = "emc"; 5043f6eaef9SThierry Reding 505954490b3SThierry Reding #interconnect-cells = <0>; 506954490b3SThierry Reding 5073f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5083f6eaef9SThierry Reding }; 509d25a3bf1SThierry Reding }; 510d25a3bf1SThierry Reding 511bd1fefcbSThierry Reding timer@3010000 { 512bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 513bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 514bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 515bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 516bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 517bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 518bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 519bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 520bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 521bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 522bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 523bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 524bd1fefcbSThierry Reding status = "disabled"; 525bd1fefcbSThierry Reding }; 526bd1fefcbSThierry Reding 52739cb62cbSJoseph Lo uarta: serial@3100000 { 52839cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 52939cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 53039cb62cbSJoseph Lo reg-shift = <2>; 53139cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 532c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 533a7a77e2eSThierry Reding clock-names = "serial"; 5347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 535a7a77e2eSThierry Reding reset-names = "serial"; 536a7a77e2eSThierry Reding status = "disabled"; 537a7a77e2eSThierry Reding }; 538a7a77e2eSThierry Reding 539a7a77e2eSThierry Reding uartb: serial@3110000 { 540a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 541a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 542a7a77e2eSThierry Reding reg-shift = <2>; 543a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 544c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 545a7a77e2eSThierry Reding clock-names = "serial"; 5467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 547a7a77e2eSThierry Reding reset-names = "serial"; 548a7a77e2eSThierry Reding status = "disabled"; 549a7a77e2eSThierry Reding }; 550a7a77e2eSThierry Reding 551a7a77e2eSThierry Reding uartd: serial@3130000 { 552a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 553a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 554a7a77e2eSThierry Reding reg-shift = <2>; 555a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 556c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 557a7a77e2eSThierry Reding clock-names = "serial"; 5587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 559a7a77e2eSThierry Reding reset-names = "serial"; 560a7a77e2eSThierry Reding status = "disabled"; 561a7a77e2eSThierry Reding }; 562a7a77e2eSThierry Reding 563a7a77e2eSThierry Reding uarte: serial@3140000 { 564a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 565a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 566a7a77e2eSThierry Reding reg-shift = <2>; 567a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 568c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 569a7a77e2eSThierry Reding clock-names = "serial"; 5707bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 571a7a77e2eSThierry Reding reset-names = "serial"; 572a7a77e2eSThierry Reding status = "disabled"; 573a7a77e2eSThierry Reding }; 574a7a77e2eSThierry Reding 575a7a77e2eSThierry Reding uartf: serial@3150000 { 576a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 577a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 578a7a77e2eSThierry Reding reg-shift = <2>; 579a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 580c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 581a7a77e2eSThierry Reding clock-names = "serial"; 5827bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 583a7a77e2eSThierry Reding reset-names = "serial"; 58439cb62cbSJoseph Lo status = "disabled"; 58539cb62cbSJoseph Lo }; 58639cb62cbSJoseph Lo 58740cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 588250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 58940cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 59040cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 59140cc83b3SThierry Reding #address-cells = <1>; 59240cc83b3SThierry Reding #size-cells = <0>; 593c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 59440cc83b3SThierry Reding clock-names = "div-clk"; 5957bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 59640cc83b3SThierry Reding reset-names = "i2c"; 59740cc83b3SThierry Reding status = "disabled"; 59840cc83b3SThierry Reding }; 59940cc83b3SThierry Reding 60040cc83b3SThierry Reding cam_i2c: i2c@3180000 { 601250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 60240cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 60340cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 60440cc83b3SThierry Reding #address-cells = <1>; 60540cc83b3SThierry Reding #size-cells = <0>; 606c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 60740cc83b3SThierry Reding clock-names = "div-clk"; 6087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 60940cc83b3SThierry Reding reset-names = "i2c"; 61040cc83b3SThierry Reding status = "disabled"; 61140cc83b3SThierry Reding }; 61240cc83b3SThierry Reding 61340cc83b3SThierry Reding /* shares pads with dpaux1 */ 61440cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 615250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 61640cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 61740cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 61840cc83b3SThierry Reding #address-cells = <1>; 61940cc83b3SThierry Reding #size-cells = <0>; 620c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 62140cc83b3SThierry Reding clock-names = "div-clk"; 6227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 62340cc83b3SThierry Reding reset-names = "i2c"; 624846137c6SThierry Reding pinctrl-names = "default", "idle"; 625846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 626846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 62740cc83b3SThierry Reding status = "disabled"; 62840cc83b3SThierry Reding }; 62940cc83b3SThierry Reding 63040cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 63140cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 632250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 63340cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 63440cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 63540cc83b3SThierry Reding #address-cells = <1>; 63640cc83b3SThierry Reding #size-cells = <0>; 637c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 63840cc83b3SThierry Reding clock-names = "div-clk"; 6397bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 64040cc83b3SThierry Reding reset-names = "i2c"; 64140cc83b3SThierry Reding status = "disabled"; 64240cc83b3SThierry Reding }; 64340cc83b3SThierry Reding 64440cc83b3SThierry Reding /* shares pads with dpaux0 */ 64540cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 646250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 64740cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 64840cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 64940cc83b3SThierry Reding #address-cells = <1>; 65040cc83b3SThierry Reding #size-cells = <0>; 651c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 65240cc83b3SThierry Reding clock-names = "div-clk"; 6537bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 65440cc83b3SThierry Reding reset-names = "i2c"; 655846137c6SThierry Reding pinctrl-names = "default", "idle"; 656846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 657846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 65840cc83b3SThierry Reding status = "disabled"; 65940cc83b3SThierry Reding }; 66040cc83b3SThierry Reding 66140cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 662250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 66340cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 66440cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 66540cc83b3SThierry Reding #address-cells = <1>; 66640cc83b3SThierry Reding #size-cells = <0>; 667c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 66840cc83b3SThierry Reding clock-names = "div-clk"; 6697bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 67040cc83b3SThierry Reding reset-names = "i2c"; 67140cc83b3SThierry Reding status = "disabled"; 67240cc83b3SThierry Reding }; 67340cc83b3SThierry Reding 67440cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 675250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 67640cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 67740cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 67840cc83b3SThierry Reding #address-cells = <1>; 67940cc83b3SThierry Reding #size-cells = <0>; 680c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 68140cc83b3SThierry Reding clock-names = "div-clk"; 6827bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 68340cc83b3SThierry Reding reset-names = "i2c"; 68440cc83b3SThierry Reding status = "disabled"; 68540cc83b3SThierry Reding }; 68640cc83b3SThierry Reding 687913f8ad4SThierry Reding pwm1: pwm@3280000 { 688913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 689913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 690913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 691913f8ad4SThierry Reding clock-names = "pwm"; 692913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 693913f8ad4SThierry Reding reset-names = "pwm"; 694913f8ad4SThierry Reding status = "disabled"; 695913f8ad4SThierry Reding #pwm-cells = <2>; 696913f8ad4SThierry Reding }; 697913f8ad4SThierry Reding 698913f8ad4SThierry Reding pwm2: pwm@3290000 { 699913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 700913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 701913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 702913f8ad4SThierry Reding clock-names = "pwm"; 703913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 704913f8ad4SThierry Reding reset-names = "pwm"; 705913f8ad4SThierry Reding status = "disabled"; 706913f8ad4SThierry Reding #pwm-cells = <2>; 707913f8ad4SThierry Reding }; 708913f8ad4SThierry Reding 709913f8ad4SThierry Reding pwm3: pwm@32a0000 { 710913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 711913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 712913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 713913f8ad4SThierry Reding clock-names = "pwm"; 714913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 715913f8ad4SThierry Reding reset-names = "pwm"; 716913f8ad4SThierry Reding status = "disabled"; 717913f8ad4SThierry Reding #pwm-cells = <2>; 718913f8ad4SThierry Reding }; 719913f8ad4SThierry Reding 720913f8ad4SThierry Reding pwm5: pwm@32c0000 { 721913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 722913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 723913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 724913f8ad4SThierry Reding clock-names = "pwm"; 725913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 726913f8ad4SThierry Reding reset-names = "pwm"; 727913f8ad4SThierry Reding status = "disabled"; 728913f8ad4SThierry Reding #pwm-cells = <2>; 729913f8ad4SThierry Reding }; 730913f8ad4SThierry Reding 731913f8ad4SThierry Reding pwm6: pwm@32d0000 { 732913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 733913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 734913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 735913f8ad4SThierry Reding clock-names = "pwm"; 736913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 737913f8ad4SThierry Reding reset-names = "pwm"; 738913f8ad4SThierry Reding status = "disabled"; 739913f8ad4SThierry Reding #pwm-cells = <2>; 740913f8ad4SThierry Reding }; 741913f8ad4SThierry Reding 742913f8ad4SThierry Reding pwm7: pwm@32e0000 { 743913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 744913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 745913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 746913f8ad4SThierry Reding clock-names = "pwm"; 747913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 748913f8ad4SThierry Reding reset-names = "pwm"; 749913f8ad4SThierry Reding status = "disabled"; 750913f8ad4SThierry Reding #pwm-cells = <2>; 751913f8ad4SThierry Reding }; 752913f8ad4SThierry Reding 753913f8ad4SThierry Reding pwm8: pwm@32f0000 { 754913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 755913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 756913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 757913f8ad4SThierry Reding clock-names = "pwm"; 758913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 759913f8ad4SThierry Reding reset-names = "pwm"; 760913f8ad4SThierry Reding status = "disabled"; 761913f8ad4SThierry Reding #pwm-cells = <2>; 762913f8ad4SThierry Reding }; 763913f8ad4SThierry Reding 76467bb17f6SThierry Reding sdmmc1: mmc@3400000 { 76599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 76699425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 76799425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 768baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 769baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 770baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 77299425dfdSThierry Reding reset-names = "sdhci"; 773954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 774954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 775954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 7768589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 77724005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 77824005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 77924005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 78041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 78141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 78241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 78341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 78441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 78541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 7866f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 7876f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 78898a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 78998a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 79098a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 79199425dfdSThierry Reding status = "disabled"; 79299425dfdSThierry Reding }; 79399425dfdSThierry Reding 79467bb17f6SThierry Reding sdmmc2: mmc@3420000 { 79599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 79699425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 79799425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 798baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 799baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 800baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 80299425dfdSThierry Reding reset-names = "sdhci"; 803954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 804954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 805954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8068589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 80724005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 80824005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 80924005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 81041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 81141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 81241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 81341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8146f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8156f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 81699425dfdSThierry Reding status = "disabled"; 81799425dfdSThierry Reding }; 81899425dfdSThierry Reding 81967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 82099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 82199425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 82299425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 823baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 824baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 825baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 82799425dfdSThierry Reding reset-names = "sdhci"; 828954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 829954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 830954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8318589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 83224005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 83324005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 83424005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 83541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 83641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 83741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 83841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 83941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 84041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8416f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8426f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 84399425dfdSThierry Reding status = "disabled"; 84499425dfdSThierry Reding }; 84599425dfdSThierry Reding 84667bb17f6SThierry Reding sdmmc4: mmc@3460000 { 84799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 84899425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 84999425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 850baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 851baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 852baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 85398a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 85498a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 85598a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 8567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 85799425dfdSThierry Reding reset-names = "sdhci"; 858954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 859954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 860954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8618589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 86241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 86341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 86441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 86541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 8664e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 8674e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 868e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 869e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 87022248e91SAapo Vienamo nvidia,dqs-trim = <63>; 871207f60baSAapo Vienamo mmc-hs400-1_8v; 872c4307836SSowjanya Komatineni supports-cqe; 87399425dfdSThierry Reding status = "disabled"; 87499425dfdSThierry Reding }; 87599425dfdSThierry Reding 876b066a310SThierry Reding hda@3510000 { 877b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 878b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 879b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 880b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 881b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 882b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 883b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 884b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 885b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 886b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 887b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 888b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 889954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 890954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 891954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 892dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 893b066a310SThierry Reding status = "disabled"; 894b066a310SThierry Reding }; 895b066a310SThierry Reding 8968bfde518SThierry Reding padctl: padctl@3520000 { 8978bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 8988bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 8998bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 9008bfde518SThierry Reding reg-names = "padctl", "ao"; 9016450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 9028bfde518SThierry Reding 9038bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 9048bfde518SThierry Reding reset-names = "padctl"; 9058bfde518SThierry Reding 9068bfde518SThierry Reding status = "disabled"; 9078bfde518SThierry Reding 9088bfde518SThierry Reding pads { 9098bfde518SThierry Reding usb2 { 9108bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 9118bfde518SThierry Reding clock-names = "trk"; 9128bfde518SThierry Reding status = "disabled"; 9138bfde518SThierry Reding 9148bfde518SThierry Reding lanes { 9158bfde518SThierry Reding usb2-0 { 9168bfde518SThierry Reding status = "disabled"; 9178bfde518SThierry Reding #phy-cells = <0>; 9188bfde518SThierry Reding }; 9198bfde518SThierry Reding 9208bfde518SThierry Reding usb2-1 { 9218bfde518SThierry Reding status = "disabled"; 9228bfde518SThierry Reding #phy-cells = <0>; 9238bfde518SThierry Reding }; 9248bfde518SThierry Reding 9258bfde518SThierry Reding usb2-2 { 9268bfde518SThierry Reding status = "disabled"; 9278bfde518SThierry Reding #phy-cells = <0>; 9288bfde518SThierry Reding }; 9298bfde518SThierry Reding }; 9308bfde518SThierry Reding }; 9318bfde518SThierry Reding 9328bfde518SThierry Reding hsic { 9338bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 9348bfde518SThierry Reding clock-names = "trk"; 9358bfde518SThierry Reding status = "disabled"; 9368bfde518SThierry Reding 9378bfde518SThierry Reding lanes { 9388bfde518SThierry Reding hsic-0 { 9398bfde518SThierry Reding status = "disabled"; 9408bfde518SThierry Reding #phy-cells = <0>; 9418bfde518SThierry Reding }; 9428bfde518SThierry Reding }; 9438bfde518SThierry Reding }; 9448bfde518SThierry Reding 9458bfde518SThierry Reding usb3 { 9468bfde518SThierry Reding status = "disabled"; 9478bfde518SThierry Reding 9488bfde518SThierry Reding lanes { 9498bfde518SThierry Reding usb3-0 { 9508bfde518SThierry Reding status = "disabled"; 9518bfde518SThierry Reding #phy-cells = <0>; 9528bfde518SThierry Reding }; 9538bfde518SThierry Reding 9548bfde518SThierry Reding usb3-1 { 9558bfde518SThierry Reding status = "disabled"; 9568bfde518SThierry Reding #phy-cells = <0>; 9578bfde518SThierry Reding }; 9588bfde518SThierry Reding 9598bfde518SThierry Reding usb3-2 { 9608bfde518SThierry Reding status = "disabled"; 9618bfde518SThierry Reding #phy-cells = <0>; 9628bfde518SThierry Reding }; 9638bfde518SThierry Reding }; 9648bfde518SThierry Reding }; 9658bfde518SThierry Reding }; 9668bfde518SThierry Reding 9678bfde518SThierry Reding ports { 9688bfde518SThierry Reding usb2-0 { 9698bfde518SThierry Reding status = "disabled"; 9708bfde518SThierry Reding }; 9718bfde518SThierry Reding 9728bfde518SThierry Reding usb2-1 { 9738bfde518SThierry Reding status = "disabled"; 9748bfde518SThierry Reding }; 9758bfde518SThierry Reding 9768bfde518SThierry Reding usb2-2 { 9778bfde518SThierry Reding status = "disabled"; 9788bfde518SThierry Reding }; 9798bfde518SThierry Reding 9808bfde518SThierry Reding hsic-0 { 9818bfde518SThierry Reding status = "disabled"; 9828bfde518SThierry Reding }; 9838bfde518SThierry Reding 9848bfde518SThierry Reding usb3-0 { 9858bfde518SThierry Reding status = "disabled"; 9868bfde518SThierry Reding }; 9878bfde518SThierry Reding 9888bfde518SThierry Reding usb3-1 { 9898bfde518SThierry Reding status = "disabled"; 9908bfde518SThierry Reding }; 9918bfde518SThierry Reding 9928bfde518SThierry Reding usb3-2 { 9938bfde518SThierry Reding status = "disabled"; 9948bfde518SThierry Reding }; 9958bfde518SThierry Reding }; 9968bfde518SThierry Reding }; 9978bfde518SThierry Reding 9988bfde518SThierry Reding usb@3530000 { 9998bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 10008bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 10018bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 10028bfde518SThierry Reding reg-names = "hcd", "fpci"; 10038bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1004a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 10058bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 10068bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 10078bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 10088bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 10098bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10108bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 10118bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 10128bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10138bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 10148bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 10158bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 10168bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 10178bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 10188bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 10198bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1020954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1021954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1022954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 102306c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 10248bfde518SThierry Reding #address-cells = <1>; 10258bfde518SThierry Reding #size-cells = <0>; 102606c6b06fSThierry Reding status = "disabled"; 102706c6b06fSThierry Reding 102806c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 10298bfde518SThierry Reding }; 10308bfde518SThierry Reding 1031584f800cSNagarjuna Kristam usb@3550000 { 1032584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1033584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1034584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1035584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1036584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1037584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1038584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1039584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1040584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1041584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1042d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1043d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1044d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1045584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1046584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1047584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1048584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1049584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1050584f800cSNagarjuna Kristam status = "disabled"; 1051584f800cSNagarjuna Kristam }; 1052584f800cSNagarjuna Kristam 105385593b75SThierry Reding fuse@3820000 { 105485593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 105585593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 105685593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 105785593b75SThierry Reding clock-names = "fuse"; 105885593b75SThierry Reding }; 105985593b75SThierry Reding 106039cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 106139cb62cbSJoseph Lo compatible = "arm,gic-400"; 106239cb62cbSJoseph Lo #interrupt-cells = <3>; 106339cb62cbSJoseph Lo interrupt-controller; 106439cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1065776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1066776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1067776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 106839cb62cbSJoseph Lo interrupts = <GIC_PPI 9 106939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 107039cb62cbSJoseph Lo interrupt-parent = <&gic>; 107139cb62cbSJoseph Lo }; 107239cb62cbSJoseph Lo 107397cf683cSThierry Reding cec@3960000 { 107497cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 107597cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 107697cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 107797cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 107897cf683cSThierry Reding clock-names = "cec"; 107997cf683cSThierry Reding status = "disabled"; 108097cf683cSThierry Reding }; 108197cf683cSThierry Reding 108239cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 108339cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 108439cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 108539cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 108639cb62cbSJoseph Lo interrupt-names = "doorbell"; 108739cb62cbSJoseph Lo #mbox-cells = <2>; 108839cb62cbSJoseph Lo status = "disabled"; 108939cb62cbSJoseph Lo }; 109039cb62cbSJoseph Lo 109140cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1092250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 109340cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 109440cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 109540cc83b3SThierry Reding #address-cells = <1>; 109640cc83b3SThierry Reding #size-cells = <0>; 1097c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 109840cc83b3SThierry Reding clock-names = "div-clk"; 10997bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 110040cc83b3SThierry Reding reset-names = "i2c"; 110140cc83b3SThierry Reding status = "disabled"; 110240cc83b3SThierry Reding }; 110340cc83b3SThierry Reding 110440cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1105250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 110640cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 110740cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 110840cc83b3SThierry Reding #address-cells = <1>; 110940cc83b3SThierry Reding #size-cells = <0>; 1110c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 111140cc83b3SThierry Reding clock-names = "div-clk"; 11127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 111340cc83b3SThierry Reding reset-names = "i2c"; 111440cc83b3SThierry Reding status = "disabled"; 111540cc83b3SThierry Reding }; 111640cc83b3SThierry Reding 1117a7a77e2eSThierry Reding uartc: serial@c280000 { 1118a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1119a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1120a7a77e2eSThierry Reding reg-shift = <2>; 1121a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1122c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1123a7a77e2eSThierry Reding clock-names = "serial"; 11247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1125a7a77e2eSThierry Reding reset-names = "serial"; 1126a7a77e2eSThierry Reding status = "disabled"; 1127a7a77e2eSThierry Reding }; 1128a7a77e2eSThierry Reding 1129a7a77e2eSThierry Reding uartg: serial@c290000 { 1130a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1131a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1132a7a77e2eSThierry Reding reg-shift = <2>; 1133a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1134c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1135a7a77e2eSThierry Reding clock-names = "serial"; 11367bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1137a7a77e2eSThierry Reding reset-names = "serial"; 1138a7a77e2eSThierry Reding status = "disabled"; 1139a7a77e2eSThierry Reding }; 1140a7a77e2eSThierry Reding 11419733a251SThierry Reding rtc: rtc@c2a0000 { 11429733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 11439733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 11449733a251SThierry Reding interrupt-parent = <&pmc>; 11459733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 11469733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 11479733a251SThierry Reding clock-names = "rtc"; 11489733a251SThierry Reding status = "disabled"; 11499733a251SThierry Reding }; 11509733a251SThierry Reding 1151fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1152fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1153fc4bb754SThierry Reding reg-names = "security", "gpio"; 1154fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1155fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1156fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1157fc4bb754SThierry Reding gpio-controller; 1158fc4bb754SThierry Reding #gpio-cells = <2>; 1159fc4bb754SThierry Reding interrupt-controller; 1160fc4bb754SThierry Reding #interrupt-cells = <2>; 1161fc4bb754SThierry Reding }; 1162fc4bb754SThierry Reding 1163913f8ad4SThierry Reding pwm4: pwm@c340000 { 1164913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1165913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1166913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1167913f8ad4SThierry Reding clock-names = "pwm"; 1168913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1169913f8ad4SThierry Reding reset-names = "pwm"; 1170913f8ad4SThierry Reding status = "disabled"; 1171913f8ad4SThierry Reding #pwm-cells = <2>; 1172913f8ad4SThierry Reding }; 1173913f8ad4SThierry Reding 117432e66e46SThierry Reding pmc: pmc@c360000 { 117573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 117673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 117773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 117873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 117973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 118073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 118124005fd1SAapo Vienamo 118232e66e46SThierry Reding #interrupt-cells = <2>; 118332e66e46SThierry Reding interrupt-controller; 118432e66e46SThierry Reding 118524005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 118624005fd1SAapo Vienamo pins = "sdmmc1-hv"; 118724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 118824005fd1SAapo Vienamo }; 118924005fd1SAapo Vienamo 119024005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 119124005fd1SAapo Vienamo pins = "sdmmc1-hv"; 119224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 119324005fd1SAapo Vienamo }; 119424005fd1SAapo Vienamo 119524005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 119624005fd1SAapo Vienamo pins = "sdmmc2-hv"; 119724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 119824005fd1SAapo Vienamo }; 119924005fd1SAapo Vienamo 120024005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 120124005fd1SAapo Vienamo pins = "sdmmc2-hv"; 120224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 120324005fd1SAapo Vienamo }; 120424005fd1SAapo Vienamo 120524005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 120624005fd1SAapo Vienamo pins = "sdmmc3-hv"; 120724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 120824005fd1SAapo Vienamo }; 120924005fd1SAapo Vienamo 121024005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 121124005fd1SAapo Vienamo pins = "sdmmc3-hv"; 121224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 121324005fd1SAapo Vienamo }; 121473bf90d4SThierry Reding }; 121573bf90d4SThierry Reding 12167b7ef494SMikko Perttunen ccplex@e000000 { 12177b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 12187b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 12197b7ef494SMikko Perttunen 12207b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 12217b7ef494SMikko Perttunen }; 12227b7ef494SMikko Perttunen 1223f8973cf4SManikanta Maddireddy pcie@10003000 { 1224f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1225f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1226f8973cf4SManikanta Maddireddy device_type = "pci"; 1227644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1228644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1229644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1230f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1231f8973cf4SManikanta Maddireddy 1232f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1233f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1234f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1235f8973cf4SManikanta Maddireddy 1236f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1237f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1238f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1239f8973cf4SManikanta Maddireddy 1240f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1241f8973cf4SManikanta Maddireddy #address-cells = <3>; 1242f8973cf4SManikanta Maddireddy #size-cells = <2>; 1243f8973cf4SManikanta Maddireddy 1244644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1245644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1246644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1247644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1248644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1249644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1250f8973cf4SManikanta Maddireddy 125178b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 125278b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1253f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 125478b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1255f8973cf4SManikanta Maddireddy 125678b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 125778b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1258f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 125978b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1260f8973cf4SManikanta Maddireddy 1261954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1262954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1263954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1264954490b3SThierry Reding 1265f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1266f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1267f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1268f2a465e7SThierry Reding 1269f8973cf4SManikanta Maddireddy status = "disabled"; 1270f8973cf4SManikanta Maddireddy 1271f8973cf4SManikanta Maddireddy pci@1,0 { 1272f8973cf4SManikanta Maddireddy device_type = "pci"; 1273f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1274f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1275f8973cf4SManikanta Maddireddy status = "disabled"; 1276f8973cf4SManikanta Maddireddy 1277f8973cf4SManikanta Maddireddy #address-cells = <3>; 1278f8973cf4SManikanta Maddireddy #size-cells = <2>; 1279f8973cf4SManikanta Maddireddy ranges; 1280f8973cf4SManikanta Maddireddy 1281f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1282f8973cf4SManikanta Maddireddy }; 1283f8973cf4SManikanta Maddireddy 1284f8973cf4SManikanta Maddireddy pci@2,0 { 1285f8973cf4SManikanta Maddireddy device_type = "pci"; 1286f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1287f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1288f8973cf4SManikanta Maddireddy status = "disabled"; 1289f8973cf4SManikanta Maddireddy 1290f8973cf4SManikanta Maddireddy #address-cells = <3>; 1291f8973cf4SManikanta Maddireddy #size-cells = <2>; 1292f8973cf4SManikanta Maddireddy ranges; 1293f8973cf4SManikanta Maddireddy 1294f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1295f8973cf4SManikanta Maddireddy }; 1296f8973cf4SManikanta Maddireddy 1297f8973cf4SManikanta Maddireddy pci@3,0 { 1298f8973cf4SManikanta Maddireddy device_type = "pci"; 1299f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1300f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1301f8973cf4SManikanta Maddireddy status = "disabled"; 1302f8973cf4SManikanta Maddireddy 1303f8973cf4SManikanta Maddireddy #address-cells = <3>; 1304f8973cf4SManikanta Maddireddy #size-cells = <2>; 1305f8973cf4SManikanta Maddireddy ranges; 1306f8973cf4SManikanta Maddireddy 1307f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1308f8973cf4SManikanta Maddireddy }; 1309f8973cf4SManikanta Maddireddy }; 1310f8973cf4SManikanta Maddireddy 1311b30a8e61SThierry Reding smmu: iommu@12000000 { 1312bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1313b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1314b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1315b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1316b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1317b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1318b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1319b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1320b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1321b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1322b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1323b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1324b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1325b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1326b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1327b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1328b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1329b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1330b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1331b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1332b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1333b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1334b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1335b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1336b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1337b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1338b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1339b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1340b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1341b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1342b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1343b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1344b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1345b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1346b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1347b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1348b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1349b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1350b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1351b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1352b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1353b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1354b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1355b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1356b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1357b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1358b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1359b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1360b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1361b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1362b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1363b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1364b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1365b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1367b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1379b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1380b30a8e61SThierry Reding #global-interrupts = <1>; 1381b30a8e61SThierry Reding #iommu-cells = <1>; 1382b966d2dbSThierry Reding 1383b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1384b30a8e61SThierry Reding }; 1385b30a8e61SThierry Reding 13865524c61fSMikko Perttunen host1x@13e00000 { 1387ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 13885524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 13895524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 13905524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 13915524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 13925524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1393052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 13945524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 13955524c61fSMikko Perttunen clock-names = "host1x"; 13965524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 13975524c61fSMikko Perttunen reset-names = "host1x"; 13985524c61fSMikko Perttunen 13995524c61fSMikko Perttunen #address-cells = <1>; 14005524c61fSMikko Perttunen #size-cells = <1>; 14015524c61fSMikko Perttunen 14025524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1403954490b3SThierry Reding 1404954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1405954490b3SThierry Reding interconnect-names = "dma-mem"; 1406954490b3SThierry Reding 1407c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1408c2599da7SThierry Reding 1409c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1410c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1411c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1412c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1413c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1414c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1415c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1416c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1417c2599da7SThierry Reding reset-names = "dpaux"; 1418c2599da7SThierry Reding status = "disabled"; 1419c2599da7SThierry Reding 1420c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1421c2599da7SThierry Reding 1422c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1423c2599da7SThierry Reding groups = "dpaux-io"; 1424c2599da7SThierry Reding function = "aux"; 1425c2599da7SThierry Reding }; 1426c2599da7SThierry Reding 1427c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1428c2599da7SThierry Reding groups = "dpaux-io"; 1429c2599da7SThierry Reding function = "i2c"; 1430c2599da7SThierry Reding }; 1431c2599da7SThierry Reding 1432c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1433c2599da7SThierry Reding groups = "dpaux-io"; 1434c2599da7SThierry Reding function = "off"; 1435c2599da7SThierry Reding }; 1436c2599da7SThierry Reding 1437c2599da7SThierry Reding i2c-bus { 1438c2599da7SThierry Reding #address-cells = <1>; 1439c2599da7SThierry Reding #size-cells = <0>; 1440c2599da7SThierry Reding }; 1441c2599da7SThierry Reding }; 1442c2599da7SThierry Reding 1443c2599da7SThierry Reding display-hub@15200000 { 1444aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1445ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1446c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1447c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1448c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1449c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1450c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1451c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1452c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1453c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1454c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1455c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1456c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1457c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1458c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1459c2599da7SThierry Reding status = "disabled"; 1460c2599da7SThierry Reding 1461c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1462c2599da7SThierry Reding 1463c2599da7SThierry Reding #address-cells = <1>; 1464c2599da7SThierry Reding #size-cells = <1>; 1465c2599da7SThierry Reding 1466c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1467c2599da7SThierry Reding 1468c2599da7SThierry Reding display@15200000 { 1469c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1470c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1471c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1472c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1473c2599da7SThierry Reding clock-names = "dc"; 1474c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1475c2599da7SThierry Reding reset-names = "dc"; 1476c2599da7SThierry Reding 1477c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1478954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1479954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1480954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1481c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1482c2599da7SThierry Reding 1483c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1484c2599da7SThierry Reding nvidia,head = <0>; 1485c2599da7SThierry Reding }; 1486c2599da7SThierry Reding 1487c2599da7SThierry Reding display@15210000 { 1488c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1489c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1490c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1491c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1492c2599da7SThierry Reding clock-names = "dc"; 1493c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1494c2599da7SThierry Reding reset-names = "dc"; 1495c2599da7SThierry Reding 1496c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1497954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1498954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1499954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1500c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1501c2599da7SThierry Reding 1502c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1503c2599da7SThierry Reding nvidia,head = <1>; 1504c2599da7SThierry Reding }; 1505c2599da7SThierry Reding 1506c2599da7SThierry Reding display@15220000 { 1507c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1508c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1509c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1510c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1511c2599da7SThierry Reding clock-names = "dc"; 1512c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1513c2599da7SThierry Reding reset-names = "dc"; 1514c2599da7SThierry Reding 1515c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1516954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1517954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1518954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1519c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1520c2599da7SThierry Reding 1521c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1522c2599da7SThierry Reding nvidia,head = <2>; 1523c2599da7SThierry Reding }; 1524c2599da7SThierry Reding }; 1525c2599da7SThierry Reding 1526c2599da7SThierry Reding dsia: dsi@15300000 { 1527c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1528c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1529c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1530c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1531c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1532c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1533c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1534c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1535c2599da7SThierry Reding reset-names = "dsi"; 1536c2599da7SThierry Reding status = "disabled"; 1537c2599da7SThierry Reding 1538c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1539c2599da7SThierry Reding }; 1540effc4b44SMikko Perttunen 1541effc4b44SMikko Perttunen vic@15340000 { 1542effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1543effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1544effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1545effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1546effc4b44SMikko Perttunen clock-names = "vic"; 1547effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1548effc4b44SMikko Perttunen reset-names = "vic"; 1549effc4b44SMikko Perttunen 1550effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1551954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1552954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1553954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 155429ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1555effc4b44SMikko Perttunen }; 1556c2599da7SThierry Reding 1557f7eb2785SJon Hunter nvjpg@15380000 { 1558f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1559f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1560f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1561f7eb2785SJon Hunter clock-names = "nvjpg"; 1562f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1563f7eb2785SJon Hunter reset-names = "nvjpg"; 1564f7eb2785SJon Hunter 1565f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1566f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1567f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1568f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1569f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1570f7eb2785SJon Hunter }; 1571f7eb2785SJon Hunter 1572c2599da7SThierry Reding dsib: dsi@15400000 { 1573c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1574c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1575c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1576c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1577c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1578c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1579c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1580c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1581c2599da7SThierry Reding reset-names = "dsi"; 1582c2599da7SThierry Reding status = "disabled"; 1583c2599da7SThierry Reding 1584c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1585c2599da7SThierry Reding }; 1586c2599da7SThierry Reding 158778a05873SMikko Perttunen nvdec@15480000 { 158878a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 158978a05873SMikko Perttunen reg = <0x15480000 0x40000>; 159078a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 159178a05873SMikko Perttunen clock-names = "nvdec"; 159278a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 159378a05873SMikko Perttunen reset-names = "nvdec"; 159478a05873SMikko Perttunen 159578a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 159678a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 159778a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 159878a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 159978a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 160078a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 160178a05873SMikko Perttunen }; 160278a05873SMikko Perttunen 1603f7eb2785SJon Hunter nvenc@154c0000 { 1604f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1605f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1606f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1607f7eb2785SJon Hunter clock-names = "nvenc"; 1608f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1609f7eb2785SJon Hunter reset-names = "nvenc"; 1610f7eb2785SJon Hunter 1611f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1612f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1613f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1614f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1615f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1616f7eb2785SJon Hunter }; 1617f7eb2785SJon Hunter 1618c2599da7SThierry Reding sor0: sor@15540000 { 1619c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1620c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1621c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1622c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1623c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1624c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1625c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1626c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1627c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1628c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1629c2599da7SThierry Reding "pad"; 1630c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1631c2599da7SThierry Reding reset-names = "sor"; 1632c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1633c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1634c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1635c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1636c2599da7SThierry Reding status = "disabled"; 1637c2599da7SThierry Reding 1638c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1639c2599da7SThierry Reding nvidia,interface = <0>; 1640c2599da7SThierry Reding }; 1641c2599da7SThierry Reding 1642c2599da7SThierry Reding sor1: sor@15580000 { 1643d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1644c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1645c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1646c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1647c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1648c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1649c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1650c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1651c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1652c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1653c2599da7SThierry Reding "pad"; 1654c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1655c2599da7SThierry Reding reset-names = "sor"; 1656c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1657c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1658c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1659c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1660c2599da7SThierry Reding status = "disabled"; 1661c2599da7SThierry Reding 1662c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1663c2599da7SThierry Reding nvidia,interface = <1>; 1664c2599da7SThierry Reding }; 1665c2599da7SThierry Reding 1666c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1667c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1668c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1669c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1670c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1671c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1672c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1673c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1674c2599da7SThierry Reding reset-names = "dpaux"; 1675c2599da7SThierry Reding status = "disabled"; 1676c2599da7SThierry Reding 1677c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1678c2599da7SThierry Reding 1679c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1680c2599da7SThierry Reding groups = "dpaux-io"; 1681c2599da7SThierry Reding function = "aux"; 1682c2599da7SThierry Reding }; 1683c2599da7SThierry Reding 1684c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1685c2599da7SThierry Reding groups = "dpaux-io"; 1686c2599da7SThierry Reding function = "i2c"; 1687c2599da7SThierry Reding }; 1688c2599da7SThierry Reding 1689c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1690c2599da7SThierry Reding groups = "dpaux-io"; 1691c2599da7SThierry Reding function = "off"; 1692c2599da7SThierry Reding }; 1693c2599da7SThierry Reding 1694c2599da7SThierry Reding i2c-bus { 1695c2599da7SThierry Reding #address-cells = <1>; 1696c2599da7SThierry Reding #size-cells = <0>; 1697c2599da7SThierry Reding }; 1698c2599da7SThierry Reding }; 1699c2599da7SThierry Reding 1700c2599da7SThierry Reding padctl@15880000 { 1701c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1702c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1703c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1704c2599da7SThierry Reding reset-names = "dsi"; 1705c2599da7SThierry Reding status = "disabled"; 1706c2599da7SThierry Reding }; 1707c2599da7SThierry Reding 1708c2599da7SThierry Reding dsic: dsi@15900000 { 1709c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1710c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1711c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1712c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1713c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1714c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1715c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1716c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1717c2599da7SThierry Reding reset-names = "dsi"; 1718c2599da7SThierry Reding status = "disabled"; 1719c2599da7SThierry Reding 1720c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1721c2599da7SThierry Reding }; 1722c2599da7SThierry Reding 1723c2599da7SThierry Reding dsid: dsi@15940000 { 1724c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1725c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1726c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1727c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1728c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1729c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1730c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1731c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1732c2599da7SThierry Reding reset-names = "dsi"; 1733c2599da7SThierry Reding status = "disabled"; 1734c2599da7SThierry Reding 1735c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1736c2599da7SThierry Reding }; 17375524c61fSMikko Perttunen }; 17385524c61fSMikko Perttunen 1739dfd7a384SAlexandre Courbot gpu@17000000 { 1740dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1741dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1742dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 174359a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 174459a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1745dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1746dfd7a384SAlexandre Courbot 1747dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1748dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1749dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1750dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1751dfd7a384SAlexandre Courbot reset-names = "gpu"; 1752dfd7a384SAlexandre Courbot status = "disabled"; 1753dfd7a384SAlexandre Courbot 1754dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1755954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1756954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1757954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1758954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1759954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1760dfd7a384SAlexandre Courbot }; 1761dfd7a384SAlexandre Courbot 1762e867fe41SThierry Reding sram@30000000 { 176339cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 176439cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1765aa78032cSThierry Reding #address-cells = <1>; 1766aa78032cSThierry Reding #size-cells = <1>; 1767aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 176839cb62cbSJoseph Lo 1769e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1770aa78032cSThierry Reding reg = <0x4e000 0x1000>; 177139cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 177239cb62cbSJoseph Lo pool; 177339cb62cbSJoseph Lo }; 177439cb62cbSJoseph Lo 1775e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1776aa78032cSThierry Reding reg = <0x4f000 0x1000>; 177739cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 177839cb62cbSJoseph Lo pool; 177939cb62cbSJoseph Lo }; 178039cb62cbSJoseph Lo }; 178139cb62cbSJoseph Lo 1782e061fbdfSSowjanya Komatineni sata@3507000 { 1783e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1784e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1785e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1786e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1787e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1788e061fbdfSSowjanya Komatineni 1789e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1790e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1791e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1792e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1793e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1794e061fbdfSSowjanya Komatineni 1795e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1796e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1797e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1798e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1799e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1800e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1801e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1802e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1803e061fbdfSSowjanya Komatineni <204000000>; 1804e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1805e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1806e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1807e061fbdfSSowjanya Komatineni status = "disabled"; 1808e061fbdfSSowjanya Komatineni }; 1809e061fbdfSSowjanya Komatineni 1810541d7c44SThierry Reding bpmp: bpmp { 1811541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1812954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1813954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1814954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1815954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1816954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1817541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1818541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1819541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 18207fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1821541d7c44SThierry Reding #clock-cells = <1>; 1822541d7c44SThierry Reding #reset-cells = <1>; 1823541d7c44SThierry Reding #power-domain-cells = <1>; 1824541d7c44SThierry Reding 1825541d7c44SThierry Reding bpmp_i2c: i2c { 1826541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1827541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1828541d7c44SThierry Reding #address-cells = <1>; 1829541d7c44SThierry Reding #size-cells = <0>; 1830541d7c44SThierry Reding status = "disabled"; 1831541d7c44SThierry Reding }; 1832541d7c44SThierry Reding 1833541d7c44SThierry Reding bpmp_thermal: thermal { 1834541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1835541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1836541d7c44SThierry Reding }; 1837541d7c44SThierry Reding }; 1838541d7c44SThierry Reding 1839cd6fe32eSThierry Reding cpus { 1840cd6fe32eSThierry Reding #address-cells = <1>; 1841cd6fe32eSThierry Reding #size-cells = <0>; 1842cd6fe32eSThierry Reding 18433b4c1378SMarc Zyngier denver_0: cpu@0 { 184431af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1845cd6fe32eSThierry Reding device_type = "cpu"; 18465298166dSJoseph Lo i-cache-size = <0x20000>; 18475298166dSJoseph Lo i-cache-line-size = <64>; 18485298166dSJoseph Lo i-cache-sets = <512>; 18495298166dSJoseph Lo d-cache-size = <0x10000>; 18505298166dSJoseph Lo d-cache-line-size = <64>; 18515298166dSJoseph Lo d-cache-sets = <256>; 18525298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1853cd6fe32eSThierry Reding reg = <0x000>; 1854cd6fe32eSThierry Reding }; 1855cd6fe32eSThierry Reding 18563b4c1378SMarc Zyngier denver_1: cpu@1 { 185731af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1858cd6fe32eSThierry Reding device_type = "cpu"; 18595298166dSJoseph Lo i-cache-size = <0x20000>; 18605298166dSJoseph Lo i-cache-line-size = <64>; 18615298166dSJoseph Lo i-cache-sets = <512>; 18625298166dSJoseph Lo d-cache-size = <0x10000>; 18635298166dSJoseph Lo d-cache-line-size = <64>; 18645298166dSJoseph Lo d-cache-sets = <256>; 18655298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1866cd6fe32eSThierry Reding reg = <0x001>; 1867cd6fe32eSThierry Reding }; 1868cd6fe32eSThierry Reding 18693b4c1378SMarc Zyngier ca57_0: cpu@2 { 187031af04cdSRob Herring compatible = "arm,cortex-a57"; 1871cd6fe32eSThierry Reding device_type = "cpu"; 18725298166dSJoseph Lo i-cache-size = <0xC000>; 18735298166dSJoseph Lo i-cache-line-size = <64>; 18745298166dSJoseph Lo i-cache-sets = <256>; 18755298166dSJoseph Lo d-cache-size = <0x8000>; 18765298166dSJoseph Lo d-cache-line-size = <64>; 18775298166dSJoseph Lo d-cache-sets = <256>; 18785298166dSJoseph Lo next-level-cache = <&L2_A57>; 1879cd6fe32eSThierry Reding reg = <0x100>; 1880cd6fe32eSThierry Reding }; 1881cd6fe32eSThierry Reding 18823b4c1378SMarc Zyngier ca57_1: cpu@3 { 188331af04cdSRob Herring compatible = "arm,cortex-a57"; 1884cd6fe32eSThierry Reding device_type = "cpu"; 18855298166dSJoseph Lo i-cache-size = <0xC000>; 18865298166dSJoseph Lo i-cache-line-size = <64>; 18875298166dSJoseph Lo i-cache-sets = <256>; 18885298166dSJoseph Lo d-cache-size = <0x8000>; 18895298166dSJoseph Lo d-cache-line-size = <64>; 18905298166dSJoseph Lo d-cache-sets = <256>; 18915298166dSJoseph Lo next-level-cache = <&L2_A57>; 1892cd6fe32eSThierry Reding reg = <0x101>; 1893cd6fe32eSThierry Reding }; 1894cd6fe32eSThierry Reding 18953b4c1378SMarc Zyngier ca57_2: cpu@4 { 189631af04cdSRob Herring compatible = "arm,cortex-a57"; 1897cd6fe32eSThierry Reding device_type = "cpu"; 18985298166dSJoseph Lo i-cache-size = <0xC000>; 18995298166dSJoseph Lo i-cache-line-size = <64>; 19005298166dSJoseph Lo i-cache-sets = <256>; 19015298166dSJoseph Lo d-cache-size = <0x8000>; 19025298166dSJoseph Lo d-cache-line-size = <64>; 19035298166dSJoseph Lo d-cache-sets = <256>; 19045298166dSJoseph Lo next-level-cache = <&L2_A57>; 1905cd6fe32eSThierry Reding reg = <0x102>; 1906cd6fe32eSThierry Reding }; 1907cd6fe32eSThierry Reding 19083b4c1378SMarc Zyngier ca57_3: cpu@5 { 190931af04cdSRob Herring compatible = "arm,cortex-a57"; 1910cd6fe32eSThierry Reding device_type = "cpu"; 19115298166dSJoseph Lo i-cache-size = <0xC000>; 19125298166dSJoseph Lo i-cache-line-size = <64>; 19135298166dSJoseph Lo i-cache-sets = <256>; 19145298166dSJoseph Lo d-cache-size = <0x8000>; 19155298166dSJoseph Lo d-cache-line-size = <64>; 19165298166dSJoseph Lo d-cache-sets = <256>; 19175298166dSJoseph Lo next-level-cache = <&L2_A57>; 1918cd6fe32eSThierry Reding reg = <0x103>; 1919cd6fe32eSThierry Reding }; 19205298166dSJoseph Lo 19215298166dSJoseph Lo L2_DENVER: l2-cache0 { 19225298166dSJoseph Lo compatible = "cache"; 19235298166dSJoseph Lo cache-unified; 19245298166dSJoseph Lo cache-level = <2>; 19255298166dSJoseph Lo cache-size = <0x200000>; 19265298166dSJoseph Lo cache-line-size = <64>; 19275298166dSJoseph Lo cache-sets = <2048>; 19285298166dSJoseph Lo }; 19295298166dSJoseph Lo 19305298166dSJoseph Lo L2_A57: l2-cache1 { 19315298166dSJoseph Lo compatible = "cache"; 19325298166dSJoseph Lo cache-unified; 19335298166dSJoseph Lo cache-level = <2>; 19345298166dSJoseph Lo cache-size = <0x200000>; 19355298166dSJoseph Lo cache-line-size = <64>; 19365298166dSJoseph Lo cache-sets = <2048>; 19375298166dSJoseph Lo }; 1938cd6fe32eSThierry Reding }; 1939cd6fe32eSThierry Reding 19403b4c1378SMarc Zyngier pmu_denver { 19413b4c1378SMarc Zyngier compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; 19423b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 19433b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 19443b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 19453b4c1378SMarc Zyngier }; 19463b4c1378SMarc Zyngier 19473b4c1378SMarc Zyngier pmu_a57 { 19483b4c1378SMarc Zyngier compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 19493b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 19503b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 19513b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 19523b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 19533b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 19543b4c1378SMarc Zyngier }; 19553b4c1378SMarc Zyngier 1956e4710376SSameer Pujar sound { 1957e4710376SSameer Pujar status = "disabled"; 1958e4710376SSameer Pujar 1959e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 1960e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1961e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 1962e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 1963e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 1964e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 1965e4710376SSameer Pujar assigned-clock-parents = <0>, 1966e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 1967e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1968e4710376SSameer Pujar /* 1969e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 1970e4710376SSameer Pujar * for this to work and oscillate between base rates required 1971e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 1972e4710376SSameer Pujar */ 1973e4710376SSameer Pujar assigned-clock-rates = <258000000>; 1974e4710376SSameer Pujar 1975e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 1976e4710376SSameer Pujar }; 1977e4710376SSameer Pujar 197815274c23SMikko Perttunen thermal-zones { 1979*fe57ff53SThierry Reding /* Cortex-A57 cluster */ 1980*fe57ff53SThierry Reding cpu-thermal { 198115274c23SMikko Perttunen polling-delay = <0>; 198215274c23SMikko Perttunen polling-delay-passive = <1000>; 198315274c23SMikko Perttunen 1984*fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 198515274c23SMikko Perttunen 198615274c23SMikko Perttunen trips { 198715274c23SMikko Perttunen critical { 198815274c23SMikko Perttunen temperature = <101000>; 198915274c23SMikko Perttunen hysteresis = <0>; 199015274c23SMikko Perttunen type = "critical"; 199115274c23SMikko Perttunen }; 199215274c23SMikko Perttunen }; 199315274c23SMikko Perttunen 199415274c23SMikko Perttunen cooling-maps { 199515274c23SMikko Perttunen }; 199615274c23SMikko Perttunen }; 199715274c23SMikko Perttunen 1998*fe57ff53SThierry Reding /* Denver cluster */ 1999*fe57ff53SThierry Reding aux-thermal { 200015274c23SMikko Perttunen polling-delay = <0>; 200115274c23SMikko Perttunen polling-delay-passive = <1000>; 200215274c23SMikko Perttunen 2003*fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 200415274c23SMikko Perttunen 200515274c23SMikko Perttunen trips { 200615274c23SMikko Perttunen critical { 200715274c23SMikko Perttunen temperature = <101000>; 200815274c23SMikko Perttunen hysteresis = <0>; 200915274c23SMikko Perttunen type = "critical"; 201015274c23SMikko Perttunen }; 201115274c23SMikko Perttunen }; 201215274c23SMikko Perttunen 201315274c23SMikko Perttunen cooling-maps { 201415274c23SMikko Perttunen }; 201515274c23SMikko Perttunen }; 201615274c23SMikko Perttunen 2017*fe57ff53SThierry Reding gpu-thermal { 201815274c23SMikko Perttunen polling-delay = <0>; 201915274c23SMikko Perttunen polling-delay-passive = <1000>; 202015274c23SMikko Perttunen 2021*fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 202215274c23SMikko Perttunen 202315274c23SMikko Perttunen trips { 202415274c23SMikko Perttunen critical { 202515274c23SMikko Perttunen temperature = <101000>; 202615274c23SMikko Perttunen hysteresis = <0>; 202715274c23SMikko Perttunen type = "critical"; 202815274c23SMikko Perttunen }; 202915274c23SMikko Perttunen }; 203015274c23SMikko Perttunen 203115274c23SMikko Perttunen cooling-maps { 203215274c23SMikko Perttunen }; 203315274c23SMikko Perttunen }; 203415274c23SMikko Perttunen 2035*fe57ff53SThierry Reding pll-thermal { 203615274c23SMikko Perttunen polling-delay = <0>; 203715274c23SMikko Perttunen polling-delay-passive = <1000>; 203815274c23SMikko Perttunen 2039*fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 204015274c23SMikko Perttunen 204115274c23SMikko Perttunen trips { 204215274c23SMikko Perttunen critical { 204315274c23SMikko Perttunen temperature = <101000>; 204415274c23SMikko Perttunen hysteresis = <0>; 204515274c23SMikko Perttunen type = "critical"; 204615274c23SMikko Perttunen }; 204715274c23SMikko Perttunen }; 204815274c23SMikko Perttunen 204915274c23SMikko Perttunen cooling-maps { 205015274c23SMikko Perttunen }; 205115274c23SMikko Perttunen }; 205215274c23SMikko Perttunen 2053*fe57ff53SThierry Reding ao-thermal { 205415274c23SMikko Perttunen polling-delay = <0>; 205515274c23SMikko Perttunen polling-delay-passive = <1000>; 205615274c23SMikko Perttunen 2057*fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 205815274c23SMikko Perttunen 205915274c23SMikko Perttunen trips { 206015274c23SMikko Perttunen critical { 206115274c23SMikko Perttunen temperature = <101000>; 206215274c23SMikko Perttunen hysteresis = <0>; 206315274c23SMikko Perttunen type = "critical"; 206415274c23SMikko Perttunen }; 206515274c23SMikko Perttunen }; 206615274c23SMikko Perttunen 206715274c23SMikko Perttunen cooling-maps { 206815274c23SMikko Perttunen }; 206915274c23SMikko Perttunen }; 207039cb62cbSJoseph Lo }; 207139cb62cbSJoseph Lo 207239cb62cbSJoseph Lo timer { 207339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 207439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 207539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207639cb62cbSJoseph Lo <GIC_PPI 14 207739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207839cb62cbSJoseph Lo <GIC_PPI 11 207939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 208039cb62cbSJoseph Lo <GIC_PPI 10 208139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 208239cb62cbSJoseph Lo interrupt-parent = <&gic>; 2083b30be673SThierry Reding always-on; 208439cb62cbSJoseph Lo }; 208539cb62cbSJoseph Lo}; 2086