1fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 239cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 339cb62cbSJoseph Lo 439cb62cbSJoseph Lo/ { 539cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 639cb62cbSJoseph Lo interrupt-parent = <&gic>; 739cb62cbSJoseph Lo #address-cells = <2>; 839cb62cbSJoseph Lo #size-cells = <2>; 939cb62cbSJoseph Lo 10fc4bb754SThierry Reding gpio: gpio@2200000 { 11fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 12fc4bb754SThierry Reding reg-names = "security", "gpio"; 13fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 14fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 15fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 16fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 17fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 18fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 19fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 20fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 21fc4bb754SThierry Reding #interrupt-cells = <2>; 22fc4bb754SThierry Reding interrupt-controller; 23fc4bb754SThierry Reding #gpio-cells = <2>; 24fc4bb754SThierry Reding gpio-controller; 25fc4bb754SThierry Reding }; 26fc4bb754SThierry Reding 2739cb62cbSJoseph Lo uarta: serial@3100000 { 2839cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 2939cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 3039cb62cbSJoseph Lo reg-shift = <2>; 3139cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 32a7a77e2eSThierry Reding clocks = <&bpmp 55>; 33a7a77e2eSThierry Reding clock-names = "serial"; 34a7a77e2eSThierry Reding resets = <&bpmp 47>; 35a7a77e2eSThierry Reding reset-names = "serial"; 36a7a77e2eSThierry Reding status = "disabled"; 37a7a77e2eSThierry Reding }; 38a7a77e2eSThierry Reding 39a7a77e2eSThierry Reding uartb: serial@3110000 { 40a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 41a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 42a7a77e2eSThierry Reding reg-shift = <2>; 43a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 44a7a77e2eSThierry Reding clocks = <&bpmp 56>; 45a7a77e2eSThierry Reding clock-names = "serial"; 46a7a77e2eSThierry Reding resets = <&bpmp 48>; 47a7a77e2eSThierry Reding reset-names = "serial"; 48a7a77e2eSThierry Reding status = "disabled"; 49a7a77e2eSThierry Reding }; 50a7a77e2eSThierry Reding 51a7a77e2eSThierry Reding uartd: serial@3130000 { 52a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 53a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 54a7a77e2eSThierry Reding reg-shift = <2>; 55a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 56a7a77e2eSThierry Reding clocks = <&bpmp 77>; 57a7a77e2eSThierry Reding clock-names = "serial"; 58a7a77e2eSThierry Reding resets = <&bpmp 50>; 59a7a77e2eSThierry Reding reset-names = "serial"; 60a7a77e2eSThierry Reding status = "disabled"; 61a7a77e2eSThierry Reding }; 62a7a77e2eSThierry Reding 63a7a77e2eSThierry Reding uarte: serial@3140000 { 64a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 65a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 66a7a77e2eSThierry Reding reg-shift = <2>; 67a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 68a7a77e2eSThierry Reding clocks = <&bpmp 194>; 69a7a77e2eSThierry Reding clock-names = "serial"; 70a7a77e2eSThierry Reding resets = <&bpmp 132>; 71a7a77e2eSThierry Reding reset-names = "serial"; 72a7a77e2eSThierry Reding status = "disabled"; 73a7a77e2eSThierry Reding }; 74a7a77e2eSThierry Reding 75a7a77e2eSThierry Reding uartf: serial@3150000 { 76a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 77a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 78a7a77e2eSThierry Reding reg-shift = <2>; 79a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 80a7a77e2eSThierry Reding clocks = <&bpmp 195>; 81a7a77e2eSThierry Reding clock-names = "serial"; 82a7a77e2eSThierry Reding resets = <&bpmp 111>; 83a7a77e2eSThierry Reding reset-names = "serial"; 8439cb62cbSJoseph Lo status = "disabled"; 8539cb62cbSJoseph Lo }; 8639cb62cbSJoseph Lo 8740cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 8840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 8940cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 9040cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 9140cc83b3SThierry Reding #address-cells = <1>; 9240cc83b3SThierry Reding #size-cells = <0>; 9340cc83b3SThierry Reding clocks = <&bpmp 47>; 9440cc83b3SThierry Reding clock-names = "div-clk"; 9540cc83b3SThierry Reding resets = <&bpmp 19>; 9640cc83b3SThierry Reding reset-names = "i2c"; 9740cc83b3SThierry Reding status = "disabled"; 9840cc83b3SThierry Reding }; 9940cc83b3SThierry Reding 10040cc83b3SThierry Reding cam_i2c: i2c@3180000 { 10140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 10240cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 10340cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 10440cc83b3SThierry Reding #address-cells = <1>; 10540cc83b3SThierry Reding #size-cells = <0>; 10640cc83b3SThierry Reding clocks = <&bpmp 75>; 10740cc83b3SThierry Reding clock-names = "div-clk"; 10840cc83b3SThierry Reding resets = <&bpmp 21>; 10940cc83b3SThierry Reding reset-names = "i2c"; 11040cc83b3SThierry Reding status = "disabled"; 11140cc83b3SThierry Reding }; 11240cc83b3SThierry Reding 11340cc83b3SThierry Reding /* shares pads with dpaux1 */ 11440cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 11540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 11640cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 11740cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 11840cc83b3SThierry Reding #address-cells = <1>; 11940cc83b3SThierry Reding #size-cells = <0>; 12040cc83b3SThierry Reding clocks = <&bpmp 86>; 12140cc83b3SThierry Reding clock-names = "div-clk"; 12240cc83b3SThierry Reding resets = <&bpmp 22>; 12340cc83b3SThierry Reding reset-names = "i2c"; 12440cc83b3SThierry Reding status = "disabled"; 12540cc83b3SThierry Reding }; 12640cc83b3SThierry Reding 12740cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 12840cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 12940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13040cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 13140cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 13240cc83b3SThierry Reding #address-cells = <1>; 13340cc83b3SThierry Reding #size-cells = <0>; 13440cc83b3SThierry Reding clocks = <&bpmp 48>; 13540cc83b3SThierry Reding clock-names = "div-clk"; 13640cc83b3SThierry Reding resets = <&bpmp 23>; 13740cc83b3SThierry Reding reset-names = "i2c"; 13840cc83b3SThierry Reding status = "disabled"; 13940cc83b3SThierry Reding }; 14040cc83b3SThierry Reding 14140cc83b3SThierry Reding /* shares pads with dpaux0 */ 14240cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 14340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14440cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 14540cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 14640cc83b3SThierry Reding #address-cells = <1>; 14740cc83b3SThierry Reding #size-cells = <0>; 14840cc83b3SThierry Reding clocks = <&bpmp 125>; 14940cc83b3SThierry Reding clock-names = "div-clk"; 15040cc83b3SThierry Reding resets = <&bpmp 24>; 15140cc83b3SThierry Reding reset-names = "i2c"; 15240cc83b3SThierry Reding status = "disabled"; 15340cc83b3SThierry Reding }; 15440cc83b3SThierry Reding 15540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 15640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 15840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 15940cc83b3SThierry Reding #address-cells = <1>; 16040cc83b3SThierry Reding #size-cells = <0>; 16140cc83b3SThierry Reding clocks = <&bpmp 182>; 16240cc83b3SThierry Reding clock-names = "div-clk"; 16340cc83b3SThierry Reding resets = <&bpmp 81>; 16440cc83b3SThierry Reding reset-names = "i2c"; 16540cc83b3SThierry Reding status = "disabled"; 16640cc83b3SThierry Reding }; 16740cc83b3SThierry Reding 16840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 16940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 17040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 17140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 17240cc83b3SThierry Reding #address-cells = <1>; 17340cc83b3SThierry Reding #size-cells = <0>; 17440cc83b3SThierry Reding clocks = <&bpmp 183>; 17540cc83b3SThierry Reding clock-names = "div-clk"; 17640cc83b3SThierry Reding resets = <&bpmp 83>; 17740cc83b3SThierry Reding reset-names = "i2c"; 17840cc83b3SThierry Reding status = "disabled"; 17940cc83b3SThierry Reding }; 18040cc83b3SThierry Reding 18199425dfdSThierry Reding sdmmc1: sdhci@3400000 { 18299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 18399425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 18499425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 18599425dfdSThierry Reding clocks = <&bpmp 52>; 18699425dfdSThierry Reding clock-names = "sdhci"; 18799425dfdSThierry Reding resets = <&bpmp 33>; 18899425dfdSThierry Reding reset-names = "sdhci"; 18999425dfdSThierry Reding status = "disabled"; 19099425dfdSThierry Reding }; 19199425dfdSThierry Reding 19299425dfdSThierry Reding sdmmc2: sdhci@3420000 { 19399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 19499425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 19599425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 19699425dfdSThierry Reding clocks = <&bpmp 53>; 19799425dfdSThierry Reding clock-names = "sdhci"; 19899425dfdSThierry Reding resets = <&bpmp 34>; 19999425dfdSThierry Reding reset-names = "sdhci"; 20099425dfdSThierry Reding status = "disabled"; 20199425dfdSThierry Reding }; 20299425dfdSThierry Reding 20399425dfdSThierry Reding sdmmc3: sdhci@3440000 { 20499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 20599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 20699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 20799425dfdSThierry Reding clocks = <&bpmp 76>; 20899425dfdSThierry Reding clock-names = "sdhci"; 20999425dfdSThierry Reding resets = <&bpmp 35>; 21099425dfdSThierry Reding reset-names = "sdhci"; 21199425dfdSThierry Reding status = "disabled"; 21299425dfdSThierry Reding }; 21399425dfdSThierry Reding 21499425dfdSThierry Reding sdmmc4: sdhci@3460000 { 21599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 21699425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 21799425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 21899425dfdSThierry Reding clocks = <&bpmp 54>; 21999425dfdSThierry Reding clock-names = "sdhci"; 22099425dfdSThierry Reding resets = <&bpmp 36>; 22199425dfdSThierry Reding reset-names = "sdhci"; 22299425dfdSThierry Reding status = "disabled"; 22399425dfdSThierry Reding }; 22499425dfdSThierry Reding 22539cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 22639cb62cbSJoseph Lo compatible = "arm,gic-400"; 22739cb62cbSJoseph Lo #interrupt-cells = <3>; 22839cb62cbSJoseph Lo interrupt-controller; 22939cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 23039cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 23139cb62cbSJoseph Lo interrupts = <GIC_PPI 9 23239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 23339cb62cbSJoseph Lo interrupt-parent = <&gic>; 23439cb62cbSJoseph Lo }; 23539cb62cbSJoseph Lo 23639cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 23739cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 23839cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 23939cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 24039cb62cbSJoseph Lo interrupt-names = "doorbell"; 24139cb62cbSJoseph Lo #mbox-cells = <2>; 24239cb62cbSJoseph Lo status = "disabled"; 24339cb62cbSJoseph Lo }; 24439cb62cbSJoseph Lo 24540cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 24640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 24740cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 24840cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 24940cc83b3SThierry Reding #address-cells = <1>; 25040cc83b3SThierry Reding #size-cells = <0>; 25140cc83b3SThierry Reding clocks = <&bpmp 218>; 25240cc83b3SThierry Reding clock-names = "div-clk"; 25340cc83b3SThierry Reding resets = <&bpmp 20>; 25440cc83b3SThierry Reding reset-names = "i2c"; 25540cc83b3SThierry Reding status = "disabled"; 25640cc83b3SThierry Reding }; 25740cc83b3SThierry Reding 25840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 25940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 26040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 26140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 26240cc83b3SThierry Reding #address-cells = <1>; 26340cc83b3SThierry Reding #size-cells = <0>; 26440cc83b3SThierry Reding clocks = <&bpmp 219>; 26540cc83b3SThierry Reding clock-names = "div-clk"; 26640cc83b3SThierry Reding resets = <&bpmp 82>; 26740cc83b3SThierry Reding reset-names = "i2c"; 26840cc83b3SThierry Reding status = "disabled"; 26940cc83b3SThierry Reding }; 27040cc83b3SThierry Reding 271a7a77e2eSThierry Reding uartc: serial@c280000 { 272a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 273a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 274a7a77e2eSThierry Reding reg-shift = <2>; 275a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 276a7a77e2eSThierry Reding clocks = <&bpmp 215>; 277a7a77e2eSThierry Reding clock-names = "serial"; 278a7a77e2eSThierry Reding resets = <&bpmp 49>; 279a7a77e2eSThierry Reding reset-names = "serial"; 280a7a77e2eSThierry Reding status = "disabled"; 281a7a77e2eSThierry Reding }; 282a7a77e2eSThierry Reding 283a7a77e2eSThierry Reding uartg: serial@c290000 { 284a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 285a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 286a7a77e2eSThierry Reding reg-shift = <2>; 287a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 288a7a77e2eSThierry Reding clocks = <&bpmp 216>; 289a7a77e2eSThierry Reding clock-names = "serial"; 290a7a77e2eSThierry Reding resets = <&bpmp 112>; 291a7a77e2eSThierry Reding reset-names = "serial"; 292a7a77e2eSThierry Reding status = "disabled"; 293a7a77e2eSThierry Reding }; 294a7a77e2eSThierry Reding 295fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 296fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 297fc4bb754SThierry Reding reg-names = "security", "gpio"; 298fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 299fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 300fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 301fc4bb754SThierry Reding gpio-controller; 302fc4bb754SThierry Reding #gpio-cells = <2>; 303fc4bb754SThierry Reding interrupt-controller; 304fc4bb754SThierry Reding #interrupt-cells = <2>; 305fc4bb754SThierry Reding }; 306fc4bb754SThierry Reding 30739cb62cbSJoseph Lo sysram@30000000 { 30839cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 30939cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 31039cb62cbSJoseph Lo #address-cells = <2>; 31139cb62cbSJoseph Lo #size-cells = <2>; 31239cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 31339cb62cbSJoseph Lo 31439cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 31539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 31639cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 31739cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 31839cb62cbSJoseph Lo pool; 31939cb62cbSJoseph Lo }; 32039cb62cbSJoseph Lo 32139cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 32239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 32339cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 32439cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 32539cb62cbSJoseph Lo pool; 32639cb62cbSJoseph Lo }; 32739cb62cbSJoseph Lo }; 32839cb62cbSJoseph Lo 329cd6fe32eSThierry Reding cpus { 330cd6fe32eSThierry Reding #address-cells = <1>; 331cd6fe32eSThierry Reding #size-cells = <0>; 332cd6fe32eSThierry Reding 333cd6fe32eSThierry Reding cpu@0 { 334cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 335cd6fe32eSThierry Reding device_type = "cpu"; 336cd6fe32eSThierry Reding reg = <0x000>; 337cd6fe32eSThierry Reding }; 338cd6fe32eSThierry Reding 339cd6fe32eSThierry Reding cpu@1 { 340cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 341cd6fe32eSThierry Reding device_type = "cpu"; 342cd6fe32eSThierry Reding reg = <0x001>; 343cd6fe32eSThierry Reding }; 344cd6fe32eSThierry Reding 345cd6fe32eSThierry Reding cpu@2 { 346cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 347cd6fe32eSThierry Reding device_type = "cpu"; 348cd6fe32eSThierry Reding reg = <0x100>; 349cd6fe32eSThierry Reding }; 350cd6fe32eSThierry Reding 351cd6fe32eSThierry Reding cpu@3 { 352cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 353cd6fe32eSThierry Reding device_type = "cpu"; 354cd6fe32eSThierry Reding reg = <0x101>; 355cd6fe32eSThierry Reding }; 356cd6fe32eSThierry Reding 357cd6fe32eSThierry Reding cpu@4 { 358cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 359cd6fe32eSThierry Reding device_type = "cpu"; 360cd6fe32eSThierry Reding reg = <0x102>; 361cd6fe32eSThierry Reding }; 362cd6fe32eSThierry Reding 363cd6fe32eSThierry Reding cpu@5 { 364cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 365cd6fe32eSThierry Reding device_type = "cpu"; 366cd6fe32eSThierry Reding reg = <0x103>; 367cd6fe32eSThierry Reding }; 368cd6fe32eSThierry Reding }; 369cd6fe32eSThierry Reding 37039cb62cbSJoseph Lo bpmp: bpmp { 37139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 37239cb62cbSJoseph Lo mboxes = <&hsp_top0 0 19>; 37339cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 37439cb62cbSJoseph Lo #clock-cells = <1>; 37539cb62cbSJoseph Lo #reset-cells = <1>; 37639cb62cbSJoseph Lo 37739cb62cbSJoseph Lo bpmp_i2c: i2c { 37839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 37939cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 38039cb62cbSJoseph Lo #address-cells = <1>; 38139cb62cbSJoseph Lo #size-cells = <0>; 38239cb62cbSJoseph Lo status = "disabled"; 38339cb62cbSJoseph Lo }; 38439cb62cbSJoseph Lo }; 38539cb62cbSJoseph Lo 38639cb62cbSJoseph Lo timer { 38739cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 38839cb62cbSJoseph Lo interrupts = <GIC_PPI 13 38939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39039cb62cbSJoseph Lo <GIC_PPI 14 39139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39239cb62cbSJoseph Lo <GIC_PPI 11 39339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39439cb62cbSJoseph Lo <GIC_PPI 10 39539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 39639cb62cbSJoseph Lo interrupt-parent = <&gic>; 39739cb62cbSJoseph Lo }; 39839cb62cbSJoseph Lo}; 399