1c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 2fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 339cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 45edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 5dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 67bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 739cb62cbSJoseph Lo 839cb62cbSJoseph Lo/ { 939cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1039cb62cbSJoseph Lo interrupt-parent = <&gic>; 1139cb62cbSJoseph Lo #address-cells = <2>; 1239cb62cbSJoseph Lo #size-cells = <2>; 1339cb62cbSJoseph Lo 14fc4bb754SThierry Reding gpio: gpio@2200000 { 15fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 16fc4bb754SThierry Reding reg-names = "security", "gpio"; 17fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 18fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 19fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 20fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 21fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 22fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 23fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 24fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 25fc4bb754SThierry Reding #interrupt-cells = <2>; 26fc4bb754SThierry Reding interrupt-controller; 27fc4bb754SThierry Reding #gpio-cells = <2>; 28fc4bb754SThierry Reding gpio-controller; 29fc4bb754SThierry Reding }; 30fc4bb754SThierry Reding 310caafbdeSThierry Reding ethernet@2490000 { 320caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 330caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 340caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 350caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 360caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 370caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 380caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 390caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 400caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 410caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 420caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 430caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 440caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 450caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 460caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 470caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 480caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 490caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 500caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 510caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 520caafbdeSThierry Reding reset-names = "eqos"; 530caafbdeSThierry Reding status = "disabled"; 540caafbdeSThierry Reding 550caafbdeSThierry Reding snps,write-requests = <1>; 560caafbdeSThierry Reding snps,read-requests = <3>; 570caafbdeSThierry Reding snps,burst-map = <0x7>; 580caafbdeSThierry Reding snps,txpbl = <32>; 590caafbdeSThierry Reding snps,rxpbl = <8>; 600caafbdeSThierry Reding }; 610caafbdeSThierry Reding 6239cb62cbSJoseph Lo uarta: serial@3100000 { 6339cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 6439cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 6539cb62cbSJoseph Lo reg-shift = <2>; 6639cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 68a7a77e2eSThierry Reding clock-names = "serial"; 697bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 70a7a77e2eSThierry Reding reset-names = "serial"; 71a7a77e2eSThierry Reding status = "disabled"; 72a7a77e2eSThierry Reding }; 73a7a77e2eSThierry Reding 74a7a77e2eSThierry Reding uartb: serial@3110000 { 75a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 76a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 77a7a77e2eSThierry Reding reg-shift = <2>; 78a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 80a7a77e2eSThierry Reding clock-names = "serial"; 817bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 82a7a77e2eSThierry Reding reset-names = "serial"; 83a7a77e2eSThierry Reding status = "disabled"; 84a7a77e2eSThierry Reding }; 85a7a77e2eSThierry Reding 86a7a77e2eSThierry Reding uartd: serial@3130000 { 87a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 88a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 89a7a77e2eSThierry Reding reg-shift = <2>; 90a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 92a7a77e2eSThierry Reding clock-names = "serial"; 937bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 94a7a77e2eSThierry Reding reset-names = "serial"; 95a7a77e2eSThierry Reding status = "disabled"; 96a7a77e2eSThierry Reding }; 97a7a77e2eSThierry Reding 98a7a77e2eSThierry Reding uarte: serial@3140000 { 99a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 100a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 101a7a77e2eSThierry Reding reg-shift = <2>; 102a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 104a7a77e2eSThierry Reding clock-names = "serial"; 1057bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 106a7a77e2eSThierry Reding reset-names = "serial"; 107a7a77e2eSThierry Reding status = "disabled"; 108a7a77e2eSThierry Reding }; 109a7a77e2eSThierry Reding 110a7a77e2eSThierry Reding uartf: serial@3150000 { 111a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 112a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 113a7a77e2eSThierry Reding reg-shift = <2>; 114a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 116a7a77e2eSThierry Reding clock-names = "serial"; 1177bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 118a7a77e2eSThierry Reding reset-names = "serial"; 11939cb62cbSJoseph Lo status = "disabled"; 12039cb62cbSJoseph Lo }; 12139cb62cbSJoseph Lo 12240cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 12340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 12440cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 12540cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 12640cc83b3SThierry Reding #address-cells = <1>; 12740cc83b3SThierry Reding #size-cells = <0>; 128c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 12940cc83b3SThierry Reding clock-names = "div-clk"; 1307bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 13140cc83b3SThierry Reding reset-names = "i2c"; 13240cc83b3SThierry Reding status = "disabled"; 13340cc83b3SThierry Reding }; 13440cc83b3SThierry Reding 13540cc83b3SThierry Reding cam_i2c: i2c@3180000 { 13640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13740cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 13840cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 13940cc83b3SThierry Reding #address-cells = <1>; 14040cc83b3SThierry Reding #size-cells = <0>; 141c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 14240cc83b3SThierry Reding clock-names = "div-clk"; 1437bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 14440cc83b3SThierry Reding reset-names = "i2c"; 14540cc83b3SThierry Reding status = "disabled"; 14640cc83b3SThierry Reding }; 14740cc83b3SThierry Reding 14840cc83b3SThierry Reding /* shares pads with dpaux1 */ 14940cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 15040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15140cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 15240cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 15340cc83b3SThierry Reding #address-cells = <1>; 15440cc83b3SThierry Reding #size-cells = <0>; 155c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 15640cc83b3SThierry Reding clock-names = "div-clk"; 1577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 15840cc83b3SThierry Reding reset-names = "i2c"; 15940cc83b3SThierry Reding status = "disabled"; 16040cc83b3SThierry Reding }; 16140cc83b3SThierry Reding 16240cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 16340cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 16440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16540cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 16640cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 16740cc83b3SThierry Reding #address-cells = <1>; 16840cc83b3SThierry Reding #size-cells = <0>; 169c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 17040cc83b3SThierry Reding clock-names = "div-clk"; 1717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 17240cc83b3SThierry Reding reset-names = "i2c"; 17340cc83b3SThierry Reding status = "disabled"; 17440cc83b3SThierry Reding }; 17540cc83b3SThierry Reding 17640cc83b3SThierry Reding /* shares pads with dpaux0 */ 17740cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 17840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 17940cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 18040cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 18140cc83b3SThierry Reding #address-cells = <1>; 18240cc83b3SThierry Reding #size-cells = <0>; 183c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 18440cc83b3SThierry Reding clock-names = "div-clk"; 1857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 18640cc83b3SThierry Reding reset-names = "i2c"; 18740cc83b3SThierry Reding status = "disabled"; 18840cc83b3SThierry Reding }; 18940cc83b3SThierry Reding 19040cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 19140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19240cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 19340cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 19440cc83b3SThierry Reding #address-cells = <1>; 19540cc83b3SThierry Reding #size-cells = <0>; 196c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 19740cc83b3SThierry Reding clock-names = "div-clk"; 1987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 19940cc83b3SThierry Reding reset-names = "i2c"; 20040cc83b3SThierry Reding status = "disabled"; 20140cc83b3SThierry Reding }; 20240cc83b3SThierry Reding 20340cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 20440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20540cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 20640cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 20740cc83b3SThierry Reding #address-cells = <1>; 20840cc83b3SThierry Reding #size-cells = <0>; 209c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 21040cc83b3SThierry Reding clock-names = "div-clk"; 2117bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 21240cc83b3SThierry Reding reset-names = "i2c"; 21340cc83b3SThierry Reding status = "disabled"; 21440cc83b3SThierry Reding }; 21540cc83b3SThierry Reding 21699425dfdSThierry Reding sdmmc1: sdhci@3400000 { 21799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 21899425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 21999425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 220c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 22199425dfdSThierry Reding clock-names = "sdhci"; 2227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 22399425dfdSThierry Reding reset-names = "sdhci"; 22499425dfdSThierry Reding status = "disabled"; 22599425dfdSThierry Reding }; 22699425dfdSThierry Reding 22799425dfdSThierry Reding sdmmc2: sdhci@3420000 { 22899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 22999425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 23099425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 231c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 23299425dfdSThierry Reding clock-names = "sdhci"; 2337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 23499425dfdSThierry Reding reset-names = "sdhci"; 23599425dfdSThierry Reding status = "disabled"; 23699425dfdSThierry Reding }; 23799425dfdSThierry Reding 23899425dfdSThierry Reding sdmmc3: sdhci@3440000 { 23999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24099425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 24199425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 242c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 24399425dfdSThierry Reding clock-names = "sdhci"; 2447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 24599425dfdSThierry Reding reset-names = "sdhci"; 24699425dfdSThierry Reding status = "disabled"; 24799425dfdSThierry Reding }; 24899425dfdSThierry Reding 24999425dfdSThierry Reding sdmmc4: sdhci@3460000 { 25099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25199425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 25299425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 253c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 25499425dfdSThierry Reding clock-names = "sdhci"; 2557bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 25699425dfdSThierry Reding reset-names = "sdhci"; 25799425dfdSThierry Reding status = "disabled"; 25899425dfdSThierry Reding }; 25999425dfdSThierry Reding 26039cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 26139cb62cbSJoseph Lo compatible = "arm,gic-400"; 26239cb62cbSJoseph Lo #interrupt-cells = <3>; 26339cb62cbSJoseph Lo interrupt-controller; 26439cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 26539cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 26639cb62cbSJoseph Lo interrupts = <GIC_PPI 9 26739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 26839cb62cbSJoseph Lo interrupt-parent = <&gic>; 26939cb62cbSJoseph Lo }; 27039cb62cbSJoseph Lo 27139cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 27239cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 27339cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 27439cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 27539cb62cbSJoseph Lo interrupt-names = "doorbell"; 27639cb62cbSJoseph Lo #mbox-cells = <2>; 27739cb62cbSJoseph Lo status = "disabled"; 27839cb62cbSJoseph Lo }; 27939cb62cbSJoseph Lo 28040cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 28140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 28240cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 28340cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 28440cc83b3SThierry Reding #address-cells = <1>; 28540cc83b3SThierry Reding #size-cells = <0>; 286c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 28740cc83b3SThierry Reding clock-names = "div-clk"; 2887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 28940cc83b3SThierry Reding reset-names = "i2c"; 29040cc83b3SThierry Reding status = "disabled"; 29140cc83b3SThierry Reding }; 29240cc83b3SThierry Reding 29340cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 29440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 29540cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 29640cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 29740cc83b3SThierry Reding #address-cells = <1>; 29840cc83b3SThierry Reding #size-cells = <0>; 299c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 30040cc83b3SThierry Reding clock-names = "div-clk"; 3017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 30240cc83b3SThierry Reding reset-names = "i2c"; 30340cc83b3SThierry Reding status = "disabled"; 30440cc83b3SThierry Reding }; 30540cc83b3SThierry Reding 306a7a77e2eSThierry Reding uartc: serial@c280000 { 307a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 308a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 309a7a77e2eSThierry Reding reg-shift = <2>; 310a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 311c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 312a7a77e2eSThierry Reding clock-names = "serial"; 3137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 314a7a77e2eSThierry Reding reset-names = "serial"; 315a7a77e2eSThierry Reding status = "disabled"; 316a7a77e2eSThierry Reding }; 317a7a77e2eSThierry Reding 318a7a77e2eSThierry Reding uartg: serial@c290000 { 319a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 320a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 321a7a77e2eSThierry Reding reg-shift = <2>; 322a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 323c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 324a7a77e2eSThierry Reding clock-names = "serial"; 3257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 326a7a77e2eSThierry Reding reset-names = "serial"; 327a7a77e2eSThierry Reding status = "disabled"; 328a7a77e2eSThierry Reding }; 329a7a77e2eSThierry Reding 330fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 331fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 332fc4bb754SThierry Reding reg-names = "security", "gpio"; 333fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 334fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 335fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 336fc4bb754SThierry Reding gpio-controller; 337fc4bb754SThierry Reding #gpio-cells = <2>; 338fc4bb754SThierry Reding interrupt-controller; 339fc4bb754SThierry Reding #interrupt-cells = <2>; 340fc4bb754SThierry Reding }; 341fc4bb754SThierry Reding 34273bf90d4SThierry Reding pmc@c360000 { 34373bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 34473bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 34573bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 34673bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 34773bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 34873bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 34973bf90d4SThierry Reding }; 35073bf90d4SThierry Reding 3517b7ef494SMikko Perttunen ccplex@e000000 { 3527b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 3537b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 3547b7ef494SMikko Perttunen 3557b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 3567b7ef494SMikko Perttunen }; 3577b7ef494SMikko Perttunen 358f8973cf4SManikanta Maddireddy pcie@10003000 { 359f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 360f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 361f8973cf4SManikanta Maddireddy device_type = "pci"; 362f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 363f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 364f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 365f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 366f8973cf4SManikanta Maddireddy 367f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 368f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 369f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 370f8973cf4SManikanta Maddireddy 371f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 372f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 373f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 374f8973cf4SManikanta Maddireddy 375f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 376f8973cf4SManikanta Maddireddy #address-cells = <3>; 377f8973cf4SManikanta Maddireddy #size-cells = <2>; 378f8973cf4SManikanta Maddireddy 379f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 380f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 381f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 382f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 383f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 384f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 385f8973cf4SManikanta Maddireddy 386f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 387f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 388f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 389f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 390f8973cf4SManikanta Maddireddy 391f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 392f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 393f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 394f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 395f8973cf4SManikanta Maddireddy 396f8973cf4SManikanta Maddireddy status = "disabled"; 397f8973cf4SManikanta Maddireddy 398f8973cf4SManikanta Maddireddy pci@1,0 { 399f8973cf4SManikanta Maddireddy device_type = "pci"; 400f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 401f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 402f8973cf4SManikanta Maddireddy status = "disabled"; 403f8973cf4SManikanta Maddireddy 404f8973cf4SManikanta Maddireddy #address-cells = <3>; 405f8973cf4SManikanta Maddireddy #size-cells = <2>; 406f8973cf4SManikanta Maddireddy ranges; 407f8973cf4SManikanta Maddireddy 408f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 409f8973cf4SManikanta Maddireddy }; 410f8973cf4SManikanta Maddireddy 411f8973cf4SManikanta Maddireddy pci@2,0 { 412f8973cf4SManikanta Maddireddy device_type = "pci"; 413f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 414f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 415f8973cf4SManikanta Maddireddy status = "disabled"; 416f8973cf4SManikanta Maddireddy 417f8973cf4SManikanta Maddireddy #address-cells = <3>; 418f8973cf4SManikanta Maddireddy #size-cells = <2>; 419f8973cf4SManikanta Maddireddy ranges; 420f8973cf4SManikanta Maddireddy 421f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 422f8973cf4SManikanta Maddireddy }; 423f8973cf4SManikanta Maddireddy 424f8973cf4SManikanta Maddireddy pci@3,0 { 425f8973cf4SManikanta Maddireddy device_type = "pci"; 426f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 427f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 428f8973cf4SManikanta Maddireddy status = "disabled"; 429f8973cf4SManikanta Maddireddy 430f8973cf4SManikanta Maddireddy #address-cells = <3>; 431f8973cf4SManikanta Maddireddy #size-cells = <2>; 432f8973cf4SManikanta Maddireddy ranges; 433f8973cf4SManikanta Maddireddy 434f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 435f8973cf4SManikanta Maddireddy }; 436f8973cf4SManikanta Maddireddy }; 437f8973cf4SManikanta Maddireddy 4385524c61fSMikko Perttunen host1x@13e00000 { 4395524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 4405524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 4415524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 4425524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 4435524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 4445524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4455524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 4465524c61fSMikko Perttunen clock-names = "host1x"; 4475524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 4485524c61fSMikko Perttunen reset-names = "host1x"; 4495524c61fSMikko Perttunen 4505524c61fSMikko Perttunen #address-cells = <1>; 4515524c61fSMikko Perttunen #size-cells = <1>; 4525524c61fSMikko Perttunen 4535524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 454effc4b44SMikko Perttunen 455effc4b44SMikko Perttunen vic@15340000 { 456effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 457effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 458effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 459effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 460effc4b44SMikko Perttunen clock-names = "vic"; 461effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 462effc4b44SMikko Perttunen reset-names = "vic"; 463effc4b44SMikko Perttunen 464effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 465effc4b44SMikko Perttunen }; 4665524c61fSMikko Perttunen }; 4675524c61fSMikko Perttunen 468dfd7a384SAlexandre Courbot gpu@17000000 { 469dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 470dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 471dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 472dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 473dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 474dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 475dfd7a384SAlexandre Courbot 476dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 477dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 478dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 479dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 480dfd7a384SAlexandre Courbot reset-names = "gpu"; 481dfd7a384SAlexandre Courbot status = "disabled"; 482dfd7a384SAlexandre Courbot 483dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 484dfd7a384SAlexandre Courbot }; 485dfd7a384SAlexandre Courbot 48639cb62cbSJoseph Lo sysram@30000000 { 48739cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 48839cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 48939cb62cbSJoseph Lo #address-cells = <2>; 49039cb62cbSJoseph Lo #size-cells = <2>; 49139cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 49239cb62cbSJoseph Lo 49339cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 49439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 49539cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 49639cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 49739cb62cbSJoseph Lo pool; 49839cb62cbSJoseph Lo }; 49939cb62cbSJoseph Lo 50039cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 50139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 50239cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 50339cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 50439cb62cbSJoseph Lo pool; 50539cb62cbSJoseph Lo }; 50639cb62cbSJoseph Lo }; 50739cb62cbSJoseph Lo 508cd6fe32eSThierry Reding cpus { 509cd6fe32eSThierry Reding #address-cells = <1>; 510cd6fe32eSThierry Reding #size-cells = <0>; 511cd6fe32eSThierry Reding 512cd6fe32eSThierry Reding cpu@0 { 513cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 514cd6fe32eSThierry Reding device_type = "cpu"; 515cd6fe32eSThierry Reding reg = <0x000>; 516cd6fe32eSThierry Reding }; 517cd6fe32eSThierry Reding 518cd6fe32eSThierry Reding cpu@1 { 519cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 520cd6fe32eSThierry Reding device_type = "cpu"; 521cd6fe32eSThierry Reding reg = <0x001>; 522cd6fe32eSThierry Reding }; 523cd6fe32eSThierry Reding 524cd6fe32eSThierry Reding cpu@2 { 525cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 526cd6fe32eSThierry Reding device_type = "cpu"; 527cd6fe32eSThierry Reding reg = <0x100>; 528cd6fe32eSThierry Reding }; 529cd6fe32eSThierry Reding 530cd6fe32eSThierry Reding cpu@3 { 531cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 532cd6fe32eSThierry Reding device_type = "cpu"; 533cd6fe32eSThierry Reding reg = <0x101>; 534cd6fe32eSThierry Reding }; 535cd6fe32eSThierry Reding 536cd6fe32eSThierry Reding cpu@4 { 537cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 538cd6fe32eSThierry Reding device_type = "cpu"; 539cd6fe32eSThierry Reding reg = <0x102>; 540cd6fe32eSThierry Reding }; 541cd6fe32eSThierry Reding 542cd6fe32eSThierry Reding cpu@5 { 543cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 544cd6fe32eSThierry Reding device_type = "cpu"; 545cd6fe32eSThierry Reding reg = <0x103>; 546cd6fe32eSThierry Reding }; 547cd6fe32eSThierry Reding }; 548cd6fe32eSThierry Reding 54939cb62cbSJoseph Lo bpmp: bpmp { 55039cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 5515edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5525edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 55339cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 55439cb62cbSJoseph Lo #clock-cells = <1>; 55539cb62cbSJoseph Lo #reset-cells = <1>; 556dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 55739cb62cbSJoseph Lo 55839cb62cbSJoseph Lo bpmp_i2c: i2c { 55939cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 56039cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 56139cb62cbSJoseph Lo #address-cells = <1>; 56239cb62cbSJoseph Lo #size-cells = <0>; 56339cb62cbSJoseph Lo status = "disabled"; 56439cb62cbSJoseph Lo }; 56539cb62cbSJoseph Lo }; 56639cb62cbSJoseph Lo 56739cb62cbSJoseph Lo timer { 56839cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 56939cb62cbSJoseph Lo interrupts = <GIC_PPI 13 57039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 57139cb62cbSJoseph Lo <GIC_PPI 14 57239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 57339cb62cbSJoseph Lo <GIC_PPI 11 57439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 57539cb62cbSJoseph Lo <GIC_PPI 10 57639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 57739cb62cbSJoseph Lo interrupt-parent = <&gic>; 57839cb62cbSJoseph Lo }; 57939cb62cbSJoseph Lo}; 580