1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 640caafbdeSThierry Reding status = "disabled"; 650caafbdeSThierry Reding 660caafbdeSThierry Reding snps,write-requests = <1>; 670caafbdeSThierry Reding snps,read-requests = <3>; 680caafbdeSThierry Reding snps,burst-map = <0x7>; 690caafbdeSThierry Reding snps,txpbl = <32>; 700caafbdeSThierry Reding snps,rxpbl = <8>; 710caafbdeSThierry Reding }; 720caafbdeSThierry Reding 73d25a3bf1SThierry Reding memory-controller@2c00000 { 74d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 75d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 76d25a3bf1SThierry Reding status = "disabled"; 77d25a3bf1SThierry Reding }; 78d25a3bf1SThierry Reding 7939cb62cbSJoseph Lo uarta: serial@3100000 { 8039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8239cb62cbSJoseph Lo reg-shift = <2>; 8339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 84c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 85a7a77e2eSThierry Reding clock-names = "serial"; 867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 87a7a77e2eSThierry Reding reset-names = "serial"; 88a7a77e2eSThierry Reding status = "disabled"; 89a7a77e2eSThierry Reding }; 90a7a77e2eSThierry Reding 91a7a77e2eSThierry Reding uartb: serial@3110000 { 92a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 93a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 94a7a77e2eSThierry Reding reg-shift = <2>; 95a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 96c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 97a7a77e2eSThierry Reding clock-names = "serial"; 987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 99a7a77e2eSThierry Reding reset-names = "serial"; 100a7a77e2eSThierry Reding status = "disabled"; 101a7a77e2eSThierry Reding }; 102a7a77e2eSThierry Reding 103a7a77e2eSThierry Reding uartd: serial@3130000 { 104a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 105a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 106a7a77e2eSThierry Reding reg-shift = <2>; 107a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 108c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 109a7a77e2eSThierry Reding clock-names = "serial"; 1107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 111a7a77e2eSThierry Reding reset-names = "serial"; 112a7a77e2eSThierry Reding status = "disabled"; 113a7a77e2eSThierry Reding }; 114a7a77e2eSThierry Reding 115a7a77e2eSThierry Reding uarte: serial@3140000 { 116a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 117a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 118a7a77e2eSThierry Reding reg-shift = <2>; 119a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 120c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 121a7a77e2eSThierry Reding clock-names = "serial"; 1227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 123a7a77e2eSThierry Reding reset-names = "serial"; 124a7a77e2eSThierry Reding status = "disabled"; 125a7a77e2eSThierry Reding }; 126a7a77e2eSThierry Reding 127a7a77e2eSThierry Reding uartf: serial@3150000 { 128a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 129a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 130a7a77e2eSThierry Reding reg-shift = <2>; 131a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 132c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 133a7a77e2eSThierry Reding clock-names = "serial"; 1347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 135a7a77e2eSThierry Reding reset-names = "serial"; 13639cb62cbSJoseph Lo status = "disabled"; 13739cb62cbSJoseph Lo }; 13839cb62cbSJoseph Lo 13940cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 140250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 14140cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14240cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14340cc83b3SThierry Reding #address-cells = <1>; 14440cc83b3SThierry Reding #size-cells = <0>; 145c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14640cc83b3SThierry Reding clock-names = "div-clk"; 1477bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14840cc83b3SThierry Reding reset-names = "i2c"; 14940cc83b3SThierry Reding status = "disabled"; 15040cc83b3SThierry Reding }; 15140cc83b3SThierry Reding 15240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 153250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 15440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15640cc83b3SThierry Reding #address-cells = <1>; 15740cc83b3SThierry Reding #size-cells = <0>; 158c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15940cc83b3SThierry Reding clock-names = "div-clk"; 1607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16140cc83b3SThierry Reding reset-names = "i2c"; 16240cc83b3SThierry Reding status = "disabled"; 16340cc83b3SThierry Reding }; 16440cc83b3SThierry Reding 16540cc83b3SThierry Reding /* shares pads with dpaux1 */ 16640cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 167250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 16840cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16940cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 17040cc83b3SThierry Reding #address-cells = <1>; 17140cc83b3SThierry Reding #size-cells = <0>; 172c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17340cc83b3SThierry Reding clock-names = "div-clk"; 1747bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17540cc83b3SThierry Reding reset-names = "i2c"; 17640cc83b3SThierry Reding status = "disabled"; 17740cc83b3SThierry Reding }; 17840cc83b3SThierry Reding 17940cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 18040cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 181250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 18240cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18340cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18440cc83b3SThierry Reding #address-cells = <1>; 18540cc83b3SThierry Reding #size-cells = <0>; 186c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18740cc83b3SThierry Reding clock-names = "div-clk"; 1887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18940cc83b3SThierry Reding reset-names = "i2c"; 19040cc83b3SThierry Reding status = "disabled"; 19140cc83b3SThierry Reding }; 19240cc83b3SThierry Reding 19340cc83b3SThierry Reding /* shares pads with dpaux0 */ 19440cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 195250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 19640cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19740cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19840cc83b3SThierry Reding #address-cells = <1>; 19940cc83b3SThierry Reding #size-cells = <0>; 200c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20140cc83b3SThierry Reding clock-names = "div-clk"; 2027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20340cc83b3SThierry Reding reset-names = "i2c"; 20440cc83b3SThierry Reding status = "disabled"; 20540cc83b3SThierry Reding }; 20640cc83b3SThierry Reding 20740cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 208250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 20940cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 21040cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21140cc83b3SThierry Reding #address-cells = <1>; 21240cc83b3SThierry Reding #size-cells = <0>; 213c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21440cc83b3SThierry Reding clock-names = "div-clk"; 2157bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21640cc83b3SThierry Reding reset-names = "i2c"; 21740cc83b3SThierry Reding status = "disabled"; 21840cc83b3SThierry Reding }; 21940cc83b3SThierry Reding 22040cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 221250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 22240cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22340cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22440cc83b3SThierry Reding #address-cells = <1>; 22540cc83b3SThierry Reding #size-cells = <0>; 226c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22740cc83b3SThierry Reding clock-names = "div-clk"; 2287bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22940cc83b3SThierry Reding reset-names = "i2c"; 23040cc83b3SThierry Reding status = "disabled"; 23140cc83b3SThierry Reding }; 23240cc83b3SThierry Reding 23399425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23599425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23699425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 237c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23899425dfdSThierry Reding clock-names = "sdhci"; 2397bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 24099425dfdSThierry Reding reset-names = "sdhci"; 2418589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 24224005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24324005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 24424005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 24541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 24641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 24741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 24841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 24941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 25041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 2516f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2526f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 25398a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 25498a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25598a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25699425dfdSThierry Reding status = "disabled"; 25799425dfdSThierry Reding }; 25899425dfdSThierry Reding 25999425dfdSThierry Reding sdmmc2: sdhci@3420000 { 26099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 26199425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 26299425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 263c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 26499425dfdSThierry Reding clock-names = "sdhci"; 2657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 26699425dfdSThierry Reding reset-names = "sdhci"; 2678589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 26824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 26924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 27024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 27141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 27241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 27341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 27441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2756f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2766f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 27799425dfdSThierry Reding status = "disabled"; 27899425dfdSThierry Reding }; 27999425dfdSThierry Reding 28099425dfdSThierry Reding sdmmc3: sdhci@3440000 { 28199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 28299425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 28399425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 284c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 28599425dfdSThierry Reding clock-names = "sdhci"; 2867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 28799425dfdSThierry Reding reset-names = "sdhci"; 2888589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 28924005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 29024005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 29124005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 29241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 29341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 29441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 29541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 29641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 29741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2986f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2996f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 30099425dfdSThierry Reding status = "disabled"; 30199425dfdSThierry Reding }; 30299425dfdSThierry Reding 30399425dfdSThierry Reding sdmmc4: sdhci@3460000 { 30499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 30599425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 30699425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 307c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 30899425dfdSThierry Reding clock-names = "sdhci"; 30998a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 31098a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 31198a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 3127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 31399425dfdSThierry Reding reset-names = "sdhci"; 3148589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 31541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 31641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 31741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 31841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3194e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3204e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 321e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 322e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 32322248e91SAapo Vienamo nvidia,dqs-trim = <63>; 324207f60baSAapo Vienamo mmc-hs400-1_8v; 325c4307836SSowjanya Komatineni supports-cqe; 32699425dfdSThierry Reding status = "disabled"; 32799425dfdSThierry Reding }; 32899425dfdSThierry Reding 329b066a310SThierry Reding hda@3510000 { 330b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 331b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 332b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 333b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 334b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 335b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 336b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 337b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 338b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 339b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 340b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 341b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 342dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 343b066a310SThierry Reding status = "disabled"; 344b066a310SThierry Reding }; 345b066a310SThierry Reding 3468bfde518SThierry Reding padctl: padctl@3520000 { 3478bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 3488bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 3498bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 3508bfde518SThierry Reding reg-names = "padctl", "ao"; 3518bfde518SThierry Reding 3528bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 3538bfde518SThierry Reding reset-names = "padctl"; 3548bfde518SThierry Reding 3558bfde518SThierry Reding status = "disabled"; 3568bfde518SThierry Reding 3578bfde518SThierry Reding pads { 3588bfde518SThierry Reding usb2 { 3598bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 3608bfde518SThierry Reding clock-names = "trk"; 3618bfde518SThierry Reding status = "disabled"; 3628bfde518SThierry Reding 3638bfde518SThierry Reding lanes { 3648bfde518SThierry Reding usb2-0 { 3658bfde518SThierry Reding status = "disabled"; 3668bfde518SThierry Reding #phy-cells = <0>; 3678bfde518SThierry Reding }; 3688bfde518SThierry Reding 3698bfde518SThierry Reding usb2-1 { 3708bfde518SThierry Reding status = "disabled"; 3718bfde518SThierry Reding #phy-cells = <0>; 3728bfde518SThierry Reding }; 3738bfde518SThierry Reding 3748bfde518SThierry Reding usb2-2 { 3758bfde518SThierry Reding status = "disabled"; 3768bfde518SThierry Reding #phy-cells = <0>; 3778bfde518SThierry Reding }; 3788bfde518SThierry Reding }; 3798bfde518SThierry Reding }; 3808bfde518SThierry Reding 3818bfde518SThierry Reding hsic { 3828bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 3838bfde518SThierry Reding clock-names = "trk"; 3848bfde518SThierry Reding status = "disabled"; 3858bfde518SThierry Reding 3868bfde518SThierry Reding lanes { 3878bfde518SThierry Reding hsic-0 { 3888bfde518SThierry Reding status = "disabled"; 3898bfde518SThierry Reding #phy-cells = <0>; 3908bfde518SThierry Reding }; 3918bfde518SThierry Reding }; 3928bfde518SThierry Reding }; 3938bfde518SThierry Reding 3948bfde518SThierry Reding usb3 { 3958bfde518SThierry Reding status = "disabled"; 3968bfde518SThierry Reding 3978bfde518SThierry Reding lanes { 3988bfde518SThierry Reding usb3-0 { 3998bfde518SThierry Reding status = "disabled"; 4008bfde518SThierry Reding #phy-cells = <0>; 4018bfde518SThierry Reding }; 4028bfde518SThierry Reding 4038bfde518SThierry Reding usb3-1 { 4048bfde518SThierry Reding status = "disabled"; 4058bfde518SThierry Reding #phy-cells = <0>; 4068bfde518SThierry Reding }; 4078bfde518SThierry Reding 4088bfde518SThierry Reding usb3-2 { 4098bfde518SThierry Reding status = "disabled"; 4108bfde518SThierry Reding #phy-cells = <0>; 4118bfde518SThierry Reding }; 4128bfde518SThierry Reding }; 4138bfde518SThierry Reding }; 4148bfde518SThierry Reding }; 4158bfde518SThierry Reding 4168bfde518SThierry Reding ports { 4178bfde518SThierry Reding usb2-0 { 4188bfde518SThierry Reding status = "disabled"; 4198bfde518SThierry Reding }; 4208bfde518SThierry Reding 4218bfde518SThierry Reding usb2-1 { 4228bfde518SThierry Reding status = "disabled"; 4238bfde518SThierry Reding }; 4248bfde518SThierry Reding 4258bfde518SThierry Reding usb2-2 { 4268bfde518SThierry Reding status = "disabled"; 4278bfde518SThierry Reding }; 4288bfde518SThierry Reding 4298bfde518SThierry Reding hsic-0 { 4308bfde518SThierry Reding status = "disabled"; 4318bfde518SThierry Reding }; 4328bfde518SThierry Reding 4338bfde518SThierry Reding usb3-0 { 4348bfde518SThierry Reding status = "disabled"; 4358bfde518SThierry Reding }; 4368bfde518SThierry Reding 4378bfde518SThierry Reding usb3-1 { 4388bfde518SThierry Reding status = "disabled"; 4398bfde518SThierry Reding }; 4408bfde518SThierry Reding 4418bfde518SThierry Reding usb3-2 { 4428bfde518SThierry Reding status = "disabled"; 4438bfde518SThierry Reding }; 4448bfde518SThierry Reding }; 4458bfde518SThierry Reding }; 4468bfde518SThierry Reding 4478bfde518SThierry Reding usb@3530000 { 4488bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 4498bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 4508bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 4518bfde518SThierry Reding reg-names = "hcd", "fpci"; 4528bfde518SThierry Reding 4538bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4548bfde518SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 4558bfde518SThierry Reding <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 4568bfde518SThierry Reding 4578bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 4588bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 4598bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 4608bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 4618bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 4628bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 4638bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 4648bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 4658bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 4668bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 4678bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 4688bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 4698bfde518SThierry Reding 4708bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 4718bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 4728bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 4738bfde518SThierry Reding nvidia,xusb-padctl = <&padctl>; 4748bfde518SThierry Reding 4758bfde518SThierry Reding status = "disabled"; 4768bfde518SThierry Reding 4778bfde518SThierry Reding #address-cells = <1>; 4788bfde518SThierry Reding #size-cells = <0>; 4798bfde518SThierry Reding }; 4808bfde518SThierry Reding 48185593b75SThierry Reding fuse@3820000 { 48285593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 48385593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 48485593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 48585593b75SThierry Reding clock-names = "fuse"; 48685593b75SThierry Reding }; 48785593b75SThierry Reding 48839cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 48939cb62cbSJoseph Lo compatible = "arm,gic-400"; 49039cb62cbSJoseph Lo #interrupt-cells = <3>; 49139cb62cbSJoseph Lo interrupt-controller; 49239cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 49339cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 49439cb62cbSJoseph Lo interrupts = <GIC_PPI 9 49539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 49639cb62cbSJoseph Lo interrupt-parent = <&gic>; 49739cb62cbSJoseph Lo }; 49839cb62cbSJoseph Lo 49997cf683cSThierry Reding cec@3960000 { 50097cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 50197cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 50297cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 50397cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 50497cf683cSThierry Reding clock-names = "cec"; 50597cf683cSThierry Reding status = "disabled"; 50697cf683cSThierry Reding }; 50797cf683cSThierry Reding 50839cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 50939cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 51039cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 51139cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 51239cb62cbSJoseph Lo interrupt-names = "doorbell"; 51339cb62cbSJoseph Lo #mbox-cells = <2>; 51439cb62cbSJoseph Lo status = "disabled"; 51539cb62cbSJoseph Lo }; 51639cb62cbSJoseph Lo 51740cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 518250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 51940cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 52040cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 52140cc83b3SThierry Reding #address-cells = <1>; 52240cc83b3SThierry Reding #size-cells = <0>; 523c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 52440cc83b3SThierry Reding clock-names = "div-clk"; 5257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 52640cc83b3SThierry Reding reset-names = "i2c"; 52740cc83b3SThierry Reding status = "disabled"; 52840cc83b3SThierry Reding }; 52940cc83b3SThierry Reding 53040cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 531250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 53240cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 53340cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 53440cc83b3SThierry Reding #address-cells = <1>; 53540cc83b3SThierry Reding #size-cells = <0>; 536c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 53740cc83b3SThierry Reding clock-names = "div-clk"; 5387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 53940cc83b3SThierry Reding reset-names = "i2c"; 54040cc83b3SThierry Reding status = "disabled"; 54140cc83b3SThierry Reding }; 54240cc83b3SThierry Reding 543a7a77e2eSThierry Reding uartc: serial@c280000 { 544a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 545a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 546a7a77e2eSThierry Reding reg-shift = <2>; 547a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 548c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 549a7a77e2eSThierry Reding clock-names = "serial"; 5507bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 551a7a77e2eSThierry Reding reset-names = "serial"; 552a7a77e2eSThierry Reding status = "disabled"; 553a7a77e2eSThierry Reding }; 554a7a77e2eSThierry Reding 555a7a77e2eSThierry Reding uartg: serial@c290000 { 556a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 557a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 558a7a77e2eSThierry Reding reg-shift = <2>; 559a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 560c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 561a7a77e2eSThierry Reding clock-names = "serial"; 5627bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 563a7a77e2eSThierry Reding reset-names = "serial"; 564a7a77e2eSThierry Reding status = "disabled"; 565a7a77e2eSThierry Reding }; 566a7a77e2eSThierry Reding 5679733a251SThierry Reding rtc: rtc@c2a0000 { 5689733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 5699733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 5709733a251SThierry Reding interrupt-parent = <&pmc>; 5719733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 5729733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 5739733a251SThierry Reding clock-names = "rtc"; 5749733a251SThierry Reding status = "disabled"; 5759733a251SThierry Reding }; 5769733a251SThierry Reding 577fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 578fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 579fc4bb754SThierry Reding reg-names = "security", "gpio"; 580fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 581fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 582fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 583fc4bb754SThierry Reding gpio-controller; 584fc4bb754SThierry Reding #gpio-cells = <2>; 585fc4bb754SThierry Reding interrupt-controller; 586fc4bb754SThierry Reding #interrupt-cells = <2>; 587fc4bb754SThierry Reding }; 588fc4bb754SThierry Reding 58932e66e46SThierry Reding pmc: pmc@c360000 { 59073bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 59173bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 59273bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 59373bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 59473bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 59573bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 59624005fd1SAapo Vienamo 59732e66e46SThierry Reding #interrupt-cells = <2>; 59832e66e46SThierry Reding interrupt-controller; 59932e66e46SThierry Reding 60024005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 60124005fd1SAapo Vienamo pins = "sdmmc1-hv"; 60224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 60324005fd1SAapo Vienamo }; 60424005fd1SAapo Vienamo 60524005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 60624005fd1SAapo Vienamo pins = "sdmmc1-hv"; 60724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 60824005fd1SAapo Vienamo }; 60924005fd1SAapo Vienamo 61024005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 61124005fd1SAapo Vienamo pins = "sdmmc2-hv"; 61224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 61324005fd1SAapo Vienamo }; 61424005fd1SAapo Vienamo 61524005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 61624005fd1SAapo Vienamo pins = "sdmmc2-hv"; 61724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 61824005fd1SAapo Vienamo }; 61924005fd1SAapo Vienamo 62024005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 62124005fd1SAapo Vienamo pins = "sdmmc3-hv"; 62224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 62324005fd1SAapo Vienamo }; 62424005fd1SAapo Vienamo 62524005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 62624005fd1SAapo Vienamo pins = "sdmmc3-hv"; 62724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 62824005fd1SAapo Vienamo }; 62973bf90d4SThierry Reding }; 63073bf90d4SThierry Reding 6317b7ef494SMikko Perttunen ccplex@e000000 { 6327b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 6337b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 6347b7ef494SMikko Perttunen 6357b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 6367b7ef494SMikko Perttunen }; 6377b7ef494SMikko Perttunen 638f8973cf4SManikanta Maddireddy pcie@10003000 { 639f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 640f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 641f8973cf4SManikanta Maddireddy device_type = "pci"; 642f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 643f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 644f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 645f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 646f8973cf4SManikanta Maddireddy 647f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 648f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 649f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 650f8973cf4SManikanta Maddireddy 651f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 652f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 653f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 654f8973cf4SManikanta Maddireddy 655f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 656f8973cf4SManikanta Maddireddy #address-cells = <3>; 657f8973cf4SManikanta Maddireddy #size-cells = <2>; 658f8973cf4SManikanta Maddireddy 659f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 660f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 661f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 662f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 663f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 664f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 665f8973cf4SManikanta Maddireddy 666f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 667f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 668f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 669f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 670f8973cf4SManikanta Maddireddy 671f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 672f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 673f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 674f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 675f8973cf4SManikanta Maddireddy 676f8973cf4SManikanta Maddireddy status = "disabled"; 677f8973cf4SManikanta Maddireddy 678f8973cf4SManikanta Maddireddy pci@1,0 { 679f8973cf4SManikanta Maddireddy device_type = "pci"; 680f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 681f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 682f8973cf4SManikanta Maddireddy status = "disabled"; 683f8973cf4SManikanta Maddireddy 684f8973cf4SManikanta Maddireddy #address-cells = <3>; 685f8973cf4SManikanta Maddireddy #size-cells = <2>; 686f8973cf4SManikanta Maddireddy ranges; 687f8973cf4SManikanta Maddireddy 688f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 689f8973cf4SManikanta Maddireddy }; 690f8973cf4SManikanta Maddireddy 691f8973cf4SManikanta Maddireddy pci@2,0 { 692f8973cf4SManikanta Maddireddy device_type = "pci"; 693f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 694f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 695f8973cf4SManikanta Maddireddy status = "disabled"; 696f8973cf4SManikanta Maddireddy 697f8973cf4SManikanta Maddireddy #address-cells = <3>; 698f8973cf4SManikanta Maddireddy #size-cells = <2>; 699f8973cf4SManikanta Maddireddy ranges; 700f8973cf4SManikanta Maddireddy 701f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 702f8973cf4SManikanta Maddireddy }; 703f8973cf4SManikanta Maddireddy 704f8973cf4SManikanta Maddireddy pci@3,0 { 705f8973cf4SManikanta Maddireddy device_type = "pci"; 706f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 707f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 708f8973cf4SManikanta Maddireddy status = "disabled"; 709f8973cf4SManikanta Maddireddy 710f8973cf4SManikanta Maddireddy #address-cells = <3>; 711f8973cf4SManikanta Maddireddy #size-cells = <2>; 712f8973cf4SManikanta Maddireddy ranges; 713f8973cf4SManikanta Maddireddy 714f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 715f8973cf4SManikanta Maddireddy }; 716f8973cf4SManikanta Maddireddy }; 717f8973cf4SManikanta Maddireddy 718b30a8e61SThierry Reding smmu: iommu@12000000 { 719b30a8e61SThierry Reding compatible = "arm,mmu-500"; 720b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 721b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 722b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 723b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 724b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 725b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 726b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 727b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 728b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 729b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 730b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 731b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 732b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 733b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 734b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 735b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 736b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 737b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 738b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 739b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 740b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 741b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 742b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 743b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 744b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 745b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 746b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 747b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 748b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 749b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 750b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 751b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 752b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 753b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 754b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 755b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 756b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 757b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 758b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 759b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 760b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 761b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 762b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 763b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 764b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 765b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 766b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 767b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 768b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 769b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 770b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 771b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 772b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 773b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 774b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 775b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 776b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 777b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 778b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 779b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 780b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 781b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 782b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 783b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 784b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 785b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 786b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 787b30a8e61SThierry Reding #global-interrupts = <1>; 788b30a8e61SThierry Reding #iommu-cells = <1>; 789b30a8e61SThierry Reding }; 790b30a8e61SThierry Reding 7915524c61fSMikko Perttunen host1x@13e00000 { 7925524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 7935524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 7945524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 7955524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 7965524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 7975524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 7985524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 7995524c61fSMikko Perttunen clock-names = "host1x"; 8005524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 8015524c61fSMikko Perttunen reset-names = "host1x"; 8025524c61fSMikko Perttunen 8035524c61fSMikko Perttunen #address-cells = <1>; 8045524c61fSMikko Perttunen #size-cells = <1>; 8055524c61fSMikko Perttunen 8065524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 807c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 808c2599da7SThierry Reding 809c2599da7SThierry Reding dpaux1: dpaux@15040000 { 810c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 811c2599da7SThierry Reding reg = <0x15040000 0x10000>; 812c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 813c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 814c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 815c2599da7SThierry Reding clock-names = "dpaux", "parent"; 816c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 817c2599da7SThierry Reding reset-names = "dpaux"; 818c2599da7SThierry Reding status = "disabled"; 819c2599da7SThierry Reding 820c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 821c2599da7SThierry Reding 822c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 823c2599da7SThierry Reding groups = "dpaux-io"; 824c2599da7SThierry Reding function = "aux"; 825c2599da7SThierry Reding }; 826c2599da7SThierry Reding 827c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 828c2599da7SThierry Reding groups = "dpaux-io"; 829c2599da7SThierry Reding function = "i2c"; 830c2599da7SThierry Reding }; 831c2599da7SThierry Reding 832c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 833c2599da7SThierry Reding groups = "dpaux-io"; 834c2599da7SThierry Reding function = "off"; 835c2599da7SThierry Reding }; 836c2599da7SThierry Reding 837c2599da7SThierry Reding i2c-bus { 838c2599da7SThierry Reding #address-cells = <1>; 839c2599da7SThierry Reding #size-cells = <0>; 840c2599da7SThierry Reding }; 841c2599da7SThierry Reding }; 842c2599da7SThierry Reding 843c2599da7SThierry Reding display-hub@15200000 { 844c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 845ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 846c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 847c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 848c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 849c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 850c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 851c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 852c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 853c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 854c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 855c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 856c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 857c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 858c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 859c2599da7SThierry Reding status = "disabled"; 860c2599da7SThierry Reding 861c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 862c2599da7SThierry Reding 863c2599da7SThierry Reding #address-cells = <1>; 864c2599da7SThierry Reding #size-cells = <1>; 865c2599da7SThierry Reding 866c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 867c2599da7SThierry Reding 868c2599da7SThierry Reding display@15200000 { 869c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 870c2599da7SThierry Reding reg = <0x15200000 0x10000>; 871c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 872c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 873c2599da7SThierry Reding clock-names = "dc"; 874c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 875c2599da7SThierry Reding reset-names = "dc"; 876c2599da7SThierry Reding 877c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 878c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 879c2599da7SThierry Reding 880c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 881c2599da7SThierry Reding nvidia,head = <0>; 882c2599da7SThierry Reding }; 883c2599da7SThierry Reding 884c2599da7SThierry Reding display@15210000 { 885c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 886c2599da7SThierry Reding reg = <0x15210000 0x10000>; 887c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 888c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 889c2599da7SThierry Reding clock-names = "dc"; 890c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 891c2599da7SThierry Reding reset-names = "dc"; 892c2599da7SThierry Reding 893c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 894c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 895c2599da7SThierry Reding 896c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 897c2599da7SThierry Reding nvidia,head = <1>; 898c2599da7SThierry Reding }; 899c2599da7SThierry Reding 900c2599da7SThierry Reding display@15220000 { 901c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 902c2599da7SThierry Reding reg = <0x15220000 0x10000>; 903c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 904c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 905c2599da7SThierry Reding clock-names = "dc"; 906c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 907c2599da7SThierry Reding reset-names = "dc"; 908c2599da7SThierry Reding 909c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 910c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 911c2599da7SThierry Reding 912c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 913c2599da7SThierry Reding nvidia,head = <2>; 914c2599da7SThierry Reding }; 915c2599da7SThierry Reding }; 916c2599da7SThierry Reding 917c2599da7SThierry Reding dsia: dsi@15300000 { 918c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 919c2599da7SThierry Reding reg = <0x15300000 0x10000>; 920c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 921c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 922c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 923c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 924c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 925c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 926c2599da7SThierry Reding reset-names = "dsi"; 927c2599da7SThierry Reding status = "disabled"; 928c2599da7SThierry Reding 929c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 930c2599da7SThierry Reding }; 931effc4b44SMikko Perttunen 932effc4b44SMikko Perttunen vic@15340000 { 933effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 934effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 935effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 936effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 937effc4b44SMikko Perttunen clock-names = "vic"; 938effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 939effc4b44SMikko Perttunen reset-names = "vic"; 940effc4b44SMikko Perttunen 941effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 942effc4b44SMikko Perttunen }; 943c2599da7SThierry Reding 944c2599da7SThierry Reding dsib: dsi@15400000 { 945c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 946c2599da7SThierry Reding reg = <0x15400000 0x10000>; 947c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 948c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 949c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 950c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 951c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 952c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 953c2599da7SThierry Reding reset-names = "dsi"; 954c2599da7SThierry Reding status = "disabled"; 955c2599da7SThierry Reding 956c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 957c2599da7SThierry Reding }; 958c2599da7SThierry Reding 959c2599da7SThierry Reding sor0: sor@15540000 { 960c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 961c2599da7SThierry Reding reg = <0x15540000 0x10000>; 962c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 963c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 964c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 965c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 966c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 967c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 968c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 969c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 970c2599da7SThierry Reding "pad"; 971c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 972c2599da7SThierry Reding reset-names = "sor"; 973c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 974c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 975c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 976c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 977c2599da7SThierry Reding status = "disabled"; 978c2599da7SThierry Reding 979c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 980c2599da7SThierry Reding nvidia,interface = <0>; 981c2599da7SThierry Reding }; 982c2599da7SThierry Reding 983c2599da7SThierry Reding sor1: sor@15580000 { 984c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 985c2599da7SThierry Reding reg = <0x15580000 0x10000>; 986c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 987c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 988c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 989c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 990c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 991c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 992c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 993c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 994c2599da7SThierry Reding "pad"; 995c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 996c2599da7SThierry Reding reset-names = "sor"; 997c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 998c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 999c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1000c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1001c2599da7SThierry Reding status = "disabled"; 1002c2599da7SThierry Reding 1003c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1004c2599da7SThierry Reding nvidia,interface = <1>; 1005c2599da7SThierry Reding }; 1006c2599da7SThierry Reding 1007c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1008c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1009c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1010c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1011c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1012c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1013c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1014c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1015c2599da7SThierry Reding reset-names = "dpaux"; 1016c2599da7SThierry Reding status = "disabled"; 1017c2599da7SThierry Reding 1018c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1019c2599da7SThierry Reding 1020c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1021c2599da7SThierry Reding groups = "dpaux-io"; 1022c2599da7SThierry Reding function = "aux"; 1023c2599da7SThierry Reding }; 1024c2599da7SThierry Reding 1025c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1026c2599da7SThierry Reding groups = "dpaux-io"; 1027c2599da7SThierry Reding function = "i2c"; 1028c2599da7SThierry Reding }; 1029c2599da7SThierry Reding 1030c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1031c2599da7SThierry Reding groups = "dpaux-io"; 1032c2599da7SThierry Reding function = "off"; 1033c2599da7SThierry Reding }; 1034c2599da7SThierry Reding 1035c2599da7SThierry Reding i2c-bus { 1036c2599da7SThierry Reding #address-cells = <1>; 1037c2599da7SThierry Reding #size-cells = <0>; 1038c2599da7SThierry Reding }; 1039c2599da7SThierry Reding }; 1040c2599da7SThierry Reding 1041c2599da7SThierry Reding padctl@15880000 { 1042c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1043c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1044c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1045c2599da7SThierry Reding reset-names = "dsi"; 1046c2599da7SThierry Reding status = "disabled"; 1047c2599da7SThierry Reding }; 1048c2599da7SThierry Reding 1049c2599da7SThierry Reding dsic: dsi@15900000 { 1050c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1051c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1052c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1053c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1054c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1055c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1056c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1057c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1058c2599da7SThierry Reding reset-names = "dsi"; 1059c2599da7SThierry Reding status = "disabled"; 1060c2599da7SThierry Reding 1061c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1062c2599da7SThierry Reding }; 1063c2599da7SThierry Reding 1064c2599da7SThierry Reding dsid: dsi@15940000 { 1065c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1066c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1067c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1068c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1069c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1070c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1071c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1072c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1073c2599da7SThierry Reding reset-names = "dsi"; 1074c2599da7SThierry Reding status = "disabled"; 1075c2599da7SThierry Reding 1076c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1077c2599da7SThierry Reding }; 10785524c61fSMikko Perttunen }; 10795524c61fSMikko Perttunen 1080dfd7a384SAlexandre Courbot gpu@17000000 { 1081dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1082dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1083dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 1084dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1085dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1086dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1087dfd7a384SAlexandre Courbot 1088dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1089dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1090dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1091dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1092dfd7a384SAlexandre Courbot reset-names = "gpu"; 1093dfd7a384SAlexandre Courbot status = "disabled"; 1094dfd7a384SAlexandre Courbot 1095dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1096dfd7a384SAlexandre Courbot }; 1097dfd7a384SAlexandre Courbot 109839cb62cbSJoseph Lo sysram@30000000 { 109939cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 110039cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 110139cb62cbSJoseph Lo #address-cells = <2>; 110239cb62cbSJoseph Lo #size-cells = <2>; 110339cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 110439cb62cbSJoseph Lo 110539cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 110639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 110739cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 110839cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 110939cb62cbSJoseph Lo pool; 111039cb62cbSJoseph Lo }; 111139cb62cbSJoseph Lo 111239cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 111339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 111439cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 111539cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 111639cb62cbSJoseph Lo pool; 111739cb62cbSJoseph Lo }; 111839cb62cbSJoseph Lo }; 111939cb62cbSJoseph Lo 1120cd6fe32eSThierry Reding cpus { 1121cd6fe32eSThierry Reding #address-cells = <1>; 1122cd6fe32eSThierry Reding #size-cells = <0>; 1123cd6fe32eSThierry Reding 1124cd6fe32eSThierry Reding cpu@0 { 112531af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1126cd6fe32eSThierry Reding device_type = "cpu"; 1127cd6fe32eSThierry Reding reg = <0x000>; 1128cd6fe32eSThierry Reding }; 1129cd6fe32eSThierry Reding 1130cd6fe32eSThierry Reding cpu@1 { 113131af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1132cd6fe32eSThierry Reding device_type = "cpu"; 1133cd6fe32eSThierry Reding reg = <0x001>; 1134cd6fe32eSThierry Reding }; 1135cd6fe32eSThierry Reding 1136cd6fe32eSThierry Reding cpu@2 { 113731af04cdSRob Herring compatible = "arm,cortex-a57"; 1138cd6fe32eSThierry Reding device_type = "cpu"; 1139cd6fe32eSThierry Reding reg = <0x100>; 1140cd6fe32eSThierry Reding }; 1141cd6fe32eSThierry Reding 1142cd6fe32eSThierry Reding cpu@3 { 114331af04cdSRob Herring compatible = "arm,cortex-a57"; 1144cd6fe32eSThierry Reding device_type = "cpu"; 1145cd6fe32eSThierry Reding reg = <0x101>; 1146cd6fe32eSThierry Reding }; 1147cd6fe32eSThierry Reding 1148cd6fe32eSThierry Reding cpu@4 { 114931af04cdSRob Herring compatible = "arm,cortex-a57"; 1150cd6fe32eSThierry Reding device_type = "cpu"; 1151cd6fe32eSThierry Reding reg = <0x102>; 1152cd6fe32eSThierry Reding }; 1153cd6fe32eSThierry Reding 1154cd6fe32eSThierry Reding cpu@5 { 115531af04cdSRob Herring compatible = "arm,cortex-a57"; 1156cd6fe32eSThierry Reding device_type = "cpu"; 1157cd6fe32eSThierry Reding reg = <0x103>; 1158cd6fe32eSThierry Reding }; 1159cd6fe32eSThierry Reding }; 1160cd6fe32eSThierry Reding 116139cb62cbSJoseph Lo bpmp: bpmp { 116239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 1163dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_BPMP>; 11645edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 11655edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 116639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 116739cb62cbSJoseph Lo #clock-cells = <1>; 116839cb62cbSJoseph Lo #reset-cells = <1>; 1169dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 117039cb62cbSJoseph Lo 117139cb62cbSJoseph Lo bpmp_i2c: i2c { 117239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 117339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 117439cb62cbSJoseph Lo #address-cells = <1>; 117539cb62cbSJoseph Lo #size-cells = <0>; 117639cb62cbSJoseph Lo status = "disabled"; 117739cb62cbSJoseph Lo }; 117815274c23SMikko Perttunen 117915274c23SMikko Perttunen bpmp_thermal: thermal { 118015274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 118115274c23SMikko Perttunen #thermal-sensor-cells = <1>; 118215274c23SMikko Perttunen }; 118315274c23SMikko Perttunen }; 118415274c23SMikko Perttunen 118515274c23SMikko Perttunen thermal-zones { 118615274c23SMikko Perttunen a57 { 118715274c23SMikko Perttunen polling-delay = <0>; 118815274c23SMikko Perttunen polling-delay-passive = <1000>; 118915274c23SMikko Perttunen 119015274c23SMikko Perttunen thermal-sensors = 119115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 119215274c23SMikko Perttunen 119315274c23SMikko Perttunen trips { 119415274c23SMikko Perttunen critical { 119515274c23SMikko Perttunen temperature = <101000>; 119615274c23SMikko Perttunen hysteresis = <0>; 119715274c23SMikko Perttunen type = "critical"; 119815274c23SMikko Perttunen }; 119915274c23SMikko Perttunen }; 120015274c23SMikko Perttunen 120115274c23SMikko Perttunen cooling-maps { 120215274c23SMikko Perttunen }; 120315274c23SMikko Perttunen }; 120415274c23SMikko Perttunen 120515274c23SMikko Perttunen denver { 120615274c23SMikko Perttunen polling-delay = <0>; 120715274c23SMikko Perttunen polling-delay-passive = <1000>; 120815274c23SMikko Perttunen 120915274c23SMikko Perttunen thermal-sensors = 121015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 121115274c23SMikko Perttunen 121215274c23SMikko Perttunen trips { 121315274c23SMikko Perttunen critical { 121415274c23SMikko Perttunen temperature = <101000>; 121515274c23SMikko Perttunen hysteresis = <0>; 121615274c23SMikko Perttunen type = "critical"; 121715274c23SMikko Perttunen }; 121815274c23SMikko Perttunen }; 121915274c23SMikko Perttunen 122015274c23SMikko Perttunen cooling-maps { 122115274c23SMikko Perttunen }; 122215274c23SMikko Perttunen }; 122315274c23SMikko Perttunen 122415274c23SMikko Perttunen gpu { 122515274c23SMikko Perttunen polling-delay = <0>; 122615274c23SMikko Perttunen polling-delay-passive = <1000>; 122715274c23SMikko Perttunen 122815274c23SMikko Perttunen thermal-sensors = 122915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 123015274c23SMikko Perttunen 123115274c23SMikko Perttunen trips { 123215274c23SMikko Perttunen critical { 123315274c23SMikko Perttunen temperature = <101000>; 123415274c23SMikko Perttunen hysteresis = <0>; 123515274c23SMikko Perttunen type = "critical"; 123615274c23SMikko Perttunen }; 123715274c23SMikko Perttunen }; 123815274c23SMikko Perttunen 123915274c23SMikko Perttunen cooling-maps { 124015274c23SMikko Perttunen }; 124115274c23SMikko Perttunen }; 124215274c23SMikko Perttunen 124315274c23SMikko Perttunen pll { 124415274c23SMikko Perttunen polling-delay = <0>; 124515274c23SMikko Perttunen polling-delay-passive = <1000>; 124615274c23SMikko Perttunen 124715274c23SMikko Perttunen thermal-sensors = 124815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 124915274c23SMikko Perttunen 125015274c23SMikko Perttunen trips { 125115274c23SMikko Perttunen critical { 125215274c23SMikko Perttunen temperature = <101000>; 125315274c23SMikko Perttunen hysteresis = <0>; 125415274c23SMikko Perttunen type = "critical"; 125515274c23SMikko Perttunen }; 125615274c23SMikko Perttunen }; 125715274c23SMikko Perttunen 125815274c23SMikko Perttunen cooling-maps { 125915274c23SMikko Perttunen }; 126015274c23SMikko Perttunen }; 126115274c23SMikko Perttunen 126215274c23SMikko Perttunen always_on { 126315274c23SMikko Perttunen polling-delay = <0>; 126415274c23SMikko Perttunen polling-delay-passive = <1000>; 126515274c23SMikko Perttunen 126615274c23SMikko Perttunen thermal-sensors = 126715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 126815274c23SMikko Perttunen 126915274c23SMikko Perttunen trips { 127015274c23SMikko Perttunen critical { 127115274c23SMikko Perttunen temperature = <101000>; 127215274c23SMikko Perttunen hysteresis = <0>; 127315274c23SMikko Perttunen type = "critical"; 127415274c23SMikko Perttunen }; 127515274c23SMikko Perttunen }; 127615274c23SMikko Perttunen 127715274c23SMikko Perttunen cooling-maps { 127815274c23SMikko Perttunen }; 127915274c23SMikko Perttunen }; 128039cb62cbSJoseph Lo }; 128139cb62cbSJoseph Lo 128239cb62cbSJoseph Lo timer { 128339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 128439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 128539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128639cb62cbSJoseph Lo <GIC_PPI 14 128739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128839cb62cbSJoseph Lo <GIC_PPI 11 128939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 129039cb62cbSJoseph Lo <GIC_PPI 10 129139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 129239cb62cbSJoseph Lo interrupt-parent = <&gic>; 129339cb62cbSJoseph Lo }; 129439cb62cbSJoseph Lo}; 1295