1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113835553b3SAkhil R #dma-cells = <1>; 114835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115835553b3SAkhil R dma-coherent; 116dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 117835553b3SAkhil R status = "okay"; 118835553b3SAkhil R }; 119835553b3SAkhil R 1204b154b94SThierry Reding aconnect@2900000 { 1215d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1225d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1235d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1245d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1255d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1265d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1275d2249ddSSameer Pujar #address-cells = <1>; 1285d2249ddSSameer Pujar #size-cells = <1>; 1295d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1305d2249ddSSameer Pujar status = "disabled"; 1315d2249ddSSameer Pujar 132177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 133177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 134177208f7SSameer Pujar reg = <0x02900800 0x800>; 135177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 136177208f7SSameer Pujar clock-names = "ahub"; 137177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138*dc6d5d85SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 139*dc6d5d85SSameer Pujar assigned-clock-rates = <81600000>; 140177208f7SSameer Pujar #address-cells = <1>; 141177208f7SSameer Pujar #size-cells = <1>; 142177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 143177208f7SSameer Pujar status = "disabled"; 144177208f7SSameer Pujar 145177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 146177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 147177208f7SSameer Pujar "nvidia,tegra210-i2s"; 148177208f7SSameer Pujar reg = <0x2901000 0x100>; 149177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 150177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 151177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 152177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 153177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 154177208f7SSameer Pujar assigned-clock-rates = <1536000>; 155177208f7SSameer Pujar sound-name-prefix = "I2S1"; 156177208f7SSameer Pujar status = "disabled"; 157177208f7SSameer Pujar }; 158177208f7SSameer Pujar 159177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 160177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 161177208f7SSameer Pujar "nvidia,tegra210-i2s"; 162177208f7SSameer Pujar reg = <0x2901100 0x100>; 163177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 164177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 165177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 166177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 167177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 168177208f7SSameer Pujar assigned-clock-rates = <1536000>; 169177208f7SSameer Pujar sound-name-prefix = "I2S2"; 170177208f7SSameer Pujar status = "disabled"; 171177208f7SSameer Pujar }; 172177208f7SSameer Pujar 173177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 174177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 175177208f7SSameer Pujar "nvidia,tegra210-i2s"; 176177208f7SSameer Pujar reg = <0x2901200 0x100>; 177177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 178177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 179177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 180177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 181177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 182177208f7SSameer Pujar assigned-clock-rates = <1536000>; 183177208f7SSameer Pujar sound-name-prefix = "I2S3"; 184177208f7SSameer Pujar status = "disabled"; 185177208f7SSameer Pujar }; 186177208f7SSameer Pujar 187177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 188177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 189177208f7SSameer Pujar "nvidia,tegra210-i2s"; 190177208f7SSameer Pujar reg = <0x2901300 0x100>; 191177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 192177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 193177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 194177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 195177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 196177208f7SSameer Pujar assigned-clock-rates = <1536000>; 197177208f7SSameer Pujar sound-name-prefix = "I2S4"; 198177208f7SSameer Pujar status = "disabled"; 199177208f7SSameer Pujar }; 200177208f7SSameer Pujar 201177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 202177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 203177208f7SSameer Pujar "nvidia,tegra210-i2s"; 204177208f7SSameer Pujar reg = <0x2901400 0x100>; 205177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 206177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 207177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 208177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 209177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 210177208f7SSameer Pujar assigned-clock-rates = <1536000>; 211177208f7SSameer Pujar sound-name-prefix = "I2S5"; 212177208f7SSameer Pujar status = "disabled"; 213177208f7SSameer Pujar }; 214177208f7SSameer Pujar 215177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 216177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 217177208f7SSameer Pujar "nvidia,tegra210-i2s"; 218177208f7SSameer Pujar reg = <0x2901500 0x100>; 219177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 220177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 221177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 222177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 223177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 224177208f7SSameer Pujar assigned-clock-rates = <1536000>; 225177208f7SSameer Pujar sound-name-prefix = "I2S6"; 226177208f7SSameer Pujar status = "disabled"; 227177208f7SSameer Pujar }; 228177208f7SSameer Pujar 22979ed18d9SThierry Reding tegra_sfc1: sfc@2902000 { 23079ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 23179ed18d9SThierry Reding "nvidia,tegra210-sfc"; 23279ed18d9SThierry Reding reg = <0x2902000 0x200>; 23379ed18d9SThierry Reding sound-name-prefix = "SFC1"; 23479ed18d9SThierry Reding status = "disabled"; 23579ed18d9SThierry Reding }; 23679ed18d9SThierry Reding 23779ed18d9SThierry Reding tegra_sfc2: sfc@2902200 { 23879ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 23979ed18d9SThierry Reding "nvidia,tegra210-sfc"; 24079ed18d9SThierry Reding reg = <0x2902200 0x200>; 24179ed18d9SThierry Reding sound-name-prefix = "SFC2"; 24279ed18d9SThierry Reding status = "disabled"; 24379ed18d9SThierry Reding }; 24479ed18d9SThierry Reding 24579ed18d9SThierry Reding tegra_sfc3: sfc@2902400 { 24679ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 24779ed18d9SThierry Reding "nvidia,tegra210-sfc"; 24879ed18d9SThierry Reding reg = <0x2902400 0x200>; 24979ed18d9SThierry Reding sound-name-prefix = "SFC3"; 25079ed18d9SThierry Reding status = "disabled"; 25179ed18d9SThierry Reding }; 25279ed18d9SThierry Reding 25379ed18d9SThierry Reding tegra_sfc4: sfc@2902600 { 25479ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 25579ed18d9SThierry Reding "nvidia,tegra210-sfc"; 25679ed18d9SThierry Reding reg = <0x2902600 0x200>; 25779ed18d9SThierry Reding sound-name-prefix = "SFC4"; 25879ed18d9SThierry Reding status = "disabled"; 25979ed18d9SThierry Reding }; 26079ed18d9SThierry Reding 26179ed18d9SThierry Reding tegra_amx1: amx@2903000 { 26279ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 26379ed18d9SThierry Reding "nvidia,tegra210-amx"; 26479ed18d9SThierry Reding reg = <0x2903000 0x100>; 26579ed18d9SThierry Reding sound-name-prefix = "AMX1"; 26679ed18d9SThierry Reding status = "disabled"; 26779ed18d9SThierry Reding }; 26879ed18d9SThierry Reding 26979ed18d9SThierry Reding tegra_amx2: amx@2903100 { 27079ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 27179ed18d9SThierry Reding "nvidia,tegra210-amx"; 27279ed18d9SThierry Reding reg = <0x2903100 0x100>; 27379ed18d9SThierry Reding sound-name-prefix = "AMX2"; 27479ed18d9SThierry Reding status = "disabled"; 27579ed18d9SThierry Reding }; 27679ed18d9SThierry Reding 27779ed18d9SThierry Reding tegra_amx3: amx@2903200 { 27879ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 27979ed18d9SThierry Reding "nvidia,tegra210-amx"; 28079ed18d9SThierry Reding reg = <0x2903200 0x100>; 28179ed18d9SThierry Reding sound-name-prefix = "AMX3"; 28279ed18d9SThierry Reding status = "disabled"; 28379ed18d9SThierry Reding }; 28479ed18d9SThierry Reding 28579ed18d9SThierry Reding tegra_amx4: amx@2903300 { 28679ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 28779ed18d9SThierry Reding "nvidia,tegra210-amx"; 28879ed18d9SThierry Reding reg = <0x2903300 0x100>; 28979ed18d9SThierry Reding sound-name-prefix = "AMX4"; 29079ed18d9SThierry Reding status = "disabled"; 29179ed18d9SThierry Reding }; 29279ed18d9SThierry Reding 29379ed18d9SThierry Reding tegra_adx1: adx@2903800 { 29479ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 29579ed18d9SThierry Reding "nvidia,tegra210-adx"; 29679ed18d9SThierry Reding reg = <0x2903800 0x100>; 29779ed18d9SThierry Reding sound-name-prefix = "ADX1"; 29879ed18d9SThierry Reding status = "disabled"; 29979ed18d9SThierry Reding }; 30079ed18d9SThierry Reding 30179ed18d9SThierry Reding tegra_adx2: adx@2903900 { 30279ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 30379ed18d9SThierry Reding "nvidia,tegra210-adx"; 30479ed18d9SThierry Reding reg = <0x2903900 0x100>; 30579ed18d9SThierry Reding sound-name-prefix = "ADX2"; 30679ed18d9SThierry Reding status = "disabled"; 30779ed18d9SThierry Reding }; 30879ed18d9SThierry Reding 30979ed18d9SThierry Reding tegra_adx3: adx@2903a00 { 31079ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 31179ed18d9SThierry Reding "nvidia,tegra210-adx"; 31279ed18d9SThierry Reding reg = <0x2903a00 0x100>; 31379ed18d9SThierry Reding sound-name-prefix = "ADX3"; 31479ed18d9SThierry Reding status = "disabled"; 31579ed18d9SThierry Reding }; 31679ed18d9SThierry Reding 31779ed18d9SThierry Reding tegra_adx4: adx@2903b00 { 31879ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 31979ed18d9SThierry Reding "nvidia,tegra210-adx"; 32079ed18d9SThierry Reding reg = <0x2903b00 0x100>; 32179ed18d9SThierry Reding sound-name-prefix = "ADX4"; 32279ed18d9SThierry Reding status = "disabled"; 32379ed18d9SThierry Reding }; 32479ed18d9SThierry Reding 325177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 326177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 327177208f7SSameer Pujar reg = <0x2904000 0x100>; 328177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 329177208f7SSameer Pujar clock-names = "dmic"; 330177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 331177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 332177208f7SSameer Pujar assigned-clock-rates = <3072000>; 333177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 334177208f7SSameer Pujar status = "disabled"; 335177208f7SSameer Pujar }; 336177208f7SSameer Pujar 337177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 338177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 339177208f7SSameer Pujar reg = <0x2904100 0x100>; 340177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 341177208f7SSameer Pujar clock-names = "dmic"; 342177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 343177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 344177208f7SSameer Pujar assigned-clock-rates = <3072000>; 345177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 346177208f7SSameer Pujar status = "disabled"; 347177208f7SSameer Pujar }; 348177208f7SSameer Pujar 349177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 350177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 351177208f7SSameer Pujar reg = <0x2904200 0x100>; 352177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 353177208f7SSameer Pujar clock-names = "dmic"; 354177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 355177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 356177208f7SSameer Pujar assigned-clock-rates = <3072000>; 357177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 358177208f7SSameer Pujar status = "disabled"; 359177208f7SSameer Pujar }; 360177208f7SSameer Pujar 361177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 362177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 363177208f7SSameer Pujar reg = <0x2904300 0x100>; 364177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 365177208f7SSameer Pujar clock-names = "dmic"; 366177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 367177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 368177208f7SSameer Pujar assigned-clock-rates = <3072000>; 369177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 370177208f7SSameer Pujar status = "disabled"; 371177208f7SSameer Pujar }; 372177208f7SSameer Pujar 373177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 374177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 375177208f7SSameer Pujar reg = <0x2905000 0x100>; 376177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 377177208f7SSameer Pujar clock-names = "dspk"; 378177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 379177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 380177208f7SSameer Pujar assigned-clock-rates = <12288000>; 381177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 382177208f7SSameer Pujar status = "disabled"; 383177208f7SSameer Pujar }; 384177208f7SSameer Pujar 385177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 386177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 387177208f7SSameer Pujar reg = <0x2905100 0x100>; 388177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 389177208f7SSameer Pujar clock-names = "dspk"; 390177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 391177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 392177208f7SSameer Pujar assigned-clock-rates = <12288000>; 393177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 394177208f7SSameer Pujar status = "disabled"; 395177208f7SSameer Pujar }; 396848f3290SSameer Pujar 3974b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3984b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-ope", 3994b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 4004b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 4014b6a1b7cSSameer Pujar #address-cells = <1>; 4024b6a1b7cSSameer Pujar #size-cells = <1>; 4034b6a1b7cSSameer Pujar ranges; 4044b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4054b6a1b7cSSameer Pujar status = "disabled"; 4064b6a1b7cSSameer Pujar 4074b6a1b7cSSameer Pujar equalizer@2908100 { 4084b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-peq", 4094b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4104b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 4114b6a1b7cSSameer Pujar }; 4124b6a1b7cSSameer Pujar 4134b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4144b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-mbdrc", 4154b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4164b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 4174b6a1b7cSSameer Pujar }; 4184b6a1b7cSSameer Pujar }; 4194b6a1b7cSSameer Pujar 42079ed18d9SThierry Reding tegra_mvc1: mvc@290a000 { 42179ed18d9SThierry Reding compatible = "nvidia,tegra186-mvc", 42279ed18d9SThierry Reding "nvidia,tegra210-mvc"; 42379ed18d9SThierry Reding reg = <0x290a000 0x200>; 42479ed18d9SThierry Reding sound-name-prefix = "MVC1"; 42579ed18d9SThierry Reding status = "disabled"; 42679ed18d9SThierry Reding }; 42779ed18d9SThierry Reding 42879ed18d9SThierry Reding tegra_mvc2: mvc@290a200 { 42979ed18d9SThierry Reding compatible = "nvidia,tegra186-mvc", 43079ed18d9SThierry Reding "nvidia,tegra210-mvc"; 43179ed18d9SThierry Reding reg = <0x290a200 0x200>; 43279ed18d9SThierry Reding sound-name-prefix = "MVC2"; 43379ed18d9SThierry Reding status = "disabled"; 43479ed18d9SThierry Reding }; 43579ed18d9SThierry Reding 436848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 437848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 438848f3290SSameer Pujar "nvidia,tegra210-amixer"; 439848f3290SSameer Pujar reg = <0x290bb00 0x800>; 440848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 441848f3290SSameer Pujar status = "disabled"; 442848f3290SSameer Pujar }; 44347a08153SSameer Pujar 44479ed18d9SThierry Reding tegra_admaif: admaif@290f000 { 44579ed18d9SThierry Reding compatible = "nvidia,tegra186-admaif"; 44679ed18d9SThierry Reding reg = <0x0290f000 0x1000>; 44779ed18d9SThierry Reding dmas = <&adma 1>, <&adma 1>, 44879ed18d9SThierry Reding <&adma 2>, <&adma 2>, 44979ed18d9SThierry Reding <&adma 3>, <&adma 3>, 45079ed18d9SThierry Reding <&adma 4>, <&adma 4>, 45179ed18d9SThierry Reding <&adma 5>, <&adma 5>, 45279ed18d9SThierry Reding <&adma 6>, <&adma 6>, 45379ed18d9SThierry Reding <&adma 7>, <&adma 7>, 45479ed18d9SThierry Reding <&adma 8>, <&adma 8>, 45579ed18d9SThierry Reding <&adma 9>, <&adma 9>, 45679ed18d9SThierry Reding <&adma 10>, <&adma 10>, 45779ed18d9SThierry Reding <&adma 11>, <&adma 11>, 45879ed18d9SThierry Reding <&adma 12>, <&adma 12>, 45979ed18d9SThierry Reding <&adma 13>, <&adma 13>, 46079ed18d9SThierry Reding <&adma 14>, <&adma 14>, 46179ed18d9SThierry Reding <&adma 15>, <&adma 15>, 46279ed18d9SThierry Reding <&adma 16>, <&adma 16>, 46379ed18d9SThierry Reding <&adma 17>, <&adma 17>, 46479ed18d9SThierry Reding <&adma 18>, <&adma 18>, 46579ed18d9SThierry Reding <&adma 19>, <&adma 19>, 46679ed18d9SThierry Reding <&adma 20>, <&adma 20>; 46779ed18d9SThierry Reding dma-names = "rx1", "tx1", 46879ed18d9SThierry Reding "rx2", "tx2", 46979ed18d9SThierry Reding "rx3", "tx3", 47079ed18d9SThierry Reding "rx4", "tx4", 47179ed18d9SThierry Reding "rx5", "tx5", 47279ed18d9SThierry Reding "rx6", "tx6", 47379ed18d9SThierry Reding "rx7", "tx7", 47479ed18d9SThierry Reding "rx8", "tx8", 47579ed18d9SThierry Reding "rx9", "tx9", 47679ed18d9SThierry Reding "rx10", "tx10", 47779ed18d9SThierry Reding "rx11", "tx11", 47879ed18d9SThierry Reding "rx12", "tx12", 47979ed18d9SThierry Reding "rx13", "tx13", 48079ed18d9SThierry Reding "rx14", "tx14", 48179ed18d9SThierry Reding "rx15", "tx15", 48279ed18d9SThierry Reding "rx16", "tx16", 48379ed18d9SThierry Reding "rx17", "tx17", 48479ed18d9SThierry Reding "rx18", "tx18", 48579ed18d9SThierry Reding "rx19", "tx19", 48679ed18d9SThierry Reding "rx20", "tx20"; 48779ed18d9SThierry Reding status = "disabled"; 48879ed18d9SThierry Reding }; 48979ed18d9SThierry Reding 49047a08153SSameer Pujar tegra_asrc: asrc@2910000 { 49147a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 49247a08153SSameer Pujar reg = <0x2910000 0x2000>; 49347a08153SSameer Pujar sound-name-prefix = "ASRC1"; 49447a08153SSameer Pujar status = "disabled"; 49547a08153SSameer Pujar }; 496177208f7SSameer Pujar }; 49779ed18d9SThierry Reding 49879ed18d9SThierry Reding adma: dma-controller@2930000 { 49979ed18d9SThierry Reding compatible = "nvidia,tegra186-adma"; 50079ed18d9SThierry Reding reg = <0x02930000 0x20000>; 50179ed18d9SThierry Reding interrupt-parent = <&agic>; 50279ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 50379ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 50479ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 50579ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 50679ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 50779ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 50879ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 50979ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 51079ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 51179ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 51279ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 51379ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 51479ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 51579ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 51679ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 51779ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 51879ed18d9SThierry Reding <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 51979ed18d9SThierry Reding <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 52079ed18d9SThierry Reding <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 52179ed18d9SThierry Reding <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 52279ed18d9SThierry Reding <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 52379ed18d9SThierry Reding <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 52479ed18d9SThierry Reding <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 52579ed18d9SThierry Reding <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 52679ed18d9SThierry Reding <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 52779ed18d9SThierry Reding <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 52879ed18d9SThierry Reding <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 52979ed18d9SThierry Reding <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 53079ed18d9SThierry Reding <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 53179ed18d9SThierry Reding <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 53279ed18d9SThierry Reding <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 53379ed18d9SThierry Reding <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 53479ed18d9SThierry Reding #dma-cells = <1>; 53579ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_AHUB>; 53679ed18d9SThierry Reding clock-names = "d_audio"; 53779ed18d9SThierry Reding status = "disabled"; 53879ed18d9SThierry Reding }; 53979ed18d9SThierry Reding 54079ed18d9SThierry Reding agic: interrupt-controller@2a40000 { 54179ed18d9SThierry Reding compatible = "nvidia,tegra186-agic", 54279ed18d9SThierry Reding "nvidia,tegra210-agic"; 54379ed18d9SThierry Reding #interrupt-cells = <3>; 54479ed18d9SThierry Reding interrupt-controller; 54579ed18d9SThierry Reding reg = <0x02a41000 0x1000>, 54679ed18d9SThierry Reding <0x02a42000 0x2000>; 54779ed18d9SThierry Reding interrupts = <GIC_SPI 145 54879ed18d9SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 54979ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_APE>; 55079ed18d9SThierry Reding clock-names = "clk"; 55179ed18d9SThierry Reding status = "disabled"; 55279ed18d9SThierry Reding }; 5535d2249ddSSameer Pujar }; 5545d2249ddSSameer Pujar 555954490b3SThierry Reding mc: memory-controller@2c00000 { 556d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 557000b99e5SAshish Mhetre reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 558000b99e5SAshish Mhetre <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 559000b99e5SAshish Mhetre <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 560000b99e5SAshish Mhetre <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 561000b99e5SAshish Mhetre <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 562000b99e5SAshish Mhetre <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 563000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 564b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 565d25a3bf1SThierry Reding status = "disabled"; 5663f6eaef9SThierry Reding 567954490b3SThierry Reding #interconnect-cells = <1>; 5683f6eaef9SThierry Reding #address-cells = <2>; 5693f6eaef9SThierry Reding #size-cells = <2>; 5703f6eaef9SThierry Reding 5713f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5723f6eaef9SThierry Reding 5733f6eaef9SThierry Reding /* 5743f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5753f6eaef9SThierry Reding * controller can address. 5763f6eaef9SThierry Reding */ 5773f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5783f6eaef9SThierry Reding 5793f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5803f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5813f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5823f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5833f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5843f6eaef9SThierry Reding clock-names = "emc"; 5853f6eaef9SThierry Reding 586954490b3SThierry Reding #interconnect-cells = <0>; 587954490b3SThierry Reding 5883f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5893f6eaef9SThierry Reding }; 590d25a3bf1SThierry Reding }; 591d25a3bf1SThierry Reding 592bd1fefcbSThierry Reding timer@3010000 { 593bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 594bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 595bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 596bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 597bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 598bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 599bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 600bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 601bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 602bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 603bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 604bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 605c710ac0bSKartik status = "okay"; 606bd1fefcbSThierry Reding }; 607bd1fefcbSThierry Reding 60839cb62cbSJoseph Lo uarta: serial@3100000 { 60939cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 61039cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 61139cb62cbSJoseph Lo reg-shift = <2>; 61239cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 613c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 6147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 615a7a77e2eSThierry Reding status = "disabled"; 616a7a77e2eSThierry Reding }; 617a7a77e2eSThierry Reding 618a7a77e2eSThierry Reding uartb: serial@3110000 { 619a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 620a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 621a7a77e2eSThierry Reding reg-shift = <2>; 622a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 623c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 624a7a77e2eSThierry Reding clock-names = "serial"; 6257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 626a7a77e2eSThierry Reding reset-names = "serial"; 627a7a77e2eSThierry Reding status = "disabled"; 628a7a77e2eSThierry Reding }; 629a7a77e2eSThierry Reding 630a7a77e2eSThierry Reding uartd: serial@3130000 { 631a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 632a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 633a7a77e2eSThierry Reding reg-shift = <2>; 634a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 635c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 636a7a77e2eSThierry Reding clock-names = "serial"; 6377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 638a7a77e2eSThierry Reding reset-names = "serial"; 639a7a77e2eSThierry Reding status = "disabled"; 640a7a77e2eSThierry Reding }; 641a7a77e2eSThierry Reding 642a7a77e2eSThierry Reding uarte: serial@3140000 { 643a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 644a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 645a7a77e2eSThierry Reding reg-shift = <2>; 646a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 647c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 648a7a77e2eSThierry Reding clock-names = "serial"; 6497bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 650a7a77e2eSThierry Reding reset-names = "serial"; 651a7a77e2eSThierry Reding status = "disabled"; 652a7a77e2eSThierry Reding }; 653a7a77e2eSThierry Reding 654a7a77e2eSThierry Reding uartf: serial@3150000 { 655a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 656a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 657a7a77e2eSThierry Reding reg-shift = <2>; 658a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 659c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 660a7a77e2eSThierry Reding clock-names = "serial"; 6617bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 662a7a77e2eSThierry Reding reset-names = "serial"; 66339cb62cbSJoseph Lo status = "disabled"; 66439cb62cbSJoseph Lo }; 66539cb62cbSJoseph Lo 66640cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 667548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 66840cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 66940cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 67040cc83b3SThierry Reding #address-cells = <1>; 67140cc83b3SThierry Reding #size-cells = <0>; 672c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 67340cc83b3SThierry Reding clock-names = "div-clk"; 6747bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 67540cc83b3SThierry Reding reset-names = "i2c"; 6768e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 6778e442805SAkhil R dma-names = "rx", "tx"; 67840cc83b3SThierry Reding status = "disabled"; 67940cc83b3SThierry Reding }; 68040cc83b3SThierry Reding 68140cc83b3SThierry Reding cam_i2c: i2c@3180000 { 682548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68340cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 68440cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 68540cc83b3SThierry Reding #address-cells = <1>; 68640cc83b3SThierry Reding #size-cells = <0>; 687c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 68840cc83b3SThierry Reding clock-names = "div-clk"; 6897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 69040cc83b3SThierry Reding reset-names = "i2c"; 6918e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 6928e442805SAkhil R dma-names = "rx", "tx"; 69340cc83b3SThierry Reding status = "disabled"; 69440cc83b3SThierry Reding }; 69540cc83b3SThierry Reding 69640cc83b3SThierry Reding /* shares pads with dpaux1 */ 69740cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 698548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 69940cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 70040cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 70140cc83b3SThierry Reding #address-cells = <1>; 70240cc83b3SThierry Reding #size-cells = <0>; 703c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 70440cc83b3SThierry Reding clock-names = "div-clk"; 7057bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 70640cc83b3SThierry Reding reset-names = "i2c"; 707846137c6SThierry Reding pinctrl-names = "default", "idle"; 708846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 709846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 7108e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7118e442805SAkhil R dma-names = "rx", "tx"; 71240cc83b3SThierry Reding status = "disabled"; 71340cc83b3SThierry Reding }; 71440cc83b3SThierry Reding 71540cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 71640cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 717548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 71840cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 71940cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 72040cc83b3SThierry Reding #address-cells = <1>; 72140cc83b3SThierry Reding #size-cells = <0>; 722c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 72340cc83b3SThierry Reding clock-names = "div-clk"; 7247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 72540cc83b3SThierry Reding reset-names = "i2c"; 72640cc83b3SThierry Reding status = "disabled"; 72740cc83b3SThierry Reding }; 72840cc83b3SThierry Reding 72940cc83b3SThierry Reding /* shares pads with dpaux0 */ 73040cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 731548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 73240cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 73340cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 73440cc83b3SThierry Reding #address-cells = <1>; 73540cc83b3SThierry Reding #size-cells = <0>; 736c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 73740cc83b3SThierry Reding clock-names = "div-clk"; 7387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 73940cc83b3SThierry Reding reset-names = "i2c"; 740846137c6SThierry Reding pinctrl-names = "default", "idle"; 741846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 742846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 7438e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7448e442805SAkhil R dma-names = "rx", "tx"; 74540cc83b3SThierry Reding status = "disabled"; 74640cc83b3SThierry Reding }; 74740cc83b3SThierry Reding 74840cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 749548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 75040cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 75140cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 75240cc83b3SThierry Reding #address-cells = <1>; 75340cc83b3SThierry Reding #size-cells = <0>; 754c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 75540cc83b3SThierry Reding clock-names = "div-clk"; 7567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 75740cc83b3SThierry Reding reset-names = "i2c"; 7588e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7598e442805SAkhil R dma-names = "rx", "tx"; 76040cc83b3SThierry Reding status = "disabled"; 76140cc83b3SThierry Reding }; 76240cc83b3SThierry Reding 76340cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 764548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 76540cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 76640cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 76740cc83b3SThierry Reding #address-cells = <1>; 76840cc83b3SThierry Reding #size-cells = <0>; 769c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 77040cc83b3SThierry Reding clock-names = "div-clk"; 7717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 77240cc83b3SThierry Reding reset-names = "i2c"; 7738e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 7748e442805SAkhil R dma-names = "rx", "tx"; 77540cc83b3SThierry Reding status = "disabled"; 77640cc83b3SThierry Reding }; 77740cc83b3SThierry Reding 778913f8ad4SThierry Reding pwm1: pwm@3280000 { 779913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 780913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 781913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 782913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 783913f8ad4SThierry Reding reset-names = "pwm"; 784913f8ad4SThierry Reding status = "disabled"; 785913f8ad4SThierry Reding #pwm-cells = <2>; 786913f8ad4SThierry Reding }; 787913f8ad4SThierry Reding 788913f8ad4SThierry Reding pwm2: pwm@3290000 { 789913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 790913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 791913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 792913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 793913f8ad4SThierry Reding reset-names = "pwm"; 794913f8ad4SThierry Reding status = "disabled"; 795913f8ad4SThierry Reding #pwm-cells = <2>; 796913f8ad4SThierry Reding }; 797913f8ad4SThierry Reding 798913f8ad4SThierry Reding pwm3: pwm@32a0000 { 799913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 800913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 801913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 802913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 803913f8ad4SThierry Reding reset-names = "pwm"; 804913f8ad4SThierry Reding status = "disabled"; 805913f8ad4SThierry Reding #pwm-cells = <2>; 806913f8ad4SThierry Reding }; 807913f8ad4SThierry Reding 808913f8ad4SThierry Reding pwm5: pwm@32c0000 { 809913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 810913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 811913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 812913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 813913f8ad4SThierry Reding reset-names = "pwm"; 814913f8ad4SThierry Reding status = "disabled"; 815913f8ad4SThierry Reding #pwm-cells = <2>; 816913f8ad4SThierry Reding }; 817913f8ad4SThierry Reding 818913f8ad4SThierry Reding pwm6: pwm@32d0000 { 819913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 820913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 821913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 822913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 823913f8ad4SThierry Reding reset-names = "pwm"; 824913f8ad4SThierry Reding status = "disabled"; 825913f8ad4SThierry Reding #pwm-cells = <2>; 826913f8ad4SThierry Reding }; 827913f8ad4SThierry Reding 828913f8ad4SThierry Reding pwm7: pwm@32e0000 { 829913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 830913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 831913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 832913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 833913f8ad4SThierry Reding reset-names = "pwm"; 834913f8ad4SThierry Reding status = "disabled"; 835913f8ad4SThierry Reding #pwm-cells = <2>; 836913f8ad4SThierry Reding }; 837913f8ad4SThierry Reding 838913f8ad4SThierry Reding pwm8: pwm@32f0000 { 839913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 840913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 841913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 842913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 843913f8ad4SThierry Reding reset-names = "pwm"; 844913f8ad4SThierry Reding status = "disabled"; 845913f8ad4SThierry Reding #pwm-cells = <2>; 846913f8ad4SThierry Reding }; 847913f8ad4SThierry Reding 84867bb17f6SThierry Reding sdmmc1: mmc@3400000 { 84999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 85099425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 85199425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 852baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 853baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 854baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8557bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 85699425dfdSThierry Reding reset-names = "sdhci"; 857954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 858954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 859954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8608589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 86124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 86224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 86324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 86441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 86541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 86641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 86741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 86841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 86941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8706f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8716f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 87298a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 87398a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 87498a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 87599425dfdSThierry Reding status = "disabled"; 87699425dfdSThierry Reding }; 87799425dfdSThierry Reding 87867bb17f6SThierry Reding sdmmc2: mmc@3420000 { 87999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 88099425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 88199425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 882baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 883baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 884baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 88699425dfdSThierry Reding reset-names = "sdhci"; 887954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 888954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 889954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8908589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 89124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 89224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 89324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 89441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 89541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 89641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 89741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8986f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8996f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 90099425dfdSThierry Reding status = "disabled"; 90199425dfdSThierry Reding }; 90299425dfdSThierry Reding 90367bb17f6SThierry Reding sdmmc3: mmc@3440000 { 90499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 90599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 90699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 907baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 908baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 909baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 91199425dfdSThierry Reding reset-names = "sdhci"; 912954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 913954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 914954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9158589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 91624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 91724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 91824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 91941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 92041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 92141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 92241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 92341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 92441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9256f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9266f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 92799425dfdSThierry Reding status = "disabled"; 92899425dfdSThierry Reding }; 92999425dfdSThierry Reding 93067bb17f6SThierry Reding sdmmc4: mmc@3460000 { 93199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 93299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 93399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 934baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 935baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 936baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 93798a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 93898a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 93998a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9407bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 94199425dfdSThierry Reding reset-names = "sdhci"; 942954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 943954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 944954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9458589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 94641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 94741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 94841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 94941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9504e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9514e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 952e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 953e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 95422248e91SAapo Vienamo nvidia,dqs-trim = <63>; 955207f60baSAapo Vienamo mmc-hs400-1_8v; 956c4307836SSowjanya Komatineni supports-cqe; 95799425dfdSThierry Reding status = "disabled"; 95899425dfdSThierry Reding }; 95999425dfdSThierry Reding 96079ed18d9SThierry Reding sata@3507000 { 96179ed18d9SThierry Reding compatible = "nvidia,tegra186-ahci"; 96279ed18d9SThierry Reding reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 96379ed18d9SThierry Reding <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 96479ed18d9SThierry Reding <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 96579ed18d9SThierry Reding interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 96679ed18d9SThierry Reding 96779ed18d9SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 96879ed18d9SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 96979ed18d9SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 97079ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 97179ed18d9SThierry Reding iommus = <&smmu TEGRA186_SID_SATA>; 97279ed18d9SThierry Reding 97379ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_SATA>, 97479ed18d9SThierry Reding <&bpmp TEGRA186_CLK_SATA_OOB>; 97579ed18d9SThierry Reding clock-names = "sata", "sata-oob"; 97679ed18d9SThierry Reding assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 97779ed18d9SThierry Reding <&bpmp TEGRA186_CLK_SATA_OOB>; 97879ed18d9SThierry Reding assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 97979ed18d9SThierry Reding <&bpmp TEGRA186_CLK_PLLP>; 98079ed18d9SThierry Reding assigned-clock-rates = <102000000>, 98179ed18d9SThierry Reding <204000000>; 98279ed18d9SThierry Reding resets = <&bpmp TEGRA186_RESET_SATA>, 98379ed18d9SThierry Reding <&bpmp TEGRA186_RESET_SATACOLD>; 98479ed18d9SThierry Reding reset-names = "sata", "sata-cold"; 98579ed18d9SThierry Reding status = "disabled"; 98679ed18d9SThierry Reding }; 98779ed18d9SThierry Reding 988b066a310SThierry Reding hda@3510000 { 989b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 990b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 991b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 992b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 993b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 994b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 995b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 996b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 997b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 998b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 999b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1000b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1001954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1002954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1003954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1004dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 1005b066a310SThierry Reding status = "disabled"; 1006b066a310SThierry Reding }; 1007b066a310SThierry Reding 10088bfde518SThierry Reding padctl: padctl@3520000 { 10098bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 10108bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 10118bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 10128bfde518SThierry Reding reg-names = "padctl", "ao"; 10136450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 10148bfde518SThierry Reding 10158bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 10168bfde518SThierry Reding reset-names = "padctl"; 10178bfde518SThierry Reding 10188bfde518SThierry Reding status = "disabled"; 10198bfde518SThierry Reding 10208bfde518SThierry Reding pads { 10218bfde518SThierry Reding usb2 { 10228bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 10238bfde518SThierry Reding clock-names = "trk"; 10248bfde518SThierry Reding status = "disabled"; 10258bfde518SThierry Reding 10268bfde518SThierry Reding lanes { 10278bfde518SThierry Reding usb2-0 { 10288bfde518SThierry Reding status = "disabled"; 10298bfde518SThierry Reding #phy-cells = <0>; 10308bfde518SThierry Reding }; 10318bfde518SThierry Reding 10328bfde518SThierry Reding usb2-1 { 10338bfde518SThierry Reding status = "disabled"; 10348bfde518SThierry Reding #phy-cells = <0>; 10358bfde518SThierry Reding }; 10368bfde518SThierry Reding 10378bfde518SThierry Reding usb2-2 { 10388bfde518SThierry Reding status = "disabled"; 10398bfde518SThierry Reding #phy-cells = <0>; 10408bfde518SThierry Reding }; 10418bfde518SThierry Reding }; 10428bfde518SThierry Reding }; 10438bfde518SThierry Reding 10448bfde518SThierry Reding hsic { 10458bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 10468bfde518SThierry Reding clock-names = "trk"; 10478bfde518SThierry Reding status = "disabled"; 10488bfde518SThierry Reding 10498bfde518SThierry Reding lanes { 10508bfde518SThierry Reding hsic-0 { 10518bfde518SThierry Reding status = "disabled"; 10528bfde518SThierry Reding #phy-cells = <0>; 10538bfde518SThierry Reding }; 10548bfde518SThierry Reding }; 10558bfde518SThierry Reding }; 10568bfde518SThierry Reding 10578bfde518SThierry Reding usb3 { 10588bfde518SThierry Reding status = "disabled"; 10598bfde518SThierry Reding 10608bfde518SThierry Reding lanes { 10618bfde518SThierry Reding usb3-0 { 10628bfde518SThierry Reding status = "disabled"; 10638bfde518SThierry Reding #phy-cells = <0>; 10648bfde518SThierry Reding }; 10658bfde518SThierry Reding 10668bfde518SThierry Reding usb3-1 { 10678bfde518SThierry Reding status = "disabled"; 10688bfde518SThierry Reding #phy-cells = <0>; 10698bfde518SThierry Reding }; 10708bfde518SThierry Reding 10718bfde518SThierry Reding usb3-2 { 10728bfde518SThierry Reding status = "disabled"; 10738bfde518SThierry Reding #phy-cells = <0>; 10748bfde518SThierry Reding }; 10758bfde518SThierry Reding }; 10768bfde518SThierry Reding }; 10778bfde518SThierry Reding }; 10788bfde518SThierry Reding 10798bfde518SThierry Reding ports { 10808bfde518SThierry Reding usb2-0 { 10818bfde518SThierry Reding status = "disabled"; 10828bfde518SThierry Reding }; 10838bfde518SThierry Reding 10848bfde518SThierry Reding usb2-1 { 10858bfde518SThierry Reding status = "disabled"; 10868bfde518SThierry Reding }; 10878bfde518SThierry Reding 10888bfde518SThierry Reding usb2-2 { 10898bfde518SThierry Reding status = "disabled"; 10908bfde518SThierry Reding }; 10918bfde518SThierry Reding 10928bfde518SThierry Reding hsic-0 { 10938bfde518SThierry Reding status = "disabled"; 10948bfde518SThierry Reding }; 10958bfde518SThierry Reding 10968bfde518SThierry Reding usb3-0 { 10978bfde518SThierry Reding status = "disabled"; 10988bfde518SThierry Reding }; 10998bfde518SThierry Reding 11008bfde518SThierry Reding usb3-1 { 11018bfde518SThierry Reding status = "disabled"; 11028bfde518SThierry Reding }; 11038bfde518SThierry Reding 11048bfde518SThierry Reding usb3-2 { 11058bfde518SThierry Reding status = "disabled"; 11068bfde518SThierry Reding }; 11078bfde518SThierry Reding }; 11088bfde518SThierry Reding }; 11098bfde518SThierry Reding 11108bfde518SThierry Reding usb@3530000 { 11118bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 11128bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 11138bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 11148bfde518SThierry Reding reg-names = "hcd", "fpci"; 11158bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1116a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11178bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 11188bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 11198bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 11208bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 11218bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11228bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 11238bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 11248bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11258bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 11268bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 11278bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 11288bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 11298bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 11308bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 11318bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1132954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1133954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1134954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 113506c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 11368bfde518SThierry Reding #address-cells = <1>; 11378bfde518SThierry Reding #size-cells = <0>; 113806c6b06fSThierry Reding status = "disabled"; 113906c6b06fSThierry Reding 114006c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 11418bfde518SThierry Reding }; 11428bfde518SThierry Reding 1143584f800cSNagarjuna Kristam usb@3550000 { 1144584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1145584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1146584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1147584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1148584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1149584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1150584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1151584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1152584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1153584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1154d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1155d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1156d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1157584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1158584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1159584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1160584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1161584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1162584f800cSNagarjuna Kristam status = "disabled"; 1163584f800cSNagarjuna Kristam }; 1164584f800cSNagarjuna Kristam 116585593b75SThierry Reding fuse@3820000 { 116685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 116785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 116885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 116985593b75SThierry Reding clock-names = "fuse"; 117085593b75SThierry Reding }; 117185593b75SThierry Reding 117239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 117339cb62cbSJoseph Lo compatible = "arm,gic-400"; 117439cb62cbSJoseph Lo #interrupt-cells = <3>; 117539cb62cbSJoseph Lo interrupt-controller; 117639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1177776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1178776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1179776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 118039cb62cbSJoseph Lo interrupts = <GIC_PPI 9 118139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 118239cb62cbSJoseph Lo interrupt-parent = <&gic>; 118339cb62cbSJoseph Lo }; 118439cb62cbSJoseph Lo 118597cf683cSThierry Reding cec@3960000 { 118697cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 118797cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 118897cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 118997cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 119097cf683cSThierry Reding clock-names = "cec"; 119197cf683cSThierry Reding status = "disabled"; 119297cf683cSThierry Reding }; 119397cf683cSThierry Reding 119439cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 119539cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 119639cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 119739cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 119839cb62cbSJoseph Lo interrupt-names = "doorbell"; 119939cb62cbSJoseph Lo #mbox-cells = <2>; 120039cb62cbSJoseph Lo status = "disabled"; 120139cb62cbSJoseph Lo }; 120239cb62cbSJoseph Lo 120340cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1204548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 120540cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 120640cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 120740cc83b3SThierry Reding #address-cells = <1>; 120840cc83b3SThierry Reding #size-cells = <0>; 1209c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 121040cc83b3SThierry Reding clock-names = "div-clk"; 12117bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 121240cc83b3SThierry Reding reset-names = "i2c"; 12138e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 12148e442805SAkhil R dma-names = "rx", "tx"; 121540cc83b3SThierry Reding status = "disabled"; 121640cc83b3SThierry Reding }; 121740cc83b3SThierry Reding 121840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1219548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 122040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 122140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 122240cc83b3SThierry Reding #address-cells = <1>; 122340cc83b3SThierry Reding #size-cells = <0>; 1224c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 122540cc83b3SThierry Reding clock-names = "div-clk"; 12267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 122740cc83b3SThierry Reding reset-names = "i2c"; 12288e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 12298e442805SAkhil R dma-names = "rx", "tx"; 123040cc83b3SThierry Reding status = "disabled"; 123140cc83b3SThierry Reding }; 123240cc83b3SThierry Reding 1233a7a77e2eSThierry Reding uartc: serial@c280000 { 1234a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1235a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1236a7a77e2eSThierry Reding reg-shift = <2>; 1237a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1238c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1239a7a77e2eSThierry Reding clock-names = "serial"; 12407bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1241a7a77e2eSThierry Reding reset-names = "serial"; 1242a7a77e2eSThierry Reding status = "disabled"; 1243a7a77e2eSThierry Reding }; 1244a7a77e2eSThierry Reding 1245a7a77e2eSThierry Reding uartg: serial@c290000 { 1246a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1247a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1248a7a77e2eSThierry Reding reg-shift = <2>; 1249a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1250c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1251a7a77e2eSThierry Reding clock-names = "serial"; 12527bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1253a7a77e2eSThierry Reding reset-names = "serial"; 1254a7a77e2eSThierry Reding status = "disabled"; 1255a7a77e2eSThierry Reding }; 1256a7a77e2eSThierry Reding 12579733a251SThierry Reding rtc: rtc@c2a0000 { 12589733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 12599733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 12609733a251SThierry Reding interrupt-parent = <&pmc>; 12619733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 12629733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 12639733a251SThierry Reding clock-names = "rtc"; 12649733a251SThierry Reding status = "disabled"; 12659733a251SThierry Reding }; 12669733a251SThierry Reding 1267fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1268fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1269fc4bb754SThierry Reding reg-names = "security", "gpio"; 1270fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1271fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1272fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1273fc4bb754SThierry Reding gpio-controller; 1274fc4bb754SThierry Reding #gpio-cells = <2>; 1275fc4bb754SThierry Reding interrupt-controller; 1276fc4bb754SThierry Reding #interrupt-cells = <2>; 1277fc4bb754SThierry Reding }; 1278fc4bb754SThierry Reding 1279913f8ad4SThierry Reding pwm4: pwm@c340000 { 1280913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1281913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1282913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1283913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1284913f8ad4SThierry Reding reset-names = "pwm"; 1285913f8ad4SThierry Reding status = "disabled"; 1286913f8ad4SThierry Reding #pwm-cells = <2>; 1287913f8ad4SThierry Reding }; 1288913f8ad4SThierry Reding 128932e66e46SThierry Reding pmc: pmc@c360000 { 129073bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 129173bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 129273bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 129373bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 129473bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 129573bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 129624005fd1SAapo Vienamo 129732e66e46SThierry Reding #interrupt-cells = <2>; 129832e66e46SThierry Reding interrupt-controller; 129932e66e46SThierry Reding 130024005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 130124005fd1SAapo Vienamo pins = "sdmmc1-hv"; 130224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 130324005fd1SAapo Vienamo }; 130424005fd1SAapo Vienamo 130579ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 130679ed18d9SThierry Reding pins = "sdmmc1-hv"; 130724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 130824005fd1SAapo Vienamo }; 130924005fd1SAapo Vienamo 131024005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 131124005fd1SAapo Vienamo pins = "sdmmc2-hv"; 131224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 131324005fd1SAapo Vienamo }; 131424005fd1SAapo Vienamo 131579ed18d9SThierry Reding sdmmc2_3v3: sdmmc2-3v3 { 131679ed18d9SThierry Reding pins = "sdmmc2-hv"; 131724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 131824005fd1SAapo Vienamo }; 131924005fd1SAapo Vienamo 132024005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 132124005fd1SAapo Vienamo pins = "sdmmc3-hv"; 132224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 132324005fd1SAapo Vienamo }; 132479ed18d9SThierry Reding 132579ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 132679ed18d9SThierry Reding pins = "sdmmc3-hv"; 132779ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 132879ed18d9SThierry Reding }; 132973bf90d4SThierry Reding }; 133073bf90d4SThierry Reding 13317b7ef494SMikko Perttunen ccplex@e000000 { 13327b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 13332b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 13347b7ef494SMikko Perttunen 13357b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 13367b7ef494SMikko Perttunen }; 13377b7ef494SMikko Perttunen 1338f8973cf4SManikanta Maddireddy pcie@10003000 { 1339f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1340f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1341f8973cf4SManikanta Maddireddy device_type = "pci"; 1342644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1343644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1344644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1345f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1346f8973cf4SManikanta Maddireddy 1347f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1348f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1349f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1350f8973cf4SManikanta Maddireddy 1351f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1352f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1353f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1354f8973cf4SManikanta Maddireddy 1355f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1356f8973cf4SManikanta Maddireddy #address-cells = <3>; 1357f8973cf4SManikanta Maddireddy #size-cells = <2>; 1358f8973cf4SManikanta Maddireddy 1359644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1360644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1361644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1362644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1363644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1364644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1365f8973cf4SManikanta Maddireddy 136678b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 136778b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1368f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 136978b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1370f8973cf4SManikanta Maddireddy 137178b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 137278b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1373f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 137478b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1375f8973cf4SManikanta Maddireddy 1376954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1377954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1378954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1379954490b3SThierry Reding 1380f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1381f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1382f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1383f2a465e7SThierry Reding 1384f8973cf4SManikanta Maddireddy status = "disabled"; 1385f8973cf4SManikanta Maddireddy 1386f8973cf4SManikanta Maddireddy pci@1,0 { 1387f8973cf4SManikanta Maddireddy device_type = "pci"; 1388f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1389f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1390f8973cf4SManikanta Maddireddy status = "disabled"; 1391f8973cf4SManikanta Maddireddy 1392f8973cf4SManikanta Maddireddy #address-cells = <3>; 1393f8973cf4SManikanta Maddireddy #size-cells = <2>; 1394f8973cf4SManikanta Maddireddy ranges; 1395f8973cf4SManikanta Maddireddy 1396f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1397f8973cf4SManikanta Maddireddy }; 1398f8973cf4SManikanta Maddireddy 1399f8973cf4SManikanta Maddireddy pci@2,0 { 1400f8973cf4SManikanta Maddireddy device_type = "pci"; 1401f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1402f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1403f8973cf4SManikanta Maddireddy status = "disabled"; 1404f8973cf4SManikanta Maddireddy 1405f8973cf4SManikanta Maddireddy #address-cells = <3>; 1406f8973cf4SManikanta Maddireddy #size-cells = <2>; 1407f8973cf4SManikanta Maddireddy ranges; 1408f8973cf4SManikanta Maddireddy 1409f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1410f8973cf4SManikanta Maddireddy }; 1411f8973cf4SManikanta Maddireddy 1412f8973cf4SManikanta Maddireddy pci@3,0 { 1413f8973cf4SManikanta Maddireddy device_type = "pci"; 1414f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1415f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1416f8973cf4SManikanta Maddireddy status = "disabled"; 1417f8973cf4SManikanta Maddireddy 1418f8973cf4SManikanta Maddireddy #address-cells = <3>; 1419f8973cf4SManikanta Maddireddy #size-cells = <2>; 1420f8973cf4SManikanta Maddireddy ranges; 1421f8973cf4SManikanta Maddireddy 1422f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1423f8973cf4SManikanta Maddireddy }; 1424f8973cf4SManikanta Maddireddy }; 1425f8973cf4SManikanta Maddireddy 1426b30a8e61SThierry Reding smmu: iommu@12000000 { 1427bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1428b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1429b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1494b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1495b30a8e61SThierry Reding #global-interrupts = <1>; 1496b30a8e61SThierry Reding #iommu-cells = <1>; 1497b966d2dbSThierry Reding 1498b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1499b30a8e61SThierry Reding }; 1500b30a8e61SThierry Reding 15015524c61fSMikko Perttunen host1x@13e00000 { 1502ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 15035524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 15045524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 15055524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 15065524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 15075524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1508052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 15095524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 15105524c61fSMikko Perttunen clock-names = "host1x"; 15115524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 15125524c61fSMikko Perttunen reset-names = "host1x"; 15135524c61fSMikko Perttunen 15145524c61fSMikko Perttunen #address-cells = <1>; 15155524c61fSMikko Perttunen #size-cells = <1>; 15165524c61fSMikko Perttunen 15175524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1518954490b3SThierry Reding 1519954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1520954490b3SThierry Reding interconnect-names = "dma-mem"; 1521954490b3SThierry Reding 1522c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1523c2599da7SThierry Reding 1524e30cf101SMikko Perttunen /* Context isolation domains */ 1525b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1526b0c1a994SThierry Reding <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1527b0c1a994SThierry Reding <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1528b0c1a994SThierry Reding <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1529b0c1a994SThierry Reding <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1530b0c1a994SThierry Reding <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1531b0c1a994SThierry Reding <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1532b0c1a994SThierry Reding <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1533e30cf101SMikko Perttunen 1534c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1535c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1536c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1537c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1538c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1539c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1540c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1541c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1542c2599da7SThierry Reding reset-names = "dpaux"; 1543c2599da7SThierry Reding status = "disabled"; 1544c2599da7SThierry Reding 1545c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1546c2599da7SThierry Reding 1547c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1548c2599da7SThierry Reding groups = "dpaux-io"; 1549c2599da7SThierry Reding function = "aux"; 1550c2599da7SThierry Reding }; 1551c2599da7SThierry Reding 1552c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1553c2599da7SThierry Reding groups = "dpaux-io"; 1554c2599da7SThierry Reding function = "i2c"; 1555c2599da7SThierry Reding }; 1556c2599da7SThierry Reding 1557c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1558c2599da7SThierry Reding groups = "dpaux-io"; 1559c2599da7SThierry Reding function = "off"; 1560c2599da7SThierry Reding }; 1561c2599da7SThierry Reding 1562c2599da7SThierry Reding i2c-bus { 1563c2599da7SThierry Reding #address-cells = <1>; 1564c2599da7SThierry Reding #size-cells = <0>; 1565c2599da7SThierry Reding }; 1566c2599da7SThierry Reding }; 1567c2599da7SThierry Reding 1568c2599da7SThierry Reding display-hub@15200000 { 1569aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1570ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1571c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1572c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1573c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1574c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1575c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1576c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1577c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1578c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1579c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1580c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1581c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1582c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1583c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1584c2599da7SThierry Reding status = "disabled"; 1585c2599da7SThierry Reding 1586c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1587c2599da7SThierry Reding 1588c2599da7SThierry Reding #address-cells = <1>; 1589c2599da7SThierry Reding #size-cells = <1>; 1590c2599da7SThierry Reding 1591c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1592c2599da7SThierry Reding 1593c2599da7SThierry Reding display@15200000 { 1594c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1595c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1596c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1597c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1598c2599da7SThierry Reding clock-names = "dc"; 1599c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1600c2599da7SThierry Reding reset-names = "dc"; 1601c2599da7SThierry Reding 1602c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1603954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1604954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1605954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1606c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1607c2599da7SThierry Reding 1608c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1609c2599da7SThierry Reding nvidia,head = <0>; 1610c2599da7SThierry Reding }; 1611c2599da7SThierry Reding 1612c2599da7SThierry Reding display@15210000 { 1613c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1614c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1615c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1616c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1617c2599da7SThierry Reding clock-names = "dc"; 1618c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1619c2599da7SThierry Reding reset-names = "dc"; 1620c2599da7SThierry Reding 1621c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1622954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1623954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1624954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1625c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1626c2599da7SThierry Reding 1627c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1628c2599da7SThierry Reding nvidia,head = <1>; 1629c2599da7SThierry Reding }; 1630c2599da7SThierry Reding 1631c2599da7SThierry Reding display@15220000 { 1632c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1633c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1634c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1635c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1636c2599da7SThierry Reding clock-names = "dc"; 1637c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1638c2599da7SThierry Reding reset-names = "dc"; 1639c2599da7SThierry Reding 1640c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1641954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1642954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1643954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1644c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1645c2599da7SThierry Reding 1646c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1647c2599da7SThierry Reding nvidia,head = <2>; 1648c2599da7SThierry Reding }; 1649c2599da7SThierry Reding }; 1650c2599da7SThierry Reding 1651c2599da7SThierry Reding dsia: dsi@15300000 { 1652c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1653c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1654c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1655c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1656c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1657c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1658c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1659c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1660c2599da7SThierry Reding reset-names = "dsi"; 1661c2599da7SThierry Reding status = "disabled"; 1662c2599da7SThierry Reding 1663c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1664c2599da7SThierry Reding }; 1665effc4b44SMikko Perttunen 1666effc4b44SMikko Perttunen vic@15340000 { 1667effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1668effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1669effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1670effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1671effc4b44SMikko Perttunen clock-names = "vic"; 1672effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1673effc4b44SMikko Perttunen reset-names = "vic"; 1674effc4b44SMikko Perttunen 1675effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1676954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1677954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1678954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 167929ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1680effc4b44SMikko Perttunen }; 1681c2599da7SThierry Reding 1682f7eb2785SJon Hunter nvjpg@15380000 { 1683f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1684f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1685f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1686f7eb2785SJon Hunter clock-names = "nvjpg"; 1687f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1688f7eb2785SJon Hunter reset-names = "nvjpg"; 1689f7eb2785SJon Hunter 1690f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1691f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1692f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1693f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1694f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1695f7eb2785SJon Hunter }; 1696f7eb2785SJon Hunter 1697c2599da7SThierry Reding dsib: dsi@15400000 { 1698c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1699c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1700c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1701c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1702c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1703c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1704c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1705c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1706c2599da7SThierry Reding reset-names = "dsi"; 1707c2599da7SThierry Reding status = "disabled"; 1708c2599da7SThierry Reding 1709c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1710c2599da7SThierry Reding }; 1711c2599da7SThierry Reding 171278a05873SMikko Perttunen nvdec@15480000 { 171378a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 171478a05873SMikko Perttunen reg = <0x15480000 0x40000>; 171578a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 171678a05873SMikko Perttunen clock-names = "nvdec"; 171778a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 171878a05873SMikko Perttunen reset-names = "nvdec"; 171978a05873SMikko Perttunen 172078a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 172178a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 172278a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 172378a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 172478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 172578a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 172678a05873SMikko Perttunen }; 172778a05873SMikko Perttunen 1728f7eb2785SJon Hunter nvenc@154c0000 { 1729f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1730f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1731f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1732f7eb2785SJon Hunter clock-names = "nvenc"; 1733f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1734f7eb2785SJon Hunter reset-names = "nvenc"; 1735f7eb2785SJon Hunter 1736f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1737f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1738f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1739f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1740f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1741f7eb2785SJon Hunter }; 1742f7eb2785SJon Hunter 1743c2599da7SThierry Reding sor0: sor@15540000 { 1744c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1745c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1746c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1747c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1748c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1749c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1750c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1751c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1752c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1753c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1754c2599da7SThierry Reding "pad"; 1755c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1756c2599da7SThierry Reding reset-names = "sor"; 1757c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1758c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1759c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1760c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1761c2599da7SThierry Reding status = "disabled"; 1762c2599da7SThierry Reding 1763c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1764c2599da7SThierry Reding nvidia,interface = <0>; 1765c2599da7SThierry Reding }; 1766c2599da7SThierry Reding 1767c2599da7SThierry Reding sor1: sor@15580000 { 1768d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1769c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1770c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1771c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1772c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1773c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1774c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1775c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1776c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1777c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1778c2599da7SThierry Reding "pad"; 1779c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1780c2599da7SThierry Reding reset-names = "sor"; 1781c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1782c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1783c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1784c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1785c2599da7SThierry Reding status = "disabled"; 1786c2599da7SThierry Reding 1787c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1788c2599da7SThierry Reding nvidia,interface = <1>; 1789c2599da7SThierry Reding }; 1790c2599da7SThierry Reding 1791c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1792c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1793c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1794c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1795c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1796c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1797c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1798c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1799c2599da7SThierry Reding reset-names = "dpaux"; 1800c2599da7SThierry Reding status = "disabled"; 1801c2599da7SThierry Reding 1802c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1803c2599da7SThierry Reding 1804c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1805c2599da7SThierry Reding groups = "dpaux-io"; 1806c2599da7SThierry Reding function = "aux"; 1807c2599da7SThierry Reding }; 1808c2599da7SThierry Reding 1809c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1810c2599da7SThierry Reding groups = "dpaux-io"; 1811c2599da7SThierry Reding function = "i2c"; 1812c2599da7SThierry Reding }; 1813c2599da7SThierry Reding 1814c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1815c2599da7SThierry Reding groups = "dpaux-io"; 1816c2599da7SThierry Reding function = "off"; 1817c2599da7SThierry Reding }; 1818c2599da7SThierry Reding 1819c2599da7SThierry Reding i2c-bus { 1820c2599da7SThierry Reding #address-cells = <1>; 1821c2599da7SThierry Reding #size-cells = <0>; 1822c2599da7SThierry Reding }; 1823c2599da7SThierry Reding }; 1824c2599da7SThierry Reding 1825c2599da7SThierry Reding padctl@15880000 { 1826c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1827c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1828c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1829c2599da7SThierry Reding reset-names = "dsi"; 1830c2599da7SThierry Reding status = "disabled"; 1831c2599da7SThierry Reding }; 1832c2599da7SThierry Reding 1833c2599da7SThierry Reding dsic: dsi@15900000 { 1834c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1835c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1836c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1837c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1838c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1839c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1840c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1841c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1842c2599da7SThierry Reding reset-names = "dsi"; 1843c2599da7SThierry Reding status = "disabled"; 1844c2599da7SThierry Reding 1845c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1846c2599da7SThierry Reding }; 1847c2599da7SThierry Reding 1848c2599da7SThierry Reding dsid: dsi@15940000 { 1849c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1850c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1851c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1852c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1853c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1854c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1855c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1856c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1857c2599da7SThierry Reding reset-names = "dsi"; 1858c2599da7SThierry Reding status = "disabled"; 1859c2599da7SThierry Reding 1860c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1861c2599da7SThierry Reding }; 18625524c61fSMikko Perttunen }; 18635524c61fSMikko Perttunen 1864dfd7a384SAlexandre Courbot gpu@17000000 { 1865dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1866dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1867dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 186859a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 186959a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1870dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1871dfd7a384SAlexandre Courbot 1872dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1873dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1874dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1875dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1876dfd7a384SAlexandre Courbot reset-names = "gpu"; 1877dfd7a384SAlexandre Courbot status = "disabled"; 1878dfd7a384SAlexandre Courbot 1879dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1880954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1881954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1882954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1883954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1884954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1885dfd7a384SAlexandre Courbot }; 1886dfd7a384SAlexandre Courbot 1887e867fe41SThierry Reding sram@30000000 { 188839cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 188939cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1890aa78032cSThierry Reding #address-cells = <1>; 1891aa78032cSThierry Reding #size-cells = <1>; 1892aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 189361192a9dSMikko Perttunen no-memory-wc; 189439cb62cbSJoseph Lo 1895e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1896aa78032cSThierry Reding reg = <0x4e000 0x1000>; 189739cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 189839cb62cbSJoseph Lo pool; 189939cb62cbSJoseph Lo }; 190039cb62cbSJoseph Lo 1901e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1902aa78032cSThierry Reding reg = <0x4f000 0x1000>; 190339cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 190439cb62cbSJoseph Lo pool; 190539cb62cbSJoseph Lo }; 190639cb62cbSJoseph Lo }; 190739cb62cbSJoseph Lo 1908541d7c44SThierry Reding bpmp: bpmp { 1909541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1910954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1911954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1912954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1913954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1914954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1915541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1916541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1917541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 19187fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1919541d7c44SThierry Reding #clock-cells = <1>; 1920541d7c44SThierry Reding #reset-cells = <1>; 1921541d7c44SThierry Reding #power-domain-cells = <1>; 1922541d7c44SThierry Reding 1923541d7c44SThierry Reding bpmp_i2c: i2c { 1924541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1925541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1926541d7c44SThierry Reding #address-cells = <1>; 1927541d7c44SThierry Reding #size-cells = <0>; 1928541d7c44SThierry Reding status = "disabled"; 1929541d7c44SThierry Reding }; 1930541d7c44SThierry Reding 1931541d7c44SThierry Reding bpmp_thermal: thermal { 1932541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1933541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1934541d7c44SThierry Reding }; 1935541d7c44SThierry Reding }; 1936541d7c44SThierry Reding 1937cd6fe32eSThierry Reding cpus { 1938cd6fe32eSThierry Reding #address-cells = <1>; 1939cd6fe32eSThierry Reding #size-cells = <0>; 1940cd6fe32eSThierry Reding 19413b4c1378SMarc Zyngier denver_0: cpu@0 { 194231af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1943cd6fe32eSThierry Reding device_type = "cpu"; 19445298166dSJoseph Lo i-cache-size = <0x20000>; 19455298166dSJoseph Lo i-cache-line-size = <64>; 19465298166dSJoseph Lo i-cache-sets = <512>; 19475298166dSJoseph Lo d-cache-size = <0x10000>; 19485298166dSJoseph Lo d-cache-line-size = <64>; 19495298166dSJoseph Lo d-cache-sets = <256>; 19505298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1951cd6fe32eSThierry Reding reg = <0x000>; 1952cd6fe32eSThierry Reding }; 1953cd6fe32eSThierry Reding 19543b4c1378SMarc Zyngier denver_1: cpu@1 { 195531af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1956cd6fe32eSThierry Reding device_type = "cpu"; 19575298166dSJoseph Lo i-cache-size = <0x20000>; 19585298166dSJoseph Lo i-cache-line-size = <64>; 19595298166dSJoseph Lo i-cache-sets = <512>; 19605298166dSJoseph Lo d-cache-size = <0x10000>; 19615298166dSJoseph Lo d-cache-line-size = <64>; 19625298166dSJoseph Lo d-cache-sets = <256>; 19635298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1964cd6fe32eSThierry Reding reg = <0x001>; 1965cd6fe32eSThierry Reding }; 1966cd6fe32eSThierry Reding 19673b4c1378SMarc Zyngier ca57_0: cpu@2 { 196831af04cdSRob Herring compatible = "arm,cortex-a57"; 1969cd6fe32eSThierry Reding device_type = "cpu"; 19705298166dSJoseph Lo i-cache-size = <0xC000>; 19715298166dSJoseph Lo i-cache-line-size = <64>; 19725298166dSJoseph Lo i-cache-sets = <256>; 19735298166dSJoseph Lo d-cache-size = <0x8000>; 19745298166dSJoseph Lo d-cache-line-size = <64>; 19755298166dSJoseph Lo d-cache-sets = <256>; 19765298166dSJoseph Lo next-level-cache = <&L2_A57>; 1977cd6fe32eSThierry Reding reg = <0x100>; 1978cd6fe32eSThierry Reding }; 1979cd6fe32eSThierry Reding 19803b4c1378SMarc Zyngier ca57_1: cpu@3 { 198131af04cdSRob Herring compatible = "arm,cortex-a57"; 1982cd6fe32eSThierry Reding device_type = "cpu"; 19835298166dSJoseph Lo i-cache-size = <0xC000>; 19845298166dSJoseph Lo i-cache-line-size = <64>; 19855298166dSJoseph Lo i-cache-sets = <256>; 19865298166dSJoseph Lo d-cache-size = <0x8000>; 19875298166dSJoseph Lo d-cache-line-size = <64>; 19885298166dSJoseph Lo d-cache-sets = <256>; 19895298166dSJoseph Lo next-level-cache = <&L2_A57>; 1990cd6fe32eSThierry Reding reg = <0x101>; 1991cd6fe32eSThierry Reding }; 1992cd6fe32eSThierry Reding 19933b4c1378SMarc Zyngier ca57_2: cpu@4 { 199431af04cdSRob Herring compatible = "arm,cortex-a57"; 1995cd6fe32eSThierry Reding device_type = "cpu"; 19965298166dSJoseph Lo i-cache-size = <0xC000>; 19975298166dSJoseph Lo i-cache-line-size = <64>; 19985298166dSJoseph Lo i-cache-sets = <256>; 19995298166dSJoseph Lo d-cache-size = <0x8000>; 20005298166dSJoseph Lo d-cache-line-size = <64>; 20015298166dSJoseph Lo d-cache-sets = <256>; 20025298166dSJoseph Lo next-level-cache = <&L2_A57>; 2003cd6fe32eSThierry Reding reg = <0x102>; 2004cd6fe32eSThierry Reding }; 2005cd6fe32eSThierry Reding 20063b4c1378SMarc Zyngier ca57_3: cpu@5 { 200731af04cdSRob Herring compatible = "arm,cortex-a57"; 2008cd6fe32eSThierry Reding device_type = "cpu"; 20095298166dSJoseph Lo i-cache-size = <0xC000>; 20105298166dSJoseph Lo i-cache-line-size = <64>; 20115298166dSJoseph Lo i-cache-sets = <256>; 20125298166dSJoseph Lo d-cache-size = <0x8000>; 20135298166dSJoseph Lo d-cache-line-size = <64>; 20145298166dSJoseph Lo d-cache-sets = <256>; 20155298166dSJoseph Lo next-level-cache = <&L2_A57>; 2016cd6fe32eSThierry Reding reg = <0x103>; 2017cd6fe32eSThierry Reding }; 20185298166dSJoseph Lo 20195298166dSJoseph Lo L2_DENVER: l2-cache0 { 20205298166dSJoseph Lo compatible = "cache"; 20215298166dSJoseph Lo cache-unified; 20225298166dSJoseph Lo cache-level = <2>; 20235298166dSJoseph Lo cache-size = <0x200000>; 20245298166dSJoseph Lo cache-line-size = <64>; 20255298166dSJoseph Lo cache-sets = <2048>; 20265298166dSJoseph Lo }; 20275298166dSJoseph Lo 20285298166dSJoseph Lo L2_A57: l2-cache1 { 20295298166dSJoseph Lo compatible = "cache"; 20305298166dSJoseph Lo cache-unified; 20315298166dSJoseph Lo cache-level = <2>; 20325298166dSJoseph Lo cache-size = <0x200000>; 20335298166dSJoseph Lo cache-line-size = <64>; 20345298166dSJoseph Lo cache-sets = <2048>; 20355298166dSJoseph Lo }; 2036cd6fe32eSThierry Reding }; 2037cd6fe32eSThierry Reding 203879ed18d9SThierry Reding pmu-a57 { 2039f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 20403b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 20413b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20423b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20433b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20443b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20453b4c1378SMarc Zyngier }; 20463b4c1378SMarc Zyngier 204779ed18d9SThierry Reding pmu-denver { 204879ed18d9SThierry Reding compatible = "nvidia,denver-pmu"; 204979ed18d9SThierry Reding interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 205079ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 205179ed18d9SThierry Reding interrupt-affinity = <&denver_0 &denver_1>; 205279ed18d9SThierry Reding }; 205379ed18d9SThierry Reding 2054e4710376SSameer Pujar sound { 2055e4710376SSameer Pujar status = "disabled"; 2056e4710376SSameer Pujar 2057e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2058e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2059e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2060e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2061e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2062e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2063e4710376SSameer Pujar assigned-clock-parents = <0>, 2064e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2065e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2066e4710376SSameer Pujar /* 2067e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2068e4710376SSameer Pujar * for this to work and oscillate between base rates required 2069e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2070e4710376SSameer Pujar */ 2071e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2072e4710376SSameer Pujar 2073e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2074e4710376SSameer Pujar }; 2075e4710376SSameer Pujar 207615274c23SMikko Perttunen thermal-zones { 2077fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2078fe57ff53SThierry Reding cpu-thermal { 207915274c23SMikko Perttunen polling-delay = <0>; 208015274c23SMikko Perttunen polling-delay-passive = <1000>; 208115274c23SMikko Perttunen 2082fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 208315274c23SMikko Perttunen 208415274c23SMikko Perttunen trips { 208515274c23SMikko Perttunen critical { 208615274c23SMikko Perttunen temperature = <101000>; 208715274c23SMikko Perttunen hysteresis = <0>; 208815274c23SMikko Perttunen type = "critical"; 208915274c23SMikko Perttunen }; 209015274c23SMikko Perttunen }; 209115274c23SMikko Perttunen 209215274c23SMikko Perttunen cooling-maps { 209315274c23SMikko Perttunen }; 209415274c23SMikko Perttunen }; 209515274c23SMikko Perttunen 2096fe57ff53SThierry Reding /* Denver cluster */ 2097fe57ff53SThierry Reding aux-thermal { 209815274c23SMikko Perttunen polling-delay = <0>; 209915274c23SMikko Perttunen polling-delay-passive = <1000>; 210015274c23SMikko Perttunen 2101fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 210215274c23SMikko Perttunen 210315274c23SMikko Perttunen trips { 210415274c23SMikko Perttunen critical { 210515274c23SMikko Perttunen temperature = <101000>; 210615274c23SMikko Perttunen hysteresis = <0>; 210715274c23SMikko Perttunen type = "critical"; 210815274c23SMikko Perttunen }; 210915274c23SMikko Perttunen }; 211015274c23SMikko Perttunen 211115274c23SMikko Perttunen cooling-maps { 211215274c23SMikko Perttunen }; 211315274c23SMikko Perttunen }; 211415274c23SMikko Perttunen 2115fe57ff53SThierry Reding gpu-thermal { 211615274c23SMikko Perttunen polling-delay = <0>; 211715274c23SMikko Perttunen polling-delay-passive = <1000>; 211815274c23SMikko Perttunen 2119fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 212015274c23SMikko Perttunen 212115274c23SMikko Perttunen trips { 212215274c23SMikko Perttunen critical { 212315274c23SMikko Perttunen temperature = <101000>; 212415274c23SMikko Perttunen hysteresis = <0>; 212515274c23SMikko Perttunen type = "critical"; 212615274c23SMikko Perttunen }; 212715274c23SMikko Perttunen }; 212815274c23SMikko Perttunen 212915274c23SMikko Perttunen cooling-maps { 213015274c23SMikko Perttunen }; 213115274c23SMikko Perttunen }; 213215274c23SMikko Perttunen 2133fe57ff53SThierry Reding pll-thermal { 213415274c23SMikko Perttunen polling-delay = <0>; 213515274c23SMikko Perttunen polling-delay-passive = <1000>; 213615274c23SMikko Perttunen 2137fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 213815274c23SMikko Perttunen 213915274c23SMikko Perttunen trips { 214015274c23SMikko Perttunen critical { 214115274c23SMikko Perttunen temperature = <101000>; 214215274c23SMikko Perttunen hysteresis = <0>; 214315274c23SMikko Perttunen type = "critical"; 214415274c23SMikko Perttunen }; 214515274c23SMikko Perttunen }; 214615274c23SMikko Perttunen 214715274c23SMikko Perttunen cooling-maps { 214815274c23SMikko Perttunen }; 214915274c23SMikko Perttunen }; 215015274c23SMikko Perttunen 2151fe57ff53SThierry Reding ao-thermal { 215215274c23SMikko Perttunen polling-delay = <0>; 215315274c23SMikko Perttunen polling-delay-passive = <1000>; 215415274c23SMikko Perttunen 2155fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 215615274c23SMikko Perttunen 215715274c23SMikko Perttunen trips { 215815274c23SMikko Perttunen critical { 215915274c23SMikko Perttunen temperature = <101000>; 216015274c23SMikko Perttunen hysteresis = <0>; 216115274c23SMikko Perttunen type = "critical"; 216215274c23SMikko Perttunen }; 216315274c23SMikko Perttunen }; 216415274c23SMikko Perttunen 216515274c23SMikko Perttunen cooling-maps { 216615274c23SMikko Perttunen }; 216715274c23SMikko Perttunen }; 216839cb62cbSJoseph Lo }; 216939cb62cbSJoseph Lo 217039cb62cbSJoseph Lo timer { 217139cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 217239cb62cbSJoseph Lo interrupts = <GIC_PPI 13 217339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217439cb62cbSJoseph Lo <GIC_PPI 14 217539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217639cb62cbSJoseph Lo <GIC_PPI 11 217739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217839cb62cbSJoseph Lo <GIC_PPI 10 217939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 218039cb62cbSJoseph Lo interrupt-parent = <&gic>; 2181b30be673SThierry Reding always-on; 218239cb62cbSJoseph Lo }; 218339cb62cbSJoseph Lo}; 2184