1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 7dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 87bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 915274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1039cb62cbSJoseph Lo 1139cb62cbSJoseph Lo/ { 1239cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1339cb62cbSJoseph Lo interrupt-parent = <&gic>; 1439cb62cbSJoseph Lo #address-cells = <2>; 1539cb62cbSJoseph Lo #size-cells = <2>; 1639cb62cbSJoseph Lo 1794e25dc3SThierry Reding misc@100000 { 1894e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 1994e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2094e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2194e25dc3SThierry Reding }; 2294e25dc3SThierry Reding 23fc4bb754SThierry Reding gpio: gpio@2200000 { 24fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 25fc4bb754SThierry Reding reg-names = "security", "gpio"; 26fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 27fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 28fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 29fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 34fc4bb754SThierry Reding #interrupt-cells = <2>; 35fc4bb754SThierry Reding interrupt-controller; 36fc4bb754SThierry Reding #gpio-cells = <2>; 37fc4bb754SThierry Reding gpio-controller; 38fc4bb754SThierry Reding }; 39fc4bb754SThierry Reding 400caafbdeSThierry Reding ethernet@2490000 { 410caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 420caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 430caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 440caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 450caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 460caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 470caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 480caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 490caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 500caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 510caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 520caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 530caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 540caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 550caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 590caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 600caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 610caafbdeSThierry Reding reset-names = "eqos"; 620caafbdeSThierry Reding status = "disabled"; 630caafbdeSThierry Reding 640caafbdeSThierry Reding snps,write-requests = <1>; 650caafbdeSThierry Reding snps,read-requests = <3>; 660caafbdeSThierry Reding snps,burst-map = <0x7>; 670caafbdeSThierry Reding snps,txpbl = <32>; 680caafbdeSThierry Reding snps,rxpbl = <8>; 690caafbdeSThierry Reding }; 700caafbdeSThierry Reding 71d25a3bf1SThierry Reding memory-controller@2c00000 { 72d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 73d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 74d25a3bf1SThierry Reding status = "disabled"; 75d25a3bf1SThierry Reding }; 76d25a3bf1SThierry Reding 7739cb62cbSJoseph Lo uarta: serial@3100000 { 7839cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 7939cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8039cb62cbSJoseph Lo reg-shift = <2>; 8139cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 82c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 83a7a77e2eSThierry Reding clock-names = "serial"; 847bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 85a7a77e2eSThierry Reding reset-names = "serial"; 86a7a77e2eSThierry Reding status = "disabled"; 87a7a77e2eSThierry Reding }; 88a7a77e2eSThierry Reding 89a7a77e2eSThierry Reding uartb: serial@3110000 { 90a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 91a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 92a7a77e2eSThierry Reding reg-shift = <2>; 93a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 94c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 95a7a77e2eSThierry Reding clock-names = "serial"; 967bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 97a7a77e2eSThierry Reding reset-names = "serial"; 98a7a77e2eSThierry Reding status = "disabled"; 99a7a77e2eSThierry Reding }; 100a7a77e2eSThierry Reding 101a7a77e2eSThierry Reding uartd: serial@3130000 { 102a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 103a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 104a7a77e2eSThierry Reding reg-shift = <2>; 105a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 106c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 107a7a77e2eSThierry Reding clock-names = "serial"; 1087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 109a7a77e2eSThierry Reding reset-names = "serial"; 110a7a77e2eSThierry Reding status = "disabled"; 111a7a77e2eSThierry Reding }; 112a7a77e2eSThierry Reding 113a7a77e2eSThierry Reding uarte: serial@3140000 { 114a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 115a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 116a7a77e2eSThierry Reding reg-shift = <2>; 117a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 118c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 119a7a77e2eSThierry Reding clock-names = "serial"; 1207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 121a7a77e2eSThierry Reding reset-names = "serial"; 122a7a77e2eSThierry Reding status = "disabled"; 123a7a77e2eSThierry Reding }; 124a7a77e2eSThierry Reding 125a7a77e2eSThierry Reding uartf: serial@3150000 { 126a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 127a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 128a7a77e2eSThierry Reding reg-shift = <2>; 129a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 130c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 131a7a77e2eSThierry Reding clock-names = "serial"; 1327bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 133a7a77e2eSThierry Reding reset-names = "serial"; 13439cb62cbSJoseph Lo status = "disabled"; 13539cb62cbSJoseph Lo }; 13639cb62cbSJoseph Lo 13740cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13940cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14040cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14140cc83b3SThierry Reding #address-cells = <1>; 14240cc83b3SThierry Reding #size-cells = <0>; 143c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14440cc83b3SThierry Reding clock-names = "div-clk"; 1457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14640cc83b3SThierry Reding reset-names = "i2c"; 14740cc83b3SThierry Reding status = "disabled"; 14840cc83b3SThierry Reding }; 14940cc83b3SThierry Reding 15040cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15240cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15340cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15440cc83b3SThierry Reding #address-cells = <1>; 15540cc83b3SThierry Reding #size-cells = <0>; 156c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15740cc83b3SThierry Reding clock-names = "div-clk"; 1587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 15940cc83b3SThierry Reding reset-names = "i2c"; 16040cc83b3SThierry Reding status = "disabled"; 16140cc83b3SThierry Reding }; 16240cc83b3SThierry Reding 16340cc83b3SThierry Reding /* shares pads with dpaux1 */ 16440cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16640cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16740cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16840cc83b3SThierry Reding #address-cells = <1>; 16940cc83b3SThierry Reding #size-cells = <0>; 170c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17140cc83b3SThierry Reding clock-names = "div-clk"; 1727bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17340cc83b3SThierry Reding reset-names = "i2c"; 17440cc83b3SThierry Reding status = "disabled"; 17540cc83b3SThierry Reding }; 17640cc83b3SThierry Reding 17740cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17840cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 17940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18040cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18140cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18240cc83b3SThierry Reding #address-cells = <1>; 18340cc83b3SThierry Reding #size-cells = <0>; 184c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18540cc83b3SThierry Reding clock-names = "div-clk"; 1867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18740cc83b3SThierry Reding reset-names = "i2c"; 18840cc83b3SThierry Reding status = "disabled"; 18940cc83b3SThierry Reding }; 19040cc83b3SThierry Reding 19140cc83b3SThierry Reding /* shares pads with dpaux0 */ 19240cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19440cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19540cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19640cc83b3SThierry Reding #address-cells = <1>; 19740cc83b3SThierry Reding #size-cells = <0>; 198c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 19940cc83b3SThierry Reding clock-names = "div-clk"; 2007bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20140cc83b3SThierry Reding reset-names = "i2c"; 20240cc83b3SThierry Reding status = "disabled"; 20340cc83b3SThierry Reding }; 20440cc83b3SThierry Reding 20540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 20940cc83b3SThierry Reding #address-cells = <1>; 21040cc83b3SThierry Reding #size-cells = <0>; 211c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21240cc83b3SThierry Reding clock-names = "div-clk"; 2137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21440cc83b3SThierry Reding reset-names = "i2c"; 21540cc83b3SThierry Reding status = "disabled"; 21640cc83b3SThierry Reding }; 21740cc83b3SThierry Reding 21840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 21940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22240cc83b3SThierry Reding #address-cells = <1>; 22340cc83b3SThierry Reding #size-cells = <0>; 224c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22540cc83b3SThierry Reding clock-names = "div-clk"; 2267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22740cc83b3SThierry Reding reset-names = "i2c"; 22840cc83b3SThierry Reding status = "disabled"; 22940cc83b3SThierry Reding }; 23040cc83b3SThierry Reding 23199425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23399425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23499425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 235c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23699425dfdSThierry Reding clock-names = "sdhci"; 2377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23899425dfdSThierry Reding reset-names = "sdhci"; 23999425dfdSThierry Reding status = "disabled"; 24099425dfdSThierry Reding }; 24199425dfdSThierry Reding 24299425dfdSThierry Reding sdmmc2: sdhci@3420000 { 24399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24499425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 24599425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 246c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 24799425dfdSThierry Reding clock-names = "sdhci"; 2487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 24999425dfdSThierry Reding reset-names = "sdhci"; 25099425dfdSThierry Reding status = "disabled"; 25199425dfdSThierry Reding }; 25299425dfdSThierry Reding 25399425dfdSThierry Reding sdmmc3: sdhci@3440000 { 25499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 25699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 257c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 25899425dfdSThierry Reding clock-names = "sdhci"; 2597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 26099425dfdSThierry Reding reset-names = "sdhci"; 26199425dfdSThierry Reding status = "disabled"; 26299425dfdSThierry Reding }; 26399425dfdSThierry Reding 26499425dfdSThierry Reding sdmmc4: sdhci@3460000 { 26599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 26699425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 26799425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 268c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 26999425dfdSThierry Reding clock-names = "sdhci"; 2707bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 27199425dfdSThierry Reding reset-names = "sdhci"; 27299425dfdSThierry Reding status = "disabled"; 27399425dfdSThierry Reding }; 27499425dfdSThierry Reding 27585593b75SThierry Reding fuse@3820000 { 27685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 27785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 27885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 27985593b75SThierry Reding clock-names = "fuse"; 28085593b75SThierry Reding }; 28185593b75SThierry Reding 28239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 28339cb62cbSJoseph Lo compatible = "arm,gic-400"; 28439cb62cbSJoseph Lo #interrupt-cells = <3>; 28539cb62cbSJoseph Lo interrupt-controller; 28639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 28739cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 28839cb62cbSJoseph Lo interrupts = <GIC_PPI 9 28939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 29039cb62cbSJoseph Lo interrupt-parent = <&gic>; 29139cb62cbSJoseph Lo }; 29239cb62cbSJoseph Lo 29339cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 29439cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 29539cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 29639cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 29739cb62cbSJoseph Lo interrupt-names = "doorbell"; 29839cb62cbSJoseph Lo #mbox-cells = <2>; 29939cb62cbSJoseph Lo status = "disabled"; 30039cb62cbSJoseph Lo }; 30139cb62cbSJoseph Lo 30240cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 30340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 30440cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 30540cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 30640cc83b3SThierry Reding #address-cells = <1>; 30740cc83b3SThierry Reding #size-cells = <0>; 308c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 30940cc83b3SThierry Reding clock-names = "div-clk"; 3107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 31140cc83b3SThierry Reding reset-names = "i2c"; 31240cc83b3SThierry Reding status = "disabled"; 31340cc83b3SThierry Reding }; 31440cc83b3SThierry Reding 31540cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 31640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 31740cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 31840cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 31940cc83b3SThierry Reding #address-cells = <1>; 32040cc83b3SThierry Reding #size-cells = <0>; 321c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 32240cc83b3SThierry Reding clock-names = "div-clk"; 3237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 32440cc83b3SThierry Reding reset-names = "i2c"; 32540cc83b3SThierry Reding status = "disabled"; 32640cc83b3SThierry Reding }; 32740cc83b3SThierry Reding 328a7a77e2eSThierry Reding uartc: serial@c280000 { 329a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 330a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 331a7a77e2eSThierry Reding reg-shift = <2>; 332a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 333c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 334a7a77e2eSThierry Reding clock-names = "serial"; 3357bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 336a7a77e2eSThierry Reding reset-names = "serial"; 337a7a77e2eSThierry Reding status = "disabled"; 338a7a77e2eSThierry Reding }; 339a7a77e2eSThierry Reding 340a7a77e2eSThierry Reding uartg: serial@c290000 { 341a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 342a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 343a7a77e2eSThierry Reding reg-shift = <2>; 344a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 345c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 346a7a77e2eSThierry Reding clock-names = "serial"; 3477bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 348a7a77e2eSThierry Reding reset-names = "serial"; 349a7a77e2eSThierry Reding status = "disabled"; 350a7a77e2eSThierry Reding }; 351a7a77e2eSThierry Reding 352fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 353fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 354fc4bb754SThierry Reding reg-names = "security", "gpio"; 355fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 356fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 357fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 358fc4bb754SThierry Reding gpio-controller; 359fc4bb754SThierry Reding #gpio-cells = <2>; 360fc4bb754SThierry Reding interrupt-controller; 361fc4bb754SThierry Reding #interrupt-cells = <2>; 362fc4bb754SThierry Reding }; 363fc4bb754SThierry Reding 36473bf90d4SThierry Reding pmc@c360000 { 36573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 36673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 36773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 36873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 36973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 37073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 37173bf90d4SThierry Reding }; 37273bf90d4SThierry Reding 3737b7ef494SMikko Perttunen ccplex@e000000 { 3747b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 3757b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 3767b7ef494SMikko Perttunen 3777b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 3787b7ef494SMikko Perttunen }; 3797b7ef494SMikko Perttunen 380f8973cf4SManikanta Maddireddy pcie@10003000 { 381f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 382f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 383f8973cf4SManikanta Maddireddy device_type = "pci"; 384f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 385f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 386f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 387f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 388f8973cf4SManikanta Maddireddy 389f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 390f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 391f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 392f8973cf4SManikanta Maddireddy 393f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 394f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 395f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 396f8973cf4SManikanta Maddireddy 397f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 398f8973cf4SManikanta Maddireddy #address-cells = <3>; 399f8973cf4SManikanta Maddireddy #size-cells = <2>; 400f8973cf4SManikanta Maddireddy 401f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 402f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 403f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 404f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 405f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 406f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 407f8973cf4SManikanta Maddireddy 408f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 409f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 410f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 411f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 412f8973cf4SManikanta Maddireddy 413f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 414f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 415f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 416f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 417f8973cf4SManikanta Maddireddy 418f8973cf4SManikanta Maddireddy status = "disabled"; 419f8973cf4SManikanta Maddireddy 420f8973cf4SManikanta Maddireddy pci@1,0 { 421f8973cf4SManikanta Maddireddy device_type = "pci"; 422f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 423f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 424f8973cf4SManikanta Maddireddy status = "disabled"; 425f8973cf4SManikanta Maddireddy 426f8973cf4SManikanta Maddireddy #address-cells = <3>; 427f8973cf4SManikanta Maddireddy #size-cells = <2>; 428f8973cf4SManikanta Maddireddy ranges; 429f8973cf4SManikanta Maddireddy 430f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 431f8973cf4SManikanta Maddireddy }; 432f8973cf4SManikanta Maddireddy 433f8973cf4SManikanta Maddireddy pci@2,0 { 434f8973cf4SManikanta Maddireddy device_type = "pci"; 435f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 436f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 437f8973cf4SManikanta Maddireddy status = "disabled"; 438f8973cf4SManikanta Maddireddy 439f8973cf4SManikanta Maddireddy #address-cells = <3>; 440f8973cf4SManikanta Maddireddy #size-cells = <2>; 441f8973cf4SManikanta Maddireddy ranges; 442f8973cf4SManikanta Maddireddy 443f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 444f8973cf4SManikanta Maddireddy }; 445f8973cf4SManikanta Maddireddy 446f8973cf4SManikanta Maddireddy pci@3,0 { 447f8973cf4SManikanta Maddireddy device_type = "pci"; 448f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 449f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 450f8973cf4SManikanta Maddireddy status = "disabled"; 451f8973cf4SManikanta Maddireddy 452f8973cf4SManikanta Maddireddy #address-cells = <3>; 453f8973cf4SManikanta Maddireddy #size-cells = <2>; 454f8973cf4SManikanta Maddireddy ranges; 455f8973cf4SManikanta Maddireddy 456f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 457f8973cf4SManikanta Maddireddy }; 458f8973cf4SManikanta Maddireddy }; 459f8973cf4SManikanta Maddireddy 4605524c61fSMikko Perttunen host1x@13e00000 { 4615524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 4625524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 4635524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 4645524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 4655524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 4665524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4675524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 4685524c61fSMikko Perttunen clock-names = "host1x"; 4695524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 4705524c61fSMikko Perttunen reset-names = "host1x"; 4715524c61fSMikko Perttunen 4725524c61fSMikko Perttunen #address-cells = <1>; 4735524c61fSMikko Perttunen #size-cells = <1>; 4745524c61fSMikko Perttunen 4755524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 476effc4b44SMikko Perttunen 477effc4b44SMikko Perttunen vic@15340000 { 478effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 479effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 480effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 481effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 482effc4b44SMikko Perttunen clock-names = "vic"; 483effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 484effc4b44SMikko Perttunen reset-names = "vic"; 485effc4b44SMikko Perttunen 486effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 487effc4b44SMikko Perttunen }; 4885524c61fSMikko Perttunen }; 4895524c61fSMikko Perttunen 490dfd7a384SAlexandre Courbot gpu@17000000 { 491dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 492dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 493dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 494dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 495dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 496dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 497dfd7a384SAlexandre Courbot 498dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 499dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 500dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 501dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 502dfd7a384SAlexandre Courbot reset-names = "gpu"; 503dfd7a384SAlexandre Courbot status = "disabled"; 504dfd7a384SAlexandre Courbot 505dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 506dfd7a384SAlexandre Courbot }; 507dfd7a384SAlexandre Courbot 50839cb62cbSJoseph Lo sysram@30000000 { 50939cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 51039cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 51139cb62cbSJoseph Lo #address-cells = <2>; 51239cb62cbSJoseph Lo #size-cells = <2>; 51339cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 51439cb62cbSJoseph Lo 51539cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 51639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 51739cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 51839cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 51939cb62cbSJoseph Lo pool; 52039cb62cbSJoseph Lo }; 52139cb62cbSJoseph Lo 52239cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 52339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 52439cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 52539cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 52639cb62cbSJoseph Lo pool; 52739cb62cbSJoseph Lo }; 52839cb62cbSJoseph Lo }; 52939cb62cbSJoseph Lo 530cd6fe32eSThierry Reding cpus { 531cd6fe32eSThierry Reding #address-cells = <1>; 532cd6fe32eSThierry Reding #size-cells = <0>; 533cd6fe32eSThierry Reding 534cd6fe32eSThierry Reding cpu@0 { 535cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 536cd6fe32eSThierry Reding device_type = "cpu"; 537cd6fe32eSThierry Reding reg = <0x000>; 538cd6fe32eSThierry Reding }; 539cd6fe32eSThierry Reding 540cd6fe32eSThierry Reding cpu@1 { 541cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 542cd6fe32eSThierry Reding device_type = "cpu"; 543cd6fe32eSThierry Reding reg = <0x001>; 544cd6fe32eSThierry Reding }; 545cd6fe32eSThierry Reding 546cd6fe32eSThierry Reding cpu@2 { 547cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 548cd6fe32eSThierry Reding device_type = "cpu"; 549cd6fe32eSThierry Reding reg = <0x100>; 550cd6fe32eSThierry Reding }; 551cd6fe32eSThierry Reding 552cd6fe32eSThierry Reding cpu@3 { 553cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 554cd6fe32eSThierry Reding device_type = "cpu"; 555cd6fe32eSThierry Reding reg = <0x101>; 556cd6fe32eSThierry Reding }; 557cd6fe32eSThierry Reding 558cd6fe32eSThierry Reding cpu@4 { 559cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 560cd6fe32eSThierry Reding device_type = "cpu"; 561cd6fe32eSThierry Reding reg = <0x102>; 562cd6fe32eSThierry Reding }; 563cd6fe32eSThierry Reding 564cd6fe32eSThierry Reding cpu@5 { 565cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 566cd6fe32eSThierry Reding device_type = "cpu"; 567cd6fe32eSThierry Reding reg = <0x103>; 568cd6fe32eSThierry Reding }; 569cd6fe32eSThierry Reding }; 570cd6fe32eSThierry Reding 57139cb62cbSJoseph Lo bpmp: bpmp { 57239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 5735edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5745edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 57539cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 57639cb62cbSJoseph Lo #clock-cells = <1>; 57739cb62cbSJoseph Lo #reset-cells = <1>; 578dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 57939cb62cbSJoseph Lo 58039cb62cbSJoseph Lo bpmp_i2c: i2c { 58139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 58239cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 58339cb62cbSJoseph Lo #address-cells = <1>; 58439cb62cbSJoseph Lo #size-cells = <0>; 58539cb62cbSJoseph Lo status = "disabled"; 58639cb62cbSJoseph Lo }; 58715274c23SMikko Perttunen 58815274c23SMikko Perttunen bpmp_thermal: thermal { 58915274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 59015274c23SMikko Perttunen #thermal-sensor-cells = <1>; 59115274c23SMikko Perttunen }; 59215274c23SMikko Perttunen }; 59315274c23SMikko Perttunen 59415274c23SMikko Perttunen thermal-zones { 59515274c23SMikko Perttunen a57 { 59615274c23SMikko Perttunen polling-delay = <0>; 59715274c23SMikko Perttunen polling-delay-passive = <1000>; 59815274c23SMikko Perttunen 59915274c23SMikko Perttunen thermal-sensors = 60015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 60115274c23SMikko Perttunen 60215274c23SMikko Perttunen trips { 60315274c23SMikko Perttunen critical { 60415274c23SMikko Perttunen temperature = <101000>; 60515274c23SMikko Perttunen hysteresis = <0>; 60615274c23SMikko Perttunen type = "critical"; 60715274c23SMikko Perttunen }; 60815274c23SMikko Perttunen }; 60915274c23SMikko Perttunen 61015274c23SMikko Perttunen cooling-maps { 61115274c23SMikko Perttunen }; 61215274c23SMikko Perttunen }; 61315274c23SMikko Perttunen 61415274c23SMikko Perttunen denver { 61515274c23SMikko Perttunen polling-delay = <0>; 61615274c23SMikko Perttunen polling-delay-passive = <1000>; 61715274c23SMikko Perttunen 61815274c23SMikko Perttunen thermal-sensors = 61915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 62015274c23SMikko Perttunen 62115274c23SMikko Perttunen trips { 62215274c23SMikko Perttunen critical { 62315274c23SMikko Perttunen temperature = <101000>; 62415274c23SMikko Perttunen hysteresis = <0>; 62515274c23SMikko Perttunen type = "critical"; 62615274c23SMikko Perttunen }; 62715274c23SMikko Perttunen }; 62815274c23SMikko Perttunen 62915274c23SMikko Perttunen cooling-maps { 63015274c23SMikko Perttunen }; 63115274c23SMikko Perttunen }; 63215274c23SMikko Perttunen 63315274c23SMikko Perttunen gpu { 63415274c23SMikko Perttunen polling-delay = <0>; 63515274c23SMikko Perttunen polling-delay-passive = <1000>; 63615274c23SMikko Perttunen 63715274c23SMikko Perttunen thermal-sensors = 63815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 63915274c23SMikko Perttunen 64015274c23SMikko Perttunen trips { 64115274c23SMikko Perttunen critical { 64215274c23SMikko Perttunen temperature = <101000>; 64315274c23SMikko Perttunen hysteresis = <0>; 64415274c23SMikko Perttunen type = "critical"; 64515274c23SMikko Perttunen }; 64615274c23SMikko Perttunen }; 64715274c23SMikko Perttunen 64815274c23SMikko Perttunen cooling-maps { 64915274c23SMikko Perttunen }; 65015274c23SMikko Perttunen }; 65115274c23SMikko Perttunen 65215274c23SMikko Perttunen pll { 65315274c23SMikko Perttunen polling-delay = <0>; 65415274c23SMikko Perttunen polling-delay-passive = <1000>; 65515274c23SMikko Perttunen 65615274c23SMikko Perttunen thermal-sensors = 65715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 65815274c23SMikko Perttunen 65915274c23SMikko Perttunen trips { 66015274c23SMikko Perttunen critical { 66115274c23SMikko Perttunen temperature = <101000>; 66215274c23SMikko Perttunen hysteresis = <0>; 66315274c23SMikko Perttunen type = "critical"; 66415274c23SMikko Perttunen }; 66515274c23SMikko Perttunen }; 66615274c23SMikko Perttunen 66715274c23SMikko Perttunen cooling-maps { 66815274c23SMikko Perttunen }; 66915274c23SMikko Perttunen }; 67015274c23SMikko Perttunen 67115274c23SMikko Perttunen always_on { 67215274c23SMikko Perttunen polling-delay = <0>; 67315274c23SMikko Perttunen polling-delay-passive = <1000>; 67415274c23SMikko Perttunen 67515274c23SMikko Perttunen thermal-sensors = 67615274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 67715274c23SMikko Perttunen 67815274c23SMikko Perttunen trips { 67915274c23SMikko Perttunen critical { 68015274c23SMikko Perttunen temperature = <101000>; 68115274c23SMikko Perttunen hysteresis = <0>; 68215274c23SMikko Perttunen type = "critical"; 68315274c23SMikko Perttunen }; 68415274c23SMikko Perttunen }; 68515274c23SMikko Perttunen 68615274c23SMikko Perttunen cooling-maps { 68715274c23SMikko Perttunen }; 68815274c23SMikko Perttunen }; 68939cb62cbSJoseph Lo }; 69039cb62cbSJoseph Lo 69139cb62cbSJoseph Lo timer { 69239cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 69339cb62cbSJoseph Lo interrupts = <GIC_PPI 13 69439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69539cb62cbSJoseph Lo <GIC_PPI 14 69639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69739cb62cbSJoseph Lo <GIC_PPI 11 69839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69939cb62cbSJoseph Lo <GIC_PPI 10 70039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 70139cb62cbSJoseph Lo interrupt-parent = <&gic>; 70239cb62cbSJoseph Lo }; 70339cb62cbSJoseph Lo}; 704