139cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h>
239cb62cbSJoseph Lo
339cb62cbSJoseph Lo/ {
439cb62cbSJoseph Lo	compatible = "nvidia,tegra186";
539cb62cbSJoseph Lo	interrupt-parent = <&gic>;
639cb62cbSJoseph Lo	#address-cells = <2>;
739cb62cbSJoseph Lo	#size-cells = <2>;
839cb62cbSJoseph Lo
939cb62cbSJoseph Lo	uarta: serial@3100000 {
1039cb62cbSJoseph Lo		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1139cb62cbSJoseph Lo		reg = <0x0 0x03100000 0x0 0x40>;
1239cb62cbSJoseph Lo		reg-shift = <2>;
1339cb62cbSJoseph Lo		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1439cb62cbSJoseph Lo		status = "disabled";
1539cb62cbSJoseph Lo	};
1639cb62cbSJoseph Lo
1739cb62cbSJoseph Lo	gic: interrupt-controller@3881000 {
1839cb62cbSJoseph Lo		compatible = "arm,gic-400";
1939cb62cbSJoseph Lo		#interrupt-cells = <3>;
2039cb62cbSJoseph Lo		interrupt-controller;
2139cb62cbSJoseph Lo		reg = <0x0 0x03881000 0x0 0x1000>,
2239cb62cbSJoseph Lo		      <0x0 0x03882000 0x0 0x2000>;
2339cb62cbSJoseph Lo		interrupts = <GIC_PPI 9
2439cb62cbSJoseph Lo			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2539cb62cbSJoseph Lo		interrupt-parent = <&gic>;
2639cb62cbSJoseph Lo	};
2739cb62cbSJoseph Lo
2839cb62cbSJoseph Lo	hsp_top0: hsp@3c00000 {
2939cb62cbSJoseph Lo		compatible = "nvidia,tegra186-hsp";
3039cb62cbSJoseph Lo		reg = <0x0 0x03c00000 0x0 0xa0000>;
3139cb62cbSJoseph Lo		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
3239cb62cbSJoseph Lo		interrupt-names = "doorbell";
3339cb62cbSJoseph Lo		#mbox-cells = <2>;
3439cb62cbSJoseph Lo		status = "disabled";
3539cb62cbSJoseph Lo	};
3639cb62cbSJoseph Lo
3739cb62cbSJoseph Lo	sysram@30000000 {
3839cb62cbSJoseph Lo		compatible = "nvidia,tegra186-sysram", "mmio-sram";
3939cb62cbSJoseph Lo		reg = <0x0 0x30000000 0x0 0x50000>;
4039cb62cbSJoseph Lo		#address-cells = <2>;
4139cb62cbSJoseph Lo		#size-cells = <2>;
4239cb62cbSJoseph Lo		ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
4339cb62cbSJoseph Lo
4439cb62cbSJoseph Lo		cpu_bpmp_tx: shmem@4e000 {
4539cb62cbSJoseph Lo			compatible = "nvidia,tegra186-bpmp-shmem";
4639cb62cbSJoseph Lo			reg = <0x0 0x4e000 0x0 0x1000>;
4739cb62cbSJoseph Lo			label = "cpu-bpmp-tx";
4839cb62cbSJoseph Lo			pool;
4939cb62cbSJoseph Lo		};
5039cb62cbSJoseph Lo
5139cb62cbSJoseph Lo		cpu_bpmp_rx: shmem@4f000 {
5239cb62cbSJoseph Lo			compatible = "nvidia,tegra186-bpmp-shmem";
5339cb62cbSJoseph Lo			reg = <0x0 0x4f000 0x0 0x1000>;
5439cb62cbSJoseph Lo			label = "cpu-bpmp-rx";
5539cb62cbSJoseph Lo			pool;
5639cb62cbSJoseph Lo		};
5739cb62cbSJoseph Lo	};
5839cb62cbSJoseph Lo
59cd6fe32eSThierry Reding	cpus {
60cd6fe32eSThierry Reding		#address-cells = <1>;
61cd6fe32eSThierry Reding		#size-cells = <0>;
62cd6fe32eSThierry Reding
63cd6fe32eSThierry Reding		cpu@0 {
64cd6fe32eSThierry Reding			compatible = "nvidia,tegra186-denver", "arm,armv8";
65cd6fe32eSThierry Reding			device_type = "cpu";
66cd6fe32eSThierry Reding			reg = <0x000>;
67cd6fe32eSThierry Reding		};
68cd6fe32eSThierry Reding
69cd6fe32eSThierry Reding		cpu@1 {
70cd6fe32eSThierry Reding			compatible = "nvidia,tegra186-denver", "arm,armv8";
71cd6fe32eSThierry Reding			device_type = "cpu";
72cd6fe32eSThierry Reding			reg = <0x001>;
73cd6fe32eSThierry Reding		};
74cd6fe32eSThierry Reding
75cd6fe32eSThierry Reding		cpu@2 {
76cd6fe32eSThierry Reding			compatible = "arm,cortex-a57", "arm,armv8";
77cd6fe32eSThierry Reding			device_type = "cpu";
78cd6fe32eSThierry Reding			reg = <0x100>;
79cd6fe32eSThierry Reding		};
80cd6fe32eSThierry Reding
81cd6fe32eSThierry Reding		cpu@3 {
82cd6fe32eSThierry Reding			compatible = "arm,cortex-a57", "arm,armv8";
83cd6fe32eSThierry Reding			device_type = "cpu";
84cd6fe32eSThierry Reding			reg = <0x101>;
85cd6fe32eSThierry Reding		};
86cd6fe32eSThierry Reding
87cd6fe32eSThierry Reding		cpu@4 {
88cd6fe32eSThierry Reding			compatible = "arm,cortex-a57", "arm,armv8";
89cd6fe32eSThierry Reding			device_type = "cpu";
90cd6fe32eSThierry Reding			reg = <0x102>;
91cd6fe32eSThierry Reding		};
92cd6fe32eSThierry Reding
93cd6fe32eSThierry Reding		cpu@5 {
94cd6fe32eSThierry Reding			compatible = "arm,cortex-a57", "arm,armv8";
95cd6fe32eSThierry Reding			device_type = "cpu";
96cd6fe32eSThierry Reding			reg = <0x103>;
97cd6fe32eSThierry Reding		};
98cd6fe32eSThierry Reding	};
99cd6fe32eSThierry Reding
10039cb62cbSJoseph Lo	bpmp: bpmp {
10139cb62cbSJoseph Lo		compatible = "nvidia,tegra186-bpmp";
10239cb62cbSJoseph Lo		mboxes = <&hsp_top0 0 19>;
10339cb62cbSJoseph Lo		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
10439cb62cbSJoseph Lo		#clock-cells = <1>;
10539cb62cbSJoseph Lo		#reset-cells = <1>;
10639cb62cbSJoseph Lo
10739cb62cbSJoseph Lo		bpmp_i2c: i2c {
10839cb62cbSJoseph Lo			compatible = "nvidia,tegra186-bpmp-i2c";
10939cb62cbSJoseph Lo			nvidia,bpmp-bus-id = <5>;
11039cb62cbSJoseph Lo			#address-cells = <1>;
11139cb62cbSJoseph Lo			#size-cells = <0>;
11239cb62cbSJoseph Lo			status = "disabled";
11339cb62cbSJoseph Lo		};
11439cb62cbSJoseph Lo	};
11539cb62cbSJoseph Lo
11639cb62cbSJoseph Lo	timer {
11739cb62cbSJoseph Lo		compatible = "arm,armv8-timer";
11839cb62cbSJoseph Lo		interrupts = <GIC_PPI 13
11939cb62cbSJoseph Lo				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
12039cb62cbSJoseph Lo			     <GIC_PPI 14
12139cb62cbSJoseph Lo				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
12239cb62cbSJoseph Lo			     <GIC_PPI 11
12339cb62cbSJoseph Lo				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
12439cb62cbSJoseph Lo			     <GIC_PPI 10
12539cb62cbSJoseph Lo				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
12639cb62cbSJoseph Lo		interrupt-parent = <&gic>;
12739cb62cbSJoseph Lo	};
12839cb62cbSJoseph Lo};
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