1c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 2fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 339cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 45edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 539cb62cbSJoseph Lo 639cb62cbSJoseph Lo/ { 739cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 839cb62cbSJoseph Lo interrupt-parent = <&gic>; 939cb62cbSJoseph Lo #address-cells = <2>; 1039cb62cbSJoseph Lo #size-cells = <2>; 1139cb62cbSJoseph Lo 12fc4bb754SThierry Reding gpio: gpio@2200000 { 13fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 14fc4bb754SThierry Reding reg-names = "security", "gpio"; 15fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 16fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 17fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 18fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 19fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 20fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 21fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 22fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 23fc4bb754SThierry Reding #interrupt-cells = <2>; 24fc4bb754SThierry Reding interrupt-controller; 25fc4bb754SThierry Reding #gpio-cells = <2>; 26fc4bb754SThierry Reding gpio-controller; 27fc4bb754SThierry Reding }; 28fc4bb754SThierry Reding 2939cb62cbSJoseph Lo uarta: serial@3100000 { 3039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 3139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 3239cb62cbSJoseph Lo reg-shift = <2>; 3339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 34c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 35a7a77e2eSThierry Reding clock-names = "serial"; 36a7a77e2eSThierry Reding resets = <&bpmp 47>; 37a7a77e2eSThierry Reding reset-names = "serial"; 38a7a77e2eSThierry Reding status = "disabled"; 39a7a77e2eSThierry Reding }; 40a7a77e2eSThierry Reding 41a7a77e2eSThierry Reding uartb: serial@3110000 { 42a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 43a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 44a7a77e2eSThierry Reding reg-shift = <2>; 45a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 46c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 47a7a77e2eSThierry Reding clock-names = "serial"; 48a7a77e2eSThierry Reding resets = <&bpmp 48>; 49a7a77e2eSThierry Reding reset-names = "serial"; 50a7a77e2eSThierry Reding status = "disabled"; 51a7a77e2eSThierry Reding }; 52a7a77e2eSThierry Reding 53a7a77e2eSThierry Reding uartd: serial@3130000 { 54a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 55a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 56a7a77e2eSThierry Reding reg-shift = <2>; 57a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 58c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 59a7a77e2eSThierry Reding clock-names = "serial"; 60a7a77e2eSThierry Reding resets = <&bpmp 50>; 61a7a77e2eSThierry Reding reset-names = "serial"; 62a7a77e2eSThierry Reding status = "disabled"; 63a7a77e2eSThierry Reding }; 64a7a77e2eSThierry Reding 65a7a77e2eSThierry Reding uarte: serial@3140000 { 66a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 67a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 68a7a77e2eSThierry Reding reg-shift = <2>; 69a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 70c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 71a7a77e2eSThierry Reding clock-names = "serial"; 72a7a77e2eSThierry Reding resets = <&bpmp 132>; 73a7a77e2eSThierry Reding reset-names = "serial"; 74a7a77e2eSThierry Reding status = "disabled"; 75a7a77e2eSThierry Reding }; 76a7a77e2eSThierry Reding 77a7a77e2eSThierry Reding uartf: serial@3150000 { 78a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 79a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 80a7a77e2eSThierry Reding reg-shift = <2>; 81a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 82c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 83a7a77e2eSThierry Reding clock-names = "serial"; 84a7a77e2eSThierry Reding resets = <&bpmp 111>; 85a7a77e2eSThierry Reding reset-names = "serial"; 8639cb62cbSJoseph Lo status = "disabled"; 8739cb62cbSJoseph Lo }; 8839cb62cbSJoseph Lo 8940cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 9040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 9140cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 9240cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 9340cc83b3SThierry Reding #address-cells = <1>; 9440cc83b3SThierry Reding #size-cells = <0>; 95c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 9640cc83b3SThierry Reding clock-names = "div-clk"; 9740cc83b3SThierry Reding resets = <&bpmp 19>; 9840cc83b3SThierry Reding reset-names = "i2c"; 9940cc83b3SThierry Reding status = "disabled"; 10040cc83b3SThierry Reding }; 10140cc83b3SThierry Reding 10240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 10340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 10440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 10540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 10640cc83b3SThierry Reding #address-cells = <1>; 10740cc83b3SThierry Reding #size-cells = <0>; 108c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 10940cc83b3SThierry Reding clock-names = "div-clk"; 11040cc83b3SThierry Reding resets = <&bpmp 21>; 11140cc83b3SThierry Reding reset-names = "i2c"; 11240cc83b3SThierry Reding status = "disabled"; 11340cc83b3SThierry Reding }; 11440cc83b3SThierry Reding 11540cc83b3SThierry Reding /* shares pads with dpaux1 */ 11640cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 11740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 11840cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 11940cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 12040cc83b3SThierry Reding #address-cells = <1>; 12140cc83b3SThierry Reding #size-cells = <0>; 122c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 12340cc83b3SThierry Reding clock-names = "div-clk"; 12440cc83b3SThierry Reding resets = <&bpmp 22>; 12540cc83b3SThierry Reding reset-names = "i2c"; 12640cc83b3SThierry Reding status = "disabled"; 12740cc83b3SThierry Reding }; 12840cc83b3SThierry Reding 12940cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 13040cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 13140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13240cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 13340cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 13440cc83b3SThierry Reding #address-cells = <1>; 13540cc83b3SThierry Reding #size-cells = <0>; 136c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 13740cc83b3SThierry Reding clock-names = "div-clk"; 13840cc83b3SThierry Reding resets = <&bpmp 23>; 13940cc83b3SThierry Reding reset-names = "i2c"; 14040cc83b3SThierry Reding status = "disabled"; 14140cc83b3SThierry Reding }; 14240cc83b3SThierry Reding 14340cc83b3SThierry Reding /* shares pads with dpaux0 */ 14440cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 14540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14640cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 14740cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 14840cc83b3SThierry Reding #address-cells = <1>; 14940cc83b3SThierry Reding #size-cells = <0>; 150c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 15140cc83b3SThierry Reding clock-names = "div-clk"; 15240cc83b3SThierry Reding resets = <&bpmp 24>; 15340cc83b3SThierry Reding reset-names = "i2c"; 15440cc83b3SThierry Reding status = "disabled"; 15540cc83b3SThierry Reding }; 15640cc83b3SThierry Reding 15740cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 15840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15940cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 16040cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 16140cc83b3SThierry Reding #address-cells = <1>; 16240cc83b3SThierry Reding #size-cells = <0>; 163c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 16440cc83b3SThierry Reding clock-names = "div-clk"; 16540cc83b3SThierry Reding resets = <&bpmp 81>; 16640cc83b3SThierry Reding reset-names = "i2c"; 16740cc83b3SThierry Reding status = "disabled"; 16840cc83b3SThierry Reding }; 16940cc83b3SThierry Reding 17040cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 17140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 17240cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 17340cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 17440cc83b3SThierry Reding #address-cells = <1>; 17540cc83b3SThierry Reding #size-cells = <0>; 176c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 17740cc83b3SThierry Reding clock-names = "div-clk"; 17840cc83b3SThierry Reding resets = <&bpmp 83>; 17940cc83b3SThierry Reding reset-names = "i2c"; 18040cc83b3SThierry Reding status = "disabled"; 18140cc83b3SThierry Reding }; 18240cc83b3SThierry Reding 18399425dfdSThierry Reding sdmmc1: sdhci@3400000 { 18499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 18599425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 18699425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 187c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 18899425dfdSThierry Reding clock-names = "sdhci"; 18999425dfdSThierry Reding resets = <&bpmp 33>; 19099425dfdSThierry Reding reset-names = "sdhci"; 19199425dfdSThierry Reding status = "disabled"; 19299425dfdSThierry Reding }; 19399425dfdSThierry Reding 19499425dfdSThierry Reding sdmmc2: sdhci@3420000 { 19599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 19699425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 19799425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 198c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 19999425dfdSThierry Reding clock-names = "sdhci"; 20099425dfdSThierry Reding resets = <&bpmp 34>; 20199425dfdSThierry Reding reset-names = "sdhci"; 20299425dfdSThierry Reding status = "disabled"; 20399425dfdSThierry Reding }; 20499425dfdSThierry Reding 20599425dfdSThierry Reding sdmmc3: sdhci@3440000 { 20699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 20799425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 20899425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 209c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 21099425dfdSThierry Reding clock-names = "sdhci"; 21199425dfdSThierry Reding resets = <&bpmp 35>; 21299425dfdSThierry Reding reset-names = "sdhci"; 21399425dfdSThierry Reding status = "disabled"; 21499425dfdSThierry Reding }; 21599425dfdSThierry Reding 21699425dfdSThierry Reding sdmmc4: sdhci@3460000 { 21799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 21899425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 21999425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 220c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 22199425dfdSThierry Reding clock-names = "sdhci"; 22299425dfdSThierry Reding resets = <&bpmp 36>; 22399425dfdSThierry Reding reset-names = "sdhci"; 22499425dfdSThierry Reding status = "disabled"; 22599425dfdSThierry Reding }; 22699425dfdSThierry Reding 22739cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 22839cb62cbSJoseph Lo compatible = "arm,gic-400"; 22939cb62cbSJoseph Lo #interrupt-cells = <3>; 23039cb62cbSJoseph Lo interrupt-controller; 23139cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 23239cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 23339cb62cbSJoseph Lo interrupts = <GIC_PPI 9 23439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 23539cb62cbSJoseph Lo interrupt-parent = <&gic>; 23639cb62cbSJoseph Lo }; 23739cb62cbSJoseph Lo 23839cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 23939cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 24039cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 24139cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 24239cb62cbSJoseph Lo interrupt-names = "doorbell"; 24339cb62cbSJoseph Lo #mbox-cells = <2>; 24439cb62cbSJoseph Lo status = "disabled"; 24539cb62cbSJoseph Lo }; 24639cb62cbSJoseph Lo 24740cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 24840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 24940cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 25040cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 25140cc83b3SThierry Reding #address-cells = <1>; 25240cc83b3SThierry Reding #size-cells = <0>; 253c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 25440cc83b3SThierry Reding clock-names = "div-clk"; 25540cc83b3SThierry Reding resets = <&bpmp 20>; 25640cc83b3SThierry Reding reset-names = "i2c"; 25740cc83b3SThierry Reding status = "disabled"; 25840cc83b3SThierry Reding }; 25940cc83b3SThierry Reding 26040cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 26140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 26240cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 26340cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 26440cc83b3SThierry Reding #address-cells = <1>; 26540cc83b3SThierry Reding #size-cells = <0>; 266c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 26740cc83b3SThierry Reding clock-names = "div-clk"; 26840cc83b3SThierry Reding resets = <&bpmp 82>; 26940cc83b3SThierry Reding reset-names = "i2c"; 27040cc83b3SThierry Reding status = "disabled"; 27140cc83b3SThierry Reding }; 27240cc83b3SThierry Reding 273a7a77e2eSThierry Reding uartc: serial@c280000 { 274a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 275a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 276a7a77e2eSThierry Reding reg-shift = <2>; 277a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 278c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 279a7a77e2eSThierry Reding clock-names = "serial"; 280a7a77e2eSThierry Reding resets = <&bpmp 49>; 281a7a77e2eSThierry Reding reset-names = "serial"; 282a7a77e2eSThierry Reding status = "disabled"; 283a7a77e2eSThierry Reding }; 284a7a77e2eSThierry Reding 285a7a77e2eSThierry Reding uartg: serial@c290000 { 286a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 287a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 288a7a77e2eSThierry Reding reg-shift = <2>; 289a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 290c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 291a7a77e2eSThierry Reding clock-names = "serial"; 292a7a77e2eSThierry Reding resets = <&bpmp 112>; 293a7a77e2eSThierry Reding reset-names = "serial"; 294a7a77e2eSThierry Reding status = "disabled"; 295a7a77e2eSThierry Reding }; 296a7a77e2eSThierry Reding 297fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 298fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 299fc4bb754SThierry Reding reg-names = "security", "gpio"; 300fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 301fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 302fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 303fc4bb754SThierry Reding gpio-controller; 304fc4bb754SThierry Reding #gpio-cells = <2>; 305fc4bb754SThierry Reding interrupt-controller; 306fc4bb754SThierry Reding #interrupt-cells = <2>; 307fc4bb754SThierry Reding }; 308fc4bb754SThierry Reding 30939cb62cbSJoseph Lo sysram@30000000 { 31039cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 31139cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 31239cb62cbSJoseph Lo #address-cells = <2>; 31339cb62cbSJoseph Lo #size-cells = <2>; 31439cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 31539cb62cbSJoseph Lo 31639cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 31739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 31839cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 31939cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 32039cb62cbSJoseph Lo pool; 32139cb62cbSJoseph Lo }; 32239cb62cbSJoseph Lo 32339cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 32439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 32539cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 32639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 32739cb62cbSJoseph Lo pool; 32839cb62cbSJoseph Lo }; 32939cb62cbSJoseph Lo }; 33039cb62cbSJoseph Lo 331cd6fe32eSThierry Reding cpus { 332cd6fe32eSThierry Reding #address-cells = <1>; 333cd6fe32eSThierry Reding #size-cells = <0>; 334cd6fe32eSThierry Reding 335cd6fe32eSThierry Reding cpu@0 { 336cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 337cd6fe32eSThierry Reding device_type = "cpu"; 338cd6fe32eSThierry Reding reg = <0x000>; 339cd6fe32eSThierry Reding }; 340cd6fe32eSThierry Reding 341cd6fe32eSThierry Reding cpu@1 { 342cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 343cd6fe32eSThierry Reding device_type = "cpu"; 344cd6fe32eSThierry Reding reg = <0x001>; 345cd6fe32eSThierry Reding }; 346cd6fe32eSThierry Reding 347cd6fe32eSThierry Reding cpu@2 { 348cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 349cd6fe32eSThierry Reding device_type = "cpu"; 350cd6fe32eSThierry Reding reg = <0x100>; 351cd6fe32eSThierry Reding }; 352cd6fe32eSThierry Reding 353cd6fe32eSThierry Reding cpu@3 { 354cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 355cd6fe32eSThierry Reding device_type = "cpu"; 356cd6fe32eSThierry Reding reg = <0x101>; 357cd6fe32eSThierry Reding }; 358cd6fe32eSThierry Reding 359cd6fe32eSThierry Reding cpu@4 { 360cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 361cd6fe32eSThierry Reding device_type = "cpu"; 362cd6fe32eSThierry Reding reg = <0x102>; 363cd6fe32eSThierry Reding }; 364cd6fe32eSThierry Reding 365cd6fe32eSThierry Reding cpu@5 { 366cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 367cd6fe32eSThierry Reding device_type = "cpu"; 368cd6fe32eSThierry Reding reg = <0x103>; 369cd6fe32eSThierry Reding }; 370cd6fe32eSThierry Reding }; 371cd6fe32eSThierry Reding 37239cb62cbSJoseph Lo bpmp: bpmp { 37339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 3745edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 3755edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 37639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 37739cb62cbSJoseph Lo #clock-cells = <1>; 37839cb62cbSJoseph Lo #reset-cells = <1>; 37939cb62cbSJoseph Lo 38039cb62cbSJoseph Lo bpmp_i2c: i2c { 38139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 38239cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 38339cb62cbSJoseph Lo #address-cells = <1>; 38439cb62cbSJoseph Lo #size-cells = <0>; 38539cb62cbSJoseph Lo status = "disabled"; 38639cb62cbSJoseph Lo }; 38739cb62cbSJoseph Lo }; 38839cb62cbSJoseph Lo 38939cb62cbSJoseph Lo timer { 39039cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 39139cb62cbSJoseph Lo interrupts = <GIC_PPI 13 39239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39339cb62cbSJoseph Lo <GIC_PPI 14 39439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39539cb62cbSJoseph Lo <GIC_PPI 11 39639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 39739cb62cbSJoseph Lo <GIC_PPI 10 39839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 39939cb62cbSJoseph Lo interrupt-parent = <&gic>; 40039cb62cbSJoseph Lo }; 40139cb62cbSJoseph Lo}; 402