1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 7dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 87bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 915274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1039cb62cbSJoseph Lo 1139cb62cbSJoseph Lo/ { 1239cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1339cb62cbSJoseph Lo interrupt-parent = <&gic>; 1439cb62cbSJoseph Lo #address-cells = <2>; 1539cb62cbSJoseph Lo #size-cells = <2>; 1639cb62cbSJoseph Lo 1794e25dc3SThierry Reding misc@100000 { 1894e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 1994e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2094e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2194e25dc3SThierry Reding }; 2294e25dc3SThierry Reding 23fc4bb754SThierry Reding gpio: gpio@2200000 { 24fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 25fc4bb754SThierry Reding reg-names = "security", "gpio"; 26fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 27fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 28fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 29fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 34fc4bb754SThierry Reding #interrupt-cells = <2>; 35fc4bb754SThierry Reding interrupt-controller; 36fc4bb754SThierry Reding #gpio-cells = <2>; 37fc4bb754SThierry Reding gpio-controller; 38fc4bb754SThierry Reding }; 39fc4bb754SThierry Reding 400caafbdeSThierry Reding ethernet@2490000 { 410caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 420caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 430caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 440caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 450caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 460caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 470caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 480caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 490caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 500caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 510caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 520caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 530caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 540caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 550caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 590caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 600caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 610caafbdeSThierry Reding reset-names = "eqos"; 620caafbdeSThierry Reding status = "disabled"; 630caafbdeSThierry Reding 640caafbdeSThierry Reding snps,write-requests = <1>; 650caafbdeSThierry Reding snps,read-requests = <3>; 660caafbdeSThierry Reding snps,burst-map = <0x7>; 670caafbdeSThierry Reding snps,txpbl = <32>; 680caafbdeSThierry Reding snps,rxpbl = <8>; 690caafbdeSThierry Reding }; 700caafbdeSThierry Reding 71d25a3bf1SThierry Reding memory-controller@2c00000 { 72d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 73d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 74d25a3bf1SThierry Reding status = "disabled"; 75d25a3bf1SThierry Reding }; 76d25a3bf1SThierry Reding 7739cb62cbSJoseph Lo uarta: serial@3100000 { 7839cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 7939cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8039cb62cbSJoseph Lo reg-shift = <2>; 8139cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 82c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 83a7a77e2eSThierry Reding clock-names = "serial"; 847bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 85a7a77e2eSThierry Reding reset-names = "serial"; 86a7a77e2eSThierry Reding status = "disabled"; 87a7a77e2eSThierry Reding }; 88a7a77e2eSThierry Reding 89a7a77e2eSThierry Reding uartb: serial@3110000 { 90a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 91a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 92a7a77e2eSThierry Reding reg-shift = <2>; 93a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 94c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 95a7a77e2eSThierry Reding clock-names = "serial"; 967bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 97a7a77e2eSThierry Reding reset-names = "serial"; 98a7a77e2eSThierry Reding status = "disabled"; 99a7a77e2eSThierry Reding }; 100a7a77e2eSThierry Reding 101a7a77e2eSThierry Reding uartd: serial@3130000 { 102a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 103a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 104a7a77e2eSThierry Reding reg-shift = <2>; 105a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 106c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 107a7a77e2eSThierry Reding clock-names = "serial"; 1087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 109a7a77e2eSThierry Reding reset-names = "serial"; 110a7a77e2eSThierry Reding status = "disabled"; 111a7a77e2eSThierry Reding }; 112a7a77e2eSThierry Reding 113a7a77e2eSThierry Reding uarte: serial@3140000 { 114a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 115a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 116a7a77e2eSThierry Reding reg-shift = <2>; 117a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 118c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 119a7a77e2eSThierry Reding clock-names = "serial"; 1207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 121a7a77e2eSThierry Reding reset-names = "serial"; 122a7a77e2eSThierry Reding status = "disabled"; 123a7a77e2eSThierry Reding }; 124a7a77e2eSThierry Reding 125a7a77e2eSThierry Reding uartf: serial@3150000 { 126a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 127a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 128a7a77e2eSThierry Reding reg-shift = <2>; 129a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 130c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 131a7a77e2eSThierry Reding clock-names = "serial"; 1327bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 133a7a77e2eSThierry Reding reset-names = "serial"; 13439cb62cbSJoseph Lo status = "disabled"; 13539cb62cbSJoseph Lo }; 13639cb62cbSJoseph Lo 13740cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13940cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14040cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14140cc83b3SThierry Reding #address-cells = <1>; 14240cc83b3SThierry Reding #size-cells = <0>; 143c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14440cc83b3SThierry Reding clock-names = "div-clk"; 1457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14640cc83b3SThierry Reding reset-names = "i2c"; 14740cc83b3SThierry Reding status = "disabled"; 14840cc83b3SThierry Reding }; 14940cc83b3SThierry Reding 15040cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15240cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15340cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15440cc83b3SThierry Reding #address-cells = <1>; 15540cc83b3SThierry Reding #size-cells = <0>; 156c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15740cc83b3SThierry Reding clock-names = "div-clk"; 1587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 15940cc83b3SThierry Reding reset-names = "i2c"; 16040cc83b3SThierry Reding status = "disabled"; 16140cc83b3SThierry Reding }; 16240cc83b3SThierry Reding 16340cc83b3SThierry Reding /* shares pads with dpaux1 */ 16440cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16640cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16740cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16840cc83b3SThierry Reding #address-cells = <1>; 16940cc83b3SThierry Reding #size-cells = <0>; 170c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17140cc83b3SThierry Reding clock-names = "div-clk"; 1727bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17340cc83b3SThierry Reding reset-names = "i2c"; 17440cc83b3SThierry Reding status = "disabled"; 17540cc83b3SThierry Reding }; 17640cc83b3SThierry Reding 17740cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17840cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 17940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18040cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18140cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18240cc83b3SThierry Reding #address-cells = <1>; 18340cc83b3SThierry Reding #size-cells = <0>; 184c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18540cc83b3SThierry Reding clock-names = "div-clk"; 1867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18740cc83b3SThierry Reding reset-names = "i2c"; 18840cc83b3SThierry Reding status = "disabled"; 18940cc83b3SThierry Reding }; 19040cc83b3SThierry Reding 19140cc83b3SThierry Reding /* shares pads with dpaux0 */ 19240cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19440cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19540cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19640cc83b3SThierry Reding #address-cells = <1>; 19740cc83b3SThierry Reding #size-cells = <0>; 198c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 19940cc83b3SThierry Reding clock-names = "div-clk"; 2007bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20140cc83b3SThierry Reding reset-names = "i2c"; 20240cc83b3SThierry Reding status = "disabled"; 20340cc83b3SThierry Reding }; 20440cc83b3SThierry Reding 20540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 20940cc83b3SThierry Reding #address-cells = <1>; 21040cc83b3SThierry Reding #size-cells = <0>; 211c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21240cc83b3SThierry Reding clock-names = "div-clk"; 2137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21440cc83b3SThierry Reding reset-names = "i2c"; 21540cc83b3SThierry Reding status = "disabled"; 21640cc83b3SThierry Reding }; 21740cc83b3SThierry Reding 21840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 21940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22240cc83b3SThierry Reding #address-cells = <1>; 22340cc83b3SThierry Reding #size-cells = <0>; 224c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22540cc83b3SThierry Reding clock-names = "div-clk"; 2267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22740cc83b3SThierry Reding reset-names = "i2c"; 22840cc83b3SThierry Reding status = "disabled"; 22940cc83b3SThierry Reding }; 23040cc83b3SThierry Reding 23199425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23399425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23499425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 235c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23699425dfdSThierry Reding clock-names = "sdhci"; 2377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23899425dfdSThierry Reding reset-names = "sdhci"; 23999425dfdSThierry Reding status = "disabled"; 24099425dfdSThierry Reding }; 24199425dfdSThierry Reding 24299425dfdSThierry Reding sdmmc2: sdhci@3420000 { 24399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24499425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 24599425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 246c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 24799425dfdSThierry Reding clock-names = "sdhci"; 2487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 24999425dfdSThierry Reding reset-names = "sdhci"; 25099425dfdSThierry Reding status = "disabled"; 25199425dfdSThierry Reding }; 25299425dfdSThierry Reding 25399425dfdSThierry Reding sdmmc3: sdhci@3440000 { 25499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 25699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 257c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 25899425dfdSThierry Reding clock-names = "sdhci"; 2597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 26099425dfdSThierry Reding reset-names = "sdhci"; 26199425dfdSThierry Reding status = "disabled"; 26299425dfdSThierry Reding }; 26399425dfdSThierry Reding 26499425dfdSThierry Reding sdmmc4: sdhci@3460000 { 26599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 26699425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 26799425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 268c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 26999425dfdSThierry Reding clock-names = "sdhci"; 2707bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 27199425dfdSThierry Reding reset-names = "sdhci"; 27299425dfdSThierry Reding status = "disabled"; 27399425dfdSThierry Reding }; 27499425dfdSThierry Reding 27585593b75SThierry Reding fuse@3820000 { 27685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 27785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 27885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 27985593b75SThierry Reding clock-names = "fuse"; 28085593b75SThierry Reding }; 28185593b75SThierry Reding 28239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 28339cb62cbSJoseph Lo compatible = "arm,gic-400"; 28439cb62cbSJoseph Lo #interrupt-cells = <3>; 28539cb62cbSJoseph Lo interrupt-controller; 28639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 28739cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 28839cb62cbSJoseph Lo interrupts = <GIC_PPI 9 28939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 29039cb62cbSJoseph Lo interrupt-parent = <&gic>; 29139cb62cbSJoseph Lo }; 29239cb62cbSJoseph Lo 29339cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 29439cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 29539cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 29639cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 29739cb62cbSJoseph Lo interrupt-names = "doorbell"; 29839cb62cbSJoseph Lo #mbox-cells = <2>; 29939cb62cbSJoseph Lo status = "disabled"; 30039cb62cbSJoseph Lo }; 30139cb62cbSJoseph Lo 30240cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 30340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 30440cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 30540cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 30640cc83b3SThierry Reding #address-cells = <1>; 30740cc83b3SThierry Reding #size-cells = <0>; 308c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 30940cc83b3SThierry Reding clock-names = "div-clk"; 3107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 31140cc83b3SThierry Reding reset-names = "i2c"; 31240cc83b3SThierry Reding status = "disabled"; 31340cc83b3SThierry Reding }; 31440cc83b3SThierry Reding 31540cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 31640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 31740cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 31840cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 31940cc83b3SThierry Reding #address-cells = <1>; 32040cc83b3SThierry Reding #size-cells = <0>; 321c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 32240cc83b3SThierry Reding clock-names = "div-clk"; 3237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 32440cc83b3SThierry Reding reset-names = "i2c"; 32540cc83b3SThierry Reding status = "disabled"; 32640cc83b3SThierry Reding }; 32740cc83b3SThierry Reding 328a7a77e2eSThierry Reding uartc: serial@c280000 { 329a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 330a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 331a7a77e2eSThierry Reding reg-shift = <2>; 332a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 333c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 334a7a77e2eSThierry Reding clock-names = "serial"; 3357bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 336a7a77e2eSThierry Reding reset-names = "serial"; 337a7a77e2eSThierry Reding status = "disabled"; 338a7a77e2eSThierry Reding }; 339a7a77e2eSThierry Reding 340a7a77e2eSThierry Reding uartg: serial@c290000 { 341a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 342a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 343a7a77e2eSThierry Reding reg-shift = <2>; 344a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 345c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 346a7a77e2eSThierry Reding clock-names = "serial"; 3477bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 348a7a77e2eSThierry Reding reset-names = "serial"; 349a7a77e2eSThierry Reding status = "disabled"; 350a7a77e2eSThierry Reding }; 351a7a77e2eSThierry Reding 352fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 353fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 354fc4bb754SThierry Reding reg-names = "security", "gpio"; 355fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 356fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 357fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 358fc4bb754SThierry Reding gpio-controller; 359fc4bb754SThierry Reding #gpio-cells = <2>; 360fc4bb754SThierry Reding interrupt-controller; 361fc4bb754SThierry Reding #interrupt-cells = <2>; 362fc4bb754SThierry Reding }; 363fc4bb754SThierry Reding 36473bf90d4SThierry Reding pmc@c360000 { 36573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 36673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 36773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 36873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 36973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 37073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 37173bf90d4SThierry Reding }; 37273bf90d4SThierry Reding 3737b7ef494SMikko Perttunen ccplex@e000000 { 3747b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 3757b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 3767b7ef494SMikko Perttunen 3777b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 3787b7ef494SMikko Perttunen }; 3797b7ef494SMikko Perttunen 380f8973cf4SManikanta Maddireddy pcie@10003000 { 381f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 382f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 383f8973cf4SManikanta Maddireddy device_type = "pci"; 384f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 385f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 386f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 387f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 388f8973cf4SManikanta Maddireddy 389f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 390f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 391f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 392f8973cf4SManikanta Maddireddy 393f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 394f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 395f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 396f8973cf4SManikanta Maddireddy 397f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 398f8973cf4SManikanta Maddireddy #address-cells = <3>; 399f8973cf4SManikanta Maddireddy #size-cells = <2>; 400f8973cf4SManikanta Maddireddy 401f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 402f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 403f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 404f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 405f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 406f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 407f8973cf4SManikanta Maddireddy 408f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 409f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 410f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 411f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 412f8973cf4SManikanta Maddireddy 413f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 414f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 415f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 416f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 417f8973cf4SManikanta Maddireddy 418f8973cf4SManikanta Maddireddy status = "disabled"; 419f8973cf4SManikanta Maddireddy 420f8973cf4SManikanta Maddireddy pci@1,0 { 421f8973cf4SManikanta Maddireddy device_type = "pci"; 422f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 423f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 424f8973cf4SManikanta Maddireddy status = "disabled"; 425f8973cf4SManikanta Maddireddy 426f8973cf4SManikanta Maddireddy #address-cells = <3>; 427f8973cf4SManikanta Maddireddy #size-cells = <2>; 428f8973cf4SManikanta Maddireddy ranges; 429f8973cf4SManikanta Maddireddy 430f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 431f8973cf4SManikanta Maddireddy }; 432f8973cf4SManikanta Maddireddy 433f8973cf4SManikanta Maddireddy pci@2,0 { 434f8973cf4SManikanta Maddireddy device_type = "pci"; 435f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 436f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 437f8973cf4SManikanta Maddireddy status = "disabled"; 438f8973cf4SManikanta Maddireddy 439f8973cf4SManikanta Maddireddy #address-cells = <3>; 440f8973cf4SManikanta Maddireddy #size-cells = <2>; 441f8973cf4SManikanta Maddireddy ranges; 442f8973cf4SManikanta Maddireddy 443f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 444f8973cf4SManikanta Maddireddy }; 445f8973cf4SManikanta Maddireddy 446f8973cf4SManikanta Maddireddy pci@3,0 { 447f8973cf4SManikanta Maddireddy device_type = "pci"; 448f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 449f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 450f8973cf4SManikanta Maddireddy status = "disabled"; 451f8973cf4SManikanta Maddireddy 452f8973cf4SManikanta Maddireddy #address-cells = <3>; 453f8973cf4SManikanta Maddireddy #size-cells = <2>; 454f8973cf4SManikanta Maddireddy ranges; 455f8973cf4SManikanta Maddireddy 456f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 457f8973cf4SManikanta Maddireddy }; 458f8973cf4SManikanta Maddireddy }; 459f8973cf4SManikanta Maddireddy 460b30a8e61SThierry Reding smmu: iommu@12000000 { 461b30a8e61SThierry Reding compatible = "arm,mmu-500"; 462b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 463b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 464b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 465b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 466b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 467b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 468b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 469b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 470b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 471b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 472b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 473b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 474b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 475b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 476b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 477b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 478b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 479b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 480b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 481b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 482b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 483b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 484b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 485b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 486b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 487b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 488b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 489b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 490b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 491b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 492b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 493b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 494b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 495b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 496b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 497b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 498b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 499b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 500b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 501b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 502b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 503b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 504b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 505b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 506b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 507b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 508b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 509b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 510b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 511b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 512b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 513b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 514b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 515b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 516b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 517b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 518b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 519b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 520b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 521b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 522b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 523b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 528b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 529b30a8e61SThierry Reding #global-interrupts = <1>; 530b30a8e61SThierry Reding #iommu-cells = <1>; 531b30a8e61SThierry Reding }; 532b30a8e61SThierry Reding 5335524c61fSMikko Perttunen host1x@13e00000 { 5345524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 5355524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 5365524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 5375524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 5385524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 5395524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5405524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 5415524c61fSMikko Perttunen clock-names = "host1x"; 5425524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 5435524c61fSMikko Perttunen reset-names = "host1x"; 5445524c61fSMikko Perttunen 5455524c61fSMikko Perttunen #address-cells = <1>; 5465524c61fSMikko Perttunen #size-cells = <1>; 5475524c61fSMikko Perttunen 5485524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 549c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 550c2599da7SThierry Reding 551c2599da7SThierry Reding dpaux1: dpaux@15040000 { 552c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 553c2599da7SThierry Reding reg = <0x15040000 0x10000>; 554c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 555c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 556c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 557c2599da7SThierry Reding clock-names = "dpaux", "parent"; 558c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 559c2599da7SThierry Reding reset-names = "dpaux"; 560c2599da7SThierry Reding status = "disabled"; 561c2599da7SThierry Reding 562c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 563c2599da7SThierry Reding 564c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 565c2599da7SThierry Reding groups = "dpaux-io"; 566c2599da7SThierry Reding function = "aux"; 567c2599da7SThierry Reding }; 568c2599da7SThierry Reding 569c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 570c2599da7SThierry Reding groups = "dpaux-io"; 571c2599da7SThierry Reding function = "i2c"; 572c2599da7SThierry Reding }; 573c2599da7SThierry Reding 574c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 575c2599da7SThierry Reding groups = "dpaux-io"; 576c2599da7SThierry Reding function = "off"; 577c2599da7SThierry Reding }; 578c2599da7SThierry Reding 579c2599da7SThierry Reding i2c-bus { 580c2599da7SThierry Reding #address-cells = <1>; 581c2599da7SThierry Reding #size-cells = <0>; 582c2599da7SThierry Reding }; 583c2599da7SThierry Reding }; 584c2599da7SThierry Reding 585c2599da7SThierry Reding display-hub@15200000 { 586c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 587c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 588c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 589c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 590c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 591c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 592c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 593c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 594c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 595c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 596c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 597c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 598c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 599c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 600c2599da7SThierry Reding status = "disabled"; 601c2599da7SThierry Reding 602c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 603c2599da7SThierry Reding 604c2599da7SThierry Reding #address-cells = <1>; 605c2599da7SThierry Reding #size-cells = <1>; 606c2599da7SThierry Reding 607c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 608c2599da7SThierry Reding 609c2599da7SThierry Reding display@15200000 { 610c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 611c2599da7SThierry Reding reg = <0x15200000 0x10000>; 612c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 613c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 614c2599da7SThierry Reding clock-names = "dc"; 615c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 616c2599da7SThierry Reding reset-names = "dc"; 617c2599da7SThierry Reding 618c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 619c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 620c2599da7SThierry Reding 621c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 622c2599da7SThierry Reding nvidia,head = <0>; 623c2599da7SThierry Reding }; 624c2599da7SThierry Reding 625c2599da7SThierry Reding display@15210000 { 626c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 627c2599da7SThierry Reding reg = <0x15210000 0x10000>; 628c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 629c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 630c2599da7SThierry Reding clock-names = "dc"; 631c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 632c2599da7SThierry Reding reset-names = "dc"; 633c2599da7SThierry Reding 634c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 635c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 636c2599da7SThierry Reding 637c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 638c2599da7SThierry Reding nvidia,head = <1>; 639c2599da7SThierry Reding }; 640c2599da7SThierry Reding 641c2599da7SThierry Reding display@15220000 { 642c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 643c2599da7SThierry Reding reg = <0x15220000 0x10000>; 644c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 645c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 646c2599da7SThierry Reding clock-names = "dc"; 647c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 648c2599da7SThierry Reding reset-names = "dc"; 649c2599da7SThierry Reding 650c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 651c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 652c2599da7SThierry Reding 653c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 654c2599da7SThierry Reding nvidia,head = <2>; 655c2599da7SThierry Reding }; 656c2599da7SThierry Reding }; 657c2599da7SThierry Reding 658c2599da7SThierry Reding dsia: dsi@15300000 { 659c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 660c2599da7SThierry Reding reg = <0x15300000 0x10000>; 661c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 662c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 663c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 664c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 665c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 666c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 667c2599da7SThierry Reding reset-names = "dsi"; 668c2599da7SThierry Reding status = "disabled"; 669c2599da7SThierry Reding 670c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 671c2599da7SThierry Reding }; 672effc4b44SMikko Perttunen 673effc4b44SMikko Perttunen vic@15340000 { 674effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 675effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 676effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 677effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 678effc4b44SMikko Perttunen clock-names = "vic"; 679effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 680effc4b44SMikko Perttunen reset-names = "vic"; 681effc4b44SMikko Perttunen 682effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 683effc4b44SMikko Perttunen }; 684c2599da7SThierry Reding 685c2599da7SThierry Reding dsib: dsi@15400000 { 686c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 687c2599da7SThierry Reding reg = <0x15400000 0x10000>; 688c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 689c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 690c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 691c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 692c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 693c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 694c2599da7SThierry Reding reset-names = "dsi"; 695c2599da7SThierry Reding status = "disabled"; 696c2599da7SThierry Reding 697c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 698c2599da7SThierry Reding }; 699c2599da7SThierry Reding 700c2599da7SThierry Reding sor0: sor@15540000 { 701c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 702c2599da7SThierry Reding reg = <0x15540000 0x10000>; 703c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 704c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 705c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 706c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 707c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 708c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 709c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 710c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 711c2599da7SThierry Reding "pad"; 712c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 713c2599da7SThierry Reding reset-names = "sor"; 714c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 715c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 716c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 717c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 718c2599da7SThierry Reding status = "disabled"; 719c2599da7SThierry Reding 720c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 721c2599da7SThierry Reding nvidia,interface = <0>; 722c2599da7SThierry Reding }; 723c2599da7SThierry Reding 724c2599da7SThierry Reding sor1: sor@15580000 { 725c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 726c2599da7SThierry Reding reg = <0x15580000 0x10000>; 727c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 728c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 729c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 730c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 731c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 732c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 733c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 734c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 735c2599da7SThierry Reding "pad"; 736c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 737c2599da7SThierry Reding reset-names = "sor"; 738c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 739c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 740c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 741c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 742c2599da7SThierry Reding status = "disabled"; 743c2599da7SThierry Reding 744c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 745c2599da7SThierry Reding nvidia,interface = <1>; 746c2599da7SThierry Reding }; 747c2599da7SThierry Reding 748c2599da7SThierry Reding dpaux: dpaux@155c0000 { 749c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 750c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 751c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 752c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 753c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 754c2599da7SThierry Reding clock-names = "dpaux", "parent"; 755c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 756c2599da7SThierry Reding reset-names = "dpaux"; 757c2599da7SThierry Reding status = "disabled"; 758c2599da7SThierry Reding 759c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 760c2599da7SThierry Reding 761c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 762c2599da7SThierry Reding groups = "dpaux-io"; 763c2599da7SThierry Reding function = "aux"; 764c2599da7SThierry Reding }; 765c2599da7SThierry Reding 766c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 767c2599da7SThierry Reding groups = "dpaux-io"; 768c2599da7SThierry Reding function = "i2c"; 769c2599da7SThierry Reding }; 770c2599da7SThierry Reding 771c2599da7SThierry Reding state_dpaux_off: pinmux-off { 772c2599da7SThierry Reding groups = "dpaux-io"; 773c2599da7SThierry Reding function = "off"; 774c2599da7SThierry Reding }; 775c2599da7SThierry Reding 776c2599da7SThierry Reding i2c-bus { 777c2599da7SThierry Reding #address-cells = <1>; 778c2599da7SThierry Reding #size-cells = <0>; 779c2599da7SThierry Reding }; 780c2599da7SThierry Reding }; 781c2599da7SThierry Reding 782c2599da7SThierry Reding padctl@15880000 { 783c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 784c2599da7SThierry Reding reg = <0x15880000 0x10000>; 785c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 786c2599da7SThierry Reding reset-names = "dsi"; 787c2599da7SThierry Reding status = "disabled"; 788c2599da7SThierry Reding }; 789c2599da7SThierry Reding 790c2599da7SThierry Reding dsic: dsi@15900000 { 791c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 792c2599da7SThierry Reding reg = <0x15900000 0x10000>; 793c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 794c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 795c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 796c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 797c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 798c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 799c2599da7SThierry Reding reset-names = "dsi"; 800c2599da7SThierry Reding status = "disabled"; 801c2599da7SThierry Reding 802c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 803c2599da7SThierry Reding }; 804c2599da7SThierry Reding 805c2599da7SThierry Reding dsid: dsi@15940000 { 806c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 807c2599da7SThierry Reding reg = <0x15940000 0x10000>; 808c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 809c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 810c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 811c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 812c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 813c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 814c2599da7SThierry Reding reset-names = "dsi"; 815c2599da7SThierry Reding status = "disabled"; 816c2599da7SThierry Reding 817c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 818c2599da7SThierry Reding }; 8195524c61fSMikko Perttunen }; 8205524c61fSMikko Perttunen 821dfd7a384SAlexandre Courbot gpu@17000000 { 822dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 823dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 824dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 825dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 826dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 827dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 828dfd7a384SAlexandre Courbot 829dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 830dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 831dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 832dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 833dfd7a384SAlexandre Courbot reset-names = "gpu"; 834dfd7a384SAlexandre Courbot status = "disabled"; 835dfd7a384SAlexandre Courbot 836dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 837dfd7a384SAlexandre Courbot }; 838dfd7a384SAlexandre Courbot 83939cb62cbSJoseph Lo sysram@30000000 { 84039cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 84139cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 84239cb62cbSJoseph Lo #address-cells = <2>; 84339cb62cbSJoseph Lo #size-cells = <2>; 84439cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 84539cb62cbSJoseph Lo 84639cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 84739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 84839cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 84939cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 85039cb62cbSJoseph Lo pool; 85139cb62cbSJoseph Lo }; 85239cb62cbSJoseph Lo 85339cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 85439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 85539cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 85639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 85739cb62cbSJoseph Lo pool; 85839cb62cbSJoseph Lo }; 85939cb62cbSJoseph Lo }; 86039cb62cbSJoseph Lo 861cd6fe32eSThierry Reding cpus { 862cd6fe32eSThierry Reding #address-cells = <1>; 863cd6fe32eSThierry Reding #size-cells = <0>; 864cd6fe32eSThierry Reding 865cd6fe32eSThierry Reding cpu@0 { 866cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 867cd6fe32eSThierry Reding device_type = "cpu"; 868cd6fe32eSThierry Reding reg = <0x000>; 869cd6fe32eSThierry Reding }; 870cd6fe32eSThierry Reding 871cd6fe32eSThierry Reding cpu@1 { 872cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 873cd6fe32eSThierry Reding device_type = "cpu"; 874cd6fe32eSThierry Reding reg = <0x001>; 875cd6fe32eSThierry Reding }; 876cd6fe32eSThierry Reding 877cd6fe32eSThierry Reding cpu@2 { 878cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 879cd6fe32eSThierry Reding device_type = "cpu"; 880cd6fe32eSThierry Reding reg = <0x100>; 881cd6fe32eSThierry Reding }; 882cd6fe32eSThierry Reding 883cd6fe32eSThierry Reding cpu@3 { 884cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 885cd6fe32eSThierry Reding device_type = "cpu"; 886cd6fe32eSThierry Reding reg = <0x101>; 887cd6fe32eSThierry Reding }; 888cd6fe32eSThierry Reding 889cd6fe32eSThierry Reding cpu@4 { 890cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 891cd6fe32eSThierry Reding device_type = "cpu"; 892cd6fe32eSThierry Reding reg = <0x102>; 893cd6fe32eSThierry Reding }; 894cd6fe32eSThierry Reding 895cd6fe32eSThierry Reding cpu@5 { 896cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 897cd6fe32eSThierry Reding device_type = "cpu"; 898cd6fe32eSThierry Reding reg = <0x103>; 899cd6fe32eSThierry Reding }; 900cd6fe32eSThierry Reding }; 901cd6fe32eSThierry Reding 90239cb62cbSJoseph Lo bpmp: bpmp { 90339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 9045edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 9055edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 90639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 90739cb62cbSJoseph Lo #clock-cells = <1>; 90839cb62cbSJoseph Lo #reset-cells = <1>; 909dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 91039cb62cbSJoseph Lo 91139cb62cbSJoseph Lo bpmp_i2c: i2c { 91239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 91339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 91439cb62cbSJoseph Lo #address-cells = <1>; 91539cb62cbSJoseph Lo #size-cells = <0>; 91639cb62cbSJoseph Lo status = "disabled"; 91739cb62cbSJoseph Lo }; 91815274c23SMikko Perttunen 91915274c23SMikko Perttunen bpmp_thermal: thermal { 92015274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 92115274c23SMikko Perttunen #thermal-sensor-cells = <1>; 92215274c23SMikko Perttunen }; 92315274c23SMikko Perttunen }; 92415274c23SMikko Perttunen 92515274c23SMikko Perttunen thermal-zones { 92615274c23SMikko Perttunen a57 { 92715274c23SMikko Perttunen polling-delay = <0>; 92815274c23SMikko Perttunen polling-delay-passive = <1000>; 92915274c23SMikko Perttunen 93015274c23SMikko Perttunen thermal-sensors = 93115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 93215274c23SMikko Perttunen 93315274c23SMikko Perttunen trips { 93415274c23SMikko Perttunen critical { 93515274c23SMikko Perttunen temperature = <101000>; 93615274c23SMikko Perttunen hysteresis = <0>; 93715274c23SMikko Perttunen type = "critical"; 93815274c23SMikko Perttunen }; 93915274c23SMikko Perttunen }; 94015274c23SMikko Perttunen 94115274c23SMikko Perttunen cooling-maps { 94215274c23SMikko Perttunen }; 94315274c23SMikko Perttunen }; 94415274c23SMikko Perttunen 94515274c23SMikko Perttunen denver { 94615274c23SMikko Perttunen polling-delay = <0>; 94715274c23SMikko Perttunen polling-delay-passive = <1000>; 94815274c23SMikko Perttunen 94915274c23SMikko Perttunen thermal-sensors = 95015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 95115274c23SMikko Perttunen 95215274c23SMikko Perttunen trips { 95315274c23SMikko Perttunen critical { 95415274c23SMikko Perttunen temperature = <101000>; 95515274c23SMikko Perttunen hysteresis = <0>; 95615274c23SMikko Perttunen type = "critical"; 95715274c23SMikko Perttunen }; 95815274c23SMikko Perttunen }; 95915274c23SMikko Perttunen 96015274c23SMikko Perttunen cooling-maps { 96115274c23SMikko Perttunen }; 96215274c23SMikko Perttunen }; 96315274c23SMikko Perttunen 96415274c23SMikko Perttunen gpu { 96515274c23SMikko Perttunen polling-delay = <0>; 96615274c23SMikko Perttunen polling-delay-passive = <1000>; 96715274c23SMikko Perttunen 96815274c23SMikko Perttunen thermal-sensors = 96915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 97015274c23SMikko Perttunen 97115274c23SMikko Perttunen trips { 97215274c23SMikko Perttunen critical { 97315274c23SMikko Perttunen temperature = <101000>; 97415274c23SMikko Perttunen hysteresis = <0>; 97515274c23SMikko Perttunen type = "critical"; 97615274c23SMikko Perttunen }; 97715274c23SMikko Perttunen }; 97815274c23SMikko Perttunen 97915274c23SMikko Perttunen cooling-maps { 98015274c23SMikko Perttunen }; 98115274c23SMikko Perttunen }; 98215274c23SMikko Perttunen 98315274c23SMikko Perttunen pll { 98415274c23SMikko Perttunen polling-delay = <0>; 98515274c23SMikko Perttunen polling-delay-passive = <1000>; 98615274c23SMikko Perttunen 98715274c23SMikko Perttunen thermal-sensors = 98815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 98915274c23SMikko Perttunen 99015274c23SMikko Perttunen trips { 99115274c23SMikko Perttunen critical { 99215274c23SMikko Perttunen temperature = <101000>; 99315274c23SMikko Perttunen hysteresis = <0>; 99415274c23SMikko Perttunen type = "critical"; 99515274c23SMikko Perttunen }; 99615274c23SMikko Perttunen }; 99715274c23SMikko Perttunen 99815274c23SMikko Perttunen cooling-maps { 99915274c23SMikko Perttunen }; 100015274c23SMikko Perttunen }; 100115274c23SMikko Perttunen 100215274c23SMikko Perttunen always_on { 100315274c23SMikko Perttunen polling-delay = <0>; 100415274c23SMikko Perttunen polling-delay-passive = <1000>; 100515274c23SMikko Perttunen 100615274c23SMikko Perttunen thermal-sensors = 100715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 100815274c23SMikko Perttunen 100915274c23SMikko Perttunen trips { 101015274c23SMikko Perttunen critical { 101115274c23SMikko Perttunen temperature = <101000>; 101215274c23SMikko Perttunen hysteresis = <0>; 101315274c23SMikko Perttunen type = "critical"; 101415274c23SMikko Perttunen }; 101515274c23SMikko Perttunen }; 101615274c23SMikko Perttunen 101715274c23SMikko Perttunen cooling-maps { 101815274c23SMikko Perttunen }; 101915274c23SMikko Perttunen }; 102039cb62cbSJoseph Lo }; 102139cb62cbSJoseph Lo 102239cb62cbSJoseph Lo timer { 102339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 102439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 102539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 102639cb62cbSJoseph Lo <GIC_PPI 14 102739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 102839cb62cbSJoseph Lo <GIC_PPI 11 102939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 103039cb62cbSJoseph Lo <GIC_PPI 10 103139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 103239cb62cbSJoseph Lo interrupt-parent = <&gic>; 103339cb62cbSJoseph Lo }; 103439cb62cbSJoseph Lo}; 1035