1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 640caafbdeSThierry Reding status = "disabled"; 650caafbdeSThierry Reding 660caafbdeSThierry Reding snps,write-requests = <1>; 670caafbdeSThierry Reding snps,read-requests = <3>; 680caafbdeSThierry Reding snps,burst-map = <0x7>; 690caafbdeSThierry Reding snps,txpbl = <32>; 700caafbdeSThierry Reding snps,rxpbl = <8>; 710caafbdeSThierry Reding }; 720caafbdeSThierry Reding 735d2249ddSSameer Pujar aconnect { 745d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 755d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 765d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 775d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 785d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 795d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 805d2249ddSSameer Pujar #address-cells = <1>; 815d2249ddSSameer Pujar #size-cells = <1>; 825d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 835d2249ddSSameer Pujar status = "disabled"; 845d2249ddSSameer Pujar 855d2249ddSSameer Pujar dma-controller@2930000 { 865d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 875d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 885d2249ddSSameer Pujar interrupt-parent = <&agic>; 895d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1215d2249ddSSameer Pujar #dma-cells = <1>; 1225d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1235d2249ddSSameer Pujar clock-names = "d_audio"; 1245d2249ddSSameer Pujar status = "disabled"; 1255d2249ddSSameer Pujar }; 1265d2249ddSSameer Pujar 1275d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1285d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1295d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1305d2249ddSSameer Pujar #interrupt-cells = <3>; 1315d2249ddSSameer Pujar interrupt-controller; 1325d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1335d2249ddSSameer Pujar <0x02a42000 0x2000>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1355d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1365d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1375d2249ddSSameer Pujar clock-names = "clk"; 1385d2249ddSSameer Pujar status = "disabled"; 1395d2249ddSSameer Pujar }; 1405d2249ddSSameer Pujar }; 1415d2249ddSSameer Pujar 142d25a3bf1SThierry Reding memory-controller@2c00000 { 143d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 144d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 145b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146d25a3bf1SThierry Reding status = "disabled"; 147d25a3bf1SThierry Reding }; 148d25a3bf1SThierry Reding 14939cb62cbSJoseph Lo uarta: serial@3100000 { 15039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 15139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 15239cb62cbSJoseph Lo reg-shift = <2>; 15339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 154c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 155a7a77e2eSThierry Reding clock-names = "serial"; 1567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 157a7a77e2eSThierry Reding reset-names = "serial"; 158a7a77e2eSThierry Reding status = "disabled"; 159a7a77e2eSThierry Reding }; 160a7a77e2eSThierry Reding 161a7a77e2eSThierry Reding uartb: serial@3110000 { 162a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 163a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 164a7a77e2eSThierry Reding reg-shift = <2>; 165a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 166c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 167a7a77e2eSThierry Reding clock-names = "serial"; 1687bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 169a7a77e2eSThierry Reding reset-names = "serial"; 170a7a77e2eSThierry Reding status = "disabled"; 171a7a77e2eSThierry Reding }; 172a7a77e2eSThierry Reding 173a7a77e2eSThierry Reding uartd: serial@3130000 { 174a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 175a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 176a7a77e2eSThierry Reding reg-shift = <2>; 177a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 178c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 179a7a77e2eSThierry Reding clock-names = "serial"; 1807bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 181a7a77e2eSThierry Reding reset-names = "serial"; 182a7a77e2eSThierry Reding status = "disabled"; 183a7a77e2eSThierry Reding }; 184a7a77e2eSThierry Reding 185a7a77e2eSThierry Reding uarte: serial@3140000 { 186a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 187a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 188a7a77e2eSThierry Reding reg-shift = <2>; 189a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 190c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 191a7a77e2eSThierry Reding clock-names = "serial"; 1927bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 193a7a77e2eSThierry Reding reset-names = "serial"; 194a7a77e2eSThierry Reding status = "disabled"; 195a7a77e2eSThierry Reding }; 196a7a77e2eSThierry Reding 197a7a77e2eSThierry Reding uartf: serial@3150000 { 198a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 199a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 200a7a77e2eSThierry Reding reg-shift = <2>; 201a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 202c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 203a7a77e2eSThierry Reding clock-names = "serial"; 2047bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 205a7a77e2eSThierry Reding reset-names = "serial"; 20639cb62cbSJoseph Lo status = "disabled"; 20739cb62cbSJoseph Lo }; 20839cb62cbSJoseph Lo 20940cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 210250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 21140cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 21240cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 21340cc83b3SThierry Reding #address-cells = <1>; 21440cc83b3SThierry Reding #size-cells = <0>; 215c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 21640cc83b3SThierry Reding clock-names = "div-clk"; 2177bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 21840cc83b3SThierry Reding reset-names = "i2c"; 21940cc83b3SThierry Reding status = "disabled"; 22040cc83b3SThierry Reding }; 22140cc83b3SThierry Reding 22240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 223250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 22440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 22540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 22640cc83b3SThierry Reding #address-cells = <1>; 22740cc83b3SThierry Reding #size-cells = <0>; 228c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 22940cc83b3SThierry Reding clock-names = "div-clk"; 2307bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 23140cc83b3SThierry Reding reset-names = "i2c"; 23240cc83b3SThierry Reding status = "disabled"; 23340cc83b3SThierry Reding }; 23440cc83b3SThierry Reding 23540cc83b3SThierry Reding /* shares pads with dpaux1 */ 23640cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 237250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 23840cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 23940cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 24040cc83b3SThierry Reding #address-cells = <1>; 24140cc83b3SThierry Reding #size-cells = <0>; 242c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 24340cc83b3SThierry Reding clock-names = "div-clk"; 2447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 24540cc83b3SThierry Reding reset-names = "i2c"; 246846137c6SThierry Reding pinctrl-names = "default", "idle"; 247846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 248846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 24940cc83b3SThierry Reding status = "disabled"; 25040cc83b3SThierry Reding }; 25140cc83b3SThierry Reding 25240cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 25340cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 254250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 25540cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 25640cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 25740cc83b3SThierry Reding #address-cells = <1>; 25840cc83b3SThierry Reding #size-cells = <0>; 259c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 26040cc83b3SThierry Reding clock-names = "div-clk"; 2617bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 26240cc83b3SThierry Reding reset-names = "i2c"; 26340cc83b3SThierry Reding status = "disabled"; 26440cc83b3SThierry Reding }; 26540cc83b3SThierry Reding 26640cc83b3SThierry Reding /* shares pads with dpaux0 */ 26740cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 268250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 26940cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 27040cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 27140cc83b3SThierry Reding #address-cells = <1>; 27240cc83b3SThierry Reding #size-cells = <0>; 273c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 27440cc83b3SThierry Reding clock-names = "div-clk"; 2757bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 27640cc83b3SThierry Reding reset-names = "i2c"; 277846137c6SThierry Reding pinctrl-names = "default", "idle"; 278846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 279846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 28040cc83b3SThierry Reding status = "disabled"; 28140cc83b3SThierry Reding }; 28240cc83b3SThierry Reding 28340cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 284250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 28540cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 28640cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 28740cc83b3SThierry Reding #address-cells = <1>; 28840cc83b3SThierry Reding #size-cells = <0>; 289c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 29040cc83b3SThierry Reding clock-names = "div-clk"; 2917bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 29240cc83b3SThierry Reding reset-names = "i2c"; 29340cc83b3SThierry Reding status = "disabled"; 29440cc83b3SThierry Reding }; 29540cc83b3SThierry Reding 29640cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 297250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 29840cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 29940cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 30040cc83b3SThierry Reding #address-cells = <1>; 30140cc83b3SThierry Reding #size-cells = <0>; 302c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 30340cc83b3SThierry Reding clock-names = "div-clk"; 3047bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 30540cc83b3SThierry Reding reset-names = "i2c"; 30640cc83b3SThierry Reding status = "disabled"; 30740cc83b3SThierry Reding }; 30840cc83b3SThierry Reding 30999425dfdSThierry Reding sdmmc1: sdhci@3400000 { 31099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 31199425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 31299425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 313c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 31499425dfdSThierry Reding clock-names = "sdhci"; 3157bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 31699425dfdSThierry Reding reset-names = "sdhci"; 3178589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 31824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 31924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 32024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 32141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 32241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 32341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 32441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 32541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 32641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 3276f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3286f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 32998a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 33098a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 33198a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 33299425dfdSThierry Reding status = "disabled"; 33399425dfdSThierry Reding }; 33499425dfdSThierry Reding 33599425dfdSThierry Reding sdmmc2: sdhci@3420000 { 33699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 33799425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 33899425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 339c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 34099425dfdSThierry Reding clock-names = "sdhci"; 3417bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 34299425dfdSThierry Reding reset-names = "sdhci"; 3438589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 34424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 34524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 34624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 34741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 34841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 34941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 35041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3516f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3526f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 35399425dfdSThierry Reding status = "disabled"; 35499425dfdSThierry Reding }; 35599425dfdSThierry Reding 35699425dfdSThierry Reding sdmmc3: sdhci@3440000 { 35799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 35899425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 35999425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 360c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 36199425dfdSThierry Reding clock-names = "sdhci"; 3627bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 36399425dfdSThierry Reding reset-names = "sdhci"; 3648589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 36524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 36624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 36724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 36841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 36941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 37041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 37141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 37241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 37341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3746f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3756f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 37699425dfdSThierry Reding status = "disabled"; 37799425dfdSThierry Reding }; 37899425dfdSThierry Reding 37999425dfdSThierry Reding sdmmc4: sdhci@3460000 { 38099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 38199425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 38299425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 383c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 38499425dfdSThierry Reding clock-names = "sdhci"; 38598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 38698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 38798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 3887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 38999425dfdSThierry Reding reset-names = "sdhci"; 3908589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 39141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 39241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 39341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 39441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3954e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3964e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 397e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 398e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 39922248e91SAapo Vienamo nvidia,dqs-trim = <63>; 400207f60baSAapo Vienamo mmc-hs400-1_8v; 401c4307836SSowjanya Komatineni supports-cqe; 40299425dfdSThierry Reding status = "disabled"; 40399425dfdSThierry Reding }; 40499425dfdSThierry Reding 405b066a310SThierry Reding hda@3510000 { 406b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 407b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 408b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 409b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 410b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 411b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 412b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 413b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 414b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 415b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 416b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 417b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 418dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 419b066a310SThierry Reding status = "disabled"; 420b066a310SThierry Reding }; 421b066a310SThierry Reding 4228bfde518SThierry Reding padctl: padctl@3520000 { 4238bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 4248bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 4258bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 4268bfde518SThierry Reding reg-names = "padctl", "ao"; 4278bfde518SThierry Reding 4288bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 4298bfde518SThierry Reding reset-names = "padctl"; 4308bfde518SThierry Reding 4318bfde518SThierry Reding status = "disabled"; 4328bfde518SThierry Reding 4338bfde518SThierry Reding pads { 4348bfde518SThierry Reding usb2 { 4358bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 4368bfde518SThierry Reding clock-names = "trk"; 4378bfde518SThierry Reding status = "disabled"; 4388bfde518SThierry Reding 4398bfde518SThierry Reding lanes { 4408bfde518SThierry Reding usb2-0 { 4418bfde518SThierry Reding status = "disabled"; 4428bfde518SThierry Reding #phy-cells = <0>; 4438bfde518SThierry Reding }; 4448bfde518SThierry Reding 4458bfde518SThierry Reding usb2-1 { 4468bfde518SThierry Reding status = "disabled"; 4478bfde518SThierry Reding #phy-cells = <0>; 4488bfde518SThierry Reding }; 4498bfde518SThierry Reding 4508bfde518SThierry Reding usb2-2 { 4518bfde518SThierry Reding status = "disabled"; 4528bfde518SThierry Reding #phy-cells = <0>; 4538bfde518SThierry Reding }; 4548bfde518SThierry Reding }; 4558bfde518SThierry Reding }; 4568bfde518SThierry Reding 4578bfde518SThierry Reding hsic { 4588bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 4598bfde518SThierry Reding clock-names = "trk"; 4608bfde518SThierry Reding status = "disabled"; 4618bfde518SThierry Reding 4628bfde518SThierry Reding lanes { 4638bfde518SThierry Reding hsic-0 { 4648bfde518SThierry Reding status = "disabled"; 4658bfde518SThierry Reding #phy-cells = <0>; 4668bfde518SThierry Reding }; 4678bfde518SThierry Reding }; 4688bfde518SThierry Reding }; 4698bfde518SThierry Reding 4708bfde518SThierry Reding usb3 { 4718bfde518SThierry Reding status = "disabled"; 4728bfde518SThierry Reding 4738bfde518SThierry Reding lanes { 4748bfde518SThierry Reding usb3-0 { 4758bfde518SThierry Reding status = "disabled"; 4768bfde518SThierry Reding #phy-cells = <0>; 4778bfde518SThierry Reding }; 4788bfde518SThierry Reding 4798bfde518SThierry Reding usb3-1 { 4808bfde518SThierry Reding status = "disabled"; 4818bfde518SThierry Reding #phy-cells = <0>; 4828bfde518SThierry Reding }; 4838bfde518SThierry Reding 4848bfde518SThierry Reding usb3-2 { 4858bfde518SThierry Reding status = "disabled"; 4868bfde518SThierry Reding #phy-cells = <0>; 4878bfde518SThierry Reding }; 4888bfde518SThierry Reding }; 4898bfde518SThierry Reding }; 4908bfde518SThierry Reding }; 4918bfde518SThierry Reding 4928bfde518SThierry Reding ports { 4938bfde518SThierry Reding usb2-0 { 4948bfde518SThierry Reding status = "disabled"; 4958bfde518SThierry Reding }; 4968bfde518SThierry Reding 4978bfde518SThierry Reding usb2-1 { 4988bfde518SThierry Reding status = "disabled"; 4998bfde518SThierry Reding }; 5008bfde518SThierry Reding 5018bfde518SThierry Reding usb2-2 { 5028bfde518SThierry Reding status = "disabled"; 5038bfde518SThierry Reding }; 5048bfde518SThierry Reding 5058bfde518SThierry Reding hsic-0 { 5068bfde518SThierry Reding status = "disabled"; 5078bfde518SThierry Reding }; 5088bfde518SThierry Reding 5098bfde518SThierry Reding usb3-0 { 5108bfde518SThierry Reding status = "disabled"; 5118bfde518SThierry Reding }; 5128bfde518SThierry Reding 5138bfde518SThierry Reding usb3-1 { 5148bfde518SThierry Reding status = "disabled"; 5158bfde518SThierry Reding }; 5168bfde518SThierry Reding 5178bfde518SThierry Reding usb3-2 { 5188bfde518SThierry Reding status = "disabled"; 5198bfde518SThierry Reding }; 5208bfde518SThierry Reding }; 5218bfde518SThierry Reding }; 5228bfde518SThierry Reding 5238bfde518SThierry Reding usb@3530000 { 5248bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 5258bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 5268bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 5278bfde518SThierry Reding reg-names = "hcd", "fpci"; 5288bfde518SThierry Reding 52905705c72SNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 5308bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 5318bfde518SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 5328bfde518SThierry Reding <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 5338bfde518SThierry Reding 5348bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 5358bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 5368bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 5378bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 5388bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5398bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 5408bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 5418bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5428bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 5438bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 5448bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 5458bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 5468bfde518SThierry Reding 5478bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 5488bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 5498bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 5508bfde518SThierry Reding nvidia,xusb-padctl = <&padctl>; 5518bfde518SThierry Reding 5528bfde518SThierry Reding status = "disabled"; 5538bfde518SThierry Reding 5548bfde518SThierry Reding #address-cells = <1>; 5558bfde518SThierry Reding #size-cells = <0>; 5568bfde518SThierry Reding }; 5578bfde518SThierry Reding 55885593b75SThierry Reding fuse@3820000 { 55985593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 56085593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 56185593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 56285593b75SThierry Reding clock-names = "fuse"; 56385593b75SThierry Reding }; 56485593b75SThierry Reding 56539cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 56639cb62cbSJoseph Lo compatible = "arm,gic-400"; 56739cb62cbSJoseph Lo #interrupt-cells = <3>; 56839cb62cbSJoseph Lo interrupt-controller; 56939cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 57039cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 57139cb62cbSJoseph Lo interrupts = <GIC_PPI 9 57239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 57339cb62cbSJoseph Lo interrupt-parent = <&gic>; 57439cb62cbSJoseph Lo }; 57539cb62cbSJoseph Lo 57697cf683cSThierry Reding cec@3960000 { 57797cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 57897cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 57997cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 58097cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 58197cf683cSThierry Reding clock-names = "cec"; 58297cf683cSThierry Reding status = "disabled"; 58397cf683cSThierry Reding }; 58497cf683cSThierry Reding 58539cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 58639cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 58739cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 58839cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 58939cb62cbSJoseph Lo interrupt-names = "doorbell"; 59039cb62cbSJoseph Lo #mbox-cells = <2>; 59139cb62cbSJoseph Lo status = "disabled"; 59239cb62cbSJoseph Lo }; 59339cb62cbSJoseph Lo 59440cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 595250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 59640cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 59740cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 59840cc83b3SThierry Reding #address-cells = <1>; 59940cc83b3SThierry Reding #size-cells = <0>; 600c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 60140cc83b3SThierry Reding clock-names = "div-clk"; 6027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 60340cc83b3SThierry Reding reset-names = "i2c"; 60440cc83b3SThierry Reding status = "disabled"; 60540cc83b3SThierry Reding }; 60640cc83b3SThierry Reding 60740cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 608250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 60940cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 61040cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 61140cc83b3SThierry Reding #address-cells = <1>; 61240cc83b3SThierry Reding #size-cells = <0>; 613c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 61440cc83b3SThierry Reding clock-names = "div-clk"; 6157bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 61640cc83b3SThierry Reding reset-names = "i2c"; 61740cc83b3SThierry Reding status = "disabled"; 61840cc83b3SThierry Reding }; 61940cc83b3SThierry Reding 620a7a77e2eSThierry Reding uartc: serial@c280000 { 621a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 622a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 623a7a77e2eSThierry Reding reg-shift = <2>; 624a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 625c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 626a7a77e2eSThierry Reding clock-names = "serial"; 6277bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 628a7a77e2eSThierry Reding reset-names = "serial"; 629a7a77e2eSThierry Reding status = "disabled"; 630a7a77e2eSThierry Reding }; 631a7a77e2eSThierry Reding 632a7a77e2eSThierry Reding uartg: serial@c290000 { 633a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 634a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 635a7a77e2eSThierry Reding reg-shift = <2>; 636a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 637c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 638a7a77e2eSThierry Reding clock-names = "serial"; 6397bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 640a7a77e2eSThierry Reding reset-names = "serial"; 641a7a77e2eSThierry Reding status = "disabled"; 642a7a77e2eSThierry Reding }; 643a7a77e2eSThierry Reding 6449733a251SThierry Reding rtc: rtc@c2a0000 { 6459733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 6469733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 6479733a251SThierry Reding interrupt-parent = <&pmc>; 6489733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 6499733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 6509733a251SThierry Reding clock-names = "rtc"; 6519733a251SThierry Reding status = "disabled"; 6529733a251SThierry Reding }; 6539733a251SThierry Reding 654fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 655fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 656fc4bb754SThierry Reding reg-names = "security", "gpio"; 657fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 658fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 659fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 660fc4bb754SThierry Reding gpio-controller; 661fc4bb754SThierry Reding #gpio-cells = <2>; 662fc4bb754SThierry Reding interrupt-controller; 663fc4bb754SThierry Reding #interrupt-cells = <2>; 664fc4bb754SThierry Reding }; 665fc4bb754SThierry Reding 66632e66e46SThierry Reding pmc: pmc@c360000 { 66773bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 66873bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 66973bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 67073bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 67173bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 67273bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 67324005fd1SAapo Vienamo 67432e66e46SThierry Reding #interrupt-cells = <2>; 67532e66e46SThierry Reding interrupt-controller; 67632e66e46SThierry Reding 67724005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 67824005fd1SAapo Vienamo pins = "sdmmc1-hv"; 67924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 68024005fd1SAapo Vienamo }; 68124005fd1SAapo Vienamo 68224005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 68324005fd1SAapo Vienamo pins = "sdmmc1-hv"; 68424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 68524005fd1SAapo Vienamo }; 68624005fd1SAapo Vienamo 68724005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 68824005fd1SAapo Vienamo pins = "sdmmc2-hv"; 68924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 69024005fd1SAapo Vienamo }; 69124005fd1SAapo Vienamo 69224005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 69324005fd1SAapo Vienamo pins = "sdmmc2-hv"; 69424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 69524005fd1SAapo Vienamo }; 69624005fd1SAapo Vienamo 69724005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 69824005fd1SAapo Vienamo pins = "sdmmc3-hv"; 69924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 70024005fd1SAapo Vienamo }; 70124005fd1SAapo Vienamo 70224005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 70324005fd1SAapo Vienamo pins = "sdmmc3-hv"; 70424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 70524005fd1SAapo Vienamo }; 70673bf90d4SThierry Reding }; 70773bf90d4SThierry Reding 7087b7ef494SMikko Perttunen ccplex@e000000 { 7097b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 7107b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 7117b7ef494SMikko Perttunen 7127b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 7137b7ef494SMikko Perttunen }; 7147b7ef494SMikko Perttunen 715f8973cf4SManikanta Maddireddy pcie@10003000 { 716f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 717f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 718f8973cf4SManikanta Maddireddy device_type = "pci"; 719f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 720f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 721f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 722f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 723f8973cf4SManikanta Maddireddy 724f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 725f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 726f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 727f8973cf4SManikanta Maddireddy 728f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 729f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 730f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 731f8973cf4SManikanta Maddireddy 732f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 733f8973cf4SManikanta Maddireddy #address-cells = <3>; 734f8973cf4SManikanta Maddireddy #size-cells = <2>; 735f8973cf4SManikanta Maddireddy 736f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 737f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 738f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 739f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 740f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 741f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 742f8973cf4SManikanta Maddireddy 743f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 744f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 745f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 746f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 747f8973cf4SManikanta Maddireddy 748f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 749f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 750f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 751f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 752f8973cf4SManikanta Maddireddy 753f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 754f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 755f2a465e7SThierry Reding iommu-map-mask = <0x0>; 756f2a465e7SThierry Reding 757f8973cf4SManikanta Maddireddy status = "disabled"; 758f8973cf4SManikanta Maddireddy 759f8973cf4SManikanta Maddireddy pci@1,0 { 760f8973cf4SManikanta Maddireddy device_type = "pci"; 761f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 762f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 763f8973cf4SManikanta Maddireddy status = "disabled"; 764f8973cf4SManikanta Maddireddy 765f8973cf4SManikanta Maddireddy #address-cells = <3>; 766f8973cf4SManikanta Maddireddy #size-cells = <2>; 767f8973cf4SManikanta Maddireddy ranges; 768f8973cf4SManikanta Maddireddy 769f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 770f8973cf4SManikanta Maddireddy }; 771f8973cf4SManikanta Maddireddy 772f8973cf4SManikanta Maddireddy pci@2,0 { 773f8973cf4SManikanta Maddireddy device_type = "pci"; 774f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 775f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 776f8973cf4SManikanta Maddireddy status = "disabled"; 777f8973cf4SManikanta Maddireddy 778f8973cf4SManikanta Maddireddy #address-cells = <3>; 779f8973cf4SManikanta Maddireddy #size-cells = <2>; 780f8973cf4SManikanta Maddireddy ranges; 781f8973cf4SManikanta Maddireddy 782f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 783f8973cf4SManikanta Maddireddy }; 784f8973cf4SManikanta Maddireddy 785f8973cf4SManikanta Maddireddy pci@3,0 { 786f8973cf4SManikanta Maddireddy device_type = "pci"; 787f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 788f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 789f8973cf4SManikanta Maddireddy status = "disabled"; 790f8973cf4SManikanta Maddireddy 791f8973cf4SManikanta Maddireddy #address-cells = <3>; 792f8973cf4SManikanta Maddireddy #size-cells = <2>; 793f8973cf4SManikanta Maddireddy ranges; 794f8973cf4SManikanta Maddireddy 795f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 796f8973cf4SManikanta Maddireddy }; 797f8973cf4SManikanta Maddireddy }; 798f8973cf4SManikanta Maddireddy 799b30a8e61SThierry Reding smmu: iommu@12000000 { 800b30a8e61SThierry Reding compatible = "arm,mmu-500"; 801b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 802b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 803b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 804b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 805b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 806b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 807b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 808b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 809b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 810b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 811b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 812b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 813b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 814b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 815b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 816b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 817b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 818b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 819b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 820b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 821b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 822b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 823b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 867b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 868b30a8e61SThierry Reding #global-interrupts = <1>; 869b30a8e61SThierry Reding #iommu-cells = <1>; 870b30a8e61SThierry Reding }; 871b30a8e61SThierry Reding 8725524c61fSMikko Perttunen host1x@13e00000 { 8735524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 8745524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 8755524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 8765524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 8775524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 8785524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 8795524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 8805524c61fSMikko Perttunen clock-names = "host1x"; 8815524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 8825524c61fSMikko Perttunen reset-names = "host1x"; 8835524c61fSMikko Perttunen 8845524c61fSMikko Perttunen #address-cells = <1>; 8855524c61fSMikko Perttunen #size-cells = <1>; 8865524c61fSMikko Perttunen 8875524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 888c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 889c2599da7SThierry Reding 890c2599da7SThierry Reding dpaux1: dpaux@15040000 { 891c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 892c2599da7SThierry Reding reg = <0x15040000 0x10000>; 893c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 894c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 895c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 896c2599da7SThierry Reding clock-names = "dpaux", "parent"; 897c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 898c2599da7SThierry Reding reset-names = "dpaux"; 899c2599da7SThierry Reding status = "disabled"; 900c2599da7SThierry Reding 901c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 902c2599da7SThierry Reding 903c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 904c2599da7SThierry Reding groups = "dpaux-io"; 905c2599da7SThierry Reding function = "aux"; 906c2599da7SThierry Reding }; 907c2599da7SThierry Reding 908c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 909c2599da7SThierry Reding groups = "dpaux-io"; 910c2599da7SThierry Reding function = "i2c"; 911c2599da7SThierry Reding }; 912c2599da7SThierry Reding 913c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 914c2599da7SThierry Reding groups = "dpaux-io"; 915c2599da7SThierry Reding function = "off"; 916c2599da7SThierry Reding }; 917c2599da7SThierry Reding 918c2599da7SThierry Reding i2c-bus { 919c2599da7SThierry Reding #address-cells = <1>; 920c2599da7SThierry Reding #size-cells = <0>; 921c2599da7SThierry Reding }; 922c2599da7SThierry Reding }; 923c2599da7SThierry Reding 924c2599da7SThierry Reding display-hub@15200000 { 925c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 926ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 927c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 928c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 929c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 930c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 931c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 932c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 933c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 934c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 935c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 936c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 937c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 938c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 939c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 940c2599da7SThierry Reding status = "disabled"; 941c2599da7SThierry Reding 942c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 943c2599da7SThierry Reding 944c2599da7SThierry Reding #address-cells = <1>; 945c2599da7SThierry Reding #size-cells = <1>; 946c2599da7SThierry Reding 947c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 948c2599da7SThierry Reding 949c2599da7SThierry Reding display@15200000 { 950c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 951c2599da7SThierry Reding reg = <0x15200000 0x10000>; 952c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 953c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 954c2599da7SThierry Reding clock-names = "dc"; 955c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 956c2599da7SThierry Reding reset-names = "dc"; 957c2599da7SThierry Reding 958c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 959c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 960c2599da7SThierry Reding 961c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 962c2599da7SThierry Reding nvidia,head = <0>; 963c2599da7SThierry Reding }; 964c2599da7SThierry Reding 965c2599da7SThierry Reding display@15210000 { 966c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 967c2599da7SThierry Reding reg = <0x15210000 0x10000>; 968c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 969c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 970c2599da7SThierry Reding clock-names = "dc"; 971c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 972c2599da7SThierry Reding reset-names = "dc"; 973c2599da7SThierry Reding 974c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 975c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 976c2599da7SThierry Reding 977c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 978c2599da7SThierry Reding nvidia,head = <1>; 979c2599da7SThierry Reding }; 980c2599da7SThierry Reding 981c2599da7SThierry Reding display@15220000 { 982c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 983c2599da7SThierry Reding reg = <0x15220000 0x10000>; 984c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 985c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 986c2599da7SThierry Reding clock-names = "dc"; 987c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 988c2599da7SThierry Reding reset-names = "dc"; 989c2599da7SThierry Reding 990c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 991c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 992c2599da7SThierry Reding 993c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 994c2599da7SThierry Reding nvidia,head = <2>; 995c2599da7SThierry Reding }; 996c2599da7SThierry Reding }; 997c2599da7SThierry Reding 998c2599da7SThierry Reding dsia: dsi@15300000 { 999c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1000c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1001c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1002c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1003c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1004c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1005c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1006c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1007c2599da7SThierry Reding reset-names = "dsi"; 1008c2599da7SThierry Reding status = "disabled"; 1009c2599da7SThierry Reding 1010c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1011c2599da7SThierry Reding }; 1012effc4b44SMikko Perttunen 1013effc4b44SMikko Perttunen vic@15340000 { 1014effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1015effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1016effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1017effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1018effc4b44SMikko Perttunen clock-names = "vic"; 1019effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1020effc4b44SMikko Perttunen reset-names = "vic"; 1021effc4b44SMikko Perttunen 1022effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 102329ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1024effc4b44SMikko Perttunen }; 1025c2599da7SThierry Reding 1026c2599da7SThierry Reding dsib: dsi@15400000 { 1027c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1028c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1029c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1030c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1031c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1032c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1033c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1034c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1035c2599da7SThierry Reding reset-names = "dsi"; 1036c2599da7SThierry Reding status = "disabled"; 1037c2599da7SThierry Reding 1038c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1039c2599da7SThierry Reding }; 1040c2599da7SThierry Reding 1041c2599da7SThierry Reding sor0: sor@15540000 { 1042c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1043c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1044c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1045c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1046c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1047c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1048c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1049c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1050c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1051c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1052c2599da7SThierry Reding "pad"; 1053c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1054c2599da7SThierry Reding reset-names = "sor"; 1055c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1056c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1057c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1058c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1059c2599da7SThierry Reding status = "disabled"; 1060c2599da7SThierry Reding 1061c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1062c2599da7SThierry Reding nvidia,interface = <0>; 1063c2599da7SThierry Reding }; 1064c2599da7SThierry Reding 1065c2599da7SThierry Reding sor1: sor@15580000 { 1066d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1067c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1068c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1069c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1070c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1071c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1072c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1073c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1074c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1075c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1076c2599da7SThierry Reding "pad"; 1077c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1078c2599da7SThierry Reding reset-names = "sor"; 1079c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1080c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1081c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1082c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1083c2599da7SThierry Reding status = "disabled"; 1084c2599da7SThierry Reding 1085c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1086c2599da7SThierry Reding nvidia,interface = <1>; 1087c2599da7SThierry Reding }; 1088c2599da7SThierry Reding 1089c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1090c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1091c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1092c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1093c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1094c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1095c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1096c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1097c2599da7SThierry Reding reset-names = "dpaux"; 1098c2599da7SThierry Reding status = "disabled"; 1099c2599da7SThierry Reding 1100c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1101c2599da7SThierry Reding 1102c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1103c2599da7SThierry Reding groups = "dpaux-io"; 1104c2599da7SThierry Reding function = "aux"; 1105c2599da7SThierry Reding }; 1106c2599da7SThierry Reding 1107c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1108c2599da7SThierry Reding groups = "dpaux-io"; 1109c2599da7SThierry Reding function = "i2c"; 1110c2599da7SThierry Reding }; 1111c2599da7SThierry Reding 1112c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1113c2599da7SThierry Reding groups = "dpaux-io"; 1114c2599da7SThierry Reding function = "off"; 1115c2599da7SThierry Reding }; 1116c2599da7SThierry Reding 1117c2599da7SThierry Reding i2c-bus { 1118c2599da7SThierry Reding #address-cells = <1>; 1119c2599da7SThierry Reding #size-cells = <0>; 1120c2599da7SThierry Reding }; 1121c2599da7SThierry Reding }; 1122c2599da7SThierry Reding 1123c2599da7SThierry Reding padctl@15880000 { 1124c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1125c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1126c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1127c2599da7SThierry Reding reset-names = "dsi"; 1128c2599da7SThierry Reding status = "disabled"; 1129c2599da7SThierry Reding }; 1130c2599da7SThierry Reding 1131c2599da7SThierry Reding dsic: dsi@15900000 { 1132c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1133c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1134c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1135c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1136c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1137c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1138c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1139c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1140c2599da7SThierry Reding reset-names = "dsi"; 1141c2599da7SThierry Reding status = "disabled"; 1142c2599da7SThierry Reding 1143c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1144c2599da7SThierry Reding }; 1145c2599da7SThierry Reding 1146c2599da7SThierry Reding dsid: dsi@15940000 { 1147c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1148c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1149c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1150c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1151c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1152c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1153c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1154c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1155c2599da7SThierry Reding reset-names = "dsi"; 1156c2599da7SThierry Reding status = "disabled"; 1157c2599da7SThierry Reding 1158c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1159c2599da7SThierry Reding }; 11605524c61fSMikko Perttunen }; 11615524c61fSMikko Perttunen 1162dfd7a384SAlexandre Courbot gpu@17000000 { 1163dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1164dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1165dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 1166dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1167dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1168dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1169dfd7a384SAlexandre Courbot 1170dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1171dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1172dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1173dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1174dfd7a384SAlexandre Courbot reset-names = "gpu"; 1175dfd7a384SAlexandre Courbot status = "disabled"; 1176dfd7a384SAlexandre Courbot 1177dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1178dfd7a384SAlexandre Courbot }; 1179dfd7a384SAlexandre Courbot 118039cb62cbSJoseph Lo sysram@30000000 { 118139cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 118239cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 118339cb62cbSJoseph Lo #address-cells = <2>; 118439cb62cbSJoseph Lo #size-cells = <2>; 118539cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 118639cb62cbSJoseph Lo 118739cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 118839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 118939cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 119039cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 119139cb62cbSJoseph Lo pool; 119239cb62cbSJoseph Lo }; 119339cb62cbSJoseph Lo 119439cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 119539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 119639cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 119739cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 119839cb62cbSJoseph Lo pool; 119939cb62cbSJoseph Lo }; 120039cb62cbSJoseph Lo }; 120139cb62cbSJoseph Lo 1202541d7c44SThierry Reding bpmp: bpmp { 1203541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1204541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1205541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1206541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1207541d7c44SThierry Reding shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1208541d7c44SThierry Reding #clock-cells = <1>; 1209541d7c44SThierry Reding #reset-cells = <1>; 1210541d7c44SThierry Reding #power-domain-cells = <1>; 1211541d7c44SThierry Reding 1212541d7c44SThierry Reding bpmp_i2c: i2c { 1213541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1214541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1215541d7c44SThierry Reding #address-cells = <1>; 1216541d7c44SThierry Reding #size-cells = <0>; 1217541d7c44SThierry Reding status = "disabled"; 1218541d7c44SThierry Reding }; 1219541d7c44SThierry Reding 1220541d7c44SThierry Reding bpmp_thermal: thermal { 1221541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1222541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1223541d7c44SThierry Reding }; 1224541d7c44SThierry Reding }; 1225541d7c44SThierry Reding 1226cd6fe32eSThierry Reding cpus { 1227cd6fe32eSThierry Reding #address-cells = <1>; 1228cd6fe32eSThierry Reding #size-cells = <0>; 1229cd6fe32eSThierry Reding 1230cd6fe32eSThierry Reding cpu@0 { 123131af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1232cd6fe32eSThierry Reding device_type = "cpu"; 12335298166dSJoseph Lo i-cache-size = <0x20000>; 12345298166dSJoseph Lo i-cache-line-size = <64>; 12355298166dSJoseph Lo i-cache-sets = <512>; 12365298166dSJoseph Lo d-cache-size = <0x10000>; 12375298166dSJoseph Lo d-cache-line-size = <64>; 12385298166dSJoseph Lo d-cache-sets = <256>; 12395298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1240cd6fe32eSThierry Reding reg = <0x000>; 1241cd6fe32eSThierry Reding }; 1242cd6fe32eSThierry Reding 1243cd6fe32eSThierry Reding cpu@1 { 124431af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1245cd6fe32eSThierry Reding device_type = "cpu"; 12465298166dSJoseph Lo i-cache-size = <0x20000>; 12475298166dSJoseph Lo i-cache-line-size = <64>; 12485298166dSJoseph Lo i-cache-sets = <512>; 12495298166dSJoseph Lo d-cache-size = <0x10000>; 12505298166dSJoseph Lo d-cache-line-size = <64>; 12515298166dSJoseph Lo d-cache-sets = <256>; 12525298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1253cd6fe32eSThierry Reding reg = <0x001>; 1254cd6fe32eSThierry Reding }; 1255cd6fe32eSThierry Reding 1256cd6fe32eSThierry Reding cpu@2 { 125731af04cdSRob Herring compatible = "arm,cortex-a57"; 1258cd6fe32eSThierry Reding device_type = "cpu"; 12595298166dSJoseph Lo i-cache-size = <0xC000>; 12605298166dSJoseph Lo i-cache-line-size = <64>; 12615298166dSJoseph Lo i-cache-sets = <256>; 12625298166dSJoseph Lo d-cache-size = <0x8000>; 12635298166dSJoseph Lo d-cache-line-size = <64>; 12645298166dSJoseph Lo d-cache-sets = <256>; 12655298166dSJoseph Lo next-level-cache = <&L2_A57>; 1266cd6fe32eSThierry Reding reg = <0x100>; 1267cd6fe32eSThierry Reding }; 1268cd6fe32eSThierry Reding 1269cd6fe32eSThierry Reding cpu@3 { 127031af04cdSRob Herring compatible = "arm,cortex-a57"; 1271cd6fe32eSThierry Reding device_type = "cpu"; 12725298166dSJoseph Lo i-cache-size = <0xC000>; 12735298166dSJoseph Lo i-cache-line-size = <64>; 12745298166dSJoseph Lo i-cache-sets = <256>; 12755298166dSJoseph Lo d-cache-size = <0x8000>; 12765298166dSJoseph Lo d-cache-line-size = <64>; 12775298166dSJoseph Lo d-cache-sets = <256>; 12785298166dSJoseph Lo next-level-cache = <&L2_A57>; 1279cd6fe32eSThierry Reding reg = <0x101>; 1280cd6fe32eSThierry Reding }; 1281cd6fe32eSThierry Reding 1282cd6fe32eSThierry Reding cpu@4 { 128331af04cdSRob Herring compatible = "arm,cortex-a57"; 1284cd6fe32eSThierry Reding device_type = "cpu"; 12855298166dSJoseph Lo i-cache-size = <0xC000>; 12865298166dSJoseph Lo i-cache-line-size = <64>; 12875298166dSJoseph Lo i-cache-sets = <256>; 12885298166dSJoseph Lo d-cache-size = <0x8000>; 12895298166dSJoseph Lo d-cache-line-size = <64>; 12905298166dSJoseph Lo d-cache-sets = <256>; 12915298166dSJoseph Lo next-level-cache = <&L2_A57>; 1292cd6fe32eSThierry Reding reg = <0x102>; 1293cd6fe32eSThierry Reding }; 1294cd6fe32eSThierry Reding 1295cd6fe32eSThierry Reding cpu@5 { 129631af04cdSRob Herring compatible = "arm,cortex-a57"; 1297cd6fe32eSThierry Reding device_type = "cpu"; 12985298166dSJoseph Lo i-cache-size = <0xC000>; 12995298166dSJoseph Lo i-cache-line-size = <64>; 13005298166dSJoseph Lo i-cache-sets = <256>; 13015298166dSJoseph Lo d-cache-size = <0x8000>; 13025298166dSJoseph Lo d-cache-line-size = <64>; 13035298166dSJoseph Lo d-cache-sets = <256>; 13045298166dSJoseph Lo next-level-cache = <&L2_A57>; 1305cd6fe32eSThierry Reding reg = <0x103>; 1306cd6fe32eSThierry Reding }; 13075298166dSJoseph Lo 13085298166dSJoseph Lo L2_DENVER: l2-cache0 { 13095298166dSJoseph Lo compatible = "cache"; 13105298166dSJoseph Lo cache-unified; 13115298166dSJoseph Lo cache-level = <2>; 13125298166dSJoseph Lo cache-size = <0x200000>; 13135298166dSJoseph Lo cache-line-size = <64>; 13145298166dSJoseph Lo cache-sets = <2048>; 13155298166dSJoseph Lo }; 13165298166dSJoseph Lo 13175298166dSJoseph Lo L2_A57: l2-cache1 { 13185298166dSJoseph Lo compatible = "cache"; 13195298166dSJoseph Lo cache-unified; 13205298166dSJoseph Lo cache-level = <2>; 13215298166dSJoseph Lo cache-size = <0x200000>; 13225298166dSJoseph Lo cache-line-size = <64>; 13235298166dSJoseph Lo cache-sets = <2048>; 13245298166dSJoseph Lo }; 1325cd6fe32eSThierry Reding }; 1326cd6fe32eSThierry Reding 132715274c23SMikko Perttunen thermal-zones { 132815274c23SMikko Perttunen a57 { 132915274c23SMikko Perttunen polling-delay = <0>; 133015274c23SMikko Perttunen polling-delay-passive = <1000>; 133115274c23SMikko Perttunen 133215274c23SMikko Perttunen thermal-sensors = 133315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 133415274c23SMikko Perttunen 133515274c23SMikko Perttunen trips { 133615274c23SMikko Perttunen critical { 133715274c23SMikko Perttunen temperature = <101000>; 133815274c23SMikko Perttunen hysteresis = <0>; 133915274c23SMikko Perttunen type = "critical"; 134015274c23SMikko Perttunen }; 134115274c23SMikko Perttunen }; 134215274c23SMikko Perttunen 134315274c23SMikko Perttunen cooling-maps { 134415274c23SMikko Perttunen }; 134515274c23SMikko Perttunen }; 134615274c23SMikko Perttunen 134715274c23SMikko Perttunen denver { 134815274c23SMikko Perttunen polling-delay = <0>; 134915274c23SMikko Perttunen polling-delay-passive = <1000>; 135015274c23SMikko Perttunen 135115274c23SMikko Perttunen thermal-sensors = 135215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 135315274c23SMikko Perttunen 135415274c23SMikko Perttunen trips { 135515274c23SMikko Perttunen critical { 135615274c23SMikko Perttunen temperature = <101000>; 135715274c23SMikko Perttunen hysteresis = <0>; 135815274c23SMikko Perttunen type = "critical"; 135915274c23SMikko Perttunen }; 136015274c23SMikko Perttunen }; 136115274c23SMikko Perttunen 136215274c23SMikko Perttunen cooling-maps { 136315274c23SMikko Perttunen }; 136415274c23SMikko Perttunen }; 136515274c23SMikko Perttunen 136615274c23SMikko Perttunen gpu { 136715274c23SMikko Perttunen polling-delay = <0>; 136815274c23SMikko Perttunen polling-delay-passive = <1000>; 136915274c23SMikko Perttunen 137015274c23SMikko Perttunen thermal-sensors = 137115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 137215274c23SMikko Perttunen 137315274c23SMikko Perttunen trips { 137415274c23SMikko Perttunen critical { 137515274c23SMikko Perttunen temperature = <101000>; 137615274c23SMikko Perttunen hysteresis = <0>; 137715274c23SMikko Perttunen type = "critical"; 137815274c23SMikko Perttunen }; 137915274c23SMikko Perttunen }; 138015274c23SMikko Perttunen 138115274c23SMikko Perttunen cooling-maps { 138215274c23SMikko Perttunen }; 138315274c23SMikko Perttunen }; 138415274c23SMikko Perttunen 138515274c23SMikko Perttunen pll { 138615274c23SMikko Perttunen polling-delay = <0>; 138715274c23SMikko Perttunen polling-delay-passive = <1000>; 138815274c23SMikko Perttunen 138915274c23SMikko Perttunen thermal-sensors = 139015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 139115274c23SMikko Perttunen 139215274c23SMikko Perttunen trips { 139315274c23SMikko Perttunen critical { 139415274c23SMikko Perttunen temperature = <101000>; 139515274c23SMikko Perttunen hysteresis = <0>; 139615274c23SMikko Perttunen type = "critical"; 139715274c23SMikko Perttunen }; 139815274c23SMikko Perttunen }; 139915274c23SMikko Perttunen 140015274c23SMikko Perttunen cooling-maps { 140115274c23SMikko Perttunen }; 140215274c23SMikko Perttunen }; 140315274c23SMikko Perttunen 140415274c23SMikko Perttunen always_on { 140515274c23SMikko Perttunen polling-delay = <0>; 140615274c23SMikko Perttunen polling-delay-passive = <1000>; 140715274c23SMikko Perttunen 140815274c23SMikko Perttunen thermal-sensors = 140915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 141015274c23SMikko Perttunen 141115274c23SMikko Perttunen trips { 141215274c23SMikko Perttunen critical { 141315274c23SMikko Perttunen temperature = <101000>; 141415274c23SMikko Perttunen hysteresis = <0>; 141515274c23SMikko Perttunen type = "critical"; 141615274c23SMikko Perttunen }; 141715274c23SMikko Perttunen }; 141815274c23SMikko Perttunen 141915274c23SMikko Perttunen cooling-maps { 142015274c23SMikko Perttunen }; 142115274c23SMikko Perttunen }; 142239cb62cbSJoseph Lo }; 142339cb62cbSJoseph Lo 142439cb62cbSJoseph Lo timer { 142539cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 142639cb62cbSJoseph Lo interrupts = <GIC_PPI 13 142739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 142839cb62cbSJoseph Lo <GIC_PPI 14 142939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 143039cb62cbSJoseph Lo <GIC_PPI 11 143139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 143239cb62cbSJoseph Lo <GIC_PPI 10 143339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 143439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1435b30be673SThierry Reding always-on; 143639cb62cbSJoseph Lo }; 143739cb62cbSJoseph Lo}; 1438