1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 77bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 839cb62cbSJoseph Lo 939cb62cbSJoseph Lo/ { 1039cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1139cb62cbSJoseph Lo interrupt-parent = <&gic>; 1239cb62cbSJoseph Lo #address-cells = <2>; 1339cb62cbSJoseph Lo #size-cells = <2>; 1439cb62cbSJoseph Lo 15fc4bb754SThierry Reding gpio: gpio@2200000 { 16fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 17fc4bb754SThierry Reding reg-names = "security", "gpio"; 18fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 19fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 20fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 21fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 22fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 23fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 24fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 25fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 26fc4bb754SThierry Reding #interrupt-cells = <2>; 27fc4bb754SThierry Reding interrupt-controller; 28fc4bb754SThierry Reding #gpio-cells = <2>; 29fc4bb754SThierry Reding gpio-controller; 30fc4bb754SThierry Reding }; 31fc4bb754SThierry Reding 320caafbdeSThierry Reding ethernet@2490000 { 330caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 340caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 350caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 360caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 370caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 380caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 390caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 400caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 410caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 420caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 430caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 440caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 450caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 460caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 470caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 480caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 490caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 500caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 510caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 520caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 530caafbdeSThierry Reding reset-names = "eqos"; 540caafbdeSThierry Reding status = "disabled"; 550caafbdeSThierry Reding 560caafbdeSThierry Reding snps,write-requests = <1>; 570caafbdeSThierry Reding snps,read-requests = <3>; 580caafbdeSThierry Reding snps,burst-map = <0x7>; 590caafbdeSThierry Reding snps,txpbl = <32>; 600caafbdeSThierry Reding snps,rxpbl = <8>; 610caafbdeSThierry Reding }; 620caafbdeSThierry Reding 6339cb62cbSJoseph Lo uarta: serial@3100000 { 6439cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 6539cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 6639cb62cbSJoseph Lo reg-shift = <2>; 6739cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 68c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 69a7a77e2eSThierry Reding clock-names = "serial"; 707bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 71a7a77e2eSThierry Reding reset-names = "serial"; 72a7a77e2eSThierry Reding status = "disabled"; 73a7a77e2eSThierry Reding }; 74a7a77e2eSThierry Reding 75a7a77e2eSThierry Reding uartb: serial@3110000 { 76a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 77a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 78a7a77e2eSThierry Reding reg-shift = <2>; 79a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 80c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 81a7a77e2eSThierry Reding clock-names = "serial"; 827bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 83a7a77e2eSThierry Reding reset-names = "serial"; 84a7a77e2eSThierry Reding status = "disabled"; 85a7a77e2eSThierry Reding }; 86a7a77e2eSThierry Reding 87a7a77e2eSThierry Reding uartd: serial@3130000 { 88a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 89a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 90a7a77e2eSThierry Reding reg-shift = <2>; 91a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 92c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 93a7a77e2eSThierry Reding clock-names = "serial"; 947bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 95a7a77e2eSThierry Reding reset-names = "serial"; 96a7a77e2eSThierry Reding status = "disabled"; 97a7a77e2eSThierry Reding }; 98a7a77e2eSThierry Reding 99a7a77e2eSThierry Reding uarte: serial@3140000 { 100a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 101a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 102a7a77e2eSThierry Reding reg-shift = <2>; 103a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 104c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 105a7a77e2eSThierry Reding clock-names = "serial"; 1067bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 107a7a77e2eSThierry Reding reset-names = "serial"; 108a7a77e2eSThierry Reding status = "disabled"; 109a7a77e2eSThierry Reding }; 110a7a77e2eSThierry Reding 111a7a77e2eSThierry Reding uartf: serial@3150000 { 112a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 113a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 114a7a77e2eSThierry Reding reg-shift = <2>; 115a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 116c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 117a7a77e2eSThierry Reding clock-names = "serial"; 1187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 119a7a77e2eSThierry Reding reset-names = "serial"; 12039cb62cbSJoseph Lo status = "disabled"; 12139cb62cbSJoseph Lo }; 12239cb62cbSJoseph Lo 12340cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 12440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 12540cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 12640cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 12740cc83b3SThierry Reding #address-cells = <1>; 12840cc83b3SThierry Reding #size-cells = <0>; 129c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 13040cc83b3SThierry Reding clock-names = "div-clk"; 1317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 13240cc83b3SThierry Reding reset-names = "i2c"; 13340cc83b3SThierry Reding status = "disabled"; 13440cc83b3SThierry Reding }; 13540cc83b3SThierry Reding 13640cc83b3SThierry Reding cam_i2c: i2c@3180000 { 13740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13840cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 13940cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 14040cc83b3SThierry Reding #address-cells = <1>; 14140cc83b3SThierry Reding #size-cells = <0>; 142c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 14340cc83b3SThierry Reding clock-names = "div-clk"; 1447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 14540cc83b3SThierry Reding reset-names = "i2c"; 14640cc83b3SThierry Reding status = "disabled"; 14740cc83b3SThierry Reding }; 14840cc83b3SThierry Reding 14940cc83b3SThierry Reding /* shares pads with dpaux1 */ 15040cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 15140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15240cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 15340cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 15440cc83b3SThierry Reding #address-cells = <1>; 15540cc83b3SThierry Reding #size-cells = <0>; 156c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 15740cc83b3SThierry Reding clock-names = "div-clk"; 1587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 15940cc83b3SThierry Reding reset-names = "i2c"; 16040cc83b3SThierry Reding status = "disabled"; 16140cc83b3SThierry Reding }; 16240cc83b3SThierry Reding 16340cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 16440cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 16540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16640cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 16740cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 16840cc83b3SThierry Reding #address-cells = <1>; 16940cc83b3SThierry Reding #size-cells = <0>; 170c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 17140cc83b3SThierry Reding clock-names = "div-clk"; 1727bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 17340cc83b3SThierry Reding reset-names = "i2c"; 17440cc83b3SThierry Reding status = "disabled"; 17540cc83b3SThierry Reding }; 17640cc83b3SThierry Reding 17740cc83b3SThierry Reding /* shares pads with dpaux0 */ 17840cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 17940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18040cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 18140cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 18240cc83b3SThierry Reding #address-cells = <1>; 18340cc83b3SThierry Reding #size-cells = <0>; 184c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 18540cc83b3SThierry Reding clock-names = "div-clk"; 1867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 18740cc83b3SThierry Reding reset-names = "i2c"; 18840cc83b3SThierry Reding status = "disabled"; 18940cc83b3SThierry Reding }; 19040cc83b3SThierry Reding 19140cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 19240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19340cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 19440cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 19540cc83b3SThierry Reding #address-cells = <1>; 19640cc83b3SThierry Reding #size-cells = <0>; 197c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 19840cc83b3SThierry Reding clock-names = "div-clk"; 1997bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 20040cc83b3SThierry Reding reset-names = "i2c"; 20140cc83b3SThierry Reding status = "disabled"; 20240cc83b3SThierry Reding }; 20340cc83b3SThierry Reding 20440cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 20540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20640cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 20740cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 20840cc83b3SThierry Reding #address-cells = <1>; 20940cc83b3SThierry Reding #size-cells = <0>; 210c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 21140cc83b3SThierry Reding clock-names = "div-clk"; 2127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 21340cc83b3SThierry Reding reset-names = "i2c"; 21440cc83b3SThierry Reding status = "disabled"; 21540cc83b3SThierry Reding }; 21640cc83b3SThierry Reding 21799425dfdSThierry Reding sdmmc1: sdhci@3400000 { 21899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 21999425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 22099425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 221c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 22299425dfdSThierry Reding clock-names = "sdhci"; 2237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 22499425dfdSThierry Reding reset-names = "sdhci"; 22599425dfdSThierry Reding status = "disabled"; 22699425dfdSThierry Reding }; 22799425dfdSThierry Reding 22899425dfdSThierry Reding sdmmc2: sdhci@3420000 { 22999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23099425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 23199425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 232c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 23399425dfdSThierry Reding clock-names = "sdhci"; 2347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 23599425dfdSThierry Reding reset-names = "sdhci"; 23699425dfdSThierry Reding status = "disabled"; 23799425dfdSThierry Reding }; 23899425dfdSThierry Reding 23999425dfdSThierry Reding sdmmc3: sdhci@3440000 { 24099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24199425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 24299425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 243c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 24499425dfdSThierry Reding clock-names = "sdhci"; 2457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 24699425dfdSThierry Reding reset-names = "sdhci"; 24799425dfdSThierry Reding status = "disabled"; 24899425dfdSThierry Reding }; 24999425dfdSThierry Reding 25099425dfdSThierry Reding sdmmc4: sdhci@3460000 { 25199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 25399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 254c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 25599425dfdSThierry Reding clock-names = "sdhci"; 2567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 25799425dfdSThierry Reding reset-names = "sdhci"; 25899425dfdSThierry Reding status = "disabled"; 25999425dfdSThierry Reding }; 26099425dfdSThierry Reding 26139cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 26239cb62cbSJoseph Lo compatible = "arm,gic-400"; 26339cb62cbSJoseph Lo #interrupt-cells = <3>; 26439cb62cbSJoseph Lo interrupt-controller; 26539cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 26639cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 26739cb62cbSJoseph Lo interrupts = <GIC_PPI 9 26839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 26939cb62cbSJoseph Lo interrupt-parent = <&gic>; 27039cb62cbSJoseph Lo }; 27139cb62cbSJoseph Lo 27239cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 27339cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 27439cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 27539cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 27639cb62cbSJoseph Lo interrupt-names = "doorbell"; 27739cb62cbSJoseph Lo #mbox-cells = <2>; 27839cb62cbSJoseph Lo status = "disabled"; 27939cb62cbSJoseph Lo }; 28039cb62cbSJoseph Lo 28140cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 28240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 28340cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 28440cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 28540cc83b3SThierry Reding #address-cells = <1>; 28640cc83b3SThierry Reding #size-cells = <0>; 287c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 28840cc83b3SThierry Reding clock-names = "div-clk"; 2897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 29040cc83b3SThierry Reding reset-names = "i2c"; 29140cc83b3SThierry Reding status = "disabled"; 29240cc83b3SThierry Reding }; 29340cc83b3SThierry Reding 29440cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 29540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 29640cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 29740cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 29840cc83b3SThierry Reding #address-cells = <1>; 29940cc83b3SThierry Reding #size-cells = <0>; 300c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 30140cc83b3SThierry Reding clock-names = "div-clk"; 3027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 30340cc83b3SThierry Reding reset-names = "i2c"; 30440cc83b3SThierry Reding status = "disabled"; 30540cc83b3SThierry Reding }; 30640cc83b3SThierry Reding 307a7a77e2eSThierry Reding uartc: serial@c280000 { 308a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 309a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 310a7a77e2eSThierry Reding reg-shift = <2>; 311a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 312c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 313a7a77e2eSThierry Reding clock-names = "serial"; 3147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 315a7a77e2eSThierry Reding reset-names = "serial"; 316a7a77e2eSThierry Reding status = "disabled"; 317a7a77e2eSThierry Reding }; 318a7a77e2eSThierry Reding 319a7a77e2eSThierry Reding uartg: serial@c290000 { 320a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 321a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 322a7a77e2eSThierry Reding reg-shift = <2>; 323a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 324c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 325a7a77e2eSThierry Reding clock-names = "serial"; 3267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 327a7a77e2eSThierry Reding reset-names = "serial"; 328a7a77e2eSThierry Reding status = "disabled"; 329a7a77e2eSThierry Reding }; 330a7a77e2eSThierry Reding 331fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 332fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 333fc4bb754SThierry Reding reg-names = "security", "gpio"; 334fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 335fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 336fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 337fc4bb754SThierry Reding gpio-controller; 338fc4bb754SThierry Reding #gpio-cells = <2>; 339fc4bb754SThierry Reding interrupt-controller; 340fc4bb754SThierry Reding #interrupt-cells = <2>; 341fc4bb754SThierry Reding }; 342fc4bb754SThierry Reding 34373bf90d4SThierry Reding pmc@c360000 { 34473bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 34573bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 34673bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 34773bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 34873bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 34973bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 35073bf90d4SThierry Reding }; 35173bf90d4SThierry Reding 3527b7ef494SMikko Perttunen ccplex@e000000 { 3537b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 3547b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 3557b7ef494SMikko Perttunen 3567b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 3577b7ef494SMikko Perttunen }; 3587b7ef494SMikko Perttunen 359dfd7a384SAlexandre Courbot gpu@17000000 { 360dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 361dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 362dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 363dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 364dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 366dfd7a384SAlexandre Courbot 367dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 368dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 369dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 370dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 371dfd7a384SAlexandre Courbot reset-names = "gpu"; 372dfd7a384SAlexandre Courbot status = "disabled"; 373dfd7a384SAlexandre Courbot 374dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 375dfd7a384SAlexandre Courbot }; 376dfd7a384SAlexandre Courbot 37739cb62cbSJoseph Lo sysram@30000000 { 37839cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 37939cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 38039cb62cbSJoseph Lo #address-cells = <2>; 38139cb62cbSJoseph Lo #size-cells = <2>; 38239cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 38339cb62cbSJoseph Lo 38439cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 38539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 38639cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 38739cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 38839cb62cbSJoseph Lo pool; 38939cb62cbSJoseph Lo }; 39039cb62cbSJoseph Lo 39139cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 39239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 39339cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 39439cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 39539cb62cbSJoseph Lo pool; 39639cb62cbSJoseph Lo }; 39739cb62cbSJoseph Lo }; 39839cb62cbSJoseph Lo 399cd6fe32eSThierry Reding cpus { 400cd6fe32eSThierry Reding #address-cells = <1>; 401cd6fe32eSThierry Reding #size-cells = <0>; 402cd6fe32eSThierry Reding 403cd6fe32eSThierry Reding cpu@0 { 404cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 405cd6fe32eSThierry Reding device_type = "cpu"; 406cd6fe32eSThierry Reding reg = <0x000>; 407cd6fe32eSThierry Reding }; 408cd6fe32eSThierry Reding 409cd6fe32eSThierry Reding cpu@1 { 410cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 411cd6fe32eSThierry Reding device_type = "cpu"; 412cd6fe32eSThierry Reding reg = <0x001>; 413cd6fe32eSThierry Reding }; 414cd6fe32eSThierry Reding 415cd6fe32eSThierry Reding cpu@2 { 416cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 417cd6fe32eSThierry Reding device_type = "cpu"; 418cd6fe32eSThierry Reding reg = <0x100>; 419cd6fe32eSThierry Reding }; 420cd6fe32eSThierry Reding 421cd6fe32eSThierry Reding cpu@3 { 422cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 423cd6fe32eSThierry Reding device_type = "cpu"; 424cd6fe32eSThierry Reding reg = <0x101>; 425cd6fe32eSThierry Reding }; 426cd6fe32eSThierry Reding 427cd6fe32eSThierry Reding cpu@4 { 428cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 429cd6fe32eSThierry Reding device_type = "cpu"; 430cd6fe32eSThierry Reding reg = <0x102>; 431cd6fe32eSThierry Reding }; 432cd6fe32eSThierry Reding 433cd6fe32eSThierry Reding cpu@5 { 434cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 435cd6fe32eSThierry Reding device_type = "cpu"; 436cd6fe32eSThierry Reding reg = <0x103>; 437cd6fe32eSThierry Reding }; 438cd6fe32eSThierry Reding }; 439cd6fe32eSThierry Reding 44039cb62cbSJoseph Lo bpmp: bpmp { 44139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 4425edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 4435edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 44439cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 44539cb62cbSJoseph Lo #clock-cells = <1>; 44639cb62cbSJoseph Lo #reset-cells = <1>; 44739cb62cbSJoseph Lo 44839cb62cbSJoseph Lo bpmp_i2c: i2c { 44939cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 45039cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 45139cb62cbSJoseph Lo #address-cells = <1>; 45239cb62cbSJoseph Lo #size-cells = <0>; 45339cb62cbSJoseph Lo status = "disabled"; 45439cb62cbSJoseph Lo }; 45539cb62cbSJoseph Lo }; 45639cb62cbSJoseph Lo 45739cb62cbSJoseph Lo timer { 45839cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 45939cb62cbSJoseph Lo interrupts = <GIC_PPI 13 46039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46139cb62cbSJoseph Lo <GIC_PPI 14 46239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46339cb62cbSJoseph Lo <GIC_PPI 11 46439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 46539cb62cbSJoseph Lo <GIC_PPI 10 46639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 46739cb62cbSJoseph Lo interrupt-parent = <&gic>; 46839cb62cbSJoseph Lo }; 46939cb62cbSJoseph Lo}; 470