1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112835553b3SAkhil R #dma-cells = <1>; 113835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114835553b3SAkhil R dma-coherent; 115835553b3SAkhil R status = "okay"; 116835553b3SAkhil R }; 117835553b3SAkhil R 1184b154b94SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1815d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1825d2249ddSSameer Pujar clock-names = "clk"; 1835d2249ddSSameer Pujar status = "disabled"; 1845d2249ddSSameer Pujar }; 185177208f7SSameer Pujar 186177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 187177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 188177208f7SSameer Pujar reg = <0x02900800 0x800>; 189177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 190177208f7SSameer Pujar clock-names = "ahub"; 191177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193177208f7SSameer Pujar #address-cells = <1>; 194177208f7SSameer Pujar #size-cells = <1>; 195177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 196177208f7SSameer Pujar status = "disabled"; 197177208f7SSameer Pujar 198177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 199177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 200177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 201177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 202177208f7SSameer Pujar <&adma 2>, <&adma 2>, 203177208f7SSameer Pujar <&adma 3>, <&adma 3>, 204177208f7SSameer Pujar <&adma 4>, <&adma 4>, 205177208f7SSameer Pujar <&adma 5>, <&adma 5>, 206177208f7SSameer Pujar <&adma 6>, <&adma 6>, 207177208f7SSameer Pujar <&adma 7>, <&adma 7>, 208177208f7SSameer Pujar <&adma 8>, <&adma 8>, 209177208f7SSameer Pujar <&adma 9>, <&adma 9>, 210177208f7SSameer Pujar <&adma 10>, <&adma 10>, 211177208f7SSameer Pujar <&adma 11>, <&adma 11>, 212177208f7SSameer Pujar <&adma 12>, <&adma 12>, 213177208f7SSameer Pujar <&adma 13>, <&adma 13>, 214177208f7SSameer Pujar <&adma 14>, <&adma 14>, 215177208f7SSameer Pujar <&adma 15>, <&adma 15>, 216177208f7SSameer Pujar <&adma 16>, <&adma 16>, 217177208f7SSameer Pujar <&adma 17>, <&adma 17>, 218177208f7SSameer Pujar <&adma 18>, <&adma 18>, 219177208f7SSameer Pujar <&adma 19>, <&adma 19>, 220177208f7SSameer Pujar <&adma 20>, <&adma 20>; 221177208f7SSameer Pujar dma-names = "rx1", "tx1", 222177208f7SSameer Pujar "rx2", "tx2", 223177208f7SSameer Pujar "rx3", "tx3", 224177208f7SSameer Pujar "rx4", "tx4", 225177208f7SSameer Pujar "rx5", "tx5", 226177208f7SSameer Pujar "rx6", "tx6", 227177208f7SSameer Pujar "rx7", "tx7", 228177208f7SSameer Pujar "rx8", "tx8", 229177208f7SSameer Pujar "rx9", "tx9", 230177208f7SSameer Pujar "rx10", "tx10", 231177208f7SSameer Pujar "rx11", "tx11", 232177208f7SSameer Pujar "rx12", "tx12", 233177208f7SSameer Pujar "rx13", "tx13", 234177208f7SSameer Pujar "rx14", "tx14", 235177208f7SSameer Pujar "rx15", "tx15", 236177208f7SSameer Pujar "rx16", "tx16", 237177208f7SSameer Pujar "rx17", "tx17", 238177208f7SSameer Pujar "rx18", "tx18", 239177208f7SSameer Pujar "rx19", "tx19", 240177208f7SSameer Pujar "rx20", "tx20"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901000 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S1"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901100 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S2"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901200 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S3"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 287177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 288177208f7SSameer Pujar "nvidia,tegra210-i2s"; 289177208f7SSameer Pujar reg = <0x2901300 0x100>; 290177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 291177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 293177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295177208f7SSameer Pujar assigned-clock-rates = <1536000>; 296177208f7SSameer Pujar sound-name-prefix = "I2S4"; 297177208f7SSameer Pujar status = "disabled"; 298177208f7SSameer Pujar }; 299177208f7SSameer Pujar 300177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 301177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 302177208f7SSameer Pujar "nvidia,tegra210-i2s"; 303177208f7SSameer Pujar reg = <0x2901400 0x100>; 304177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 305177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <1536000>; 310177208f7SSameer Pujar sound-name-prefix = "I2S5"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 315177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 316177208f7SSameer Pujar "nvidia,tegra210-i2s"; 317177208f7SSameer Pujar reg = <0x2901500 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 319177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 321177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323177208f7SSameer Pujar assigned-clock-rates = <1536000>; 324177208f7SSameer Pujar sound-name-prefix = "I2S6"; 325177208f7SSameer Pujar status = "disabled"; 326177208f7SSameer Pujar }; 327177208f7SSameer Pujar 328177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 329177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904000 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 341177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 342177208f7SSameer Pujar reg = <0x2904100 0x100>; 343177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344177208f7SSameer Pujar clock-names = "dmic"; 345177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347177208f7SSameer Pujar assigned-clock-rates = <3072000>; 348177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 349177208f7SSameer Pujar status = "disabled"; 350177208f7SSameer Pujar }; 351177208f7SSameer Pujar 352177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 353177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 354177208f7SSameer Pujar reg = <0x2904200 0x100>; 355177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356177208f7SSameer Pujar clock-names = "dmic"; 357177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359177208f7SSameer Pujar assigned-clock-rates = <3072000>; 360177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 361177208f7SSameer Pujar status = "disabled"; 362177208f7SSameer Pujar }; 363177208f7SSameer Pujar 364177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 365177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 366177208f7SSameer Pujar reg = <0x2904300 0x100>; 367177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368177208f7SSameer Pujar clock-names = "dmic"; 369177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371177208f7SSameer Pujar assigned-clock-rates = <3072000>; 372177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 373177208f7SSameer Pujar status = "disabled"; 374177208f7SSameer Pujar }; 375177208f7SSameer Pujar 376177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 377177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 378177208f7SSameer Pujar reg = <0x2905000 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380177208f7SSameer Pujar clock-names = "dspk"; 381177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383177208f7SSameer Pujar assigned-clock-rates = <12288000>; 384177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 385177208f7SSameer Pujar status = "disabled"; 386177208f7SSameer Pujar }; 387177208f7SSameer Pujar 388177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 389177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 390177208f7SSameer Pujar reg = <0x2905100 0x100>; 391177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392177208f7SSameer Pujar clock-names = "dspk"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <12288000>; 396177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399848f3290SSameer Pujar 400848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 401848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 402848f3290SSameer Pujar "nvidia,tegra210-sfc"; 403848f3290SSameer Pujar reg = <0x2902000 0x200>; 404848f3290SSameer Pujar sound-name-prefix = "SFC1"; 405848f3290SSameer Pujar status = "disabled"; 406848f3290SSameer Pujar }; 407848f3290SSameer Pujar 408848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 409848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 410848f3290SSameer Pujar "nvidia,tegra210-sfc"; 411848f3290SSameer Pujar reg = <0x2902200 0x200>; 412848f3290SSameer Pujar sound-name-prefix = "SFC2"; 413848f3290SSameer Pujar status = "disabled"; 414848f3290SSameer Pujar }; 415848f3290SSameer Pujar 416848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 417848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 418848f3290SSameer Pujar "nvidia,tegra210-sfc"; 419848f3290SSameer Pujar reg = <0x2902400 0x200>; 420848f3290SSameer Pujar sound-name-prefix = "SFC3"; 421848f3290SSameer Pujar status = "disabled"; 422848f3290SSameer Pujar }; 423848f3290SSameer Pujar 424848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 425848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 426848f3290SSameer Pujar "nvidia,tegra210-sfc"; 427848f3290SSameer Pujar reg = <0x2902600 0x200>; 428848f3290SSameer Pujar sound-name-prefix = "SFC4"; 429848f3290SSameer Pujar status = "disabled"; 430848f3290SSameer Pujar }; 431848f3290SSameer Pujar 432848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 433848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 434848f3290SSameer Pujar "nvidia,tegra210-mvc"; 435848f3290SSameer Pujar reg = <0x290a000 0x200>; 436848f3290SSameer Pujar sound-name-prefix = "MVC1"; 437848f3290SSameer Pujar status = "disabled"; 438848f3290SSameer Pujar }; 439848f3290SSameer Pujar 440848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 441848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 442848f3290SSameer Pujar "nvidia,tegra210-mvc"; 443848f3290SSameer Pujar reg = <0x290a200 0x200>; 444848f3290SSameer Pujar sound-name-prefix = "MVC2"; 445848f3290SSameer Pujar status = "disabled"; 446848f3290SSameer Pujar }; 447848f3290SSameer Pujar 448848f3290SSameer Pujar tegra_amx1: amx@2903000 { 449848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 450848f3290SSameer Pujar "nvidia,tegra210-amx"; 451848f3290SSameer Pujar reg = <0x2903000 0x100>; 452848f3290SSameer Pujar sound-name-prefix = "AMX1"; 453848f3290SSameer Pujar status = "disabled"; 454848f3290SSameer Pujar }; 455848f3290SSameer Pujar 456848f3290SSameer Pujar tegra_amx2: amx@2903100 { 457848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 458848f3290SSameer Pujar "nvidia,tegra210-amx"; 459848f3290SSameer Pujar reg = <0x2903100 0x100>; 460848f3290SSameer Pujar sound-name-prefix = "AMX2"; 461848f3290SSameer Pujar status = "disabled"; 462848f3290SSameer Pujar }; 463848f3290SSameer Pujar 464848f3290SSameer Pujar tegra_amx3: amx@2903200 { 465848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 466848f3290SSameer Pujar "nvidia,tegra210-amx"; 467848f3290SSameer Pujar reg = <0x2903200 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX3"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx4: amx@2903300 { 473848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 474848f3290SSameer Pujar "nvidia,tegra210-amx"; 475848f3290SSameer Pujar reg = <0x2903300 0x100>; 476848f3290SSameer Pujar sound-name-prefix = "AMX4"; 477848f3290SSameer Pujar status = "disabled"; 478848f3290SSameer Pujar }; 479848f3290SSameer Pujar 480848f3290SSameer Pujar tegra_adx1: adx@2903800 { 481848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 482848f3290SSameer Pujar "nvidia,tegra210-adx"; 483848f3290SSameer Pujar reg = <0x2903800 0x100>; 484848f3290SSameer Pujar sound-name-prefix = "ADX1"; 485848f3290SSameer Pujar status = "disabled"; 486848f3290SSameer Pujar }; 487848f3290SSameer Pujar 488848f3290SSameer Pujar tegra_adx2: adx@2903900 { 489848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 490848f3290SSameer Pujar "nvidia,tegra210-adx"; 491848f3290SSameer Pujar reg = <0x2903900 0x100>; 492848f3290SSameer Pujar sound-name-prefix = "ADX2"; 493848f3290SSameer Pujar status = "disabled"; 494848f3290SSameer Pujar }; 495848f3290SSameer Pujar 496848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 497848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 498848f3290SSameer Pujar "nvidia,tegra210-adx"; 499848f3290SSameer Pujar reg = <0x2903a00 0x100>; 500848f3290SSameer Pujar sound-name-prefix = "ADX3"; 501848f3290SSameer Pujar status = "disabled"; 502848f3290SSameer Pujar }; 503848f3290SSameer Pujar 504848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 505848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 506848f3290SSameer Pujar "nvidia,tegra210-adx"; 507848f3290SSameer Pujar reg = <0x2903b00 0x100>; 508848f3290SSameer Pujar sound-name-prefix = "ADX4"; 509848f3290SSameer Pujar status = "disabled"; 510848f3290SSameer Pujar }; 511848f3290SSameer Pujar 5124b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5134b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-ope", 5144b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5154b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5164b6a1b7cSSameer Pujar #address-cells = <1>; 5174b6a1b7cSSameer Pujar #size-cells = <1>; 5184b6a1b7cSSameer Pujar ranges; 5194b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5204b6a1b7cSSameer Pujar status = "disabled"; 5214b6a1b7cSSameer Pujar 5224b6a1b7cSSameer Pujar equalizer@2908100 { 5234b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-peq", 5244b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5254b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 5264b6a1b7cSSameer Pujar }; 5274b6a1b7cSSameer Pujar 5284b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 5294b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-mbdrc", 5304b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 5314b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 5324b6a1b7cSSameer Pujar }; 5334b6a1b7cSSameer Pujar }; 5344b6a1b7cSSameer Pujar 535848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 536848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 537848f3290SSameer Pujar "nvidia,tegra210-amixer"; 538848f3290SSameer Pujar reg = <0x290bb00 0x800>; 539848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 540848f3290SSameer Pujar status = "disabled"; 541848f3290SSameer Pujar }; 54247a08153SSameer Pujar 54347a08153SSameer Pujar tegra_asrc: asrc@2910000 { 54447a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 54547a08153SSameer Pujar reg = <0x2910000 0x2000>; 54647a08153SSameer Pujar sound-name-prefix = "ASRC1"; 54747a08153SSameer Pujar status = "disabled"; 54847a08153SSameer Pujar }; 549177208f7SSameer Pujar }; 5505d2249ddSSameer Pujar }; 5515d2249ddSSameer Pujar 552954490b3SThierry Reding mc: memory-controller@2c00000 { 553d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 554000b99e5SAshish Mhetre reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 555000b99e5SAshish Mhetre <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 556000b99e5SAshish Mhetre <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 557000b99e5SAshish Mhetre <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 558000b99e5SAshish Mhetre <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 559000b99e5SAshish Mhetre <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 560000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 561b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 562d25a3bf1SThierry Reding status = "disabled"; 5633f6eaef9SThierry Reding 564954490b3SThierry Reding #interconnect-cells = <1>; 5653f6eaef9SThierry Reding #address-cells = <2>; 5663f6eaef9SThierry Reding #size-cells = <2>; 5673f6eaef9SThierry Reding 5683f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5693f6eaef9SThierry Reding 5703f6eaef9SThierry Reding /* 5713f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5723f6eaef9SThierry Reding * controller can address. 5733f6eaef9SThierry Reding */ 5743f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5753f6eaef9SThierry Reding 5763f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5773f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5783f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5793f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5803f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5813f6eaef9SThierry Reding clock-names = "emc"; 5823f6eaef9SThierry Reding 583954490b3SThierry Reding #interconnect-cells = <0>; 584954490b3SThierry Reding 5853f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5863f6eaef9SThierry Reding }; 587d25a3bf1SThierry Reding }; 588d25a3bf1SThierry Reding 589bd1fefcbSThierry Reding timer@3010000 { 590bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 591bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 592bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 593bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 594bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 595bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 596bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 599bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 600bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 601bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 602c710ac0bSKartik status = "okay"; 603bd1fefcbSThierry Reding }; 604bd1fefcbSThierry Reding 60539cb62cbSJoseph Lo uarta: serial@3100000 { 60639cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 60739cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 60839cb62cbSJoseph Lo reg-shift = <2>; 60939cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 611a7a77e2eSThierry Reding clock-names = "serial"; 6127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 613a7a77e2eSThierry Reding reset-names = "serial"; 614a7a77e2eSThierry Reding status = "disabled"; 615a7a77e2eSThierry Reding }; 616a7a77e2eSThierry Reding 617a7a77e2eSThierry Reding uartb: serial@3110000 { 618a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 620a7a77e2eSThierry Reding reg-shift = <2>; 621a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 623a7a77e2eSThierry Reding clock-names = "serial"; 6247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 625a7a77e2eSThierry Reding reset-names = "serial"; 626a7a77e2eSThierry Reding status = "disabled"; 627a7a77e2eSThierry Reding }; 628a7a77e2eSThierry Reding 629a7a77e2eSThierry Reding uartd: serial@3130000 { 630a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 632a7a77e2eSThierry Reding reg-shift = <2>; 633a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 635a7a77e2eSThierry Reding clock-names = "serial"; 6367bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 637a7a77e2eSThierry Reding reset-names = "serial"; 638a7a77e2eSThierry Reding status = "disabled"; 639a7a77e2eSThierry Reding }; 640a7a77e2eSThierry Reding 641a7a77e2eSThierry Reding uarte: serial@3140000 { 642a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 644a7a77e2eSThierry Reding reg-shift = <2>; 645a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 647a7a77e2eSThierry Reding clock-names = "serial"; 6487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 649a7a77e2eSThierry Reding reset-names = "serial"; 650a7a77e2eSThierry Reding status = "disabled"; 651a7a77e2eSThierry Reding }; 652a7a77e2eSThierry Reding 653a7a77e2eSThierry Reding uartf: serial@3150000 { 654a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 656a7a77e2eSThierry Reding reg-shift = <2>; 657a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 659a7a77e2eSThierry Reding clock-names = "serial"; 6607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 661a7a77e2eSThierry Reding reset-names = "serial"; 66239cb62cbSJoseph Lo status = "disabled"; 66339cb62cbSJoseph Lo }; 66439cb62cbSJoseph Lo 66540cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 666548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 66740cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 66840cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 66940cc83b3SThierry Reding #address-cells = <1>; 67040cc83b3SThierry Reding #size-cells = <0>; 671c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 67240cc83b3SThierry Reding clock-names = "div-clk"; 6737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 67440cc83b3SThierry Reding reset-names = "i2c"; 67540cc83b3SThierry Reding status = "disabled"; 67640cc83b3SThierry Reding }; 67740cc83b3SThierry Reding 67840cc83b3SThierry Reding cam_i2c: i2c@3180000 { 679548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68040cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 68140cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 68240cc83b3SThierry Reding #address-cells = <1>; 68340cc83b3SThierry Reding #size-cells = <0>; 684c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 68540cc83b3SThierry Reding clock-names = "div-clk"; 6867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 68740cc83b3SThierry Reding reset-names = "i2c"; 68840cc83b3SThierry Reding status = "disabled"; 68940cc83b3SThierry Reding }; 69040cc83b3SThierry Reding 69140cc83b3SThierry Reding /* shares pads with dpaux1 */ 69240cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 693548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 69440cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 69540cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 69640cc83b3SThierry Reding #address-cells = <1>; 69740cc83b3SThierry Reding #size-cells = <0>; 698c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 69940cc83b3SThierry Reding clock-names = "div-clk"; 7007bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 70140cc83b3SThierry Reding reset-names = "i2c"; 702846137c6SThierry Reding pinctrl-names = "default", "idle"; 703846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 704846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 70540cc83b3SThierry Reding status = "disabled"; 70640cc83b3SThierry Reding }; 70740cc83b3SThierry Reding 70840cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 70940cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 710548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 71140cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 71240cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 71340cc83b3SThierry Reding #address-cells = <1>; 71440cc83b3SThierry Reding #size-cells = <0>; 715c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 71640cc83b3SThierry Reding clock-names = "div-clk"; 7177bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 71840cc83b3SThierry Reding reset-names = "i2c"; 71940cc83b3SThierry Reding status = "disabled"; 72040cc83b3SThierry Reding }; 72140cc83b3SThierry Reding 72240cc83b3SThierry Reding /* shares pads with dpaux0 */ 72340cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 724548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 72540cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 72640cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 72740cc83b3SThierry Reding #address-cells = <1>; 72840cc83b3SThierry Reding #size-cells = <0>; 729c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 73040cc83b3SThierry Reding clock-names = "div-clk"; 7317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 73240cc83b3SThierry Reding reset-names = "i2c"; 733846137c6SThierry Reding pinctrl-names = "default", "idle"; 734846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 735846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 73640cc83b3SThierry Reding status = "disabled"; 73740cc83b3SThierry Reding }; 73840cc83b3SThierry Reding 73940cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 740548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 74140cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 74240cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 74340cc83b3SThierry Reding #address-cells = <1>; 74440cc83b3SThierry Reding #size-cells = <0>; 745c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 74640cc83b3SThierry Reding clock-names = "div-clk"; 7477bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 74840cc83b3SThierry Reding reset-names = "i2c"; 74940cc83b3SThierry Reding status = "disabled"; 75040cc83b3SThierry Reding }; 75140cc83b3SThierry Reding 75240cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 753548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 75440cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 75540cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 75640cc83b3SThierry Reding #address-cells = <1>; 75740cc83b3SThierry Reding #size-cells = <0>; 758c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 75940cc83b3SThierry Reding clock-names = "div-clk"; 7607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 76140cc83b3SThierry Reding reset-names = "i2c"; 76240cc83b3SThierry Reding status = "disabled"; 76340cc83b3SThierry Reding }; 76440cc83b3SThierry Reding 765913f8ad4SThierry Reding pwm1: pwm@3280000 { 766913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 767913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 768913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 769913f8ad4SThierry Reding clock-names = "pwm"; 770913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 771913f8ad4SThierry Reding reset-names = "pwm"; 772913f8ad4SThierry Reding status = "disabled"; 773913f8ad4SThierry Reding #pwm-cells = <2>; 774913f8ad4SThierry Reding }; 775913f8ad4SThierry Reding 776913f8ad4SThierry Reding pwm2: pwm@3290000 { 777913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 778913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 779913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 780913f8ad4SThierry Reding clock-names = "pwm"; 781913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 782913f8ad4SThierry Reding reset-names = "pwm"; 783913f8ad4SThierry Reding status = "disabled"; 784913f8ad4SThierry Reding #pwm-cells = <2>; 785913f8ad4SThierry Reding }; 786913f8ad4SThierry Reding 787913f8ad4SThierry Reding pwm3: pwm@32a0000 { 788913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 789913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 790913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 791913f8ad4SThierry Reding clock-names = "pwm"; 792913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 793913f8ad4SThierry Reding reset-names = "pwm"; 794913f8ad4SThierry Reding status = "disabled"; 795913f8ad4SThierry Reding #pwm-cells = <2>; 796913f8ad4SThierry Reding }; 797913f8ad4SThierry Reding 798913f8ad4SThierry Reding pwm5: pwm@32c0000 { 799913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 800913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 801913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 802913f8ad4SThierry Reding clock-names = "pwm"; 803913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 804913f8ad4SThierry Reding reset-names = "pwm"; 805913f8ad4SThierry Reding status = "disabled"; 806913f8ad4SThierry Reding #pwm-cells = <2>; 807913f8ad4SThierry Reding }; 808913f8ad4SThierry Reding 809913f8ad4SThierry Reding pwm6: pwm@32d0000 { 810913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 811913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 812913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 813913f8ad4SThierry Reding clock-names = "pwm"; 814913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 815913f8ad4SThierry Reding reset-names = "pwm"; 816913f8ad4SThierry Reding status = "disabled"; 817913f8ad4SThierry Reding #pwm-cells = <2>; 818913f8ad4SThierry Reding }; 819913f8ad4SThierry Reding 820913f8ad4SThierry Reding pwm7: pwm@32e0000 { 821913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 822913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 823913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 824913f8ad4SThierry Reding clock-names = "pwm"; 825913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 826913f8ad4SThierry Reding reset-names = "pwm"; 827913f8ad4SThierry Reding status = "disabled"; 828913f8ad4SThierry Reding #pwm-cells = <2>; 829913f8ad4SThierry Reding }; 830913f8ad4SThierry Reding 831913f8ad4SThierry Reding pwm8: pwm@32f0000 { 832913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 833913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 834913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 835913f8ad4SThierry Reding clock-names = "pwm"; 836913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 837913f8ad4SThierry Reding reset-names = "pwm"; 838913f8ad4SThierry Reding status = "disabled"; 839913f8ad4SThierry Reding #pwm-cells = <2>; 840913f8ad4SThierry Reding }; 841913f8ad4SThierry Reding 84267bb17f6SThierry Reding sdmmc1: mmc@3400000 { 84399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 84499425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 84599425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 846baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 847baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 848baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8497bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 85099425dfdSThierry Reding reset-names = "sdhci"; 851954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 852954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 853954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8548589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 85524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 85624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 85724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 85841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 85941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 86041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 86141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 86241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 86341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8646f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8656f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 86698a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 86798a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 86898a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 86999425dfdSThierry Reding status = "disabled"; 87099425dfdSThierry Reding }; 87199425dfdSThierry Reding 87267bb17f6SThierry Reding sdmmc2: mmc@3420000 { 87399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 87499425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 87599425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 876baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 877baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 878baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8797bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 88099425dfdSThierry Reding reset-names = "sdhci"; 881954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 882954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 883954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8848589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 88524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 88624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 88724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 88841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 88941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 89041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 89141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8926f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8936f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 89499425dfdSThierry Reding status = "disabled"; 89599425dfdSThierry Reding }; 89699425dfdSThierry Reding 89767bb17f6SThierry Reding sdmmc3: mmc@3440000 { 89899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 89999425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 90099425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 901baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 902baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 903baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9047bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 90599425dfdSThierry Reding reset-names = "sdhci"; 906954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 907954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 908954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9098589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 91024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 91124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 91224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 91341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 91441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 91541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 91641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 91741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 91841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9196f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9206f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 92199425dfdSThierry Reding status = "disabled"; 92299425dfdSThierry Reding }; 92399425dfdSThierry Reding 92467bb17f6SThierry Reding sdmmc4: mmc@3460000 { 92599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 92699425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 92799425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 928baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 929baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 930baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 93198a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 93298a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 93398a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 93599425dfdSThierry Reding reset-names = "sdhci"; 936954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 937954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 938954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9398589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 94041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 94141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 94241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 94341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9444e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9454e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 946e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 947e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 94822248e91SAapo Vienamo nvidia,dqs-trim = <63>; 949207f60baSAapo Vienamo mmc-hs400-1_8v; 950c4307836SSowjanya Komatineni supports-cqe; 95199425dfdSThierry Reding status = "disabled"; 95299425dfdSThierry Reding }; 95399425dfdSThierry Reding 954b066a310SThierry Reding hda@3510000 { 955b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 956b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 957b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 958b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 959b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 960b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 961b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 962b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 963b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 964b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 965b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 966b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 967954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 968954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 969954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 970dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 971b066a310SThierry Reding status = "disabled"; 972b066a310SThierry Reding }; 973b066a310SThierry Reding 9748bfde518SThierry Reding padctl: padctl@3520000 { 9758bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 9768bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 9778bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 9788bfde518SThierry Reding reg-names = "padctl", "ao"; 9796450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 9808bfde518SThierry Reding 9818bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 9828bfde518SThierry Reding reset-names = "padctl"; 9838bfde518SThierry Reding 9848bfde518SThierry Reding status = "disabled"; 9858bfde518SThierry Reding 9868bfde518SThierry Reding pads { 9878bfde518SThierry Reding usb2 { 9888bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 9898bfde518SThierry Reding clock-names = "trk"; 9908bfde518SThierry Reding status = "disabled"; 9918bfde518SThierry Reding 9928bfde518SThierry Reding lanes { 9938bfde518SThierry Reding usb2-0 { 9948bfde518SThierry Reding status = "disabled"; 9958bfde518SThierry Reding #phy-cells = <0>; 9968bfde518SThierry Reding }; 9978bfde518SThierry Reding 9988bfde518SThierry Reding usb2-1 { 9998bfde518SThierry Reding status = "disabled"; 10008bfde518SThierry Reding #phy-cells = <0>; 10018bfde518SThierry Reding }; 10028bfde518SThierry Reding 10038bfde518SThierry Reding usb2-2 { 10048bfde518SThierry Reding status = "disabled"; 10058bfde518SThierry Reding #phy-cells = <0>; 10068bfde518SThierry Reding }; 10078bfde518SThierry Reding }; 10088bfde518SThierry Reding }; 10098bfde518SThierry Reding 10108bfde518SThierry Reding hsic { 10118bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 10128bfde518SThierry Reding clock-names = "trk"; 10138bfde518SThierry Reding status = "disabled"; 10148bfde518SThierry Reding 10158bfde518SThierry Reding lanes { 10168bfde518SThierry Reding hsic-0 { 10178bfde518SThierry Reding status = "disabled"; 10188bfde518SThierry Reding #phy-cells = <0>; 10198bfde518SThierry Reding }; 10208bfde518SThierry Reding }; 10218bfde518SThierry Reding }; 10228bfde518SThierry Reding 10238bfde518SThierry Reding usb3 { 10248bfde518SThierry Reding status = "disabled"; 10258bfde518SThierry Reding 10268bfde518SThierry Reding lanes { 10278bfde518SThierry Reding usb3-0 { 10288bfde518SThierry Reding status = "disabled"; 10298bfde518SThierry Reding #phy-cells = <0>; 10308bfde518SThierry Reding }; 10318bfde518SThierry Reding 10328bfde518SThierry Reding usb3-1 { 10338bfde518SThierry Reding status = "disabled"; 10348bfde518SThierry Reding #phy-cells = <0>; 10358bfde518SThierry Reding }; 10368bfde518SThierry Reding 10378bfde518SThierry Reding usb3-2 { 10388bfde518SThierry Reding status = "disabled"; 10398bfde518SThierry Reding #phy-cells = <0>; 10408bfde518SThierry Reding }; 10418bfde518SThierry Reding }; 10428bfde518SThierry Reding }; 10438bfde518SThierry Reding }; 10448bfde518SThierry Reding 10458bfde518SThierry Reding ports { 10468bfde518SThierry Reding usb2-0 { 10478bfde518SThierry Reding status = "disabled"; 10488bfde518SThierry Reding }; 10498bfde518SThierry Reding 10508bfde518SThierry Reding usb2-1 { 10518bfde518SThierry Reding status = "disabled"; 10528bfde518SThierry Reding }; 10538bfde518SThierry Reding 10548bfde518SThierry Reding usb2-2 { 10558bfde518SThierry Reding status = "disabled"; 10568bfde518SThierry Reding }; 10578bfde518SThierry Reding 10588bfde518SThierry Reding hsic-0 { 10598bfde518SThierry Reding status = "disabled"; 10608bfde518SThierry Reding }; 10618bfde518SThierry Reding 10628bfde518SThierry Reding usb3-0 { 10638bfde518SThierry Reding status = "disabled"; 10648bfde518SThierry Reding }; 10658bfde518SThierry Reding 10668bfde518SThierry Reding usb3-1 { 10678bfde518SThierry Reding status = "disabled"; 10688bfde518SThierry Reding }; 10698bfde518SThierry Reding 10708bfde518SThierry Reding usb3-2 { 10718bfde518SThierry Reding status = "disabled"; 10728bfde518SThierry Reding }; 10738bfde518SThierry Reding }; 10748bfde518SThierry Reding }; 10758bfde518SThierry Reding 10768bfde518SThierry Reding usb@3530000 { 10778bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 10788bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 10798bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 10808bfde518SThierry Reding reg-names = "hcd", "fpci"; 10818bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1082a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 10838bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 10848bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 10858bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 10868bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 10878bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10888bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 10898bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 10908bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10918bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 10928bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 10938bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 10948bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 10958bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 10968bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 10978bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1098954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1099954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1100954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 110106c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 11028bfde518SThierry Reding #address-cells = <1>; 11038bfde518SThierry Reding #size-cells = <0>; 110406c6b06fSThierry Reding status = "disabled"; 110506c6b06fSThierry Reding 110606c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 11078bfde518SThierry Reding }; 11088bfde518SThierry Reding 1109584f800cSNagarjuna Kristam usb@3550000 { 1110584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1111584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1112584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1113584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1114584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1115584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1116584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1117584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1118584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1119584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1120d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1121d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1122d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1123584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1124584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1125584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1126584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1127584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1128584f800cSNagarjuna Kristam status = "disabled"; 1129584f800cSNagarjuna Kristam }; 1130584f800cSNagarjuna Kristam 113185593b75SThierry Reding fuse@3820000 { 113285593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 113385593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 113485593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 113585593b75SThierry Reding clock-names = "fuse"; 113685593b75SThierry Reding }; 113785593b75SThierry Reding 113839cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 113939cb62cbSJoseph Lo compatible = "arm,gic-400"; 114039cb62cbSJoseph Lo #interrupt-cells = <3>; 114139cb62cbSJoseph Lo interrupt-controller; 114239cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1143776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1144776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1145776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 114639cb62cbSJoseph Lo interrupts = <GIC_PPI 9 114739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 114839cb62cbSJoseph Lo interrupt-parent = <&gic>; 114939cb62cbSJoseph Lo }; 115039cb62cbSJoseph Lo 115197cf683cSThierry Reding cec@3960000 { 115297cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 115397cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 115497cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 115597cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 115697cf683cSThierry Reding clock-names = "cec"; 115797cf683cSThierry Reding status = "disabled"; 115897cf683cSThierry Reding }; 115997cf683cSThierry Reding 116039cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 116139cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 116239cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 116339cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 116439cb62cbSJoseph Lo interrupt-names = "doorbell"; 116539cb62cbSJoseph Lo #mbox-cells = <2>; 116639cb62cbSJoseph Lo status = "disabled"; 116739cb62cbSJoseph Lo }; 116839cb62cbSJoseph Lo 116940cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1170548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 117140cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 117240cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 117340cc83b3SThierry Reding #address-cells = <1>; 117440cc83b3SThierry Reding #size-cells = <0>; 1175c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 117640cc83b3SThierry Reding clock-names = "div-clk"; 11777bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 117840cc83b3SThierry Reding reset-names = "i2c"; 117940cc83b3SThierry Reding status = "disabled"; 118040cc83b3SThierry Reding }; 118140cc83b3SThierry Reding 118240cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1183548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 118440cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 118540cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 118640cc83b3SThierry Reding #address-cells = <1>; 118740cc83b3SThierry Reding #size-cells = <0>; 1188c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 118940cc83b3SThierry Reding clock-names = "div-clk"; 11907bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 119140cc83b3SThierry Reding reset-names = "i2c"; 119240cc83b3SThierry Reding status = "disabled"; 119340cc83b3SThierry Reding }; 119440cc83b3SThierry Reding 1195a7a77e2eSThierry Reding uartc: serial@c280000 { 1196a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1197a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1198a7a77e2eSThierry Reding reg-shift = <2>; 1199a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1200c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1201a7a77e2eSThierry Reding clock-names = "serial"; 12027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1203a7a77e2eSThierry Reding reset-names = "serial"; 1204a7a77e2eSThierry Reding status = "disabled"; 1205a7a77e2eSThierry Reding }; 1206a7a77e2eSThierry Reding 1207a7a77e2eSThierry Reding uartg: serial@c290000 { 1208a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1209a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1210a7a77e2eSThierry Reding reg-shift = <2>; 1211a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1212c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1213a7a77e2eSThierry Reding clock-names = "serial"; 12147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1215a7a77e2eSThierry Reding reset-names = "serial"; 1216a7a77e2eSThierry Reding status = "disabled"; 1217a7a77e2eSThierry Reding }; 1218a7a77e2eSThierry Reding 12199733a251SThierry Reding rtc: rtc@c2a0000 { 12209733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 12219733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 12229733a251SThierry Reding interrupt-parent = <&pmc>; 12239733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 12249733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 12259733a251SThierry Reding clock-names = "rtc"; 12269733a251SThierry Reding status = "disabled"; 12279733a251SThierry Reding }; 12289733a251SThierry Reding 1229fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1230fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1231fc4bb754SThierry Reding reg-names = "security", "gpio"; 1232fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1233fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1234fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1235fc4bb754SThierry Reding gpio-controller; 1236fc4bb754SThierry Reding #gpio-cells = <2>; 1237fc4bb754SThierry Reding interrupt-controller; 1238fc4bb754SThierry Reding #interrupt-cells = <2>; 1239fc4bb754SThierry Reding }; 1240fc4bb754SThierry Reding 1241913f8ad4SThierry Reding pwm4: pwm@c340000 { 1242913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1243913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1244913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1245913f8ad4SThierry Reding clock-names = "pwm"; 1246913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1247913f8ad4SThierry Reding reset-names = "pwm"; 1248913f8ad4SThierry Reding status = "disabled"; 1249913f8ad4SThierry Reding #pwm-cells = <2>; 1250913f8ad4SThierry Reding }; 1251913f8ad4SThierry Reding 125232e66e46SThierry Reding pmc: pmc@c360000 { 125373bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 125473bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 125573bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 125673bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 125773bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 125873bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 125924005fd1SAapo Vienamo 126032e66e46SThierry Reding #interrupt-cells = <2>; 126132e66e46SThierry Reding interrupt-controller; 126232e66e46SThierry Reding 126324005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 126424005fd1SAapo Vienamo pins = "sdmmc1-hv"; 126524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 126624005fd1SAapo Vienamo }; 126724005fd1SAapo Vienamo 126824005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 126924005fd1SAapo Vienamo pins = "sdmmc1-hv"; 127024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 127124005fd1SAapo Vienamo }; 127224005fd1SAapo Vienamo 127324005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 127424005fd1SAapo Vienamo pins = "sdmmc2-hv"; 127524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 127624005fd1SAapo Vienamo }; 127724005fd1SAapo Vienamo 127824005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 127924005fd1SAapo Vienamo pins = "sdmmc2-hv"; 128024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 128124005fd1SAapo Vienamo }; 128224005fd1SAapo Vienamo 128324005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 128424005fd1SAapo Vienamo pins = "sdmmc3-hv"; 128524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 128624005fd1SAapo Vienamo }; 128724005fd1SAapo Vienamo 128824005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 128924005fd1SAapo Vienamo pins = "sdmmc3-hv"; 129024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 129124005fd1SAapo Vienamo }; 129273bf90d4SThierry Reding }; 129373bf90d4SThierry Reding 12947b7ef494SMikko Perttunen ccplex@e000000 { 12957b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 12962b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 12977b7ef494SMikko Perttunen 12987b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 12997b7ef494SMikko Perttunen }; 13007b7ef494SMikko Perttunen 1301f8973cf4SManikanta Maddireddy pcie@10003000 { 1302f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1303f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1304f8973cf4SManikanta Maddireddy device_type = "pci"; 1305644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1306644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1307644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1308f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1309f8973cf4SManikanta Maddireddy 1310f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1311f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1312f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1313f8973cf4SManikanta Maddireddy 1314f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1315f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1316f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1317f8973cf4SManikanta Maddireddy 1318f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1319f8973cf4SManikanta Maddireddy #address-cells = <3>; 1320f8973cf4SManikanta Maddireddy #size-cells = <2>; 1321f8973cf4SManikanta Maddireddy 1322644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1323644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1324644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1325644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1326644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1327644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1328f8973cf4SManikanta Maddireddy 132978b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 133078b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1331f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 133278b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1333f8973cf4SManikanta Maddireddy 133478b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 133578b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1336f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 133778b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1338f8973cf4SManikanta Maddireddy 1339954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1340954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1341954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1342954490b3SThierry Reding 1343f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1344f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1345f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1346f2a465e7SThierry Reding 1347f8973cf4SManikanta Maddireddy status = "disabled"; 1348f8973cf4SManikanta Maddireddy 1349f8973cf4SManikanta Maddireddy pci@1,0 { 1350f8973cf4SManikanta Maddireddy device_type = "pci"; 1351f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1352f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1353f8973cf4SManikanta Maddireddy status = "disabled"; 1354f8973cf4SManikanta Maddireddy 1355f8973cf4SManikanta Maddireddy #address-cells = <3>; 1356f8973cf4SManikanta Maddireddy #size-cells = <2>; 1357f8973cf4SManikanta Maddireddy ranges; 1358f8973cf4SManikanta Maddireddy 1359f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1360f8973cf4SManikanta Maddireddy }; 1361f8973cf4SManikanta Maddireddy 1362f8973cf4SManikanta Maddireddy pci@2,0 { 1363f8973cf4SManikanta Maddireddy device_type = "pci"; 1364f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1365f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1366f8973cf4SManikanta Maddireddy status = "disabled"; 1367f8973cf4SManikanta Maddireddy 1368f8973cf4SManikanta Maddireddy #address-cells = <3>; 1369f8973cf4SManikanta Maddireddy #size-cells = <2>; 1370f8973cf4SManikanta Maddireddy ranges; 1371f8973cf4SManikanta Maddireddy 1372f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1373f8973cf4SManikanta Maddireddy }; 1374f8973cf4SManikanta Maddireddy 1375f8973cf4SManikanta Maddireddy pci@3,0 { 1376f8973cf4SManikanta Maddireddy device_type = "pci"; 1377f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1378f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1379f8973cf4SManikanta Maddireddy status = "disabled"; 1380f8973cf4SManikanta Maddireddy 1381f8973cf4SManikanta Maddireddy #address-cells = <3>; 1382f8973cf4SManikanta Maddireddy #size-cells = <2>; 1383f8973cf4SManikanta Maddireddy ranges; 1384f8973cf4SManikanta Maddireddy 1385f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1386f8973cf4SManikanta Maddireddy }; 1387f8973cf4SManikanta Maddireddy }; 1388f8973cf4SManikanta Maddireddy 1389b30a8e61SThierry Reding smmu: iommu@12000000 { 1390bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1391b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1392b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1457b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1458b30a8e61SThierry Reding #global-interrupts = <1>; 1459b30a8e61SThierry Reding #iommu-cells = <1>; 1460b966d2dbSThierry Reding 1461b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1462b30a8e61SThierry Reding }; 1463b30a8e61SThierry Reding 14645524c61fSMikko Perttunen host1x@13e00000 { 1465ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 14665524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 14675524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 14685524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 14695524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 14705524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1471052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 14725524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 14735524c61fSMikko Perttunen clock-names = "host1x"; 14745524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 14755524c61fSMikko Perttunen reset-names = "host1x"; 14765524c61fSMikko Perttunen 14775524c61fSMikko Perttunen #address-cells = <1>; 14785524c61fSMikko Perttunen #size-cells = <1>; 14795524c61fSMikko Perttunen 14805524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1481954490b3SThierry Reding 1482954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1483954490b3SThierry Reding interconnect-names = "dma-mem"; 1484954490b3SThierry Reding 1485c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1486c2599da7SThierry Reding 1487e30cf101SMikko Perttunen /* Context isolation domains */ 1488*b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1489*b0c1a994SThierry Reding <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1490*b0c1a994SThierry Reding <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1491*b0c1a994SThierry Reding <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1492*b0c1a994SThierry Reding <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1493*b0c1a994SThierry Reding <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1494*b0c1a994SThierry Reding <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1495*b0c1a994SThierry Reding <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1496e30cf101SMikko Perttunen 1497c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1498c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1499c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1500c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1501c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1502c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1503c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1504c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1505c2599da7SThierry Reding reset-names = "dpaux"; 1506c2599da7SThierry Reding status = "disabled"; 1507c2599da7SThierry Reding 1508c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1509c2599da7SThierry Reding 1510c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1511c2599da7SThierry Reding groups = "dpaux-io"; 1512c2599da7SThierry Reding function = "aux"; 1513c2599da7SThierry Reding }; 1514c2599da7SThierry Reding 1515c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1516c2599da7SThierry Reding groups = "dpaux-io"; 1517c2599da7SThierry Reding function = "i2c"; 1518c2599da7SThierry Reding }; 1519c2599da7SThierry Reding 1520c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1521c2599da7SThierry Reding groups = "dpaux-io"; 1522c2599da7SThierry Reding function = "off"; 1523c2599da7SThierry Reding }; 1524c2599da7SThierry Reding 1525c2599da7SThierry Reding i2c-bus { 1526c2599da7SThierry Reding #address-cells = <1>; 1527c2599da7SThierry Reding #size-cells = <0>; 1528c2599da7SThierry Reding }; 1529c2599da7SThierry Reding }; 1530c2599da7SThierry Reding 1531c2599da7SThierry Reding display-hub@15200000 { 1532aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1533ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1534c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1535c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1536c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1537c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1538c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1539c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1540c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1541c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1542c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1543c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1544c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1545c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1546c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1547c2599da7SThierry Reding status = "disabled"; 1548c2599da7SThierry Reding 1549c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1550c2599da7SThierry Reding 1551c2599da7SThierry Reding #address-cells = <1>; 1552c2599da7SThierry Reding #size-cells = <1>; 1553c2599da7SThierry Reding 1554c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1555c2599da7SThierry Reding 1556c2599da7SThierry Reding display@15200000 { 1557c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1558c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1559c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1560c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1561c2599da7SThierry Reding clock-names = "dc"; 1562c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1563c2599da7SThierry Reding reset-names = "dc"; 1564c2599da7SThierry Reding 1565c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1566954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1567954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1568954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1569c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1570c2599da7SThierry Reding 1571c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1572c2599da7SThierry Reding nvidia,head = <0>; 1573c2599da7SThierry Reding }; 1574c2599da7SThierry Reding 1575c2599da7SThierry Reding display@15210000 { 1576c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1577c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1578c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1579c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1580c2599da7SThierry Reding clock-names = "dc"; 1581c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1582c2599da7SThierry Reding reset-names = "dc"; 1583c2599da7SThierry Reding 1584c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1585954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1586954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1587954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1588c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1589c2599da7SThierry Reding 1590c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1591c2599da7SThierry Reding nvidia,head = <1>; 1592c2599da7SThierry Reding }; 1593c2599da7SThierry Reding 1594c2599da7SThierry Reding display@15220000 { 1595c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1596c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1597c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1598c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1599c2599da7SThierry Reding clock-names = "dc"; 1600c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1601c2599da7SThierry Reding reset-names = "dc"; 1602c2599da7SThierry Reding 1603c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1604954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1605954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1606954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1607c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1608c2599da7SThierry Reding 1609c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1610c2599da7SThierry Reding nvidia,head = <2>; 1611c2599da7SThierry Reding }; 1612c2599da7SThierry Reding }; 1613c2599da7SThierry Reding 1614c2599da7SThierry Reding dsia: dsi@15300000 { 1615c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1616c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1617c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1618c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1619c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1620c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1621c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1622c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1623c2599da7SThierry Reding reset-names = "dsi"; 1624c2599da7SThierry Reding status = "disabled"; 1625c2599da7SThierry Reding 1626c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1627c2599da7SThierry Reding }; 1628effc4b44SMikko Perttunen 1629effc4b44SMikko Perttunen vic@15340000 { 1630effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1631effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1632effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1633effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1634effc4b44SMikko Perttunen clock-names = "vic"; 1635effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1636effc4b44SMikko Perttunen reset-names = "vic"; 1637effc4b44SMikko Perttunen 1638effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1639954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1640954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1641954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 164229ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1643effc4b44SMikko Perttunen }; 1644c2599da7SThierry Reding 1645f7eb2785SJon Hunter nvjpg@15380000 { 1646f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1647f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1648f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1649f7eb2785SJon Hunter clock-names = "nvjpg"; 1650f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1651f7eb2785SJon Hunter reset-names = "nvjpg"; 1652f7eb2785SJon Hunter 1653f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1654f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1655f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1656f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1657f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1658f7eb2785SJon Hunter }; 1659f7eb2785SJon Hunter 1660c2599da7SThierry Reding dsib: dsi@15400000 { 1661c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1662c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1663c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1664c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1665c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1666c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1667c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1668c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1669c2599da7SThierry Reding reset-names = "dsi"; 1670c2599da7SThierry Reding status = "disabled"; 1671c2599da7SThierry Reding 1672c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1673c2599da7SThierry Reding }; 1674c2599da7SThierry Reding 167578a05873SMikko Perttunen nvdec@15480000 { 167678a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 167778a05873SMikko Perttunen reg = <0x15480000 0x40000>; 167878a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 167978a05873SMikko Perttunen clock-names = "nvdec"; 168078a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 168178a05873SMikko Perttunen reset-names = "nvdec"; 168278a05873SMikko Perttunen 168378a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 168478a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 168578a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 168678a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 168778a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 168878a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 168978a05873SMikko Perttunen }; 169078a05873SMikko Perttunen 1691f7eb2785SJon Hunter nvenc@154c0000 { 1692f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1693f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1694f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1695f7eb2785SJon Hunter clock-names = "nvenc"; 1696f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1697f7eb2785SJon Hunter reset-names = "nvenc"; 1698f7eb2785SJon Hunter 1699f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1700f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1701f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1702f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1703f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1704f7eb2785SJon Hunter }; 1705f7eb2785SJon Hunter 1706c2599da7SThierry Reding sor0: sor@15540000 { 1707c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1708c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1709c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1710c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1711c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1712c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1713c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1714c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1715c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1716c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1717c2599da7SThierry Reding "pad"; 1718c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1719c2599da7SThierry Reding reset-names = "sor"; 1720c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1721c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1722c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1723c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1724c2599da7SThierry Reding status = "disabled"; 1725c2599da7SThierry Reding 1726c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1727c2599da7SThierry Reding nvidia,interface = <0>; 1728c2599da7SThierry Reding }; 1729c2599da7SThierry Reding 1730c2599da7SThierry Reding sor1: sor@15580000 { 1731d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1732c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1733c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1734c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1735c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1736c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1737c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1738c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1739c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1740c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1741c2599da7SThierry Reding "pad"; 1742c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1743c2599da7SThierry Reding reset-names = "sor"; 1744c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1745c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1746c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1747c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1748c2599da7SThierry Reding status = "disabled"; 1749c2599da7SThierry Reding 1750c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1751c2599da7SThierry Reding nvidia,interface = <1>; 1752c2599da7SThierry Reding }; 1753c2599da7SThierry Reding 1754c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1755c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1756c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1757c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1758c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1759c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1760c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1761c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1762c2599da7SThierry Reding reset-names = "dpaux"; 1763c2599da7SThierry Reding status = "disabled"; 1764c2599da7SThierry Reding 1765c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1766c2599da7SThierry Reding 1767c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1768c2599da7SThierry Reding groups = "dpaux-io"; 1769c2599da7SThierry Reding function = "aux"; 1770c2599da7SThierry Reding }; 1771c2599da7SThierry Reding 1772c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1773c2599da7SThierry Reding groups = "dpaux-io"; 1774c2599da7SThierry Reding function = "i2c"; 1775c2599da7SThierry Reding }; 1776c2599da7SThierry Reding 1777c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1778c2599da7SThierry Reding groups = "dpaux-io"; 1779c2599da7SThierry Reding function = "off"; 1780c2599da7SThierry Reding }; 1781c2599da7SThierry Reding 1782c2599da7SThierry Reding i2c-bus { 1783c2599da7SThierry Reding #address-cells = <1>; 1784c2599da7SThierry Reding #size-cells = <0>; 1785c2599da7SThierry Reding }; 1786c2599da7SThierry Reding }; 1787c2599da7SThierry Reding 1788c2599da7SThierry Reding padctl@15880000 { 1789c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1790c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1791c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1792c2599da7SThierry Reding reset-names = "dsi"; 1793c2599da7SThierry Reding status = "disabled"; 1794c2599da7SThierry Reding }; 1795c2599da7SThierry Reding 1796c2599da7SThierry Reding dsic: dsi@15900000 { 1797c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1798c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1799c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1800c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1801c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1802c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1803c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1804c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1805c2599da7SThierry Reding reset-names = "dsi"; 1806c2599da7SThierry Reding status = "disabled"; 1807c2599da7SThierry Reding 1808c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1809c2599da7SThierry Reding }; 1810c2599da7SThierry Reding 1811c2599da7SThierry Reding dsid: dsi@15940000 { 1812c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1813c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1814c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1815c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1816c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1817c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1818c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1819c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1820c2599da7SThierry Reding reset-names = "dsi"; 1821c2599da7SThierry Reding status = "disabled"; 1822c2599da7SThierry Reding 1823c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1824c2599da7SThierry Reding }; 18255524c61fSMikko Perttunen }; 18265524c61fSMikko Perttunen 1827dfd7a384SAlexandre Courbot gpu@17000000 { 1828dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1829dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1830dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 183159a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 183259a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1833dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1834dfd7a384SAlexandre Courbot 1835dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1836dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1837dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1838dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1839dfd7a384SAlexandre Courbot reset-names = "gpu"; 1840dfd7a384SAlexandre Courbot status = "disabled"; 1841dfd7a384SAlexandre Courbot 1842dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1843954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1844954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1845954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1846954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1847954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1848dfd7a384SAlexandre Courbot }; 1849dfd7a384SAlexandre Courbot 1850e867fe41SThierry Reding sram@30000000 { 185139cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 185239cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1853aa78032cSThierry Reding #address-cells = <1>; 1854aa78032cSThierry Reding #size-cells = <1>; 1855aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 185661192a9dSMikko Perttunen no-memory-wc; 185739cb62cbSJoseph Lo 1858e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1859aa78032cSThierry Reding reg = <0x4e000 0x1000>; 186039cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 186139cb62cbSJoseph Lo pool; 186239cb62cbSJoseph Lo }; 186339cb62cbSJoseph Lo 1864e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1865aa78032cSThierry Reding reg = <0x4f000 0x1000>; 186639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 186739cb62cbSJoseph Lo pool; 186839cb62cbSJoseph Lo }; 186939cb62cbSJoseph Lo }; 187039cb62cbSJoseph Lo 1871e061fbdfSSowjanya Komatineni sata@3507000 { 1872e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1873e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1874e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1875e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1876e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1877e061fbdfSSowjanya Komatineni 1878e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1879e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1880e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1881e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1882e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1883e061fbdfSSowjanya Komatineni 1884e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1885e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1886e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1887e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1888e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1889e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1890e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1891e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1892e061fbdfSSowjanya Komatineni <204000000>; 1893e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1894e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1895e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1896e061fbdfSSowjanya Komatineni status = "disabled"; 1897e061fbdfSSowjanya Komatineni }; 1898e061fbdfSSowjanya Komatineni 1899541d7c44SThierry Reding bpmp: bpmp { 1900541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1901954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1902954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1903954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1904954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1905954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1906541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1907541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1908541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 19097fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1910541d7c44SThierry Reding #clock-cells = <1>; 1911541d7c44SThierry Reding #reset-cells = <1>; 1912541d7c44SThierry Reding #power-domain-cells = <1>; 1913541d7c44SThierry Reding 1914541d7c44SThierry Reding bpmp_i2c: i2c { 1915541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1916541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1917541d7c44SThierry Reding #address-cells = <1>; 1918541d7c44SThierry Reding #size-cells = <0>; 1919541d7c44SThierry Reding status = "disabled"; 1920541d7c44SThierry Reding }; 1921541d7c44SThierry Reding 1922541d7c44SThierry Reding bpmp_thermal: thermal { 1923541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1924541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1925541d7c44SThierry Reding }; 1926541d7c44SThierry Reding }; 1927541d7c44SThierry Reding 1928cd6fe32eSThierry Reding cpus { 1929cd6fe32eSThierry Reding #address-cells = <1>; 1930cd6fe32eSThierry Reding #size-cells = <0>; 1931cd6fe32eSThierry Reding 19323b4c1378SMarc Zyngier denver_0: cpu@0 { 193331af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1934cd6fe32eSThierry Reding device_type = "cpu"; 19355298166dSJoseph Lo i-cache-size = <0x20000>; 19365298166dSJoseph Lo i-cache-line-size = <64>; 19375298166dSJoseph Lo i-cache-sets = <512>; 19385298166dSJoseph Lo d-cache-size = <0x10000>; 19395298166dSJoseph Lo d-cache-line-size = <64>; 19405298166dSJoseph Lo d-cache-sets = <256>; 19415298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1942cd6fe32eSThierry Reding reg = <0x000>; 1943cd6fe32eSThierry Reding }; 1944cd6fe32eSThierry Reding 19453b4c1378SMarc Zyngier denver_1: cpu@1 { 194631af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1947cd6fe32eSThierry Reding device_type = "cpu"; 19485298166dSJoseph Lo i-cache-size = <0x20000>; 19495298166dSJoseph Lo i-cache-line-size = <64>; 19505298166dSJoseph Lo i-cache-sets = <512>; 19515298166dSJoseph Lo d-cache-size = <0x10000>; 19525298166dSJoseph Lo d-cache-line-size = <64>; 19535298166dSJoseph Lo d-cache-sets = <256>; 19545298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1955cd6fe32eSThierry Reding reg = <0x001>; 1956cd6fe32eSThierry Reding }; 1957cd6fe32eSThierry Reding 19583b4c1378SMarc Zyngier ca57_0: cpu@2 { 195931af04cdSRob Herring compatible = "arm,cortex-a57"; 1960cd6fe32eSThierry Reding device_type = "cpu"; 19615298166dSJoseph Lo i-cache-size = <0xC000>; 19625298166dSJoseph Lo i-cache-line-size = <64>; 19635298166dSJoseph Lo i-cache-sets = <256>; 19645298166dSJoseph Lo d-cache-size = <0x8000>; 19655298166dSJoseph Lo d-cache-line-size = <64>; 19665298166dSJoseph Lo d-cache-sets = <256>; 19675298166dSJoseph Lo next-level-cache = <&L2_A57>; 1968cd6fe32eSThierry Reding reg = <0x100>; 1969cd6fe32eSThierry Reding }; 1970cd6fe32eSThierry Reding 19713b4c1378SMarc Zyngier ca57_1: cpu@3 { 197231af04cdSRob Herring compatible = "arm,cortex-a57"; 1973cd6fe32eSThierry Reding device_type = "cpu"; 19745298166dSJoseph Lo i-cache-size = <0xC000>; 19755298166dSJoseph Lo i-cache-line-size = <64>; 19765298166dSJoseph Lo i-cache-sets = <256>; 19775298166dSJoseph Lo d-cache-size = <0x8000>; 19785298166dSJoseph Lo d-cache-line-size = <64>; 19795298166dSJoseph Lo d-cache-sets = <256>; 19805298166dSJoseph Lo next-level-cache = <&L2_A57>; 1981cd6fe32eSThierry Reding reg = <0x101>; 1982cd6fe32eSThierry Reding }; 1983cd6fe32eSThierry Reding 19843b4c1378SMarc Zyngier ca57_2: cpu@4 { 198531af04cdSRob Herring compatible = "arm,cortex-a57"; 1986cd6fe32eSThierry Reding device_type = "cpu"; 19875298166dSJoseph Lo i-cache-size = <0xC000>; 19885298166dSJoseph Lo i-cache-line-size = <64>; 19895298166dSJoseph Lo i-cache-sets = <256>; 19905298166dSJoseph Lo d-cache-size = <0x8000>; 19915298166dSJoseph Lo d-cache-line-size = <64>; 19925298166dSJoseph Lo d-cache-sets = <256>; 19935298166dSJoseph Lo next-level-cache = <&L2_A57>; 1994cd6fe32eSThierry Reding reg = <0x102>; 1995cd6fe32eSThierry Reding }; 1996cd6fe32eSThierry Reding 19973b4c1378SMarc Zyngier ca57_3: cpu@5 { 199831af04cdSRob Herring compatible = "arm,cortex-a57"; 1999cd6fe32eSThierry Reding device_type = "cpu"; 20005298166dSJoseph Lo i-cache-size = <0xC000>; 20015298166dSJoseph Lo i-cache-line-size = <64>; 20025298166dSJoseph Lo i-cache-sets = <256>; 20035298166dSJoseph Lo d-cache-size = <0x8000>; 20045298166dSJoseph Lo d-cache-line-size = <64>; 20055298166dSJoseph Lo d-cache-sets = <256>; 20065298166dSJoseph Lo next-level-cache = <&L2_A57>; 2007cd6fe32eSThierry Reding reg = <0x103>; 2008cd6fe32eSThierry Reding }; 20095298166dSJoseph Lo 20105298166dSJoseph Lo L2_DENVER: l2-cache0 { 20115298166dSJoseph Lo compatible = "cache"; 20125298166dSJoseph Lo cache-unified; 20135298166dSJoseph Lo cache-level = <2>; 20145298166dSJoseph Lo cache-size = <0x200000>; 20155298166dSJoseph Lo cache-line-size = <64>; 20165298166dSJoseph Lo cache-sets = <2048>; 20175298166dSJoseph Lo }; 20185298166dSJoseph Lo 20195298166dSJoseph Lo L2_A57: l2-cache1 { 20205298166dSJoseph Lo compatible = "cache"; 20215298166dSJoseph Lo cache-unified; 20225298166dSJoseph Lo cache-level = <2>; 20235298166dSJoseph Lo cache-size = <0x200000>; 20245298166dSJoseph Lo cache-line-size = <64>; 20255298166dSJoseph Lo cache-sets = <2048>; 20265298166dSJoseph Lo }; 2027cd6fe32eSThierry Reding }; 2028cd6fe32eSThierry Reding 20293b4c1378SMarc Zyngier pmu_denver { 2030f0a48120SThierry Reding compatible = "nvidia,denver-pmu"; 20313b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 20323b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 20333b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 20343b4c1378SMarc Zyngier }; 20353b4c1378SMarc Zyngier 20363b4c1378SMarc Zyngier pmu_a57 { 2037f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 20383b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 20393b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20403b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20413b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20423b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20433b4c1378SMarc Zyngier }; 20443b4c1378SMarc Zyngier 2045e4710376SSameer Pujar sound { 2046e4710376SSameer Pujar status = "disabled"; 2047e4710376SSameer Pujar 2048e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2049e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2050e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2051e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2052e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2053e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2054e4710376SSameer Pujar assigned-clock-parents = <0>, 2055e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2056e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2057e4710376SSameer Pujar /* 2058e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2059e4710376SSameer Pujar * for this to work and oscillate between base rates required 2060e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2061e4710376SSameer Pujar */ 2062e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2063e4710376SSameer Pujar 2064e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2065e4710376SSameer Pujar }; 2066e4710376SSameer Pujar 206715274c23SMikko Perttunen thermal-zones { 2068fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2069fe57ff53SThierry Reding cpu-thermal { 207015274c23SMikko Perttunen polling-delay = <0>; 207115274c23SMikko Perttunen polling-delay-passive = <1000>; 207215274c23SMikko Perttunen 2073fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 207415274c23SMikko Perttunen 207515274c23SMikko Perttunen trips { 207615274c23SMikko Perttunen critical { 207715274c23SMikko Perttunen temperature = <101000>; 207815274c23SMikko Perttunen hysteresis = <0>; 207915274c23SMikko Perttunen type = "critical"; 208015274c23SMikko Perttunen }; 208115274c23SMikko Perttunen }; 208215274c23SMikko Perttunen 208315274c23SMikko Perttunen cooling-maps { 208415274c23SMikko Perttunen }; 208515274c23SMikko Perttunen }; 208615274c23SMikko Perttunen 2087fe57ff53SThierry Reding /* Denver cluster */ 2088fe57ff53SThierry Reding aux-thermal { 208915274c23SMikko Perttunen polling-delay = <0>; 209015274c23SMikko Perttunen polling-delay-passive = <1000>; 209115274c23SMikko Perttunen 2092fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 209315274c23SMikko Perttunen 209415274c23SMikko Perttunen trips { 209515274c23SMikko Perttunen critical { 209615274c23SMikko Perttunen temperature = <101000>; 209715274c23SMikko Perttunen hysteresis = <0>; 209815274c23SMikko Perttunen type = "critical"; 209915274c23SMikko Perttunen }; 210015274c23SMikko Perttunen }; 210115274c23SMikko Perttunen 210215274c23SMikko Perttunen cooling-maps { 210315274c23SMikko Perttunen }; 210415274c23SMikko Perttunen }; 210515274c23SMikko Perttunen 2106fe57ff53SThierry Reding gpu-thermal { 210715274c23SMikko Perttunen polling-delay = <0>; 210815274c23SMikko Perttunen polling-delay-passive = <1000>; 210915274c23SMikko Perttunen 2110fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 211115274c23SMikko Perttunen 211215274c23SMikko Perttunen trips { 211315274c23SMikko Perttunen critical { 211415274c23SMikko Perttunen temperature = <101000>; 211515274c23SMikko Perttunen hysteresis = <0>; 211615274c23SMikko Perttunen type = "critical"; 211715274c23SMikko Perttunen }; 211815274c23SMikko Perttunen }; 211915274c23SMikko Perttunen 212015274c23SMikko Perttunen cooling-maps { 212115274c23SMikko Perttunen }; 212215274c23SMikko Perttunen }; 212315274c23SMikko Perttunen 2124fe57ff53SThierry Reding pll-thermal { 212515274c23SMikko Perttunen polling-delay = <0>; 212615274c23SMikko Perttunen polling-delay-passive = <1000>; 212715274c23SMikko Perttunen 2128fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 212915274c23SMikko Perttunen 213015274c23SMikko Perttunen trips { 213115274c23SMikko Perttunen critical { 213215274c23SMikko Perttunen temperature = <101000>; 213315274c23SMikko Perttunen hysteresis = <0>; 213415274c23SMikko Perttunen type = "critical"; 213515274c23SMikko Perttunen }; 213615274c23SMikko Perttunen }; 213715274c23SMikko Perttunen 213815274c23SMikko Perttunen cooling-maps { 213915274c23SMikko Perttunen }; 214015274c23SMikko Perttunen }; 214115274c23SMikko Perttunen 2142fe57ff53SThierry Reding ao-thermal { 214315274c23SMikko Perttunen polling-delay = <0>; 214415274c23SMikko Perttunen polling-delay-passive = <1000>; 214515274c23SMikko Perttunen 2146fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 214715274c23SMikko Perttunen 214815274c23SMikko Perttunen trips { 214915274c23SMikko Perttunen critical { 215015274c23SMikko Perttunen temperature = <101000>; 215115274c23SMikko Perttunen hysteresis = <0>; 215215274c23SMikko Perttunen type = "critical"; 215315274c23SMikko Perttunen }; 215415274c23SMikko Perttunen }; 215515274c23SMikko Perttunen 215615274c23SMikko Perttunen cooling-maps { 215715274c23SMikko Perttunen }; 215815274c23SMikko Perttunen }; 215939cb62cbSJoseph Lo }; 216039cb62cbSJoseph Lo 216139cb62cbSJoseph Lo timer { 216239cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 216339cb62cbSJoseph Lo interrupts = <GIC_PPI 13 216439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216539cb62cbSJoseph Lo <GIC_PPI 14 216639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216739cb62cbSJoseph Lo <GIC_PPI 11 216839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216939cb62cbSJoseph Lo <GIC_PPI 10 217039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 217139cb62cbSJoseph Lo interrupt-parent = <&gic>; 2172b30be673SThierry Reding always-on; 217339cb62cbSJoseph Lo }; 217439cb62cbSJoseph Lo}; 2175