139cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 239cb62cbSJoseph Lo 339cb62cbSJoseph Lo/ { 439cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 539cb62cbSJoseph Lo interrupt-parent = <&gic>; 639cb62cbSJoseph Lo #address-cells = <2>; 739cb62cbSJoseph Lo #size-cells = <2>; 839cb62cbSJoseph Lo 939cb62cbSJoseph Lo uarta: serial@3100000 { 1039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 1239cb62cbSJoseph Lo reg-shift = <2>; 1339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14a7a77e2eSThierry Reding clocks = <&bpmp 55>; 15a7a77e2eSThierry Reding clock-names = "serial"; 16a7a77e2eSThierry Reding resets = <&bpmp 47>; 17a7a77e2eSThierry Reding reset-names = "serial"; 18a7a77e2eSThierry Reding status = "disabled"; 19a7a77e2eSThierry Reding }; 20a7a77e2eSThierry Reding 21a7a77e2eSThierry Reding uartb: serial@3110000 { 22a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 23a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 24a7a77e2eSThierry Reding reg-shift = <2>; 25a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 26a7a77e2eSThierry Reding clocks = <&bpmp 56>; 27a7a77e2eSThierry Reding clock-names = "serial"; 28a7a77e2eSThierry Reding resets = <&bpmp 48>; 29a7a77e2eSThierry Reding reset-names = "serial"; 30a7a77e2eSThierry Reding status = "disabled"; 31a7a77e2eSThierry Reding }; 32a7a77e2eSThierry Reding 33a7a77e2eSThierry Reding uartd: serial@3130000 { 34a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 35a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 36a7a77e2eSThierry Reding reg-shift = <2>; 37a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 38a7a77e2eSThierry Reding clocks = <&bpmp 77>; 39a7a77e2eSThierry Reding clock-names = "serial"; 40a7a77e2eSThierry Reding resets = <&bpmp 50>; 41a7a77e2eSThierry Reding reset-names = "serial"; 42a7a77e2eSThierry Reding status = "disabled"; 43a7a77e2eSThierry Reding }; 44a7a77e2eSThierry Reding 45a7a77e2eSThierry Reding uarte: serial@3140000 { 46a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 47a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 48a7a77e2eSThierry Reding reg-shift = <2>; 49a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 50a7a77e2eSThierry Reding clocks = <&bpmp 194>; 51a7a77e2eSThierry Reding clock-names = "serial"; 52a7a77e2eSThierry Reding resets = <&bpmp 132>; 53a7a77e2eSThierry Reding reset-names = "serial"; 54a7a77e2eSThierry Reding status = "disabled"; 55a7a77e2eSThierry Reding }; 56a7a77e2eSThierry Reding 57a7a77e2eSThierry Reding uartf: serial@3150000 { 58a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 59a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 60a7a77e2eSThierry Reding reg-shift = <2>; 61a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62a7a77e2eSThierry Reding clocks = <&bpmp 195>; 63a7a77e2eSThierry Reding clock-names = "serial"; 64a7a77e2eSThierry Reding resets = <&bpmp 111>; 65a7a77e2eSThierry Reding reset-names = "serial"; 6639cb62cbSJoseph Lo status = "disabled"; 6739cb62cbSJoseph Lo }; 6839cb62cbSJoseph Lo 6939cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 7039cb62cbSJoseph Lo compatible = "arm,gic-400"; 7139cb62cbSJoseph Lo #interrupt-cells = <3>; 7239cb62cbSJoseph Lo interrupt-controller; 7339cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 7439cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 7539cb62cbSJoseph Lo interrupts = <GIC_PPI 9 7639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 7739cb62cbSJoseph Lo interrupt-parent = <&gic>; 7839cb62cbSJoseph Lo }; 7939cb62cbSJoseph Lo 8039cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 8139cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 8239cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 8339cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 8439cb62cbSJoseph Lo interrupt-names = "doorbell"; 8539cb62cbSJoseph Lo #mbox-cells = <2>; 8639cb62cbSJoseph Lo status = "disabled"; 8739cb62cbSJoseph Lo }; 8839cb62cbSJoseph Lo 89a7a77e2eSThierry Reding uartc: serial@c280000 { 90a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 91a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 92a7a77e2eSThierry Reding reg-shift = <2>; 93a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 94a7a77e2eSThierry Reding clocks = <&bpmp 215>; 95a7a77e2eSThierry Reding clock-names = "serial"; 96a7a77e2eSThierry Reding resets = <&bpmp 49>; 97a7a77e2eSThierry Reding reset-names = "serial"; 98a7a77e2eSThierry Reding status = "disabled"; 99a7a77e2eSThierry Reding }; 100a7a77e2eSThierry Reding 101a7a77e2eSThierry Reding uartg: serial@c290000 { 102a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 103a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 104a7a77e2eSThierry Reding reg-shift = <2>; 105a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 106a7a77e2eSThierry Reding clocks = <&bpmp 216>; 107a7a77e2eSThierry Reding clock-names = "serial"; 108a7a77e2eSThierry Reding resets = <&bpmp 112>; 109a7a77e2eSThierry Reding reset-names = "serial"; 110a7a77e2eSThierry Reding status = "disabled"; 111a7a77e2eSThierry Reding }; 112a7a77e2eSThierry Reding 11339cb62cbSJoseph Lo sysram@30000000 { 11439cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 11539cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 11639cb62cbSJoseph Lo #address-cells = <2>; 11739cb62cbSJoseph Lo #size-cells = <2>; 11839cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 11939cb62cbSJoseph Lo 12039cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 12139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 12239cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 12339cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 12439cb62cbSJoseph Lo pool; 12539cb62cbSJoseph Lo }; 12639cb62cbSJoseph Lo 12739cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 12839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 12939cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 13039cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 13139cb62cbSJoseph Lo pool; 13239cb62cbSJoseph Lo }; 13339cb62cbSJoseph Lo }; 13439cb62cbSJoseph Lo 135cd6fe32eSThierry Reding cpus { 136cd6fe32eSThierry Reding #address-cells = <1>; 137cd6fe32eSThierry Reding #size-cells = <0>; 138cd6fe32eSThierry Reding 139cd6fe32eSThierry Reding cpu@0 { 140cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 141cd6fe32eSThierry Reding device_type = "cpu"; 142cd6fe32eSThierry Reding reg = <0x000>; 143cd6fe32eSThierry Reding }; 144cd6fe32eSThierry Reding 145cd6fe32eSThierry Reding cpu@1 { 146cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 147cd6fe32eSThierry Reding device_type = "cpu"; 148cd6fe32eSThierry Reding reg = <0x001>; 149cd6fe32eSThierry Reding }; 150cd6fe32eSThierry Reding 151cd6fe32eSThierry Reding cpu@2 { 152cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 153cd6fe32eSThierry Reding device_type = "cpu"; 154cd6fe32eSThierry Reding reg = <0x100>; 155cd6fe32eSThierry Reding }; 156cd6fe32eSThierry Reding 157cd6fe32eSThierry Reding cpu@3 { 158cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 159cd6fe32eSThierry Reding device_type = "cpu"; 160cd6fe32eSThierry Reding reg = <0x101>; 161cd6fe32eSThierry Reding }; 162cd6fe32eSThierry Reding 163cd6fe32eSThierry Reding cpu@4 { 164cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 165cd6fe32eSThierry Reding device_type = "cpu"; 166cd6fe32eSThierry Reding reg = <0x102>; 167cd6fe32eSThierry Reding }; 168cd6fe32eSThierry Reding 169cd6fe32eSThierry Reding cpu@5 { 170cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 171cd6fe32eSThierry Reding device_type = "cpu"; 172cd6fe32eSThierry Reding reg = <0x103>; 173cd6fe32eSThierry Reding }; 174cd6fe32eSThierry Reding }; 175cd6fe32eSThierry Reding 17639cb62cbSJoseph Lo bpmp: bpmp { 17739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 17839cb62cbSJoseph Lo mboxes = <&hsp_top0 0 19>; 17939cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 18039cb62cbSJoseph Lo #clock-cells = <1>; 18139cb62cbSJoseph Lo #reset-cells = <1>; 18239cb62cbSJoseph Lo 18339cb62cbSJoseph Lo bpmp_i2c: i2c { 18439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 18539cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 18639cb62cbSJoseph Lo #address-cells = <1>; 18739cb62cbSJoseph Lo #size-cells = <0>; 18839cb62cbSJoseph Lo status = "disabled"; 18939cb62cbSJoseph Lo }; 19039cb62cbSJoseph Lo }; 19139cb62cbSJoseph Lo 19239cb62cbSJoseph Lo timer { 19339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 19439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 19539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 19639cb62cbSJoseph Lo <GIC_PPI 14 19739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 19839cb62cbSJoseph Lo <GIC_PPI 11 19939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 20039cb62cbSJoseph Lo <GIC_PPI 10 20139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 20239cb62cbSJoseph Lo interrupt-parent = <&gic>; 20339cb62cbSJoseph Lo }; 20439cb62cbSJoseph Lo}; 205