1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 765d2249ddSSameer Pujar aconnect { 775d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 785d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 795d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 805d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 815d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 825d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 835d2249ddSSameer Pujar #address-cells = <1>; 845d2249ddSSameer Pujar #size-cells = <1>; 855d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 865d2249ddSSameer Pujar status = "disabled"; 875d2249ddSSameer Pujar 885d2249ddSSameer Pujar dma-controller@2930000 { 895d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 1435d2249ddSSameer Pujar }; 1445d2249ddSSameer Pujar 145954490b3SThierry Reding mc: memory-controller@2c00000 { 146d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 147d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 148b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 149d25a3bf1SThierry Reding status = "disabled"; 1503f6eaef9SThierry Reding 151954490b3SThierry Reding #interconnect-cells = <1>; 1523f6eaef9SThierry Reding #address-cells = <2>; 1533f6eaef9SThierry Reding #size-cells = <2>; 1543f6eaef9SThierry Reding 1553f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 1563f6eaef9SThierry Reding 1573f6eaef9SThierry Reding /* 1583f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 1593f6eaef9SThierry Reding * controller can address. 1603f6eaef9SThierry Reding */ 1613f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 1623f6eaef9SThierry Reding 1633f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 1643f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 1653f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 1663f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1673f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 1683f6eaef9SThierry Reding clock-names = "emc"; 1693f6eaef9SThierry Reding 170954490b3SThierry Reding #interconnect-cells = <0>; 171954490b3SThierry Reding 1723f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 1733f6eaef9SThierry Reding }; 174d25a3bf1SThierry Reding }; 175d25a3bf1SThierry Reding 17639cb62cbSJoseph Lo uarta: serial@3100000 { 17739cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 17839cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 17939cb62cbSJoseph Lo reg-shift = <2>; 18039cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 181c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 182a7a77e2eSThierry Reding clock-names = "serial"; 1837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 184a7a77e2eSThierry Reding reset-names = "serial"; 185a7a77e2eSThierry Reding status = "disabled"; 186a7a77e2eSThierry Reding }; 187a7a77e2eSThierry Reding 188a7a77e2eSThierry Reding uartb: serial@3110000 { 189a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 190a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 191a7a77e2eSThierry Reding reg-shift = <2>; 192a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 193c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 194a7a77e2eSThierry Reding clock-names = "serial"; 1957bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 196a7a77e2eSThierry Reding reset-names = "serial"; 197a7a77e2eSThierry Reding status = "disabled"; 198a7a77e2eSThierry Reding }; 199a7a77e2eSThierry Reding 200a7a77e2eSThierry Reding uartd: serial@3130000 { 201a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 202a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 203a7a77e2eSThierry Reding reg-shift = <2>; 204a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 205c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 206a7a77e2eSThierry Reding clock-names = "serial"; 2077bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 208a7a77e2eSThierry Reding reset-names = "serial"; 209a7a77e2eSThierry Reding status = "disabled"; 210a7a77e2eSThierry Reding }; 211a7a77e2eSThierry Reding 212a7a77e2eSThierry Reding uarte: serial@3140000 { 213a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 214a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 215a7a77e2eSThierry Reding reg-shift = <2>; 216a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 217c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 218a7a77e2eSThierry Reding clock-names = "serial"; 2197bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 220a7a77e2eSThierry Reding reset-names = "serial"; 221a7a77e2eSThierry Reding status = "disabled"; 222a7a77e2eSThierry Reding }; 223a7a77e2eSThierry Reding 224a7a77e2eSThierry Reding uartf: serial@3150000 { 225a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 226a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 227a7a77e2eSThierry Reding reg-shift = <2>; 228a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 229c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 230a7a77e2eSThierry Reding clock-names = "serial"; 2317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 232a7a77e2eSThierry Reding reset-names = "serial"; 23339cb62cbSJoseph Lo status = "disabled"; 23439cb62cbSJoseph Lo }; 23539cb62cbSJoseph Lo 23640cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 237250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 23840cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 23940cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 24040cc83b3SThierry Reding #address-cells = <1>; 24140cc83b3SThierry Reding #size-cells = <0>; 242c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 24340cc83b3SThierry Reding clock-names = "div-clk"; 2447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 24540cc83b3SThierry Reding reset-names = "i2c"; 24640cc83b3SThierry Reding status = "disabled"; 24740cc83b3SThierry Reding }; 24840cc83b3SThierry Reding 24940cc83b3SThierry Reding cam_i2c: i2c@3180000 { 250250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 25140cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 25240cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 25340cc83b3SThierry Reding #address-cells = <1>; 25440cc83b3SThierry Reding #size-cells = <0>; 255c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 25640cc83b3SThierry Reding clock-names = "div-clk"; 2577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 25840cc83b3SThierry Reding reset-names = "i2c"; 25940cc83b3SThierry Reding status = "disabled"; 26040cc83b3SThierry Reding }; 26140cc83b3SThierry Reding 26240cc83b3SThierry Reding /* shares pads with dpaux1 */ 26340cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 264250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 26540cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 26640cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 26740cc83b3SThierry Reding #address-cells = <1>; 26840cc83b3SThierry Reding #size-cells = <0>; 269c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 27040cc83b3SThierry Reding clock-names = "div-clk"; 2717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 27240cc83b3SThierry Reding reset-names = "i2c"; 273846137c6SThierry Reding pinctrl-names = "default", "idle"; 274846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 275846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 27640cc83b3SThierry Reding status = "disabled"; 27740cc83b3SThierry Reding }; 27840cc83b3SThierry Reding 27940cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 28040cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 281250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 28240cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 28340cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 28440cc83b3SThierry Reding #address-cells = <1>; 28540cc83b3SThierry Reding #size-cells = <0>; 286c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 28740cc83b3SThierry Reding clock-names = "div-clk"; 2887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 28940cc83b3SThierry Reding reset-names = "i2c"; 29040cc83b3SThierry Reding status = "disabled"; 29140cc83b3SThierry Reding }; 29240cc83b3SThierry Reding 29340cc83b3SThierry Reding /* shares pads with dpaux0 */ 29440cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 295250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 29640cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 29740cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 29840cc83b3SThierry Reding #address-cells = <1>; 29940cc83b3SThierry Reding #size-cells = <0>; 300c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 30140cc83b3SThierry Reding clock-names = "div-clk"; 3027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 30340cc83b3SThierry Reding reset-names = "i2c"; 304846137c6SThierry Reding pinctrl-names = "default", "idle"; 305846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 306846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 30740cc83b3SThierry Reding status = "disabled"; 30840cc83b3SThierry Reding }; 30940cc83b3SThierry Reding 31040cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 311250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 31240cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 31340cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 31440cc83b3SThierry Reding #address-cells = <1>; 31540cc83b3SThierry Reding #size-cells = <0>; 316c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 31740cc83b3SThierry Reding clock-names = "div-clk"; 3187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 31940cc83b3SThierry Reding reset-names = "i2c"; 32040cc83b3SThierry Reding status = "disabled"; 32140cc83b3SThierry Reding }; 32240cc83b3SThierry Reding 32340cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 324250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 32540cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 32640cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 32740cc83b3SThierry Reding #address-cells = <1>; 32840cc83b3SThierry Reding #size-cells = <0>; 329c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 33040cc83b3SThierry Reding clock-names = "div-clk"; 3317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 33240cc83b3SThierry Reding reset-names = "i2c"; 33340cc83b3SThierry Reding status = "disabled"; 33440cc83b3SThierry Reding }; 33540cc83b3SThierry Reding 33667bb17f6SThierry Reding sdmmc1: mmc@3400000 { 33799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 33899425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 33999425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 340c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 34199425dfdSThierry Reding clock-names = "sdhci"; 3427bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 34399425dfdSThierry Reding reset-names = "sdhci"; 344954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 345954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 346954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 3478589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 34824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 34924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 35024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 35141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 35241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 35341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 35441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 35541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 35641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 3576f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3586f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 35998a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 36098a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 36198a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 36299425dfdSThierry Reding status = "disabled"; 36399425dfdSThierry Reding }; 36499425dfdSThierry Reding 36567bb17f6SThierry Reding sdmmc2: mmc@3420000 { 36699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 36799425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 36899425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 369c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 37099425dfdSThierry Reding clock-names = "sdhci"; 3717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 37299425dfdSThierry Reding reset-names = "sdhci"; 373954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 374954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 375954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 3768589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 37724005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 37824005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 37924005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 38041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 38141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 38241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 38341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3846f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3856f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 38699425dfdSThierry Reding status = "disabled"; 38799425dfdSThierry Reding }; 38899425dfdSThierry Reding 38967bb17f6SThierry Reding sdmmc3: mmc@3440000 { 39099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 39199425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 39299425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 393c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 39499425dfdSThierry Reding clock-names = "sdhci"; 3957bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 39699425dfdSThierry Reding reset-names = "sdhci"; 397954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 398954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 399954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 4008589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 40124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 40224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 40324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 40441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 40541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 40641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 40741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 40841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 40941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 4106f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 4116f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 41299425dfdSThierry Reding status = "disabled"; 41399425dfdSThierry Reding }; 41499425dfdSThierry Reding 41567bb17f6SThierry Reding sdmmc4: mmc@3460000 { 41699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 41799425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 41899425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 419c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 42099425dfdSThierry Reding clock-names = "sdhci"; 42198a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 42298a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 42398a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 4247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 42599425dfdSThierry Reding reset-names = "sdhci"; 426954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 427954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 428954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 4298589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 43041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 43141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 43241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 43341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 4344e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 4354e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 436e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 437e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 43822248e91SAapo Vienamo nvidia,dqs-trim = <63>; 439207f60baSAapo Vienamo mmc-hs400-1_8v; 440c4307836SSowjanya Komatineni supports-cqe; 44199425dfdSThierry Reding status = "disabled"; 44299425dfdSThierry Reding }; 44399425dfdSThierry Reding 444b066a310SThierry Reding hda@3510000 { 445b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 446b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 447b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 448b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 449b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 450b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 451b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 452b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 453b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 454b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 455b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 456b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 457954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 458954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 459954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 460dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 461b066a310SThierry Reding status = "disabled"; 462b066a310SThierry Reding }; 463b066a310SThierry Reding 4648bfde518SThierry Reding padctl: padctl@3520000 { 4658bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 4668bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 4678bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 4688bfde518SThierry Reding reg-names = "padctl", "ao"; 4698bfde518SThierry Reding 4708bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 4718bfde518SThierry Reding reset-names = "padctl"; 4728bfde518SThierry Reding 4738bfde518SThierry Reding status = "disabled"; 4748bfde518SThierry Reding 4758bfde518SThierry Reding pads { 4768bfde518SThierry Reding usb2 { 4778bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 4788bfde518SThierry Reding clock-names = "trk"; 4798bfde518SThierry Reding status = "disabled"; 4808bfde518SThierry Reding 4818bfde518SThierry Reding lanes { 4828bfde518SThierry Reding usb2-0 { 4838bfde518SThierry Reding status = "disabled"; 4848bfde518SThierry Reding #phy-cells = <0>; 4858bfde518SThierry Reding }; 4868bfde518SThierry Reding 4878bfde518SThierry Reding usb2-1 { 4888bfde518SThierry Reding status = "disabled"; 4898bfde518SThierry Reding #phy-cells = <0>; 4908bfde518SThierry Reding }; 4918bfde518SThierry Reding 4928bfde518SThierry Reding usb2-2 { 4938bfde518SThierry Reding status = "disabled"; 4948bfde518SThierry Reding #phy-cells = <0>; 4958bfde518SThierry Reding }; 4968bfde518SThierry Reding }; 4978bfde518SThierry Reding }; 4988bfde518SThierry Reding 4998bfde518SThierry Reding hsic { 5008bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 5018bfde518SThierry Reding clock-names = "trk"; 5028bfde518SThierry Reding status = "disabled"; 5038bfde518SThierry Reding 5048bfde518SThierry Reding lanes { 5058bfde518SThierry Reding hsic-0 { 5068bfde518SThierry Reding status = "disabled"; 5078bfde518SThierry Reding #phy-cells = <0>; 5088bfde518SThierry Reding }; 5098bfde518SThierry Reding }; 5108bfde518SThierry Reding }; 5118bfde518SThierry Reding 5128bfde518SThierry Reding usb3 { 5138bfde518SThierry Reding status = "disabled"; 5148bfde518SThierry Reding 5158bfde518SThierry Reding lanes { 5168bfde518SThierry Reding usb3-0 { 5178bfde518SThierry Reding status = "disabled"; 5188bfde518SThierry Reding #phy-cells = <0>; 5198bfde518SThierry Reding }; 5208bfde518SThierry Reding 5218bfde518SThierry Reding usb3-1 { 5228bfde518SThierry Reding status = "disabled"; 5238bfde518SThierry Reding #phy-cells = <0>; 5248bfde518SThierry Reding }; 5258bfde518SThierry Reding 5268bfde518SThierry Reding usb3-2 { 5278bfde518SThierry Reding status = "disabled"; 5288bfde518SThierry Reding #phy-cells = <0>; 5298bfde518SThierry Reding }; 5308bfde518SThierry Reding }; 5318bfde518SThierry Reding }; 5328bfde518SThierry Reding }; 5338bfde518SThierry Reding 5348bfde518SThierry Reding ports { 5358bfde518SThierry Reding usb2-0 { 5368bfde518SThierry Reding status = "disabled"; 5378bfde518SThierry Reding }; 5388bfde518SThierry Reding 5398bfde518SThierry Reding usb2-1 { 5408bfde518SThierry Reding status = "disabled"; 5418bfde518SThierry Reding }; 5428bfde518SThierry Reding 5438bfde518SThierry Reding usb2-2 { 5448bfde518SThierry Reding status = "disabled"; 5458bfde518SThierry Reding }; 5468bfde518SThierry Reding 5478bfde518SThierry Reding hsic-0 { 5488bfde518SThierry Reding status = "disabled"; 5498bfde518SThierry Reding }; 5508bfde518SThierry Reding 5518bfde518SThierry Reding usb3-0 { 5528bfde518SThierry Reding status = "disabled"; 5538bfde518SThierry Reding }; 5548bfde518SThierry Reding 5558bfde518SThierry Reding usb3-1 { 5568bfde518SThierry Reding status = "disabled"; 5578bfde518SThierry Reding }; 5588bfde518SThierry Reding 5598bfde518SThierry Reding usb3-2 { 5608bfde518SThierry Reding status = "disabled"; 5618bfde518SThierry Reding }; 5628bfde518SThierry Reding }; 5638bfde518SThierry Reding }; 5648bfde518SThierry Reding 5658bfde518SThierry Reding usb@3530000 { 5668bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 5678bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 5688bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 5698bfde518SThierry Reding reg-names = "hcd", "fpci"; 5708bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 571a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 5728bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 5738bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 5748bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 5758bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 5768bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5778bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 5788bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 5798bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5808bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 5818bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 5828bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 5838bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 5848bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 5858bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 5868bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 587954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 588954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 589954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 59006c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 5918bfde518SThierry Reding #address-cells = <1>; 5928bfde518SThierry Reding #size-cells = <0>; 59306c6b06fSThierry Reding status = "disabled"; 59406c6b06fSThierry Reding 59506c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 5968bfde518SThierry Reding }; 5978bfde518SThierry Reding 598584f800cSNagarjuna Kristam usb@3550000 { 599584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 600584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 601584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 602584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 603584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 604584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 605584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 606584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 607584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 608584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 609584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 610584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 611584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 612584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 613584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 614584f800cSNagarjuna Kristam status = "disabled"; 615584f800cSNagarjuna Kristam }; 616584f800cSNagarjuna Kristam 61785593b75SThierry Reding fuse@3820000 { 61885593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 61985593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 62085593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 62185593b75SThierry Reding clock-names = "fuse"; 62285593b75SThierry Reding }; 62385593b75SThierry Reding 62439cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 62539cb62cbSJoseph Lo compatible = "arm,gic-400"; 62639cb62cbSJoseph Lo #interrupt-cells = <3>; 62739cb62cbSJoseph Lo interrupt-controller; 62839cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 62939cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 63039cb62cbSJoseph Lo interrupts = <GIC_PPI 9 63139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 63239cb62cbSJoseph Lo interrupt-parent = <&gic>; 63339cb62cbSJoseph Lo }; 63439cb62cbSJoseph Lo 63597cf683cSThierry Reding cec@3960000 { 63697cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 63797cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 63897cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 63997cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 64097cf683cSThierry Reding clock-names = "cec"; 64197cf683cSThierry Reding status = "disabled"; 64297cf683cSThierry Reding }; 64397cf683cSThierry Reding 64439cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 64539cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 64639cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 64739cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 64839cb62cbSJoseph Lo interrupt-names = "doorbell"; 64939cb62cbSJoseph Lo #mbox-cells = <2>; 65039cb62cbSJoseph Lo status = "disabled"; 65139cb62cbSJoseph Lo }; 65239cb62cbSJoseph Lo 65340cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 654250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 65540cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 65640cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 65740cc83b3SThierry Reding #address-cells = <1>; 65840cc83b3SThierry Reding #size-cells = <0>; 659c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 66040cc83b3SThierry Reding clock-names = "div-clk"; 6617bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 66240cc83b3SThierry Reding reset-names = "i2c"; 66340cc83b3SThierry Reding status = "disabled"; 66440cc83b3SThierry Reding }; 66540cc83b3SThierry Reding 66640cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 667250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 66840cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 66940cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 67040cc83b3SThierry Reding #address-cells = <1>; 67140cc83b3SThierry Reding #size-cells = <0>; 672c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 67340cc83b3SThierry Reding clock-names = "div-clk"; 6747bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 67540cc83b3SThierry Reding reset-names = "i2c"; 67640cc83b3SThierry Reding status = "disabled"; 67740cc83b3SThierry Reding }; 67840cc83b3SThierry Reding 679a7a77e2eSThierry Reding uartc: serial@c280000 { 680a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 681a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 682a7a77e2eSThierry Reding reg-shift = <2>; 683a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 684c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 685a7a77e2eSThierry Reding clock-names = "serial"; 6867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 687a7a77e2eSThierry Reding reset-names = "serial"; 688a7a77e2eSThierry Reding status = "disabled"; 689a7a77e2eSThierry Reding }; 690a7a77e2eSThierry Reding 691a7a77e2eSThierry Reding uartg: serial@c290000 { 692a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 693a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 694a7a77e2eSThierry Reding reg-shift = <2>; 695a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 696c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 697a7a77e2eSThierry Reding clock-names = "serial"; 6987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 699a7a77e2eSThierry Reding reset-names = "serial"; 700a7a77e2eSThierry Reding status = "disabled"; 701a7a77e2eSThierry Reding }; 702a7a77e2eSThierry Reding 7039733a251SThierry Reding rtc: rtc@c2a0000 { 7049733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 7059733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 7069733a251SThierry Reding interrupt-parent = <&pmc>; 7079733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 7089733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 7099733a251SThierry Reding clock-names = "rtc"; 7109733a251SThierry Reding status = "disabled"; 7119733a251SThierry Reding }; 7129733a251SThierry Reding 713fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 714fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 715fc4bb754SThierry Reding reg-names = "security", "gpio"; 716fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 717fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 718fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 719fc4bb754SThierry Reding gpio-controller; 720fc4bb754SThierry Reding #gpio-cells = <2>; 721fc4bb754SThierry Reding interrupt-controller; 722fc4bb754SThierry Reding #interrupt-cells = <2>; 723fc4bb754SThierry Reding }; 724fc4bb754SThierry Reding 72532e66e46SThierry Reding pmc: pmc@c360000 { 72673bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 72773bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 72873bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 72973bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 73073bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 73173bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 73224005fd1SAapo Vienamo 73332e66e46SThierry Reding #interrupt-cells = <2>; 73432e66e46SThierry Reding interrupt-controller; 73532e66e46SThierry Reding 73624005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 73724005fd1SAapo Vienamo pins = "sdmmc1-hv"; 73824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 73924005fd1SAapo Vienamo }; 74024005fd1SAapo Vienamo 74124005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 74224005fd1SAapo Vienamo pins = "sdmmc1-hv"; 74324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 74424005fd1SAapo Vienamo }; 74524005fd1SAapo Vienamo 74624005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 74724005fd1SAapo Vienamo pins = "sdmmc2-hv"; 74824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 74924005fd1SAapo Vienamo }; 75024005fd1SAapo Vienamo 75124005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 75224005fd1SAapo Vienamo pins = "sdmmc2-hv"; 75324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 75424005fd1SAapo Vienamo }; 75524005fd1SAapo Vienamo 75624005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 75724005fd1SAapo Vienamo pins = "sdmmc3-hv"; 75824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 75924005fd1SAapo Vienamo }; 76024005fd1SAapo Vienamo 76124005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 76224005fd1SAapo Vienamo pins = "sdmmc3-hv"; 76324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 76424005fd1SAapo Vienamo }; 76573bf90d4SThierry Reding }; 76673bf90d4SThierry Reding 7677b7ef494SMikko Perttunen ccplex@e000000 { 7687b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 7697b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 7707b7ef494SMikko Perttunen 7717b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 7727b7ef494SMikko Perttunen }; 7737b7ef494SMikko Perttunen 774f8973cf4SManikanta Maddireddy pcie@10003000 { 775f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 776f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 777f8973cf4SManikanta Maddireddy device_type = "pci"; 778644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 779644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 780644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 781f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 782f8973cf4SManikanta Maddireddy 783f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 784f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 785f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 786f8973cf4SManikanta Maddireddy 787f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 788f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 789f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 790f8973cf4SManikanta Maddireddy 791f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 792f8973cf4SManikanta Maddireddy #address-cells = <3>; 793f8973cf4SManikanta Maddireddy #size-cells = <2>; 794f8973cf4SManikanta Maddireddy 795644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 796644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 797644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 798644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 799644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 800644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 801f8973cf4SManikanta Maddireddy 802f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 803f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 804f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 805f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 806f8973cf4SManikanta Maddireddy 807f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 808f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 809f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 810f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 811f8973cf4SManikanta Maddireddy 812954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 813954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 814954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 815954490b3SThierry Reding 816f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 817f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 818f2a465e7SThierry Reding iommu-map-mask = <0x0>; 819f2a465e7SThierry Reding 820f8973cf4SManikanta Maddireddy status = "disabled"; 821f8973cf4SManikanta Maddireddy 822f8973cf4SManikanta Maddireddy pci@1,0 { 823f8973cf4SManikanta Maddireddy device_type = "pci"; 824f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 825f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 826f8973cf4SManikanta Maddireddy status = "disabled"; 827f8973cf4SManikanta Maddireddy 828f8973cf4SManikanta Maddireddy #address-cells = <3>; 829f8973cf4SManikanta Maddireddy #size-cells = <2>; 830f8973cf4SManikanta Maddireddy ranges; 831f8973cf4SManikanta Maddireddy 832f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 833f8973cf4SManikanta Maddireddy }; 834f8973cf4SManikanta Maddireddy 835f8973cf4SManikanta Maddireddy pci@2,0 { 836f8973cf4SManikanta Maddireddy device_type = "pci"; 837f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 838f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 839f8973cf4SManikanta Maddireddy status = "disabled"; 840f8973cf4SManikanta Maddireddy 841f8973cf4SManikanta Maddireddy #address-cells = <3>; 842f8973cf4SManikanta Maddireddy #size-cells = <2>; 843f8973cf4SManikanta Maddireddy ranges; 844f8973cf4SManikanta Maddireddy 845f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 846f8973cf4SManikanta Maddireddy }; 847f8973cf4SManikanta Maddireddy 848f8973cf4SManikanta Maddireddy pci@3,0 { 849f8973cf4SManikanta Maddireddy device_type = "pci"; 850f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 851f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 852f8973cf4SManikanta Maddireddy status = "disabled"; 853f8973cf4SManikanta Maddireddy 854f8973cf4SManikanta Maddireddy #address-cells = <3>; 855f8973cf4SManikanta Maddireddy #size-cells = <2>; 856f8973cf4SManikanta Maddireddy ranges; 857f8973cf4SManikanta Maddireddy 858f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 859f8973cf4SManikanta Maddireddy }; 860f8973cf4SManikanta Maddireddy }; 861f8973cf4SManikanta Maddireddy 862b30a8e61SThierry Reding smmu: iommu@12000000 { 863b30a8e61SThierry Reding compatible = "arm,mmu-500"; 864b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 865b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 888b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 889b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 890b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 891b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 892b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 893b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 894b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 895b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 896b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 897b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 898b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 899b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 900b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 901b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 902b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 903b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 904b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 905b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 906b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 907b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 908b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 909b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 910b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 911b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 912b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 913b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 914b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 915b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 916b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 917b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 918b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 919b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 920b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 921b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 922b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 923b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 924b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 925b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 926b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 927b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 928b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 929b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 930b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 931b30a8e61SThierry Reding #global-interrupts = <1>; 932b30a8e61SThierry Reding #iommu-cells = <1>; 933b30a8e61SThierry Reding }; 934b30a8e61SThierry Reding 9355524c61fSMikko Perttunen host1x@13e00000 { 936ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 9375524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 9385524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 9395524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 9405524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 9415524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 942052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 9435524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 9445524c61fSMikko Perttunen clock-names = "host1x"; 9455524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 9465524c61fSMikko Perttunen reset-names = "host1x"; 9475524c61fSMikko Perttunen 9485524c61fSMikko Perttunen #address-cells = <1>; 9495524c61fSMikko Perttunen #size-cells = <1>; 9505524c61fSMikko Perttunen 9515524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 952954490b3SThierry Reding 953954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 954954490b3SThierry Reding interconnect-names = "dma-mem"; 955954490b3SThierry Reding 956c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 957c2599da7SThierry Reding 958c2599da7SThierry Reding dpaux1: dpaux@15040000 { 959c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 960c2599da7SThierry Reding reg = <0x15040000 0x10000>; 961c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 962c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 963c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 964c2599da7SThierry Reding clock-names = "dpaux", "parent"; 965c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 966c2599da7SThierry Reding reset-names = "dpaux"; 967c2599da7SThierry Reding status = "disabled"; 968c2599da7SThierry Reding 969c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 970c2599da7SThierry Reding 971c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 972c2599da7SThierry Reding groups = "dpaux-io"; 973c2599da7SThierry Reding function = "aux"; 974c2599da7SThierry Reding }; 975c2599da7SThierry Reding 976c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 977c2599da7SThierry Reding groups = "dpaux-io"; 978c2599da7SThierry Reding function = "i2c"; 979c2599da7SThierry Reding }; 980c2599da7SThierry Reding 981c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 982c2599da7SThierry Reding groups = "dpaux-io"; 983c2599da7SThierry Reding function = "off"; 984c2599da7SThierry Reding }; 985c2599da7SThierry Reding 986c2599da7SThierry Reding i2c-bus { 987c2599da7SThierry Reding #address-cells = <1>; 988c2599da7SThierry Reding #size-cells = <0>; 989c2599da7SThierry Reding }; 990c2599da7SThierry Reding }; 991c2599da7SThierry Reding 992c2599da7SThierry Reding display-hub@15200000 { 993c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 994ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 995c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 996c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 997c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 998c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 999c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1000c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1001c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1002c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1003c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1004c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1005c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1006c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1007c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1008c2599da7SThierry Reding status = "disabled"; 1009c2599da7SThierry Reding 1010c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1011c2599da7SThierry Reding 1012c2599da7SThierry Reding #address-cells = <1>; 1013c2599da7SThierry Reding #size-cells = <1>; 1014c2599da7SThierry Reding 1015c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1016c2599da7SThierry Reding 1017c2599da7SThierry Reding display@15200000 { 1018c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1019c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1020c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1021c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1022c2599da7SThierry Reding clock-names = "dc"; 1023c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1024c2599da7SThierry Reding reset-names = "dc"; 1025c2599da7SThierry Reding 1026c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1027954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1028954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1029954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1030c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1031c2599da7SThierry Reding 1032c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1033c2599da7SThierry Reding nvidia,head = <0>; 1034c2599da7SThierry Reding }; 1035c2599da7SThierry Reding 1036c2599da7SThierry Reding display@15210000 { 1037c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1038c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1039c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1040c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1041c2599da7SThierry Reding clock-names = "dc"; 1042c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1043c2599da7SThierry Reding reset-names = "dc"; 1044c2599da7SThierry Reding 1045c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1046954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1047954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1048954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1049c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1050c2599da7SThierry Reding 1051c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1052c2599da7SThierry Reding nvidia,head = <1>; 1053c2599da7SThierry Reding }; 1054c2599da7SThierry Reding 1055c2599da7SThierry Reding display@15220000 { 1056c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1057c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1058c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1059c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1060c2599da7SThierry Reding clock-names = "dc"; 1061c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1062c2599da7SThierry Reding reset-names = "dc"; 1063c2599da7SThierry Reding 1064c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1065954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1066954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1067954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1068c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1069c2599da7SThierry Reding 1070c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1071c2599da7SThierry Reding nvidia,head = <2>; 1072c2599da7SThierry Reding }; 1073c2599da7SThierry Reding }; 1074c2599da7SThierry Reding 1075c2599da7SThierry Reding dsia: dsi@15300000 { 1076c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1077c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1078c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1079c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1080c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1081c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1082c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1083c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1084c2599da7SThierry Reding reset-names = "dsi"; 1085c2599da7SThierry Reding status = "disabled"; 1086c2599da7SThierry Reding 1087c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1088c2599da7SThierry Reding }; 1089effc4b44SMikko Perttunen 1090effc4b44SMikko Perttunen vic@15340000 { 1091effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1092effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1093effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1094effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1095effc4b44SMikko Perttunen clock-names = "vic"; 1096effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1097effc4b44SMikko Perttunen reset-names = "vic"; 1098effc4b44SMikko Perttunen 1099effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1100954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1101954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1102954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 110329ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1104effc4b44SMikko Perttunen }; 1105c2599da7SThierry Reding 1106c2599da7SThierry Reding dsib: dsi@15400000 { 1107c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1108c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1109c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1110c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1111c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1112c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1113c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1114c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1115c2599da7SThierry Reding reset-names = "dsi"; 1116c2599da7SThierry Reding status = "disabled"; 1117c2599da7SThierry Reding 1118c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1119c2599da7SThierry Reding }; 1120c2599da7SThierry Reding 1121c2599da7SThierry Reding sor0: sor@15540000 { 1122c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1123c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1124c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1125c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1126c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1127c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1128c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1129c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1130c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1131c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1132c2599da7SThierry Reding "pad"; 1133c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1134c2599da7SThierry Reding reset-names = "sor"; 1135c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1136c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1137c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1138c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1139c2599da7SThierry Reding status = "disabled"; 1140c2599da7SThierry Reding 1141c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1142c2599da7SThierry Reding nvidia,interface = <0>; 1143c2599da7SThierry Reding }; 1144c2599da7SThierry Reding 1145c2599da7SThierry Reding sor1: sor@15580000 { 1146d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1147c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1148c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1149c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1150c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1151c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1152c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1153c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1154c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1155c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1156c2599da7SThierry Reding "pad"; 1157c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1158c2599da7SThierry Reding reset-names = "sor"; 1159c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1160c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1161c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1162c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1163c2599da7SThierry Reding status = "disabled"; 1164c2599da7SThierry Reding 1165c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1166c2599da7SThierry Reding nvidia,interface = <1>; 1167c2599da7SThierry Reding }; 1168c2599da7SThierry Reding 1169c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1170c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1171c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1172c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1173c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1174c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1175c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1176c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1177c2599da7SThierry Reding reset-names = "dpaux"; 1178c2599da7SThierry Reding status = "disabled"; 1179c2599da7SThierry Reding 1180c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1181c2599da7SThierry Reding 1182c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1183c2599da7SThierry Reding groups = "dpaux-io"; 1184c2599da7SThierry Reding function = "aux"; 1185c2599da7SThierry Reding }; 1186c2599da7SThierry Reding 1187c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1188c2599da7SThierry Reding groups = "dpaux-io"; 1189c2599da7SThierry Reding function = "i2c"; 1190c2599da7SThierry Reding }; 1191c2599da7SThierry Reding 1192c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1193c2599da7SThierry Reding groups = "dpaux-io"; 1194c2599da7SThierry Reding function = "off"; 1195c2599da7SThierry Reding }; 1196c2599da7SThierry Reding 1197c2599da7SThierry Reding i2c-bus { 1198c2599da7SThierry Reding #address-cells = <1>; 1199c2599da7SThierry Reding #size-cells = <0>; 1200c2599da7SThierry Reding }; 1201c2599da7SThierry Reding }; 1202c2599da7SThierry Reding 1203c2599da7SThierry Reding padctl@15880000 { 1204c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1205c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1206c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1207c2599da7SThierry Reding reset-names = "dsi"; 1208c2599da7SThierry Reding status = "disabled"; 1209c2599da7SThierry Reding }; 1210c2599da7SThierry Reding 1211c2599da7SThierry Reding dsic: dsi@15900000 { 1212c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1213c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1214c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1215c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1216c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1217c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1218c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1219c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1220c2599da7SThierry Reding reset-names = "dsi"; 1221c2599da7SThierry Reding status = "disabled"; 1222c2599da7SThierry Reding 1223c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1224c2599da7SThierry Reding }; 1225c2599da7SThierry Reding 1226c2599da7SThierry Reding dsid: dsi@15940000 { 1227c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1228c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1229c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1230c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1231c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1232c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1233c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1234c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1235c2599da7SThierry Reding reset-names = "dsi"; 1236c2599da7SThierry Reding status = "disabled"; 1237c2599da7SThierry Reding 1238c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1239c2599da7SThierry Reding }; 12405524c61fSMikko Perttunen }; 12415524c61fSMikko Perttunen 1242dfd7a384SAlexandre Courbot gpu@17000000 { 1243dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1244dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1245dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 124659a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 124759a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1248dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1249dfd7a384SAlexandre Courbot 1250dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1251dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1252dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1253dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1254dfd7a384SAlexandre Courbot reset-names = "gpu"; 1255dfd7a384SAlexandre Courbot status = "disabled"; 1256dfd7a384SAlexandre Courbot 1257dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1258954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1259954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1260954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1261954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1262954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1263dfd7a384SAlexandre Courbot }; 1264dfd7a384SAlexandre Courbot 126539cb62cbSJoseph Lo sysram@30000000 { 126639cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 126739cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1268aa78032cSThierry Reding #address-cells = <1>; 1269aa78032cSThierry Reding #size-cells = <1>; 1270aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 127139cb62cbSJoseph Lo 127239cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 127339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 1274aa78032cSThierry Reding reg = <0x4e000 0x1000>; 127539cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 127639cb62cbSJoseph Lo pool; 127739cb62cbSJoseph Lo }; 127839cb62cbSJoseph Lo 127939cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 128039cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 1281aa78032cSThierry Reding reg = <0x4f000 0x1000>; 128239cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 128339cb62cbSJoseph Lo pool; 128439cb62cbSJoseph Lo }; 128539cb62cbSJoseph Lo }; 128639cb62cbSJoseph Lo 1287541d7c44SThierry Reding bpmp: bpmp { 1288541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1289954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1290954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1291954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1292954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1293954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1294541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1295541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1296541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1297541d7c44SThierry Reding shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1298541d7c44SThierry Reding #clock-cells = <1>; 1299541d7c44SThierry Reding #reset-cells = <1>; 1300541d7c44SThierry Reding #power-domain-cells = <1>; 1301541d7c44SThierry Reding 1302541d7c44SThierry Reding bpmp_i2c: i2c { 1303541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1304541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1305541d7c44SThierry Reding #address-cells = <1>; 1306541d7c44SThierry Reding #size-cells = <0>; 1307541d7c44SThierry Reding status = "disabled"; 1308541d7c44SThierry Reding }; 1309541d7c44SThierry Reding 1310541d7c44SThierry Reding bpmp_thermal: thermal { 1311541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1312541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1313541d7c44SThierry Reding }; 1314541d7c44SThierry Reding }; 1315541d7c44SThierry Reding 1316cd6fe32eSThierry Reding cpus { 1317cd6fe32eSThierry Reding #address-cells = <1>; 1318cd6fe32eSThierry Reding #size-cells = <0>; 1319cd6fe32eSThierry Reding 1320cd6fe32eSThierry Reding cpu@0 { 132131af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1322cd6fe32eSThierry Reding device_type = "cpu"; 13235298166dSJoseph Lo i-cache-size = <0x20000>; 13245298166dSJoseph Lo i-cache-line-size = <64>; 13255298166dSJoseph Lo i-cache-sets = <512>; 13265298166dSJoseph Lo d-cache-size = <0x10000>; 13275298166dSJoseph Lo d-cache-line-size = <64>; 13285298166dSJoseph Lo d-cache-sets = <256>; 13295298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1330cd6fe32eSThierry Reding reg = <0x000>; 1331cd6fe32eSThierry Reding }; 1332cd6fe32eSThierry Reding 1333cd6fe32eSThierry Reding cpu@1 { 133431af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1335cd6fe32eSThierry Reding device_type = "cpu"; 13365298166dSJoseph Lo i-cache-size = <0x20000>; 13375298166dSJoseph Lo i-cache-line-size = <64>; 13385298166dSJoseph Lo i-cache-sets = <512>; 13395298166dSJoseph Lo d-cache-size = <0x10000>; 13405298166dSJoseph Lo d-cache-line-size = <64>; 13415298166dSJoseph Lo d-cache-sets = <256>; 13425298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1343cd6fe32eSThierry Reding reg = <0x001>; 1344cd6fe32eSThierry Reding }; 1345cd6fe32eSThierry Reding 1346cd6fe32eSThierry Reding cpu@2 { 134731af04cdSRob Herring compatible = "arm,cortex-a57"; 1348cd6fe32eSThierry Reding device_type = "cpu"; 13495298166dSJoseph Lo i-cache-size = <0xC000>; 13505298166dSJoseph Lo i-cache-line-size = <64>; 13515298166dSJoseph Lo i-cache-sets = <256>; 13525298166dSJoseph Lo d-cache-size = <0x8000>; 13535298166dSJoseph Lo d-cache-line-size = <64>; 13545298166dSJoseph Lo d-cache-sets = <256>; 13555298166dSJoseph Lo next-level-cache = <&L2_A57>; 1356cd6fe32eSThierry Reding reg = <0x100>; 1357cd6fe32eSThierry Reding }; 1358cd6fe32eSThierry Reding 1359cd6fe32eSThierry Reding cpu@3 { 136031af04cdSRob Herring compatible = "arm,cortex-a57"; 1361cd6fe32eSThierry Reding device_type = "cpu"; 13625298166dSJoseph Lo i-cache-size = <0xC000>; 13635298166dSJoseph Lo i-cache-line-size = <64>; 13645298166dSJoseph Lo i-cache-sets = <256>; 13655298166dSJoseph Lo d-cache-size = <0x8000>; 13665298166dSJoseph Lo d-cache-line-size = <64>; 13675298166dSJoseph Lo d-cache-sets = <256>; 13685298166dSJoseph Lo next-level-cache = <&L2_A57>; 1369cd6fe32eSThierry Reding reg = <0x101>; 1370cd6fe32eSThierry Reding }; 1371cd6fe32eSThierry Reding 1372cd6fe32eSThierry Reding cpu@4 { 137331af04cdSRob Herring compatible = "arm,cortex-a57"; 1374cd6fe32eSThierry Reding device_type = "cpu"; 13755298166dSJoseph Lo i-cache-size = <0xC000>; 13765298166dSJoseph Lo i-cache-line-size = <64>; 13775298166dSJoseph Lo i-cache-sets = <256>; 13785298166dSJoseph Lo d-cache-size = <0x8000>; 13795298166dSJoseph Lo d-cache-line-size = <64>; 13805298166dSJoseph Lo d-cache-sets = <256>; 13815298166dSJoseph Lo next-level-cache = <&L2_A57>; 1382cd6fe32eSThierry Reding reg = <0x102>; 1383cd6fe32eSThierry Reding }; 1384cd6fe32eSThierry Reding 1385cd6fe32eSThierry Reding cpu@5 { 138631af04cdSRob Herring compatible = "arm,cortex-a57"; 1387cd6fe32eSThierry Reding device_type = "cpu"; 13885298166dSJoseph Lo i-cache-size = <0xC000>; 13895298166dSJoseph Lo i-cache-line-size = <64>; 13905298166dSJoseph Lo i-cache-sets = <256>; 13915298166dSJoseph Lo d-cache-size = <0x8000>; 13925298166dSJoseph Lo d-cache-line-size = <64>; 13935298166dSJoseph Lo d-cache-sets = <256>; 13945298166dSJoseph Lo next-level-cache = <&L2_A57>; 1395cd6fe32eSThierry Reding reg = <0x103>; 1396cd6fe32eSThierry Reding }; 13975298166dSJoseph Lo 13985298166dSJoseph Lo L2_DENVER: l2-cache0 { 13995298166dSJoseph Lo compatible = "cache"; 14005298166dSJoseph Lo cache-unified; 14015298166dSJoseph Lo cache-level = <2>; 14025298166dSJoseph Lo cache-size = <0x200000>; 14035298166dSJoseph Lo cache-line-size = <64>; 14045298166dSJoseph Lo cache-sets = <2048>; 14055298166dSJoseph Lo }; 14065298166dSJoseph Lo 14075298166dSJoseph Lo L2_A57: l2-cache1 { 14085298166dSJoseph Lo compatible = "cache"; 14095298166dSJoseph Lo cache-unified; 14105298166dSJoseph Lo cache-level = <2>; 14115298166dSJoseph Lo cache-size = <0x200000>; 14125298166dSJoseph Lo cache-line-size = <64>; 14135298166dSJoseph Lo cache-sets = <2048>; 14145298166dSJoseph Lo }; 1415cd6fe32eSThierry Reding }; 1416cd6fe32eSThierry Reding 141715274c23SMikko Perttunen thermal-zones { 141815274c23SMikko Perttunen a57 { 141915274c23SMikko Perttunen polling-delay = <0>; 142015274c23SMikko Perttunen polling-delay-passive = <1000>; 142115274c23SMikko Perttunen 142215274c23SMikko Perttunen thermal-sensors = 142315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 142415274c23SMikko Perttunen 142515274c23SMikko Perttunen trips { 142615274c23SMikko Perttunen critical { 142715274c23SMikko Perttunen temperature = <101000>; 142815274c23SMikko Perttunen hysteresis = <0>; 142915274c23SMikko Perttunen type = "critical"; 143015274c23SMikko Perttunen }; 143115274c23SMikko Perttunen }; 143215274c23SMikko Perttunen 143315274c23SMikko Perttunen cooling-maps { 143415274c23SMikko Perttunen }; 143515274c23SMikko Perttunen }; 143615274c23SMikko Perttunen 143715274c23SMikko Perttunen denver { 143815274c23SMikko Perttunen polling-delay = <0>; 143915274c23SMikko Perttunen polling-delay-passive = <1000>; 144015274c23SMikko Perttunen 144115274c23SMikko Perttunen thermal-sensors = 144215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 144315274c23SMikko Perttunen 144415274c23SMikko Perttunen trips { 144515274c23SMikko Perttunen critical { 144615274c23SMikko Perttunen temperature = <101000>; 144715274c23SMikko Perttunen hysteresis = <0>; 144815274c23SMikko Perttunen type = "critical"; 144915274c23SMikko Perttunen }; 145015274c23SMikko Perttunen }; 145115274c23SMikko Perttunen 145215274c23SMikko Perttunen cooling-maps { 145315274c23SMikko Perttunen }; 145415274c23SMikko Perttunen }; 145515274c23SMikko Perttunen 145615274c23SMikko Perttunen gpu { 145715274c23SMikko Perttunen polling-delay = <0>; 145815274c23SMikko Perttunen polling-delay-passive = <1000>; 145915274c23SMikko Perttunen 146015274c23SMikko Perttunen thermal-sensors = 146115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 146215274c23SMikko Perttunen 146315274c23SMikko Perttunen trips { 146415274c23SMikko Perttunen critical { 146515274c23SMikko Perttunen temperature = <101000>; 146615274c23SMikko Perttunen hysteresis = <0>; 146715274c23SMikko Perttunen type = "critical"; 146815274c23SMikko Perttunen }; 146915274c23SMikko Perttunen }; 147015274c23SMikko Perttunen 147115274c23SMikko Perttunen cooling-maps { 147215274c23SMikko Perttunen }; 147315274c23SMikko Perttunen }; 147415274c23SMikko Perttunen 147515274c23SMikko Perttunen pll { 147615274c23SMikko Perttunen polling-delay = <0>; 147715274c23SMikko Perttunen polling-delay-passive = <1000>; 147815274c23SMikko Perttunen 147915274c23SMikko Perttunen thermal-sensors = 148015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 148115274c23SMikko Perttunen 148215274c23SMikko Perttunen trips { 148315274c23SMikko Perttunen critical { 148415274c23SMikko Perttunen temperature = <101000>; 148515274c23SMikko Perttunen hysteresis = <0>; 148615274c23SMikko Perttunen type = "critical"; 148715274c23SMikko Perttunen }; 148815274c23SMikko Perttunen }; 148915274c23SMikko Perttunen 149015274c23SMikko Perttunen cooling-maps { 149115274c23SMikko Perttunen }; 149215274c23SMikko Perttunen }; 149315274c23SMikko Perttunen 149415274c23SMikko Perttunen always_on { 149515274c23SMikko Perttunen polling-delay = <0>; 149615274c23SMikko Perttunen polling-delay-passive = <1000>; 149715274c23SMikko Perttunen 149815274c23SMikko Perttunen thermal-sensors = 149915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 150015274c23SMikko Perttunen 150115274c23SMikko Perttunen trips { 150215274c23SMikko Perttunen critical { 150315274c23SMikko Perttunen temperature = <101000>; 150415274c23SMikko Perttunen hysteresis = <0>; 150515274c23SMikko Perttunen type = "critical"; 150615274c23SMikko Perttunen }; 150715274c23SMikko Perttunen }; 150815274c23SMikko Perttunen 150915274c23SMikko Perttunen cooling-maps { 151015274c23SMikko Perttunen }; 151115274c23SMikko Perttunen }; 151239cb62cbSJoseph Lo }; 151339cb62cbSJoseph Lo 151439cb62cbSJoseph Lo timer { 151539cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 151639cb62cbSJoseph Lo interrupts = <GIC_PPI 13 151739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 151839cb62cbSJoseph Lo <GIC_PPI 14 151939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 152039cb62cbSJoseph Lo <GIC_PPI 11 152139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 152239cb62cbSJoseph Lo <GIC_PPI 10 152339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 152439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1525b30be673SThierry Reding always-on; 152639cb62cbSJoseph Lo }; 152739cb62cbSJoseph Lo}; 1528