139cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 239cb62cbSJoseph Lo 339cb62cbSJoseph Lo/ { 439cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 539cb62cbSJoseph Lo interrupt-parent = <&gic>; 639cb62cbSJoseph Lo #address-cells = <2>; 739cb62cbSJoseph Lo #size-cells = <2>; 839cb62cbSJoseph Lo 939cb62cbSJoseph Lo uarta: serial@3100000 { 1039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 1239cb62cbSJoseph Lo reg-shift = <2>; 1339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14a7a77e2eSThierry Reding clocks = <&bpmp 55>; 15a7a77e2eSThierry Reding clock-names = "serial"; 16a7a77e2eSThierry Reding resets = <&bpmp 47>; 17a7a77e2eSThierry Reding reset-names = "serial"; 18a7a77e2eSThierry Reding status = "disabled"; 19a7a77e2eSThierry Reding }; 20a7a77e2eSThierry Reding 21a7a77e2eSThierry Reding uartb: serial@3110000 { 22a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 23a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 24a7a77e2eSThierry Reding reg-shift = <2>; 25a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 26a7a77e2eSThierry Reding clocks = <&bpmp 56>; 27a7a77e2eSThierry Reding clock-names = "serial"; 28a7a77e2eSThierry Reding resets = <&bpmp 48>; 29a7a77e2eSThierry Reding reset-names = "serial"; 30a7a77e2eSThierry Reding status = "disabled"; 31a7a77e2eSThierry Reding }; 32a7a77e2eSThierry Reding 33a7a77e2eSThierry Reding uartd: serial@3130000 { 34a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 35a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 36a7a77e2eSThierry Reding reg-shift = <2>; 37a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 38a7a77e2eSThierry Reding clocks = <&bpmp 77>; 39a7a77e2eSThierry Reding clock-names = "serial"; 40a7a77e2eSThierry Reding resets = <&bpmp 50>; 41a7a77e2eSThierry Reding reset-names = "serial"; 42a7a77e2eSThierry Reding status = "disabled"; 43a7a77e2eSThierry Reding }; 44a7a77e2eSThierry Reding 45a7a77e2eSThierry Reding uarte: serial@3140000 { 46a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 47a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 48a7a77e2eSThierry Reding reg-shift = <2>; 49a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 50a7a77e2eSThierry Reding clocks = <&bpmp 194>; 51a7a77e2eSThierry Reding clock-names = "serial"; 52a7a77e2eSThierry Reding resets = <&bpmp 132>; 53a7a77e2eSThierry Reding reset-names = "serial"; 54a7a77e2eSThierry Reding status = "disabled"; 55a7a77e2eSThierry Reding }; 56a7a77e2eSThierry Reding 57a7a77e2eSThierry Reding uartf: serial@3150000 { 58a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 59a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 60a7a77e2eSThierry Reding reg-shift = <2>; 61a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62a7a77e2eSThierry Reding clocks = <&bpmp 195>; 63a7a77e2eSThierry Reding clock-names = "serial"; 64a7a77e2eSThierry Reding resets = <&bpmp 111>; 65a7a77e2eSThierry Reding reset-names = "serial"; 6639cb62cbSJoseph Lo status = "disabled"; 6739cb62cbSJoseph Lo }; 6839cb62cbSJoseph Lo 6940cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 7040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 7140cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 7240cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 7340cc83b3SThierry Reding #address-cells = <1>; 7440cc83b3SThierry Reding #size-cells = <0>; 7540cc83b3SThierry Reding clocks = <&bpmp 47>; 7640cc83b3SThierry Reding clock-names = "div-clk"; 7740cc83b3SThierry Reding resets = <&bpmp 19>; 7840cc83b3SThierry Reding reset-names = "i2c"; 7940cc83b3SThierry Reding status = "disabled"; 8040cc83b3SThierry Reding }; 8140cc83b3SThierry Reding 8240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 8340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 8440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 8540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 8640cc83b3SThierry Reding #address-cells = <1>; 8740cc83b3SThierry Reding #size-cells = <0>; 8840cc83b3SThierry Reding clocks = <&bpmp 75>; 8940cc83b3SThierry Reding clock-names = "div-clk"; 9040cc83b3SThierry Reding resets = <&bpmp 21>; 9140cc83b3SThierry Reding reset-names = "i2c"; 9240cc83b3SThierry Reding status = "disabled"; 9340cc83b3SThierry Reding }; 9440cc83b3SThierry Reding 9540cc83b3SThierry Reding /* shares pads with dpaux1 */ 9640cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 9740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 9840cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 9940cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 10040cc83b3SThierry Reding #address-cells = <1>; 10140cc83b3SThierry Reding #size-cells = <0>; 10240cc83b3SThierry Reding clocks = <&bpmp 86>; 10340cc83b3SThierry Reding clock-names = "div-clk"; 10440cc83b3SThierry Reding resets = <&bpmp 22>; 10540cc83b3SThierry Reding reset-names = "i2c"; 10640cc83b3SThierry Reding status = "disabled"; 10740cc83b3SThierry Reding }; 10840cc83b3SThierry Reding 10940cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 11040cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 11140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 11240cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 11340cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 11440cc83b3SThierry Reding #address-cells = <1>; 11540cc83b3SThierry Reding #size-cells = <0>; 11640cc83b3SThierry Reding clocks = <&bpmp 48>; 11740cc83b3SThierry Reding clock-names = "div-clk"; 11840cc83b3SThierry Reding resets = <&bpmp 23>; 11940cc83b3SThierry Reding reset-names = "i2c"; 12040cc83b3SThierry Reding status = "disabled"; 12140cc83b3SThierry Reding }; 12240cc83b3SThierry Reding 12340cc83b3SThierry Reding /* shares pads with dpaux0 */ 12440cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 12540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 12640cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 12740cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 12840cc83b3SThierry Reding #address-cells = <1>; 12940cc83b3SThierry Reding #size-cells = <0>; 13040cc83b3SThierry Reding clocks = <&bpmp 125>; 13140cc83b3SThierry Reding clock-names = "div-clk"; 13240cc83b3SThierry Reding resets = <&bpmp 24>; 13340cc83b3SThierry Reding reset-names = "i2c"; 13440cc83b3SThierry Reding status = "disabled"; 13540cc83b3SThierry Reding }; 13640cc83b3SThierry Reding 13740cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 13840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13940cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 14040cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 14140cc83b3SThierry Reding #address-cells = <1>; 14240cc83b3SThierry Reding #size-cells = <0>; 14340cc83b3SThierry Reding clocks = <&bpmp 182>; 14440cc83b3SThierry Reding clock-names = "div-clk"; 14540cc83b3SThierry Reding resets = <&bpmp 81>; 14640cc83b3SThierry Reding reset-names = "i2c"; 14740cc83b3SThierry Reding status = "disabled"; 14840cc83b3SThierry Reding }; 14940cc83b3SThierry Reding 15040cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 15140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15240cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 15340cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 15440cc83b3SThierry Reding #address-cells = <1>; 15540cc83b3SThierry Reding #size-cells = <0>; 15640cc83b3SThierry Reding clocks = <&bpmp 183>; 15740cc83b3SThierry Reding clock-names = "div-clk"; 15840cc83b3SThierry Reding resets = <&bpmp 83>; 15940cc83b3SThierry Reding reset-names = "i2c"; 16040cc83b3SThierry Reding status = "disabled"; 16140cc83b3SThierry Reding }; 16240cc83b3SThierry Reding 16399425dfdSThierry Reding sdmmc1: sdhci@3400000 { 16499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 16599425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 16699425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 16799425dfdSThierry Reding clocks = <&bpmp 52>; 16899425dfdSThierry Reding clock-names = "sdhci"; 16999425dfdSThierry Reding resets = <&bpmp 33>; 17099425dfdSThierry Reding reset-names = "sdhci"; 17199425dfdSThierry Reding status = "disabled"; 17299425dfdSThierry Reding }; 17399425dfdSThierry Reding 17499425dfdSThierry Reding sdmmc2: sdhci@3420000 { 17599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 17699425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 17799425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 17899425dfdSThierry Reding clocks = <&bpmp 53>; 17999425dfdSThierry Reding clock-names = "sdhci"; 18099425dfdSThierry Reding resets = <&bpmp 34>; 18199425dfdSThierry Reding reset-names = "sdhci"; 18299425dfdSThierry Reding status = "disabled"; 18399425dfdSThierry Reding }; 18499425dfdSThierry Reding 18599425dfdSThierry Reding sdmmc3: sdhci@3440000 { 18699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 18799425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 18899425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 18999425dfdSThierry Reding clocks = <&bpmp 76>; 19099425dfdSThierry Reding clock-names = "sdhci"; 19199425dfdSThierry Reding resets = <&bpmp 35>; 19299425dfdSThierry Reding reset-names = "sdhci"; 19399425dfdSThierry Reding status = "disabled"; 19499425dfdSThierry Reding }; 19599425dfdSThierry Reding 19699425dfdSThierry Reding sdmmc4: sdhci@3460000 { 19799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 19899425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 19999425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 20099425dfdSThierry Reding clocks = <&bpmp 54>; 20199425dfdSThierry Reding clock-names = "sdhci"; 20299425dfdSThierry Reding resets = <&bpmp 36>; 20399425dfdSThierry Reding reset-names = "sdhci"; 20499425dfdSThierry Reding status = "disabled"; 20599425dfdSThierry Reding }; 20699425dfdSThierry Reding 20739cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 20839cb62cbSJoseph Lo compatible = "arm,gic-400"; 20939cb62cbSJoseph Lo #interrupt-cells = <3>; 21039cb62cbSJoseph Lo interrupt-controller; 21139cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 21239cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 21339cb62cbSJoseph Lo interrupts = <GIC_PPI 9 21439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 21539cb62cbSJoseph Lo interrupt-parent = <&gic>; 21639cb62cbSJoseph Lo }; 21739cb62cbSJoseph Lo 21839cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 21939cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 22039cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 22139cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 22239cb62cbSJoseph Lo interrupt-names = "doorbell"; 22339cb62cbSJoseph Lo #mbox-cells = <2>; 22439cb62cbSJoseph Lo status = "disabled"; 22539cb62cbSJoseph Lo }; 22639cb62cbSJoseph Lo 22740cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 22840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22940cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 23040cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 23140cc83b3SThierry Reding #address-cells = <1>; 23240cc83b3SThierry Reding #size-cells = <0>; 23340cc83b3SThierry Reding clocks = <&bpmp 218>; 23440cc83b3SThierry Reding clock-names = "div-clk"; 23540cc83b3SThierry Reding resets = <&bpmp 20>; 23640cc83b3SThierry Reding reset-names = "i2c"; 23740cc83b3SThierry Reding status = "disabled"; 23840cc83b3SThierry Reding }; 23940cc83b3SThierry Reding 24040cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 24140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 24240cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 24340cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 24440cc83b3SThierry Reding #address-cells = <1>; 24540cc83b3SThierry Reding #size-cells = <0>; 24640cc83b3SThierry Reding clocks = <&bpmp 219>; 24740cc83b3SThierry Reding clock-names = "div-clk"; 24840cc83b3SThierry Reding resets = <&bpmp 82>; 24940cc83b3SThierry Reding reset-names = "i2c"; 25040cc83b3SThierry Reding status = "disabled"; 25140cc83b3SThierry Reding }; 25240cc83b3SThierry Reding 253a7a77e2eSThierry Reding uartc: serial@c280000 { 254a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 255a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 256a7a77e2eSThierry Reding reg-shift = <2>; 257a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 258a7a77e2eSThierry Reding clocks = <&bpmp 215>; 259a7a77e2eSThierry Reding clock-names = "serial"; 260a7a77e2eSThierry Reding resets = <&bpmp 49>; 261a7a77e2eSThierry Reding reset-names = "serial"; 262a7a77e2eSThierry Reding status = "disabled"; 263a7a77e2eSThierry Reding }; 264a7a77e2eSThierry Reding 265a7a77e2eSThierry Reding uartg: serial@c290000 { 266a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 267a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 268a7a77e2eSThierry Reding reg-shift = <2>; 269a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 270a7a77e2eSThierry Reding clocks = <&bpmp 216>; 271a7a77e2eSThierry Reding clock-names = "serial"; 272a7a77e2eSThierry Reding resets = <&bpmp 112>; 273a7a77e2eSThierry Reding reset-names = "serial"; 274a7a77e2eSThierry Reding status = "disabled"; 275a7a77e2eSThierry Reding }; 276a7a77e2eSThierry Reding 27739cb62cbSJoseph Lo sysram@30000000 { 27839cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 27939cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 28039cb62cbSJoseph Lo #address-cells = <2>; 28139cb62cbSJoseph Lo #size-cells = <2>; 28239cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 28339cb62cbSJoseph Lo 28439cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 28539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 28639cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 28739cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 28839cb62cbSJoseph Lo pool; 28939cb62cbSJoseph Lo }; 29039cb62cbSJoseph Lo 29139cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 29239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 29339cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 29439cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 29539cb62cbSJoseph Lo pool; 29639cb62cbSJoseph Lo }; 29739cb62cbSJoseph Lo }; 29839cb62cbSJoseph Lo 299cd6fe32eSThierry Reding cpus { 300cd6fe32eSThierry Reding #address-cells = <1>; 301cd6fe32eSThierry Reding #size-cells = <0>; 302cd6fe32eSThierry Reding 303cd6fe32eSThierry Reding cpu@0 { 304cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 305cd6fe32eSThierry Reding device_type = "cpu"; 306cd6fe32eSThierry Reding reg = <0x000>; 307cd6fe32eSThierry Reding }; 308cd6fe32eSThierry Reding 309cd6fe32eSThierry Reding cpu@1 { 310cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 311cd6fe32eSThierry Reding device_type = "cpu"; 312cd6fe32eSThierry Reding reg = <0x001>; 313cd6fe32eSThierry Reding }; 314cd6fe32eSThierry Reding 315cd6fe32eSThierry Reding cpu@2 { 316cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 317cd6fe32eSThierry Reding device_type = "cpu"; 318cd6fe32eSThierry Reding reg = <0x100>; 319cd6fe32eSThierry Reding }; 320cd6fe32eSThierry Reding 321cd6fe32eSThierry Reding cpu@3 { 322cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 323cd6fe32eSThierry Reding device_type = "cpu"; 324cd6fe32eSThierry Reding reg = <0x101>; 325cd6fe32eSThierry Reding }; 326cd6fe32eSThierry Reding 327cd6fe32eSThierry Reding cpu@4 { 328cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 329cd6fe32eSThierry Reding device_type = "cpu"; 330cd6fe32eSThierry Reding reg = <0x102>; 331cd6fe32eSThierry Reding }; 332cd6fe32eSThierry Reding 333cd6fe32eSThierry Reding cpu@5 { 334cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 335cd6fe32eSThierry Reding device_type = "cpu"; 336cd6fe32eSThierry Reding reg = <0x103>; 337cd6fe32eSThierry Reding }; 338cd6fe32eSThierry Reding }; 339cd6fe32eSThierry Reding 34039cb62cbSJoseph Lo bpmp: bpmp { 34139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 34239cb62cbSJoseph Lo mboxes = <&hsp_top0 0 19>; 34339cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 34439cb62cbSJoseph Lo #clock-cells = <1>; 34539cb62cbSJoseph Lo #reset-cells = <1>; 34639cb62cbSJoseph Lo 34739cb62cbSJoseph Lo bpmp_i2c: i2c { 34839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 34939cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 35039cb62cbSJoseph Lo #address-cells = <1>; 35139cb62cbSJoseph Lo #size-cells = <0>; 35239cb62cbSJoseph Lo status = "disabled"; 35339cb62cbSJoseph Lo }; 35439cb62cbSJoseph Lo }; 35539cb62cbSJoseph Lo 35639cb62cbSJoseph Lo timer { 35739cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 35839cb62cbSJoseph Lo interrupts = <GIC_PPI 13 35939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 36039cb62cbSJoseph Lo <GIC_PPI 14 36139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 36239cb62cbSJoseph Lo <GIC_PPI 11 36339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 36439cb62cbSJoseph Lo <GIC_PPI 10 36539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 36639cb62cbSJoseph Lo interrupt-parent = <&gic>; 36739cb62cbSJoseph Lo }; 36839cb62cbSJoseph Lo}; 369