1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 630caafbdeSThierry Reding status = "disabled"; 640caafbdeSThierry Reding 650caafbdeSThierry Reding snps,write-requests = <1>; 660caafbdeSThierry Reding snps,read-requests = <3>; 670caafbdeSThierry Reding snps,burst-map = <0x7>; 680caafbdeSThierry Reding snps,txpbl = <32>; 690caafbdeSThierry Reding snps,rxpbl = <8>; 700caafbdeSThierry Reding }; 710caafbdeSThierry Reding 72d25a3bf1SThierry Reding memory-controller@2c00000 { 73d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 74d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 75d25a3bf1SThierry Reding status = "disabled"; 76d25a3bf1SThierry Reding }; 77d25a3bf1SThierry Reding 7839cb62cbSJoseph Lo uarta: serial@3100000 { 7939cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8039cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8139cb62cbSJoseph Lo reg-shift = <2>; 8239cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 84a7a77e2eSThierry Reding clock-names = "serial"; 857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 86a7a77e2eSThierry Reding reset-names = "serial"; 87a7a77e2eSThierry Reding status = "disabled"; 88a7a77e2eSThierry Reding }; 89a7a77e2eSThierry Reding 90a7a77e2eSThierry Reding uartb: serial@3110000 { 91a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 93a7a77e2eSThierry Reding reg-shift = <2>; 94a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 96a7a77e2eSThierry Reding clock-names = "serial"; 977bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 98a7a77e2eSThierry Reding reset-names = "serial"; 99a7a77e2eSThierry Reding status = "disabled"; 100a7a77e2eSThierry Reding }; 101a7a77e2eSThierry Reding 102a7a77e2eSThierry Reding uartd: serial@3130000 { 103a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 105a7a77e2eSThierry Reding reg-shift = <2>; 106a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 108a7a77e2eSThierry Reding clock-names = "serial"; 1097bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 110a7a77e2eSThierry Reding reset-names = "serial"; 111a7a77e2eSThierry Reding status = "disabled"; 112a7a77e2eSThierry Reding }; 113a7a77e2eSThierry Reding 114a7a77e2eSThierry Reding uarte: serial@3140000 { 115a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 117a7a77e2eSThierry Reding reg-shift = <2>; 118a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 120a7a77e2eSThierry Reding clock-names = "serial"; 1217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 122a7a77e2eSThierry Reding reset-names = "serial"; 123a7a77e2eSThierry Reding status = "disabled"; 124a7a77e2eSThierry Reding }; 125a7a77e2eSThierry Reding 126a7a77e2eSThierry Reding uartf: serial@3150000 { 127a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 129a7a77e2eSThierry Reding reg-shift = <2>; 130a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 132a7a77e2eSThierry Reding clock-names = "serial"; 1337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 134a7a77e2eSThierry Reding reset-names = "serial"; 13539cb62cbSJoseph Lo status = "disabled"; 13639cb62cbSJoseph Lo }; 13739cb62cbSJoseph Lo 13840cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14040cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14140cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14240cc83b3SThierry Reding #address-cells = <1>; 14340cc83b3SThierry Reding #size-cells = <0>; 144c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14540cc83b3SThierry Reding clock-names = "div-clk"; 1467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14740cc83b3SThierry Reding reset-names = "i2c"; 14840cc83b3SThierry Reding status = "disabled"; 14940cc83b3SThierry Reding }; 15040cc83b3SThierry Reding 15140cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15340cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15440cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15540cc83b3SThierry Reding #address-cells = <1>; 15640cc83b3SThierry Reding #size-cells = <0>; 157c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15840cc83b3SThierry Reding clock-names = "div-clk"; 1597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16040cc83b3SThierry Reding reset-names = "i2c"; 16140cc83b3SThierry Reding status = "disabled"; 16240cc83b3SThierry Reding }; 16340cc83b3SThierry Reding 16440cc83b3SThierry Reding /* shares pads with dpaux1 */ 16540cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16740cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16840cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16940cc83b3SThierry Reding #address-cells = <1>; 17040cc83b3SThierry Reding #size-cells = <0>; 171c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17240cc83b3SThierry Reding clock-names = "div-clk"; 1737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17440cc83b3SThierry Reding reset-names = "i2c"; 17540cc83b3SThierry Reding status = "disabled"; 17640cc83b3SThierry Reding }; 17740cc83b3SThierry Reding 17840cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17940cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 18040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18140cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18240cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18340cc83b3SThierry Reding #address-cells = <1>; 18440cc83b3SThierry Reding #size-cells = <0>; 185c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18640cc83b3SThierry Reding clock-names = "div-clk"; 1877bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18840cc83b3SThierry Reding reset-names = "i2c"; 18940cc83b3SThierry Reding status = "disabled"; 19040cc83b3SThierry Reding }; 19140cc83b3SThierry Reding 19240cc83b3SThierry Reding /* shares pads with dpaux0 */ 19340cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19540cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19640cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19740cc83b3SThierry Reding #address-cells = <1>; 19840cc83b3SThierry Reding #size-cells = <0>; 199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20040cc83b3SThierry Reding clock-names = "div-clk"; 2017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20240cc83b3SThierry Reding reset-names = "i2c"; 20340cc83b3SThierry Reding status = "disabled"; 20440cc83b3SThierry Reding }; 20540cc83b3SThierry Reding 20640cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20840cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20940cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21040cc83b3SThierry Reding #address-cells = <1>; 21140cc83b3SThierry Reding #size-cells = <0>; 212c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21340cc83b3SThierry Reding clock-names = "div-clk"; 2147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21540cc83b3SThierry Reding reset-names = "i2c"; 21640cc83b3SThierry Reding status = "disabled"; 21740cc83b3SThierry Reding }; 21840cc83b3SThierry Reding 21940cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 22040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22140cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22240cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22340cc83b3SThierry Reding #address-cells = <1>; 22440cc83b3SThierry Reding #size-cells = <0>; 225c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22640cc83b3SThierry Reding clock-names = "div-clk"; 2277bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22840cc83b3SThierry Reding reset-names = "i2c"; 22940cc83b3SThierry Reding status = "disabled"; 23040cc83b3SThierry Reding }; 23140cc83b3SThierry Reding 23299425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23499425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23599425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23799425dfdSThierry Reding clock-names = "sdhci"; 2387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23999425dfdSThierry Reding reset-names = "sdhci"; 24024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 24224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 24341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 24441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 24541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 24641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 24741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 24841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 2496f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2506f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 25198a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 25298a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25398a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25499425dfdSThierry Reding status = "disabled"; 25599425dfdSThierry Reding }; 25699425dfdSThierry Reding 25799425dfdSThierry Reding sdmmc2: sdhci@3420000 { 25899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25999425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 26099425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 26299425dfdSThierry Reding clock-names = "sdhci"; 2637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 26499425dfdSThierry Reding reset-names = "sdhci"; 26524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 26624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 26724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 26841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 26941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 27041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 27141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2726f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2736f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 27499425dfdSThierry Reding status = "disabled"; 27599425dfdSThierry Reding }; 27699425dfdSThierry Reding 27799425dfdSThierry Reding sdmmc3: sdhci@3440000 { 27899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 27999425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 28099425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 28299425dfdSThierry Reding clock-names = "sdhci"; 2837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 28499425dfdSThierry Reding reset-names = "sdhci"; 28524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 28624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 28724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 28841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 28941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 29041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 29141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 29241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 29341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2946f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2956f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 29699425dfdSThierry Reding status = "disabled"; 29799425dfdSThierry Reding }; 29899425dfdSThierry Reding 29999425dfdSThierry Reding sdmmc4: sdhci@3460000 { 30099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 30199425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 30299425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 30499425dfdSThierry Reding clock-names = "sdhci"; 30598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 30698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 30798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 3087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 30999425dfdSThierry Reding reset-names = "sdhci"; 31041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 31141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 31241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 31341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3146f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3156f90c6f0SAapo Vienamo nvidia,default-trim = <0x9>; 31622248e91SAapo Vienamo nvidia,dqs-trim = <63>; 317207f60baSAapo Vienamo mmc-hs400-1_8v; 31899425dfdSThierry Reding status = "disabled"; 31999425dfdSThierry Reding }; 32099425dfdSThierry Reding 321b066a310SThierry Reding hda@3510000 { 322b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 323b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 324b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 325b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 326b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 327b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 328b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 329b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 330b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 331b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 332b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 333b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 334b066a310SThierry Reding status = "disabled"; 335b066a310SThierry Reding }; 336b066a310SThierry Reding 33785593b75SThierry Reding fuse@3820000 { 33885593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 33985593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 34085593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 34185593b75SThierry Reding clock-names = "fuse"; 34285593b75SThierry Reding }; 34385593b75SThierry Reding 34439cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 34539cb62cbSJoseph Lo compatible = "arm,gic-400"; 34639cb62cbSJoseph Lo #interrupt-cells = <3>; 34739cb62cbSJoseph Lo interrupt-controller; 34839cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 34939cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 35039cb62cbSJoseph Lo interrupts = <GIC_PPI 9 35139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 35239cb62cbSJoseph Lo interrupt-parent = <&gic>; 35339cb62cbSJoseph Lo }; 35439cb62cbSJoseph Lo 35597cf683cSThierry Reding cec@3960000 { 35697cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 35797cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 35897cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 35997cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 36097cf683cSThierry Reding clock-names = "cec"; 36197cf683cSThierry Reding status = "disabled"; 36297cf683cSThierry Reding }; 36397cf683cSThierry Reding 36439cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 36539cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 36639cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 36739cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 36839cb62cbSJoseph Lo interrupt-names = "doorbell"; 36939cb62cbSJoseph Lo #mbox-cells = <2>; 37039cb62cbSJoseph Lo status = "disabled"; 37139cb62cbSJoseph Lo }; 37239cb62cbSJoseph Lo 37340cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 37440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 37540cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 37640cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 37740cc83b3SThierry Reding #address-cells = <1>; 37840cc83b3SThierry Reding #size-cells = <0>; 379c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 38040cc83b3SThierry Reding clock-names = "div-clk"; 3817bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 38240cc83b3SThierry Reding reset-names = "i2c"; 38340cc83b3SThierry Reding status = "disabled"; 38440cc83b3SThierry Reding }; 38540cc83b3SThierry Reding 38640cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 38740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 38840cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 38940cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 39040cc83b3SThierry Reding #address-cells = <1>; 39140cc83b3SThierry Reding #size-cells = <0>; 392c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 39340cc83b3SThierry Reding clock-names = "div-clk"; 3947bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 39540cc83b3SThierry Reding reset-names = "i2c"; 39640cc83b3SThierry Reding status = "disabled"; 39740cc83b3SThierry Reding }; 39840cc83b3SThierry Reding 399a7a77e2eSThierry Reding uartc: serial@c280000 { 400a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 401a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 402a7a77e2eSThierry Reding reg-shift = <2>; 403a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 404c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 405a7a77e2eSThierry Reding clock-names = "serial"; 4067bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 407a7a77e2eSThierry Reding reset-names = "serial"; 408a7a77e2eSThierry Reding status = "disabled"; 409a7a77e2eSThierry Reding }; 410a7a77e2eSThierry Reding 411a7a77e2eSThierry Reding uartg: serial@c290000 { 412a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 413a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 414a7a77e2eSThierry Reding reg-shift = <2>; 415a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 416c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 417a7a77e2eSThierry Reding clock-names = "serial"; 4187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 419a7a77e2eSThierry Reding reset-names = "serial"; 420a7a77e2eSThierry Reding status = "disabled"; 421a7a77e2eSThierry Reding }; 422a7a77e2eSThierry Reding 4239733a251SThierry Reding rtc: rtc@c2a0000 { 4249733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 4259733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 4269733a251SThierry Reding interrupt-parent = <&pmc>; 4279733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 4289733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 4299733a251SThierry Reding clock-names = "rtc"; 4309733a251SThierry Reding status = "disabled"; 4319733a251SThierry Reding }; 4329733a251SThierry Reding 433fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 434fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 435fc4bb754SThierry Reding reg-names = "security", "gpio"; 436fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 437fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 438fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 439fc4bb754SThierry Reding gpio-controller; 440fc4bb754SThierry Reding #gpio-cells = <2>; 441fc4bb754SThierry Reding interrupt-controller; 442fc4bb754SThierry Reding #interrupt-cells = <2>; 443fc4bb754SThierry Reding }; 444fc4bb754SThierry Reding 44532e66e46SThierry Reding pmc: pmc@c360000 { 44673bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 44773bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 44873bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 44973bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 45073bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 45173bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 45224005fd1SAapo Vienamo 45332e66e46SThierry Reding #interrupt-cells = <2>; 45432e66e46SThierry Reding interrupt-controller; 45532e66e46SThierry Reding 45624005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 45724005fd1SAapo Vienamo pins = "sdmmc1-hv"; 45824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 45924005fd1SAapo Vienamo }; 46024005fd1SAapo Vienamo 46124005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 46224005fd1SAapo Vienamo pins = "sdmmc1-hv"; 46324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 46424005fd1SAapo Vienamo }; 46524005fd1SAapo Vienamo 46624005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 46724005fd1SAapo Vienamo pins = "sdmmc2-hv"; 46824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 46924005fd1SAapo Vienamo }; 47024005fd1SAapo Vienamo 47124005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 47224005fd1SAapo Vienamo pins = "sdmmc2-hv"; 47324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 47424005fd1SAapo Vienamo }; 47524005fd1SAapo Vienamo 47624005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 47724005fd1SAapo Vienamo pins = "sdmmc3-hv"; 47824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 47924005fd1SAapo Vienamo }; 48024005fd1SAapo Vienamo 48124005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 48224005fd1SAapo Vienamo pins = "sdmmc3-hv"; 48324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 48424005fd1SAapo Vienamo }; 48573bf90d4SThierry Reding }; 48673bf90d4SThierry Reding 4877b7ef494SMikko Perttunen ccplex@e000000 { 4887b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 4897b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 4907b7ef494SMikko Perttunen 4917b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 4927b7ef494SMikko Perttunen }; 4937b7ef494SMikko Perttunen 494f8973cf4SManikanta Maddireddy pcie@10003000 { 495f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 496f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 497f8973cf4SManikanta Maddireddy device_type = "pci"; 498f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 499f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 500f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 501f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 502f8973cf4SManikanta Maddireddy 503f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 504f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 505f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 506f8973cf4SManikanta Maddireddy 507f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 508f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 509f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 510f8973cf4SManikanta Maddireddy 511f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 512f8973cf4SManikanta Maddireddy #address-cells = <3>; 513f8973cf4SManikanta Maddireddy #size-cells = <2>; 514f8973cf4SManikanta Maddireddy 515f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 516f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 517f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 518f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 519f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 520f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 521f8973cf4SManikanta Maddireddy 522f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 523f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 524f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 525f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 526f8973cf4SManikanta Maddireddy 527f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 528f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 529f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 530f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 531f8973cf4SManikanta Maddireddy 532f8973cf4SManikanta Maddireddy status = "disabled"; 533f8973cf4SManikanta Maddireddy 534f8973cf4SManikanta Maddireddy pci@1,0 { 535f8973cf4SManikanta Maddireddy device_type = "pci"; 536f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 537f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 538f8973cf4SManikanta Maddireddy status = "disabled"; 539f8973cf4SManikanta Maddireddy 540f8973cf4SManikanta Maddireddy #address-cells = <3>; 541f8973cf4SManikanta Maddireddy #size-cells = <2>; 542f8973cf4SManikanta Maddireddy ranges; 543f8973cf4SManikanta Maddireddy 544f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 545f8973cf4SManikanta Maddireddy }; 546f8973cf4SManikanta Maddireddy 547f8973cf4SManikanta Maddireddy pci@2,0 { 548f8973cf4SManikanta Maddireddy device_type = "pci"; 549f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 550f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 551f8973cf4SManikanta Maddireddy status = "disabled"; 552f8973cf4SManikanta Maddireddy 553f8973cf4SManikanta Maddireddy #address-cells = <3>; 554f8973cf4SManikanta Maddireddy #size-cells = <2>; 555f8973cf4SManikanta Maddireddy ranges; 556f8973cf4SManikanta Maddireddy 557f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 558f8973cf4SManikanta Maddireddy }; 559f8973cf4SManikanta Maddireddy 560f8973cf4SManikanta Maddireddy pci@3,0 { 561f8973cf4SManikanta Maddireddy device_type = "pci"; 562f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 563f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 564f8973cf4SManikanta Maddireddy status = "disabled"; 565f8973cf4SManikanta Maddireddy 566f8973cf4SManikanta Maddireddy #address-cells = <3>; 567f8973cf4SManikanta Maddireddy #size-cells = <2>; 568f8973cf4SManikanta Maddireddy ranges; 569f8973cf4SManikanta Maddireddy 570f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 571f8973cf4SManikanta Maddireddy }; 572f8973cf4SManikanta Maddireddy }; 573f8973cf4SManikanta Maddireddy 574b30a8e61SThierry Reding smmu: iommu@12000000 { 575b30a8e61SThierry Reding compatible = "arm,mmu-500"; 576b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 577b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 617b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 618b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 619b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 620b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 621b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 622b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 623b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 624b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 625b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 626b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 627b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 628b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 629b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 630b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 631b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 632b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 633b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 634b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 635b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 636b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 637b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 638b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 639b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 640b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 641b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 642b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 643b30a8e61SThierry Reding #global-interrupts = <1>; 644b30a8e61SThierry Reding #iommu-cells = <1>; 645b30a8e61SThierry Reding }; 646b30a8e61SThierry Reding 6475524c61fSMikko Perttunen host1x@13e00000 { 6485524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 6495524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 6505524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 6515524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 6525524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 6535524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 6545524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 6555524c61fSMikko Perttunen clock-names = "host1x"; 6565524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 6575524c61fSMikko Perttunen reset-names = "host1x"; 6585524c61fSMikko Perttunen 6595524c61fSMikko Perttunen #address-cells = <1>; 6605524c61fSMikko Perttunen #size-cells = <1>; 6615524c61fSMikko Perttunen 6625524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 663c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 664c2599da7SThierry Reding 665c2599da7SThierry Reding dpaux1: dpaux@15040000 { 666c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 667c2599da7SThierry Reding reg = <0x15040000 0x10000>; 668c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 669c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 670c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 671c2599da7SThierry Reding clock-names = "dpaux", "parent"; 672c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 673c2599da7SThierry Reding reset-names = "dpaux"; 674c2599da7SThierry Reding status = "disabled"; 675c2599da7SThierry Reding 676c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 677c2599da7SThierry Reding 678c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 679c2599da7SThierry Reding groups = "dpaux-io"; 680c2599da7SThierry Reding function = "aux"; 681c2599da7SThierry Reding }; 682c2599da7SThierry Reding 683c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 684c2599da7SThierry Reding groups = "dpaux-io"; 685c2599da7SThierry Reding function = "i2c"; 686c2599da7SThierry Reding }; 687c2599da7SThierry Reding 688c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 689c2599da7SThierry Reding groups = "dpaux-io"; 690c2599da7SThierry Reding function = "off"; 691c2599da7SThierry Reding }; 692c2599da7SThierry Reding 693c2599da7SThierry Reding i2c-bus { 694c2599da7SThierry Reding #address-cells = <1>; 695c2599da7SThierry Reding #size-cells = <0>; 696c2599da7SThierry Reding }; 697c2599da7SThierry Reding }; 698c2599da7SThierry Reding 699c2599da7SThierry Reding display-hub@15200000 { 700c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 701c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 702c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 703c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 704c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 705c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 706c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 707c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 708c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 709c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 710c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 711c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 712c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 713c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 714c2599da7SThierry Reding status = "disabled"; 715c2599da7SThierry Reding 716c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 717c2599da7SThierry Reding 718c2599da7SThierry Reding #address-cells = <1>; 719c2599da7SThierry Reding #size-cells = <1>; 720c2599da7SThierry Reding 721c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 722c2599da7SThierry Reding 723c2599da7SThierry Reding display@15200000 { 724c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 725c2599da7SThierry Reding reg = <0x15200000 0x10000>; 726c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 727c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 728c2599da7SThierry Reding clock-names = "dc"; 729c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 730c2599da7SThierry Reding reset-names = "dc"; 731c2599da7SThierry Reding 732c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 733c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 734c2599da7SThierry Reding 735c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 736c2599da7SThierry Reding nvidia,head = <0>; 737c2599da7SThierry Reding }; 738c2599da7SThierry Reding 739c2599da7SThierry Reding display@15210000 { 740c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 741c2599da7SThierry Reding reg = <0x15210000 0x10000>; 742c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 743c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 744c2599da7SThierry Reding clock-names = "dc"; 745c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 746c2599da7SThierry Reding reset-names = "dc"; 747c2599da7SThierry Reding 748c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 749c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 750c2599da7SThierry Reding 751c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 752c2599da7SThierry Reding nvidia,head = <1>; 753c2599da7SThierry Reding }; 754c2599da7SThierry Reding 755c2599da7SThierry Reding display@15220000 { 756c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 757c2599da7SThierry Reding reg = <0x15220000 0x10000>; 758c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 759c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 760c2599da7SThierry Reding clock-names = "dc"; 761c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 762c2599da7SThierry Reding reset-names = "dc"; 763c2599da7SThierry Reding 764c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 765c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 766c2599da7SThierry Reding 767c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 768c2599da7SThierry Reding nvidia,head = <2>; 769c2599da7SThierry Reding }; 770c2599da7SThierry Reding }; 771c2599da7SThierry Reding 772c2599da7SThierry Reding dsia: dsi@15300000 { 773c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 774c2599da7SThierry Reding reg = <0x15300000 0x10000>; 775c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 776c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 777c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 778c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 779c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 780c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 781c2599da7SThierry Reding reset-names = "dsi"; 782c2599da7SThierry Reding status = "disabled"; 783c2599da7SThierry Reding 784c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 785c2599da7SThierry Reding }; 786effc4b44SMikko Perttunen 787effc4b44SMikko Perttunen vic@15340000 { 788effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 789effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 790effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 791effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 792effc4b44SMikko Perttunen clock-names = "vic"; 793effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 794effc4b44SMikko Perttunen reset-names = "vic"; 795effc4b44SMikko Perttunen 796effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 797effc4b44SMikko Perttunen }; 798c2599da7SThierry Reding 799c2599da7SThierry Reding dsib: dsi@15400000 { 800c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 801c2599da7SThierry Reding reg = <0x15400000 0x10000>; 802c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 803c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 804c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 805c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 806c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 807c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 808c2599da7SThierry Reding reset-names = "dsi"; 809c2599da7SThierry Reding status = "disabled"; 810c2599da7SThierry Reding 811c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 812c2599da7SThierry Reding }; 813c2599da7SThierry Reding 814c2599da7SThierry Reding sor0: sor@15540000 { 815c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 816c2599da7SThierry Reding reg = <0x15540000 0x10000>; 817c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 818c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 819c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 820c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 821c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 822c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 823c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 824c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 825c2599da7SThierry Reding "pad"; 826c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 827c2599da7SThierry Reding reset-names = "sor"; 828c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 829c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 830c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 831c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 832c2599da7SThierry Reding status = "disabled"; 833c2599da7SThierry Reding 834c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 835c2599da7SThierry Reding nvidia,interface = <0>; 836c2599da7SThierry Reding }; 837c2599da7SThierry Reding 838c2599da7SThierry Reding sor1: sor@15580000 { 839c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 840c2599da7SThierry Reding reg = <0x15580000 0x10000>; 841c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 842c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 843c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 844c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 845c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 846c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 847c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 848c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 849c2599da7SThierry Reding "pad"; 850c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 851c2599da7SThierry Reding reset-names = "sor"; 852c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 853c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 854c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 855c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 856c2599da7SThierry Reding status = "disabled"; 857c2599da7SThierry Reding 858c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 859c2599da7SThierry Reding nvidia,interface = <1>; 860c2599da7SThierry Reding }; 861c2599da7SThierry Reding 862c2599da7SThierry Reding dpaux: dpaux@155c0000 { 863c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 864c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 865c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 866c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 867c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 868c2599da7SThierry Reding clock-names = "dpaux", "parent"; 869c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 870c2599da7SThierry Reding reset-names = "dpaux"; 871c2599da7SThierry Reding status = "disabled"; 872c2599da7SThierry Reding 873c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 874c2599da7SThierry Reding 875c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 876c2599da7SThierry Reding groups = "dpaux-io"; 877c2599da7SThierry Reding function = "aux"; 878c2599da7SThierry Reding }; 879c2599da7SThierry Reding 880c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 881c2599da7SThierry Reding groups = "dpaux-io"; 882c2599da7SThierry Reding function = "i2c"; 883c2599da7SThierry Reding }; 884c2599da7SThierry Reding 885c2599da7SThierry Reding state_dpaux_off: pinmux-off { 886c2599da7SThierry Reding groups = "dpaux-io"; 887c2599da7SThierry Reding function = "off"; 888c2599da7SThierry Reding }; 889c2599da7SThierry Reding 890c2599da7SThierry Reding i2c-bus { 891c2599da7SThierry Reding #address-cells = <1>; 892c2599da7SThierry Reding #size-cells = <0>; 893c2599da7SThierry Reding }; 894c2599da7SThierry Reding }; 895c2599da7SThierry Reding 896c2599da7SThierry Reding padctl@15880000 { 897c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 898c2599da7SThierry Reding reg = <0x15880000 0x10000>; 899c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 900c2599da7SThierry Reding reset-names = "dsi"; 901c2599da7SThierry Reding status = "disabled"; 902c2599da7SThierry Reding }; 903c2599da7SThierry Reding 904c2599da7SThierry Reding dsic: dsi@15900000 { 905c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 906c2599da7SThierry Reding reg = <0x15900000 0x10000>; 907c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 908c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 909c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 910c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 911c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 912c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 913c2599da7SThierry Reding reset-names = "dsi"; 914c2599da7SThierry Reding status = "disabled"; 915c2599da7SThierry Reding 916c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 917c2599da7SThierry Reding }; 918c2599da7SThierry Reding 919c2599da7SThierry Reding dsid: dsi@15940000 { 920c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 921c2599da7SThierry Reding reg = <0x15940000 0x10000>; 922c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 923c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 924c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 925c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 926c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 927c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 928c2599da7SThierry Reding reset-names = "dsi"; 929c2599da7SThierry Reding status = "disabled"; 930c2599da7SThierry Reding 931c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 932c2599da7SThierry Reding }; 9335524c61fSMikko Perttunen }; 9345524c61fSMikko Perttunen 935dfd7a384SAlexandre Courbot gpu@17000000 { 936dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 937dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 938dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 939dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 940dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 941dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 942dfd7a384SAlexandre Courbot 943dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 944dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 945dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 946dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 947dfd7a384SAlexandre Courbot reset-names = "gpu"; 948dfd7a384SAlexandre Courbot status = "disabled"; 949dfd7a384SAlexandre Courbot 950dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 951dfd7a384SAlexandre Courbot }; 952dfd7a384SAlexandre Courbot 95339cb62cbSJoseph Lo sysram@30000000 { 95439cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 95539cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 95639cb62cbSJoseph Lo #address-cells = <2>; 95739cb62cbSJoseph Lo #size-cells = <2>; 95839cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 95939cb62cbSJoseph Lo 96039cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 96139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 96239cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 96339cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 96439cb62cbSJoseph Lo pool; 96539cb62cbSJoseph Lo }; 96639cb62cbSJoseph Lo 96739cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 96839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 96939cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 97039cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 97139cb62cbSJoseph Lo pool; 97239cb62cbSJoseph Lo }; 97339cb62cbSJoseph Lo }; 97439cb62cbSJoseph Lo 975cd6fe32eSThierry Reding cpus { 976cd6fe32eSThierry Reding #address-cells = <1>; 977cd6fe32eSThierry Reding #size-cells = <0>; 978cd6fe32eSThierry Reding 979cd6fe32eSThierry Reding cpu@0 { 980cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 981cd6fe32eSThierry Reding device_type = "cpu"; 982cd6fe32eSThierry Reding reg = <0x000>; 983cd6fe32eSThierry Reding }; 984cd6fe32eSThierry Reding 985cd6fe32eSThierry Reding cpu@1 { 986cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 987cd6fe32eSThierry Reding device_type = "cpu"; 988cd6fe32eSThierry Reding reg = <0x001>; 989cd6fe32eSThierry Reding }; 990cd6fe32eSThierry Reding 991cd6fe32eSThierry Reding cpu@2 { 992cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 993cd6fe32eSThierry Reding device_type = "cpu"; 994cd6fe32eSThierry Reding reg = <0x100>; 995cd6fe32eSThierry Reding }; 996cd6fe32eSThierry Reding 997cd6fe32eSThierry Reding cpu@3 { 998cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 999cd6fe32eSThierry Reding device_type = "cpu"; 1000cd6fe32eSThierry Reding reg = <0x101>; 1001cd6fe32eSThierry Reding }; 1002cd6fe32eSThierry Reding 1003cd6fe32eSThierry Reding cpu@4 { 1004cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 1005cd6fe32eSThierry Reding device_type = "cpu"; 1006cd6fe32eSThierry Reding reg = <0x102>; 1007cd6fe32eSThierry Reding }; 1008cd6fe32eSThierry Reding 1009cd6fe32eSThierry Reding cpu@5 { 1010cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 1011cd6fe32eSThierry Reding device_type = "cpu"; 1012cd6fe32eSThierry Reding reg = <0x103>; 1013cd6fe32eSThierry Reding }; 1014cd6fe32eSThierry Reding }; 1015cd6fe32eSThierry Reding 101639cb62cbSJoseph Lo bpmp: bpmp { 101739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 10185edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 10195edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 102039cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 102139cb62cbSJoseph Lo #clock-cells = <1>; 102239cb62cbSJoseph Lo #reset-cells = <1>; 1023dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 102439cb62cbSJoseph Lo 102539cb62cbSJoseph Lo bpmp_i2c: i2c { 102639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 102739cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 102839cb62cbSJoseph Lo #address-cells = <1>; 102939cb62cbSJoseph Lo #size-cells = <0>; 103039cb62cbSJoseph Lo status = "disabled"; 103139cb62cbSJoseph Lo }; 103215274c23SMikko Perttunen 103315274c23SMikko Perttunen bpmp_thermal: thermal { 103415274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 103515274c23SMikko Perttunen #thermal-sensor-cells = <1>; 103615274c23SMikko Perttunen }; 103715274c23SMikko Perttunen }; 103815274c23SMikko Perttunen 103915274c23SMikko Perttunen thermal-zones { 104015274c23SMikko Perttunen a57 { 104115274c23SMikko Perttunen polling-delay = <0>; 104215274c23SMikko Perttunen polling-delay-passive = <1000>; 104315274c23SMikko Perttunen 104415274c23SMikko Perttunen thermal-sensors = 104515274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 104615274c23SMikko Perttunen 104715274c23SMikko Perttunen trips { 104815274c23SMikko Perttunen critical { 104915274c23SMikko Perttunen temperature = <101000>; 105015274c23SMikko Perttunen hysteresis = <0>; 105115274c23SMikko Perttunen type = "critical"; 105215274c23SMikko Perttunen }; 105315274c23SMikko Perttunen }; 105415274c23SMikko Perttunen 105515274c23SMikko Perttunen cooling-maps { 105615274c23SMikko Perttunen }; 105715274c23SMikko Perttunen }; 105815274c23SMikko Perttunen 105915274c23SMikko Perttunen denver { 106015274c23SMikko Perttunen polling-delay = <0>; 106115274c23SMikko Perttunen polling-delay-passive = <1000>; 106215274c23SMikko Perttunen 106315274c23SMikko Perttunen thermal-sensors = 106415274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 106515274c23SMikko Perttunen 106615274c23SMikko Perttunen trips { 106715274c23SMikko Perttunen critical { 106815274c23SMikko Perttunen temperature = <101000>; 106915274c23SMikko Perttunen hysteresis = <0>; 107015274c23SMikko Perttunen type = "critical"; 107115274c23SMikko Perttunen }; 107215274c23SMikko Perttunen }; 107315274c23SMikko Perttunen 107415274c23SMikko Perttunen cooling-maps { 107515274c23SMikko Perttunen }; 107615274c23SMikko Perttunen }; 107715274c23SMikko Perttunen 107815274c23SMikko Perttunen gpu { 107915274c23SMikko Perttunen polling-delay = <0>; 108015274c23SMikko Perttunen polling-delay-passive = <1000>; 108115274c23SMikko Perttunen 108215274c23SMikko Perttunen thermal-sensors = 108315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 108415274c23SMikko Perttunen 108515274c23SMikko Perttunen trips { 108615274c23SMikko Perttunen critical { 108715274c23SMikko Perttunen temperature = <101000>; 108815274c23SMikko Perttunen hysteresis = <0>; 108915274c23SMikko Perttunen type = "critical"; 109015274c23SMikko Perttunen }; 109115274c23SMikko Perttunen }; 109215274c23SMikko Perttunen 109315274c23SMikko Perttunen cooling-maps { 109415274c23SMikko Perttunen }; 109515274c23SMikko Perttunen }; 109615274c23SMikko Perttunen 109715274c23SMikko Perttunen pll { 109815274c23SMikko Perttunen polling-delay = <0>; 109915274c23SMikko Perttunen polling-delay-passive = <1000>; 110015274c23SMikko Perttunen 110115274c23SMikko Perttunen thermal-sensors = 110215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 110315274c23SMikko Perttunen 110415274c23SMikko Perttunen trips { 110515274c23SMikko Perttunen critical { 110615274c23SMikko Perttunen temperature = <101000>; 110715274c23SMikko Perttunen hysteresis = <0>; 110815274c23SMikko Perttunen type = "critical"; 110915274c23SMikko Perttunen }; 111015274c23SMikko Perttunen }; 111115274c23SMikko Perttunen 111215274c23SMikko Perttunen cooling-maps { 111315274c23SMikko Perttunen }; 111415274c23SMikko Perttunen }; 111515274c23SMikko Perttunen 111615274c23SMikko Perttunen always_on { 111715274c23SMikko Perttunen polling-delay = <0>; 111815274c23SMikko Perttunen polling-delay-passive = <1000>; 111915274c23SMikko Perttunen 112015274c23SMikko Perttunen thermal-sensors = 112115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 112215274c23SMikko Perttunen 112315274c23SMikko Perttunen trips { 112415274c23SMikko Perttunen critical { 112515274c23SMikko Perttunen temperature = <101000>; 112615274c23SMikko Perttunen hysteresis = <0>; 112715274c23SMikko Perttunen type = "critical"; 112815274c23SMikko Perttunen }; 112915274c23SMikko Perttunen }; 113015274c23SMikko Perttunen 113115274c23SMikko Perttunen cooling-maps { 113215274c23SMikko Perttunen }; 113315274c23SMikko Perttunen }; 113439cb62cbSJoseph Lo }; 113539cb62cbSJoseph Lo 113639cb62cbSJoseph Lo timer { 113739cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 113839cb62cbSJoseph Lo interrupts = <GIC_PPI 13 113939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114039cb62cbSJoseph Lo <GIC_PPI 14 114139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114239cb62cbSJoseph Lo <GIC_PPI 11 114339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114439cb62cbSJoseph Lo <GIC_PPI 10 114539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 114639cb62cbSJoseph Lo interrupt-parent = <&gic>; 114739cb62cbSJoseph Lo }; 114839cb62cbSJoseph Lo}; 1149