1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 630caafbdeSThierry Reding status = "disabled"; 640caafbdeSThierry Reding 650caafbdeSThierry Reding snps,write-requests = <1>; 660caafbdeSThierry Reding snps,read-requests = <3>; 670caafbdeSThierry Reding snps,burst-map = <0x7>; 680caafbdeSThierry Reding snps,txpbl = <32>; 690caafbdeSThierry Reding snps,rxpbl = <8>; 700caafbdeSThierry Reding }; 710caafbdeSThierry Reding 72d25a3bf1SThierry Reding memory-controller@2c00000 { 73d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 74d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 75d25a3bf1SThierry Reding status = "disabled"; 76d25a3bf1SThierry Reding }; 77d25a3bf1SThierry Reding 7839cb62cbSJoseph Lo uarta: serial@3100000 { 7939cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8039cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8139cb62cbSJoseph Lo reg-shift = <2>; 8239cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 84a7a77e2eSThierry Reding clock-names = "serial"; 857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 86a7a77e2eSThierry Reding reset-names = "serial"; 87a7a77e2eSThierry Reding status = "disabled"; 88a7a77e2eSThierry Reding }; 89a7a77e2eSThierry Reding 90a7a77e2eSThierry Reding uartb: serial@3110000 { 91a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 93a7a77e2eSThierry Reding reg-shift = <2>; 94a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 96a7a77e2eSThierry Reding clock-names = "serial"; 977bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 98a7a77e2eSThierry Reding reset-names = "serial"; 99a7a77e2eSThierry Reding status = "disabled"; 100a7a77e2eSThierry Reding }; 101a7a77e2eSThierry Reding 102a7a77e2eSThierry Reding uartd: serial@3130000 { 103a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 105a7a77e2eSThierry Reding reg-shift = <2>; 106a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 108a7a77e2eSThierry Reding clock-names = "serial"; 1097bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 110a7a77e2eSThierry Reding reset-names = "serial"; 111a7a77e2eSThierry Reding status = "disabled"; 112a7a77e2eSThierry Reding }; 113a7a77e2eSThierry Reding 114a7a77e2eSThierry Reding uarte: serial@3140000 { 115a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 117a7a77e2eSThierry Reding reg-shift = <2>; 118a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 120a7a77e2eSThierry Reding clock-names = "serial"; 1217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 122a7a77e2eSThierry Reding reset-names = "serial"; 123a7a77e2eSThierry Reding status = "disabled"; 124a7a77e2eSThierry Reding }; 125a7a77e2eSThierry Reding 126a7a77e2eSThierry Reding uartf: serial@3150000 { 127a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 129a7a77e2eSThierry Reding reg-shift = <2>; 130a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 132a7a77e2eSThierry Reding clock-names = "serial"; 1337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 134a7a77e2eSThierry Reding reset-names = "serial"; 13539cb62cbSJoseph Lo status = "disabled"; 13639cb62cbSJoseph Lo }; 13739cb62cbSJoseph Lo 13840cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14040cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14140cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14240cc83b3SThierry Reding #address-cells = <1>; 14340cc83b3SThierry Reding #size-cells = <0>; 144c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14540cc83b3SThierry Reding clock-names = "div-clk"; 1467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14740cc83b3SThierry Reding reset-names = "i2c"; 14840cc83b3SThierry Reding status = "disabled"; 14940cc83b3SThierry Reding }; 15040cc83b3SThierry Reding 15140cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15340cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15440cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15540cc83b3SThierry Reding #address-cells = <1>; 15640cc83b3SThierry Reding #size-cells = <0>; 157c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15840cc83b3SThierry Reding clock-names = "div-clk"; 1597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16040cc83b3SThierry Reding reset-names = "i2c"; 16140cc83b3SThierry Reding status = "disabled"; 16240cc83b3SThierry Reding }; 16340cc83b3SThierry Reding 16440cc83b3SThierry Reding /* shares pads with dpaux1 */ 16540cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16740cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16840cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16940cc83b3SThierry Reding #address-cells = <1>; 17040cc83b3SThierry Reding #size-cells = <0>; 171c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17240cc83b3SThierry Reding clock-names = "div-clk"; 1737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17440cc83b3SThierry Reding reset-names = "i2c"; 17540cc83b3SThierry Reding status = "disabled"; 17640cc83b3SThierry Reding }; 17740cc83b3SThierry Reding 17840cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17940cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 18040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18140cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18240cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18340cc83b3SThierry Reding #address-cells = <1>; 18440cc83b3SThierry Reding #size-cells = <0>; 185c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18640cc83b3SThierry Reding clock-names = "div-clk"; 1877bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18840cc83b3SThierry Reding reset-names = "i2c"; 18940cc83b3SThierry Reding status = "disabled"; 19040cc83b3SThierry Reding }; 19140cc83b3SThierry Reding 19240cc83b3SThierry Reding /* shares pads with dpaux0 */ 19340cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19540cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19640cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19740cc83b3SThierry Reding #address-cells = <1>; 19840cc83b3SThierry Reding #size-cells = <0>; 199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20040cc83b3SThierry Reding clock-names = "div-clk"; 2017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20240cc83b3SThierry Reding reset-names = "i2c"; 20340cc83b3SThierry Reding status = "disabled"; 20440cc83b3SThierry Reding }; 20540cc83b3SThierry Reding 20640cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20840cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20940cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21040cc83b3SThierry Reding #address-cells = <1>; 21140cc83b3SThierry Reding #size-cells = <0>; 212c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21340cc83b3SThierry Reding clock-names = "div-clk"; 2147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21540cc83b3SThierry Reding reset-names = "i2c"; 21640cc83b3SThierry Reding status = "disabled"; 21740cc83b3SThierry Reding }; 21840cc83b3SThierry Reding 21940cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 22040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22140cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22240cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22340cc83b3SThierry Reding #address-cells = <1>; 22440cc83b3SThierry Reding #size-cells = <0>; 225c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22640cc83b3SThierry Reding clock-names = "div-clk"; 2277bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22840cc83b3SThierry Reding reset-names = "i2c"; 22940cc83b3SThierry Reding status = "disabled"; 23040cc83b3SThierry Reding }; 23140cc83b3SThierry Reding 23299425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23499425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23599425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23799425dfdSThierry Reding clock-names = "sdhci"; 2387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23999425dfdSThierry Reding reset-names = "sdhci"; 24024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 24224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 24341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 24441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 24541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 24641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 24741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 24841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 2496f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2506f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 25198a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 25298a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25398a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 25499425dfdSThierry Reding status = "disabled"; 25599425dfdSThierry Reding }; 25699425dfdSThierry Reding 25799425dfdSThierry Reding sdmmc2: sdhci@3420000 { 25899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25999425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 26099425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 26299425dfdSThierry Reding clock-names = "sdhci"; 2637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 26499425dfdSThierry Reding reset-names = "sdhci"; 26524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 26624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 26724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 26841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 26941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 27041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 27141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2726f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2736f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 27499425dfdSThierry Reding status = "disabled"; 27599425dfdSThierry Reding }; 27699425dfdSThierry Reding 27799425dfdSThierry Reding sdmmc3: sdhci@3440000 { 27899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 27999425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 28099425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 28299425dfdSThierry Reding clock-names = "sdhci"; 2837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 28499425dfdSThierry Reding reset-names = "sdhci"; 28524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 28624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 28724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 28841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 28941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 29041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 29141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 29241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 29341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2946f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2956f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 29699425dfdSThierry Reding status = "disabled"; 29799425dfdSThierry Reding }; 29899425dfdSThierry Reding 29999425dfdSThierry Reding sdmmc4: sdhci@3460000 { 30099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 30199425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 30299425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 30499425dfdSThierry Reding clock-names = "sdhci"; 30598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 30698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 30798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 3087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 30999425dfdSThierry Reding reset-names = "sdhci"; 31041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 31141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 31241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 31341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3146f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3156f90c6f0SAapo Vienamo nvidia,default-trim = <0x9>; 31622248e91SAapo Vienamo nvidia,dqs-trim = <63>; 317207f60baSAapo Vienamo mmc-hs400-1_8v; 31899425dfdSThierry Reding status = "disabled"; 31999425dfdSThierry Reding }; 32099425dfdSThierry Reding 32185593b75SThierry Reding fuse@3820000 { 32285593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 32385593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 32485593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 32585593b75SThierry Reding clock-names = "fuse"; 32685593b75SThierry Reding }; 32785593b75SThierry Reding 32839cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 32939cb62cbSJoseph Lo compatible = "arm,gic-400"; 33039cb62cbSJoseph Lo #interrupt-cells = <3>; 33139cb62cbSJoseph Lo interrupt-controller; 33239cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 33339cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 33439cb62cbSJoseph Lo interrupts = <GIC_PPI 9 33539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 33639cb62cbSJoseph Lo interrupt-parent = <&gic>; 33739cb62cbSJoseph Lo }; 33839cb62cbSJoseph Lo 33939cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 34039cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 34139cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 34239cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 34339cb62cbSJoseph Lo interrupt-names = "doorbell"; 34439cb62cbSJoseph Lo #mbox-cells = <2>; 34539cb62cbSJoseph Lo status = "disabled"; 34639cb62cbSJoseph Lo }; 34739cb62cbSJoseph Lo 34840cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 34940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 35040cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 35140cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 35240cc83b3SThierry Reding #address-cells = <1>; 35340cc83b3SThierry Reding #size-cells = <0>; 354c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 35540cc83b3SThierry Reding clock-names = "div-clk"; 3567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 35740cc83b3SThierry Reding reset-names = "i2c"; 35840cc83b3SThierry Reding status = "disabled"; 35940cc83b3SThierry Reding }; 36040cc83b3SThierry Reding 36140cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 36240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 36340cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 36440cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 36540cc83b3SThierry Reding #address-cells = <1>; 36640cc83b3SThierry Reding #size-cells = <0>; 367c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 36840cc83b3SThierry Reding clock-names = "div-clk"; 3697bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 37040cc83b3SThierry Reding reset-names = "i2c"; 37140cc83b3SThierry Reding status = "disabled"; 37240cc83b3SThierry Reding }; 37340cc83b3SThierry Reding 374a7a77e2eSThierry Reding uartc: serial@c280000 { 375a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 376a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 377a7a77e2eSThierry Reding reg-shift = <2>; 378a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 379c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 380a7a77e2eSThierry Reding clock-names = "serial"; 3817bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 382a7a77e2eSThierry Reding reset-names = "serial"; 383a7a77e2eSThierry Reding status = "disabled"; 384a7a77e2eSThierry Reding }; 385a7a77e2eSThierry Reding 386a7a77e2eSThierry Reding uartg: serial@c290000 { 387a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 388a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 389a7a77e2eSThierry Reding reg-shift = <2>; 390a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 391c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 392a7a77e2eSThierry Reding clock-names = "serial"; 3937bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 394a7a77e2eSThierry Reding reset-names = "serial"; 395a7a77e2eSThierry Reding status = "disabled"; 396a7a77e2eSThierry Reding }; 397a7a77e2eSThierry Reding 3989733a251SThierry Reding rtc: rtc@c2a0000 { 3999733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 4009733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 4019733a251SThierry Reding interrupt-parent = <&pmc>; 4029733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 4039733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 4049733a251SThierry Reding clock-names = "rtc"; 4059733a251SThierry Reding status = "disabled"; 4069733a251SThierry Reding }; 4079733a251SThierry Reding 408fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 409fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 410fc4bb754SThierry Reding reg-names = "security", "gpio"; 411fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 412fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 413fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 414fc4bb754SThierry Reding gpio-controller; 415fc4bb754SThierry Reding #gpio-cells = <2>; 416fc4bb754SThierry Reding interrupt-controller; 417fc4bb754SThierry Reding #interrupt-cells = <2>; 418fc4bb754SThierry Reding }; 419fc4bb754SThierry Reding 42032e66e46SThierry Reding pmc: pmc@c360000 { 42173bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 42273bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 42373bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 42473bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 42573bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 42673bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 42724005fd1SAapo Vienamo 42832e66e46SThierry Reding #interrupt-cells = <2>; 42932e66e46SThierry Reding interrupt-controller; 43032e66e46SThierry Reding 43124005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 43224005fd1SAapo Vienamo pins = "sdmmc1-hv"; 43324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 43424005fd1SAapo Vienamo }; 43524005fd1SAapo Vienamo 43624005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 43724005fd1SAapo Vienamo pins = "sdmmc1-hv"; 43824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 43924005fd1SAapo Vienamo }; 44024005fd1SAapo Vienamo 44124005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 44224005fd1SAapo Vienamo pins = "sdmmc2-hv"; 44324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 44424005fd1SAapo Vienamo }; 44524005fd1SAapo Vienamo 44624005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 44724005fd1SAapo Vienamo pins = "sdmmc2-hv"; 44824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 44924005fd1SAapo Vienamo }; 45024005fd1SAapo Vienamo 45124005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 45224005fd1SAapo Vienamo pins = "sdmmc3-hv"; 45324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 45424005fd1SAapo Vienamo }; 45524005fd1SAapo Vienamo 45624005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 45724005fd1SAapo Vienamo pins = "sdmmc3-hv"; 45824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 45924005fd1SAapo Vienamo }; 46073bf90d4SThierry Reding }; 46173bf90d4SThierry Reding 4627b7ef494SMikko Perttunen ccplex@e000000 { 4637b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 4647b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 4657b7ef494SMikko Perttunen 4667b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 4677b7ef494SMikko Perttunen }; 4687b7ef494SMikko Perttunen 469f8973cf4SManikanta Maddireddy pcie@10003000 { 470f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 471f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 472f8973cf4SManikanta Maddireddy device_type = "pci"; 473f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 474f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 475f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 476f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 477f8973cf4SManikanta Maddireddy 478f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 479f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 480f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 481f8973cf4SManikanta Maddireddy 482f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 483f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 484f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 485f8973cf4SManikanta Maddireddy 486f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 487f8973cf4SManikanta Maddireddy #address-cells = <3>; 488f8973cf4SManikanta Maddireddy #size-cells = <2>; 489f8973cf4SManikanta Maddireddy 490f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 491f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 492f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 493f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 494f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 495f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 496f8973cf4SManikanta Maddireddy 497f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 498f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 499f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 500f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 501f8973cf4SManikanta Maddireddy 502f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 503f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 504f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 505f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 506f8973cf4SManikanta Maddireddy 507f8973cf4SManikanta Maddireddy status = "disabled"; 508f8973cf4SManikanta Maddireddy 509f8973cf4SManikanta Maddireddy pci@1,0 { 510f8973cf4SManikanta Maddireddy device_type = "pci"; 511f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 512f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 513f8973cf4SManikanta Maddireddy status = "disabled"; 514f8973cf4SManikanta Maddireddy 515f8973cf4SManikanta Maddireddy #address-cells = <3>; 516f8973cf4SManikanta Maddireddy #size-cells = <2>; 517f8973cf4SManikanta Maddireddy ranges; 518f8973cf4SManikanta Maddireddy 519f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 520f8973cf4SManikanta Maddireddy }; 521f8973cf4SManikanta Maddireddy 522f8973cf4SManikanta Maddireddy pci@2,0 { 523f8973cf4SManikanta Maddireddy device_type = "pci"; 524f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 525f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 526f8973cf4SManikanta Maddireddy status = "disabled"; 527f8973cf4SManikanta Maddireddy 528f8973cf4SManikanta Maddireddy #address-cells = <3>; 529f8973cf4SManikanta Maddireddy #size-cells = <2>; 530f8973cf4SManikanta Maddireddy ranges; 531f8973cf4SManikanta Maddireddy 532f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 533f8973cf4SManikanta Maddireddy }; 534f8973cf4SManikanta Maddireddy 535f8973cf4SManikanta Maddireddy pci@3,0 { 536f8973cf4SManikanta Maddireddy device_type = "pci"; 537f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 538f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 539f8973cf4SManikanta Maddireddy status = "disabled"; 540f8973cf4SManikanta Maddireddy 541f8973cf4SManikanta Maddireddy #address-cells = <3>; 542f8973cf4SManikanta Maddireddy #size-cells = <2>; 543f8973cf4SManikanta Maddireddy ranges; 544f8973cf4SManikanta Maddireddy 545f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 546f8973cf4SManikanta Maddireddy }; 547f8973cf4SManikanta Maddireddy }; 548f8973cf4SManikanta Maddireddy 549b30a8e61SThierry Reding smmu: iommu@12000000 { 550b30a8e61SThierry Reding compatible = "arm,mmu-500"; 551b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 552b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 617b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 618b30a8e61SThierry Reding #global-interrupts = <1>; 619b30a8e61SThierry Reding #iommu-cells = <1>; 620b30a8e61SThierry Reding }; 621b30a8e61SThierry Reding 6225524c61fSMikko Perttunen host1x@13e00000 { 6235524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 6245524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 6255524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 6265524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 6275524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 6285524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 6295524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 6305524c61fSMikko Perttunen clock-names = "host1x"; 6315524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 6325524c61fSMikko Perttunen reset-names = "host1x"; 6335524c61fSMikko Perttunen 6345524c61fSMikko Perttunen #address-cells = <1>; 6355524c61fSMikko Perttunen #size-cells = <1>; 6365524c61fSMikko Perttunen 6375524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 638c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 639c2599da7SThierry Reding 640c2599da7SThierry Reding dpaux1: dpaux@15040000 { 641c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 642c2599da7SThierry Reding reg = <0x15040000 0x10000>; 643c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 644c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 645c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 646c2599da7SThierry Reding clock-names = "dpaux", "parent"; 647c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 648c2599da7SThierry Reding reset-names = "dpaux"; 649c2599da7SThierry Reding status = "disabled"; 650c2599da7SThierry Reding 651c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 652c2599da7SThierry Reding 653c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 654c2599da7SThierry Reding groups = "dpaux-io"; 655c2599da7SThierry Reding function = "aux"; 656c2599da7SThierry Reding }; 657c2599da7SThierry Reding 658c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 659c2599da7SThierry Reding groups = "dpaux-io"; 660c2599da7SThierry Reding function = "i2c"; 661c2599da7SThierry Reding }; 662c2599da7SThierry Reding 663c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 664c2599da7SThierry Reding groups = "dpaux-io"; 665c2599da7SThierry Reding function = "off"; 666c2599da7SThierry Reding }; 667c2599da7SThierry Reding 668c2599da7SThierry Reding i2c-bus { 669c2599da7SThierry Reding #address-cells = <1>; 670c2599da7SThierry Reding #size-cells = <0>; 671c2599da7SThierry Reding }; 672c2599da7SThierry Reding }; 673c2599da7SThierry Reding 674c2599da7SThierry Reding display-hub@15200000 { 675c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 676c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 677c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 678c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 679c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 680c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 681c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 682c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 683c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 684c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 685c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 686c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 687c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 688c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 689c2599da7SThierry Reding status = "disabled"; 690c2599da7SThierry Reding 691c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 692c2599da7SThierry Reding 693c2599da7SThierry Reding #address-cells = <1>; 694c2599da7SThierry Reding #size-cells = <1>; 695c2599da7SThierry Reding 696c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 697c2599da7SThierry Reding 698c2599da7SThierry Reding display@15200000 { 699c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 700c2599da7SThierry Reding reg = <0x15200000 0x10000>; 701c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 702c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 703c2599da7SThierry Reding clock-names = "dc"; 704c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 705c2599da7SThierry Reding reset-names = "dc"; 706c2599da7SThierry Reding 707c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 708c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 709c2599da7SThierry Reding 710c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 711c2599da7SThierry Reding nvidia,head = <0>; 712c2599da7SThierry Reding }; 713c2599da7SThierry Reding 714c2599da7SThierry Reding display@15210000 { 715c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 716c2599da7SThierry Reding reg = <0x15210000 0x10000>; 717c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 718c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 719c2599da7SThierry Reding clock-names = "dc"; 720c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 721c2599da7SThierry Reding reset-names = "dc"; 722c2599da7SThierry Reding 723c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 724c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 725c2599da7SThierry Reding 726c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 727c2599da7SThierry Reding nvidia,head = <1>; 728c2599da7SThierry Reding }; 729c2599da7SThierry Reding 730c2599da7SThierry Reding display@15220000 { 731c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 732c2599da7SThierry Reding reg = <0x15220000 0x10000>; 733c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 734c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 735c2599da7SThierry Reding clock-names = "dc"; 736c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 737c2599da7SThierry Reding reset-names = "dc"; 738c2599da7SThierry Reding 739c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 740c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 741c2599da7SThierry Reding 742c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 743c2599da7SThierry Reding nvidia,head = <2>; 744c2599da7SThierry Reding }; 745c2599da7SThierry Reding }; 746c2599da7SThierry Reding 747c2599da7SThierry Reding dsia: dsi@15300000 { 748c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 749c2599da7SThierry Reding reg = <0x15300000 0x10000>; 750c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 751c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 752c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 753c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 754c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 755c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 756c2599da7SThierry Reding reset-names = "dsi"; 757c2599da7SThierry Reding status = "disabled"; 758c2599da7SThierry Reding 759c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 760c2599da7SThierry Reding }; 761effc4b44SMikko Perttunen 762effc4b44SMikko Perttunen vic@15340000 { 763effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 764effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 765effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 766effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 767effc4b44SMikko Perttunen clock-names = "vic"; 768effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 769effc4b44SMikko Perttunen reset-names = "vic"; 770effc4b44SMikko Perttunen 771effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 772effc4b44SMikko Perttunen }; 773c2599da7SThierry Reding 774c2599da7SThierry Reding dsib: dsi@15400000 { 775c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 776c2599da7SThierry Reding reg = <0x15400000 0x10000>; 777c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 778c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 779c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 780c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 781c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 782c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 783c2599da7SThierry Reding reset-names = "dsi"; 784c2599da7SThierry Reding status = "disabled"; 785c2599da7SThierry Reding 786c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 787c2599da7SThierry Reding }; 788c2599da7SThierry Reding 789c2599da7SThierry Reding sor0: sor@15540000 { 790c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 791c2599da7SThierry Reding reg = <0x15540000 0x10000>; 792c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 793c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 794c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 795c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 796c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 797c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 798c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 799c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 800c2599da7SThierry Reding "pad"; 801c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 802c2599da7SThierry Reding reset-names = "sor"; 803c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 804c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 805c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 806c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 807c2599da7SThierry Reding status = "disabled"; 808c2599da7SThierry Reding 809c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 810c2599da7SThierry Reding nvidia,interface = <0>; 811c2599da7SThierry Reding }; 812c2599da7SThierry Reding 813c2599da7SThierry Reding sor1: sor@15580000 { 814c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 815c2599da7SThierry Reding reg = <0x15580000 0x10000>; 816c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 817c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 818c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 819c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 820c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 821c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 822c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 823c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 824c2599da7SThierry Reding "pad"; 825c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 826c2599da7SThierry Reding reset-names = "sor"; 827c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 828c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 829c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 830c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 831c2599da7SThierry Reding status = "disabled"; 832c2599da7SThierry Reding 833c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 834c2599da7SThierry Reding nvidia,interface = <1>; 835c2599da7SThierry Reding }; 836c2599da7SThierry Reding 837c2599da7SThierry Reding dpaux: dpaux@155c0000 { 838c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 839c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 840c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 841c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 842c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 843c2599da7SThierry Reding clock-names = "dpaux", "parent"; 844c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 845c2599da7SThierry Reding reset-names = "dpaux"; 846c2599da7SThierry Reding status = "disabled"; 847c2599da7SThierry Reding 848c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 849c2599da7SThierry Reding 850c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 851c2599da7SThierry Reding groups = "dpaux-io"; 852c2599da7SThierry Reding function = "aux"; 853c2599da7SThierry Reding }; 854c2599da7SThierry Reding 855c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 856c2599da7SThierry Reding groups = "dpaux-io"; 857c2599da7SThierry Reding function = "i2c"; 858c2599da7SThierry Reding }; 859c2599da7SThierry Reding 860c2599da7SThierry Reding state_dpaux_off: pinmux-off { 861c2599da7SThierry Reding groups = "dpaux-io"; 862c2599da7SThierry Reding function = "off"; 863c2599da7SThierry Reding }; 864c2599da7SThierry Reding 865c2599da7SThierry Reding i2c-bus { 866c2599da7SThierry Reding #address-cells = <1>; 867c2599da7SThierry Reding #size-cells = <0>; 868c2599da7SThierry Reding }; 869c2599da7SThierry Reding }; 870c2599da7SThierry Reding 871c2599da7SThierry Reding padctl@15880000 { 872c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 873c2599da7SThierry Reding reg = <0x15880000 0x10000>; 874c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 875c2599da7SThierry Reding reset-names = "dsi"; 876c2599da7SThierry Reding status = "disabled"; 877c2599da7SThierry Reding }; 878c2599da7SThierry Reding 879c2599da7SThierry Reding dsic: dsi@15900000 { 880c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 881c2599da7SThierry Reding reg = <0x15900000 0x10000>; 882c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 883c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 884c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 885c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 886c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 887c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 888c2599da7SThierry Reding reset-names = "dsi"; 889c2599da7SThierry Reding status = "disabled"; 890c2599da7SThierry Reding 891c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 892c2599da7SThierry Reding }; 893c2599da7SThierry Reding 894c2599da7SThierry Reding dsid: dsi@15940000 { 895c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 896c2599da7SThierry Reding reg = <0x15940000 0x10000>; 897c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 898c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 899c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 900c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 901c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 902c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 903c2599da7SThierry Reding reset-names = "dsi"; 904c2599da7SThierry Reding status = "disabled"; 905c2599da7SThierry Reding 906c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 907c2599da7SThierry Reding }; 9085524c61fSMikko Perttunen }; 9095524c61fSMikko Perttunen 910dfd7a384SAlexandre Courbot gpu@17000000 { 911dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 912dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 913dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 914dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 915dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 916dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 917dfd7a384SAlexandre Courbot 918dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 919dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 920dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 921dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 922dfd7a384SAlexandre Courbot reset-names = "gpu"; 923dfd7a384SAlexandre Courbot status = "disabled"; 924dfd7a384SAlexandre Courbot 925dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 926dfd7a384SAlexandre Courbot }; 927dfd7a384SAlexandre Courbot 92839cb62cbSJoseph Lo sysram@30000000 { 92939cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 93039cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 93139cb62cbSJoseph Lo #address-cells = <2>; 93239cb62cbSJoseph Lo #size-cells = <2>; 93339cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 93439cb62cbSJoseph Lo 93539cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 93639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 93739cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 93839cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 93939cb62cbSJoseph Lo pool; 94039cb62cbSJoseph Lo }; 94139cb62cbSJoseph Lo 94239cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 94339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 94439cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 94539cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 94639cb62cbSJoseph Lo pool; 94739cb62cbSJoseph Lo }; 94839cb62cbSJoseph Lo }; 94939cb62cbSJoseph Lo 950cd6fe32eSThierry Reding cpus { 951cd6fe32eSThierry Reding #address-cells = <1>; 952cd6fe32eSThierry Reding #size-cells = <0>; 953cd6fe32eSThierry Reding 954cd6fe32eSThierry Reding cpu@0 { 955cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 956cd6fe32eSThierry Reding device_type = "cpu"; 957cd6fe32eSThierry Reding reg = <0x000>; 958cd6fe32eSThierry Reding }; 959cd6fe32eSThierry Reding 960cd6fe32eSThierry Reding cpu@1 { 961cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 962cd6fe32eSThierry Reding device_type = "cpu"; 963cd6fe32eSThierry Reding reg = <0x001>; 964cd6fe32eSThierry Reding }; 965cd6fe32eSThierry Reding 966cd6fe32eSThierry Reding cpu@2 { 967cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 968cd6fe32eSThierry Reding device_type = "cpu"; 969cd6fe32eSThierry Reding reg = <0x100>; 970cd6fe32eSThierry Reding }; 971cd6fe32eSThierry Reding 972cd6fe32eSThierry Reding cpu@3 { 973cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 974cd6fe32eSThierry Reding device_type = "cpu"; 975cd6fe32eSThierry Reding reg = <0x101>; 976cd6fe32eSThierry Reding }; 977cd6fe32eSThierry Reding 978cd6fe32eSThierry Reding cpu@4 { 979cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 980cd6fe32eSThierry Reding device_type = "cpu"; 981cd6fe32eSThierry Reding reg = <0x102>; 982cd6fe32eSThierry Reding }; 983cd6fe32eSThierry Reding 984cd6fe32eSThierry Reding cpu@5 { 985cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 986cd6fe32eSThierry Reding device_type = "cpu"; 987cd6fe32eSThierry Reding reg = <0x103>; 988cd6fe32eSThierry Reding }; 989cd6fe32eSThierry Reding }; 990cd6fe32eSThierry Reding 99139cb62cbSJoseph Lo bpmp: bpmp { 99239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 9935edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 9945edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 99539cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 99639cb62cbSJoseph Lo #clock-cells = <1>; 99739cb62cbSJoseph Lo #reset-cells = <1>; 998dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 99939cb62cbSJoseph Lo 100039cb62cbSJoseph Lo bpmp_i2c: i2c { 100139cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 100239cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 100339cb62cbSJoseph Lo #address-cells = <1>; 100439cb62cbSJoseph Lo #size-cells = <0>; 100539cb62cbSJoseph Lo status = "disabled"; 100639cb62cbSJoseph Lo }; 100715274c23SMikko Perttunen 100815274c23SMikko Perttunen bpmp_thermal: thermal { 100915274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 101015274c23SMikko Perttunen #thermal-sensor-cells = <1>; 101115274c23SMikko Perttunen }; 101215274c23SMikko Perttunen }; 101315274c23SMikko Perttunen 101415274c23SMikko Perttunen thermal-zones { 101515274c23SMikko Perttunen a57 { 101615274c23SMikko Perttunen polling-delay = <0>; 101715274c23SMikko Perttunen polling-delay-passive = <1000>; 101815274c23SMikko Perttunen 101915274c23SMikko Perttunen thermal-sensors = 102015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 102115274c23SMikko Perttunen 102215274c23SMikko Perttunen trips { 102315274c23SMikko Perttunen critical { 102415274c23SMikko Perttunen temperature = <101000>; 102515274c23SMikko Perttunen hysteresis = <0>; 102615274c23SMikko Perttunen type = "critical"; 102715274c23SMikko Perttunen }; 102815274c23SMikko Perttunen }; 102915274c23SMikko Perttunen 103015274c23SMikko Perttunen cooling-maps { 103115274c23SMikko Perttunen }; 103215274c23SMikko Perttunen }; 103315274c23SMikko Perttunen 103415274c23SMikko Perttunen denver { 103515274c23SMikko Perttunen polling-delay = <0>; 103615274c23SMikko Perttunen polling-delay-passive = <1000>; 103715274c23SMikko Perttunen 103815274c23SMikko Perttunen thermal-sensors = 103915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 104015274c23SMikko Perttunen 104115274c23SMikko Perttunen trips { 104215274c23SMikko Perttunen critical { 104315274c23SMikko Perttunen temperature = <101000>; 104415274c23SMikko Perttunen hysteresis = <0>; 104515274c23SMikko Perttunen type = "critical"; 104615274c23SMikko Perttunen }; 104715274c23SMikko Perttunen }; 104815274c23SMikko Perttunen 104915274c23SMikko Perttunen cooling-maps { 105015274c23SMikko Perttunen }; 105115274c23SMikko Perttunen }; 105215274c23SMikko Perttunen 105315274c23SMikko Perttunen gpu { 105415274c23SMikko Perttunen polling-delay = <0>; 105515274c23SMikko Perttunen polling-delay-passive = <1000>; 105615274c23SMikko Perttunen 105715274c23SMikko Perttunen thermal-sensors = 105815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 105915274c23SMikko Perttunen 106015274c23SMikko Perttunen trips { 106115274c23SMikko Perttunen critical { 106215274c23SMikko Perttunen temperature = <101000>; 106315274c23SMikko Perttunen hysteresis = <0>; 106415274c23SMikko Perttunen type = "critical"; 106515274c23SMikko Perttunen }; 106615274c23SMikko Perttunen }; 106715274c23SMikko Perttunen 106815274c23SMikko Perttunen cooling-maps { 106915274c23SMikko Perttunen }; 107015274c23SMikko Perttunen }; 107115274c23SMikko Perttunen 107215274c23SMikko Perttunen pll { 107315274c23SMikko Perttunen polling-delay = <0>; 107415274c23SMikko Perttunen polling-delay-passive = <1000>; 107515274c23SMikko Perttunen 107615274c23SMikko Perttunen thermal-sensors = 107715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 107815274c23SMikko Perttunen 107915274c23SMikko Perttunen trips { 108015274c23SMikko Perttunen critical { 108115274c23SMikko Perttunen temperature = <101000>; 108215274c23SMikko Perttunen hysteresis = <0>; 108315274c23SMikko Perttunen type = "critical"; 108415274c23SMikko Perttunen }; 108515274c23SMikko Perttunen }; 108615274c23SMikko Perttunen 108715274c23SMikko Perttunen cooling-maps { 108815274c23SMikko Perttunen }; 108915274c23SMikko Perttunen }; 109015274c23SMikko Perttunen 109115274c23SMikko Perttunen always_on { 109215274c23SMikko Perttunen polling-delay = <0>; 109315274c23SMikko Perttunen polling-delay-passive = <1000>; 109415274c23SMikko Perttunen 109515274c23SMikko Perttunen thermal-sensors = 109615274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 109715274c23SMikko Perttunen 109815274c23SMikko Perttunen trips { 109915274c23SMikko Perttunen critical { 110015274c23SMikko Perttunen temperature = <101000>; 110115274c23SMikko Perttunen hysteresis = <0>; 110215274c23SMikko Perttunen type = "critical"; 110315274c23SMikko Perttunen }; 110415274c23SMikko Perttunen }; 110515274c23SMikko Perttunen 110615274c23SMikko Perttunen cooling-maps { 110715274c23SMikko Perttunen }; 110815274c23SMikko Perttunen }; 110939cb62cbSJoseph Lo }; 111039cb62cbSJoseph Lo 111139cb62cbSJoseph Lo timer { 111239cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 111339cb62cbSJoseph Lo interrupts = <GIC_PPI 13 111439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 111539cb62cbSJoseph Lo <GIC_PPI 14 111639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 111739cb62cbSJoseph Lo <GIC_PPI 11 111839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 111939cb62cbSJoseph Lo <GIC_PPI 10 112039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 112139cb62cbSJoseph Lo interrupt-parent = <&gic>; 112239cb62cbSJoseph Lo }; 112339cb62cbSJoseph Lo}; 1124