1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112835553b3SAkhil R #dma-cells = <1>; 113835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114835553b3SAkhil R dma-coherent; 115835553b3SAkhil R status = "okay"; 116835553b3SAkhil R }; 117835553b3SAkhil R 1184b154b94SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1815d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1825d2249ddSSameer Pujar clock-names = "clk"; 1835d2249ddSSameer Pujar status = "disabled"; 1845d2249ddSSameer Pujar }; 185177208f7SSameer Pujar 186177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 187177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 188177208f7SSameer Pujar reg = <0x02900800 0x800>; 189177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 190177208f7SSameer Pujar clock-names = "ahub"; 191177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193177208f7SSameer Pujar #address-cells = <1>; 194177208f7SSameer Pujar #size-cells = <1>; 195177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 196177208f7SSameer Pujar status = "disabled"; 197177208f7SSameer Pujar 198177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 199177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 200177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 201177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 202177208f7SSameer Pujar <&adma 2>, <&adma 2>, 203177208f7SSameer Pujar <&adma 3>, <&adma 3>, 204177208f7SSameer Pujar <&adma 4>, <&adma 4>, 205177208f7SSameer Pujar <&adma 5>, <&adma 5>, 206177208f7SSameer Pujar <&adma 6>, <&adma 6>, 207177208f7SSameer Pujar <&adma 7>, <&adma 7>, 208177208f7SSameer Pujar <&adma 8>, <&adma 8>, 209177208f7SSameer Pujar <&adma 9>, <&adma 9>, 210177208f7SSameer Pujar <&adma 10>, <&adma 10>, 211177208f7SSameer Pujar <&adma 11>, <&adma 11>, 212177208f7SSameer Pujar <&adma 12>, <&adma 12>, 213177208f7SSameer Pujar <&adma 13>, <&adma 13>, 214177208f7SSameer Pujar <&adma 14>, <&adma 14>, 215177208f7SSameer Pujar <&adma 15>, <&adma 15>, 216177208f7SSameer Pujar <&adma 16>, <&adma 16>, 217177208f7SSameer Pujar <&adma 17>, <&adma 17>, 218177208f7SSameer Pujar <&adma 18>, <&adma 18>, 219177208f7SSameer Pujar <&adma 19>, <&adma 19>, 220177208f7SSameer Pujar <&adma 20>, <&adma 20>; 221177208f7SSameer Pujar dma-names = "rx1", "tx1", 222177208f7SSameer Pujar "rx2", "tx2", 223177208f7SSameer Pujar "rx3", "tx3", 224177208f7SSameer Pujar "rx4", "tx4", 225177208f7SSameer Pujar "rx5", "tx5", 226177208f7SSameer Pujar "rx6", "tx6", 227177208f7SSameer Pujar "rx7", "tx7", 228177208f7SSameer Pujar "rx8", "tx8", 229177208f7SSameer Pujar "rx9", "tx9", 230177208f7SSameer Pujar "rx10", "tx10", 231177208f7SSameer Pujar "rx11", "tx11", 232177208f7SSameer Pujar "rx12", "tx12", 233177208f7SSameer Pujar "rx13", "tx13", 234177208f7SSameer Pujar "rx14", "tx14", 235177208f7SSameer Pujar "rx15", "tx15", 236177208f7SSameer Pujar "rx16", "tx16", 237177208f7SSameer Pujar "rx17", "tx17", 238177208f7SSameer Pujar "rx18", "tx18", 239177208f7SSameer Pujar "rx19", "tx19", 240177208f7SSameer Pujar "rx20", "tx20"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901000 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S1"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901100 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S2"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901200 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S3"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 287177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 288177208f7SSameer Pujar "nvidia,tegra210-i2s"; 289177208f7SSameer Pujar reg = <0x2901300 0x100>; 290177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 291177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 293177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295177208f7SSameer Pujar assigned-clock-rates = <1536000>; 296177208f7SSameer Pujar sound-name-prefix = "I2S4"; 297177208f7SSameer Pujar status = "disabled"; 298177208f7SSameer Pujar }; 299177208f7SSameer Pujar 300177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 301177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 302177208f7SSameer Pujar "nvidia,tegra210-i2s"; 303177208f7SSameer Pujar reg = <0x2901400 0x100>; 304177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 305177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <1536000>; 310177208f7SSameer Pujar sound-name-prefix = "I2S5"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 315177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 316177208f7SSameer Pujar "nvidia,tegra210-i2s"; 317177208f7SSameer Pujar reg = <0x2901500 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 319177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 321177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323177208f7SSameer Pujar assigned-clock-rates = <1536000>; 324177208f7SSameer Pujar sound-name-prefix = "I2S6"; 325177208f7SSameer Pujar status = "disabled"; 326177208f7SSameer Pujar }; 327177208f7SSameer Pujar 328177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 329177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904000 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 341177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 342177208f7SSameer Pujar reg = <0x2904100 0x100>; 343177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344177208f7SSameer Pujar clock-names = "dmic"; 345177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347177208f7SSameer Pujar assigned-clock-rates = <3072000>; 348177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 349177208f7SSameer Pujar status = "disabled"; 350177208f7SSameer Pujar }; 351177208f7SSameer Pujar 352177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 353177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 354177208f7SSameer Pujar reg = <0x2904200 0x100>; 355177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356177208f7SSameer Pujar clock-names = "dmic"; 357177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359177208f7SSameer Pujar assigned-clock-rates = <3072000>; 360177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 361177208f7SSameer Pujar status = "disabled"; 362177208f7SSameer Pujar }; 363177208f7SSameer Pujar 364177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 365177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 366177208f7SSameer Pujar reg = <0x2904300 0x100>; 367177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368177208f7SSameer Pujar clock-names = "dmic"; 369177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371177208f7SSameer Pujar assigned-clock-rates = <3072000>; 372177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 373177208f7SSameer Pujar status = "disabled"; 374177208f7SSameer Pujar }; 375177208f7SSameer Pujar 376177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 377177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 378177208f7SSameer Pujar reg = <0x2905000 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380177208f7SSameer Pujar clock-names = "dspk"; 381177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383177208f7SSameer Pujar assigned-clock-rates = <12288000>; 384177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 385177208f7SSameer Pujar status = "disabled"; 386177208f7SSameer Pujar }; 387177208f7SSameer Pujar 388177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 389177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 390177208f7SSameer Pujar reg = <0x2905100 0x100>; 391177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392177208f7SSameer Pujar clock-names = "dspk"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <12288000>; 396177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399848f3290SSameer Pujar 400848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 401848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 402848f3290SSameer Pujar "nvidia,tegra210-sfc"; 403848f3290SSameer Pujar reg = <0x2902000 0x200>; 404848f3290SSameer Pujar sound-name-prefix = "SFC1"; 405848f3290SSameer Pujar status = "disabled"; 406848f3290SSameer Pujar }; 407848f3290SSameer Pujar 408848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 409848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 410848f3290SSameer Pujar "nvidia,tegra210-sfc"; 411848f3290SSameer Pujar reg = <0x2902200 0x200>; 412848f3290SSameer Pujar sound-name-prefix = "SFC2"; 413848f3290SSameer Pujar status = "disabled"; 414848f3290SSameer Pujar }; 415848f3290SSameer Pujar 416848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 417848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 418848f3290SSameer Pujar "nvidia,tegra210-sfc"; 419848f3290SSameer Pujar reg = <0x2902400 0x200>; 420848f3290SSameer Pujar sound-name-prefix = "SFC3"; 421848f3290SSameer Pujar status = "disabled"; 422848f3290SSameer Pujar }; 423848f3290SSameer Pujar 424848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 425848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 426848f3290SSameer Pujar "nvidia,tegra210-sfc"; 427848f3290SSameer Pujar reg = <0x2902600 0x200>; 428848f3290SSameer Pujar sound-name-prefix = "SFC4"; 429848f3290SSameer Pujar status = "disabled"; 430848f3290SSameer Pujar }; 431848f3290SSameer Pujar 432848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 433848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 434848f3290SSameer Pujar "nvidia,tegra210-mvc"; 435848f3290SSameer Pujar reg = <0x290a000 0x200>; 436848f3290SSameer Pujar sound-name-prefix = "MVC1"; 437848f3290SSameer Pujar status = "disabled"; 438848f3290SSameer Pujar }; 439848f3290SSameer Pujar 440848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 441848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 442848f3290SSameer Pujar "nvidia,tegra210-mvc"; 443848f3290SSameer Pujar reg = <0x290a200 0x200>; 444848f3290SSameer Pujar sound-name-prefix = "MVC2"; 445848f3290SSameer Pujar status = "disabled"; 446848f3290SSameer Pujar }; 447848f3290SSameer Pujar 448848f3290SSameer Pujar tegra_amx1: amx@2903000 { 449848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 450848f3290SSameer Pujar "nvidia,tegra210-amx"; 451848f3290SSameer Pujar reg = <0x2903000 0x100>; 452848f3290SSameer Pujar sound-name-prefix = "AMX1"; 453848f3290SSameer Pujar status = "disabled"; 454848f3290SSameer Pujar }; 455848f3290SSameer Pujar 456848f3290SSameer Pujar tegra_amx2: amx@2903100 { 457848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 458848f3290SSameer Pujar "nvidia,tegra210-amx"; 459848f3290SSameer Pujar reg = <0x2903100 0x100>; 460848f3290SSameer Pujar sound-name-prefix = "AMX2"; 461848f3290SSameer Pujar status = "disabled"; 462848f3290SSameer Pujar }; 463848f3290SSameer Pujar 464848f3290SSameer Pujar tegra_amx3: amx@2903200 { 465848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 466848f3290SSameer Pujar "nvidia,tegra210-amx"; 467848f3290SSameer Pujar reg = <0x2903200 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX3"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx4: amx@2903300 { 473848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 474848f3290SSameer Pujar "nvidia,tegra210-amx"; 475848f3290SSameer Pujar reg = <0x2903300 0x100>; 476848f3290SSameer Pujar sound-name-prefix = "AMX4"; 477848f3290SSameer Pujar status = "disabled"; 478848f3290SSameer Pujar }; 479848f3290SSameer Pujar 480848f3290SSameer Pujar tegra_adx1: adx@2903800 { 481848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 482848f3290SSameer Pujar "nvidia,tegra210-adx"; 483848f3290SSameer Pujar reg = <0x2903800 0x100>; 484848f3290SSameer Pujar sound-name-prefix = "ADX1"; 485848f3290SSameer Pujar status = "disabled"; 486848f3290SSameer Pujar }; 487848f3290SSameer Pujar 488848f3290SSameer Pujar tegra_adx2: adx@2903900 { 489848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 490848f3290SSameer Pujar "nvidia,tegra210-adx"; 491848f3290SSameer Pujar reg = <0x2903900 0x100>; 492848f3290SSameer Pujar sound-name-prefix = "ADX2"; 493848f3290SSameer Pujar status = "disabled"; 494848f3290SSameer Pujar }; 495848f3290SSameer Pujar 496848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 497848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 498848f3290SSameer Pujar "nvidia,tegra210-adx"; 499848f3290SSameer Pujar reg = <0x2903a00 0x100>; 500848f3290SSameer Pujar sound-name-prefix = "ADX3"; 501848f3290SSameer Pujar status = "disabled"; 502848f3290SSameer Pujar }; 503848f3290SSameer Pujar 504848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 505848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 506848f3290SSameer Pujar "nvidia,tegra210-adx"; 507848f3290SSameer Pujar reg = <0x2903b00 0x100>; 508848f3290SSameer Pujar sound-name-prefix = "ADX4"; 509848f3290SSameer Pujar status = "disabled"; 510848f3290SSameer Pujar }; 511848f3290SSameer Pujar 5124b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 5134b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-ope", 5144b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 5154b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 5164b6a1b7cSSameer Pujar #address-cells = <1>; 5174b6a1b7cSSameer Pujar #size-cells = <1>; 5184b6a1b7cSSameer Pujar ranges; 5194b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 5204b6a1b7cSSameer Pujar status = "disabled"; 5214b6a1b7cSSameer Pujar 5224b6a1b7cSSameer Pujar equalizer@2908100 { 5234b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-peq", 5244b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 5254b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 5264b6a1b7cSSameer Pujar }; 5274b6a1b7cSSameer Pujar 5284b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 5294b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-mbdrc", 5304b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 5314b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 5324b6a1b7cSSameer Pujar }; 5334b6a1b7cSSameer Pujar }; 5344b6a1b7cSSameer Pujar 535848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 536848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 537848f3290SSameer Pujar "nvidia,tegra210-amixer"; 538848f3290SSameer Pujar reg = <0x290bb00 0x800>; 539848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 540848f3290SSameer Pujar status = "disabled"; 541848f3290SSameer Pujar }; 54247a08153SSameer Pujar 54347a08153SSameer Pujar tegra_asrc: asrc@2910000 { 54447a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 54547a08153SSameer Pujar reg = <0x2910000 0x2000>; 54647a08153SSameer Pujar sound-name-prefix = "ASRC1"; 54747a08153SSameer Pujar status = "disabled"; 54847a08153SSameer Pujar }; 549177208f7SSameer Pujar }; 5505d2249ddSSameer Pujar }; 5515d2249ddSSameer Pujar 552954490b3SThierry Reding mc: memory-controller@2c00000 { 553d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 554000b99e5SAshish Mhetre reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 555000b99e5SAshish Mhetre <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 556000b99e5SAshish Mhetre <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 557000b99e5SAshish Mhetre <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 558000b99e5SAshish Mhetre <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 559000b99e5SAshish Mhetre <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 560000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 561b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 562d25a3bf1SThierry Reding status = "disabled"; 5633f6eaef9SThierry Reding 564954490b3SThierry Reding #interconnect-cells = <1>; 5653f6eaef9SThierry Reding #address-cells = <2>; 5663f6eaef9SThierry Reding #size-cells = <2>; 5673f6eaef9SThierry Reding 5683f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5693f6eaef9SThierry Reding 5703f6eaef9SThierry Reding /* 5713f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5723f6eaef9SThierry Reding * controller can address. 5733f6eaef9SThierry Reding */ 5743f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5753f6eaef9SThierry Reding 5763f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5773f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5783f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5793f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5803f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5813f6eaef9SThierry Reding clock-names = "emc"; 5823f6eaef9SThierry Reding 583954490b3SThierry Reding #interconnect-cells = <0>; 584954490b3SThierry Reding 5853f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5863f6eaef9SThierry Reding }; 587d25a3bf1SThierry Reding }; 588d25a3bf1SThierry Reding 589bd1fefcbSThierry Reding timer@3010000 { 590bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 591bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 592bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 593bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 594bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 595bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 596bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 597bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 598bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 599bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 600bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 601bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 602c710ac0bSKartik status = "okay"; 603bd1fefcbSThierry Reding }; 604bd1fefcbSThierry Reding 60539cb62cbSJoseph Lo uarta: serial@3100000 { 60639cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 60739cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 60839cb62cbSJoseph Lo reg-shift = <2>; 60939cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 610c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 611a7a77e2eSThierry Reding clock-names = "serial"; 6127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 613a7a77e2eSThierry Reding reset-names = "serial"; 614a7a77e2eSThierry Reding status = "disabled"; 615a7a77e2eSThierry Reding }; 616a7a77e2eSThierry Reding 617a7a77e2eSThierry Reding uartb: serial@3110000 { 618a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 619a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 620a7a77e2eSThierry Reding reg-shift = <2>; 621a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 622c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 623a7a77e2eSThierry Reding clock-names = "serial"; 6247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 625a7a77e2eSThierry Reding reset-names = "serial"; 626a7a77e2eSThierry Reding status = "disabled"; 627a7a77e2eSThierry Reding }; 628a7a77e2eSThierry Reding 629a7a77e2eSThierry Reding uartd: serial@3130000 { 630a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 631a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 632a7a77e2eSThierry Reding reg-shift = <2>; 633a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 634c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 635a7a77e2eSThierry Reding clock-names = "serial"; 6367bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 637a7a77e2eSThierry Reding reset-names = "serial"; 638a7a77e2eSThierry Reding status = "disabled"; 639a7a77e2eSThierry Reding }; 640a7a77e2eSThierry Reding 641a7a77e2eSThierry Reding uarte: serial@3140000 { 642a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 644a7a77e2eSThierry Reding reg-shift = <2>; 645a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 646c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 647a7a77e2eSThierry Reding clock-names = "serial"; 6487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 649a7a77e2eSThierry Reding reset-names = "serial"; 650a7a77e2eSThierry Reding status = "disabled"; 651a7a77e2eSThierry Reding }; 652a7a77e2eSThierry Reding 653a7a77e2eSThierry Reding uartf: serial@3150000 { 654a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 656a7a77e2eSThierry Reding reg-shift = <2>; 657a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 658c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 659a7a77e2eSThierry Reding clock-names = "serial"; 6607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 661a7a77e2eSThierry Reding reset-names = "serial"; 66239cb62cbSJoseph Lo status = "disabled"; 66339cb62cbSJoseph Lo }; 66439cb62cbSJoseph Lo 66540cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 666548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 66740cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 66840cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 66940cc83b3SThierry Reding #address-cells = <1>; 67040cc83b3SThierry Reding #size-cells = <0>; 671c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 67240cc83b3SThierry Reding clock-names = "div-clk"; 6737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 67440cc83b3SThierry Reding reset-names = "i2c"; 675*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 676*8e442805SAkhil R dma-coherent; 677*8e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 678*8e442805SAkhil R dma-names = "rx", "tx"; 67940cc83b3SThierry Reding status = "disabled"; 68040cc83b3SThierry Reding }; 68140cc83b3SThierry Reding 68240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 683548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 68540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 68640cc83b3SThierry Reding #address-cells = <1>; 68740cc83b3SThierry Reding #size-cells = <0>; 688c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 68940cc83b3SThierry Reding clock-names = "div-clk"; 6907bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 69140cc83b3SThierry Reding reset-names = "i2c"; 692*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 693*8e442805SAkhil R dma-coherent; 694*8e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 695*8e442805SAkhil R dma-names = "rx", "tx"; 69640cc83b3SThierry Reding status = "disabled"; 69740cc83b3SThierry Reding }; 69840cc83b3SThierry Reding 69940cc83b3SThierry Reding /* shares pads with dpaux1 */ 70040cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 701548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 70240cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 70340cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 70440cc83b3SThierry Reding #address-cells = <1>; 70540cc83b3SThierry Reding #size-cells = <0>; 706c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 70740cc83b3SThierry Reding clock-names = "div-clk"; 7087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 70940cc83b3SThierry Reding reset-names = "i2c"; 710846137c6SThierry Reding pinctrl-names = "default", "idle"; 711846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 712846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 713*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 714*8e442805SAkhil R dma-coherent; 715*8e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 716*8e442805SAkhil R dma-names = "rx", "tx"; 71740cc83b3SThierry Reding status = "disabled"; 71840cc83b3SThierry Reding }; 71940cc83b3SThierry Reding 72040cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 72140cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 722548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 72340cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 72440cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 72540cc83b3SThierry Reding #address-cells = <1>; 72640cc83b3SThierry Reding #size-cells = <0>; 727c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 72840cc83b3SThierry Reding clock-names = "div-clk"; 7297bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 73040cc83b3SThierry Reding reset-names = "i2c"; 73140cc83b3SThierry Reding status = "disabled"; 73240cc83b3SThierry Reding }; 73340cc83b3SThierry Reding 73440cc83b3SThierry Reding /* shares pads with dpaux0 */ 73540cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 736548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 73740cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 73840cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 73940cc83b3SThierry Reding #address-cells = <1>; 74040cc83b3SThierry Reding #size-cells = <0>; 741c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 74240cc83b3SThierry Reding clock-names = "div-clk"; 7437bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 74440cc83b3SThierry Reding reset-names = "i2c"; 745846137c6SThierry Reding pinctrl-names = "default", "idle"; 746846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 747846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 748*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 749*8e442805SAkhil R dma-coherent; 750*8e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 751*8e442805SAkhil R dma-names = "rx", "tx"; 75240cc83b3SThierry Reding status = "disabled"; 75340cc83b3SThierry Reding }; 75440cc83b3SThierry Reding 75540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 756548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 75740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 75840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 75940cc83b3SThierry Reding #address-cells = <1>; 76040cc83b3SThierry Reding #size-cells = <0>; 761c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 76240cc83b3SThierry Reding clock-names = "div-clk"; 7637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 76440cc83b3SThierry Reding reset-names = "i2c"; 765*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 766*8e442805SAkhil R dma-coherent; 767*8e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 768*8e442805SAkhil R dma-names = "rx", "tx"; 76940cc83b3SThierry Reding status = "disabled"; 77040cc83b3SThierry Reding }; 77140cc83b3SThierry Reding 77240cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 773548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 77440cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 77540cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 77640cc83b3SThierry Reding #address-cells = <1>; 77740cc83b3SThierry Reding #size-cells = <0>; 778c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 77940cc83b3SThierry Reding clock-names = "div-clk"; 7807bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 78140cc83b3SThierry Reding reset-names = "i2c"; 782*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 783*8e442805SAkhil R dma-coherent; 784*8e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 785*8e442805SAkhil R dma-names = "rx", "tx"; 78640cc83b3SThierry Reding status = "disabled"; 78740cc83b3SThierry Reding }; 78840cc83b3SThierry Reding 789913f8ad4SThierry Reding pwm1: pwm@3280000 { 790913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 791913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 792913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 793913f8ad4SThierry Reding clock-names = "pwm"; 794913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 795913f8ad4SThierry Reding reset-names = "pwm"; 796913f8ad4SThierry Reding status = "disabled"; 797913f8ad4SThierry Reding #pwm-cells = <2>; 798913f8ad4SThierry Reding }; 799913f8ad4SThierry Reding 800913f8ad4SThierry Reding pwm2: pwm@3290000 { 801913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 802913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 803913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 804913f8ad4SThierry Reding clock-names = "pwm"; 805913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 806913f8ad4SThierry Reding reset-names = "pwm"; 807913f8ad4SThierry Reding status = "disabled"; 808913f8ad4SThierry Reding #pwm-cells = <2>; 809913f8ad4SThierry Reding }; 810913f8ad4SThierry Reding 811913f8ad4SThierry Reding pwm3: pwm@32a0000 { 812913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 813913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 814913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 815913f8ad4SThierry Reding clock-names = "pwm"; 816913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 817913f8ad4SThierry Reding reset-names = "pwm"; 818913f8ad4SThierry Reding status = "disabled"; 819913f8ad4SThierry Reding #pwm-cells = <2>; 820913f8ad4SThierry Reding }; 821913f8ad4SThierry Reding 822913f8ad4SThierry Reding pwm5: pwm@32c0000 { 823913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 824913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 825913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 826913f8ad4SThierry Reding clock-names = "pwm"; 827913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 828913f8ad4SThierry Reding reset-names = "pwm"; 829913f8ad4SThierry Reding status = "disabled"; 830913f8ad4SThierry Reding #pwm-cells = <2>; 831913f8ad4SThierry Reding }; 832913f8ad4SThierry Reding 833913f8ad4SThierry Reding pwm6: pwm@32d0000 { 834913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 835913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 836913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 837913f8ad4SThierry Reding clock-names = "pwm"; 838913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 839913f8ad4SThierry Reding reset-names = "pwm"; 840913f8ad4SThierry Reding status = "disabled"; 841913f8ad4SThierry Reding #pwm-cells = <2>; 842913f8ad4SThierry Reding }; 843913f8ad4SThierry Reding 844913f8ad4SThierry Reding pwm7: pwm@32e0000 { 845913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 846913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 847913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 848913f8ad4SThierry Reding clock-names = "pwm"; 849913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 850913f8ad4SThierry Reding reset-names = "pwm"; 851913f8ad4SThierry Reding status = "disabled"; 852913f8ad4SThierry Reding #pwm-cells = <2>; 853913f8ad4SThierry Reding }; 854913f8ad4SThierry Reding 855913f8ad4SThierry Reding pwm8: pwm@32f0000 { 856913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 857913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 858913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 859913f8ad4SThierry Reding clock-names = "pwm"; 860913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 861913f8ad4SThierry Reding reset-names = "pwm"; 862913f8ad4SThierry Reding status = "disabled"; 863913f8ad4SThierry Reding #pwm-cells = <2>; 864913f8ad4SThierry Reding }; 865913f8ad4SThierry Reding 86667bb17f6SThierry Reding sdmmc1: mmc@3400000 { 86799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 86899425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 86999425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 870baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 871baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 872baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 87499425dfdSThierry Reding reset-names = "sdhci"; 875954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 876954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 877954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8788589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 87924005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 88024005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 88124005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 88241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 88341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 88441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 88541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 88641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 88741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8886f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8896f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 89098a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 89198a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 89298a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 89399425dfdSThierry Reding status = "disabled"; 89499425dfdSThierry Reding }; 89599425dfdSThierry Reding 89667bb17f6SThierry Reding sdmmc2: mmc@3420000 { 89799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 89899425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 89999425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 900baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 901baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 902baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9037bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 90499425dfdSThierry Reding reset-names = "sdhci"; 905954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 906954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 907954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9088589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 90924005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 91024005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 91124005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 91241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 91341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 91441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 91541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9166f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9176f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 91899425dfdSThierry Reding status = "disabled"; 91999425dfdSThierry Reding }; 92099425dfdSThierry Reding 92167bb17f6SThierry Reding sdmmc3: mmc@3440000 { 92299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 92399425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 92499425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 925baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 926baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 927baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9287bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 92999425dfdSThierry Reding reset-names = "sdhci"; 930954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 931954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 932954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9338589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 93424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 93524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 93624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 93741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 93841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 93941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 94041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 94141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 94241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9436f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9446f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 94599425dfdSThierry Reding status = "disabled"; 94699425dfdSThierry Reding }; 94799425dfdSThierry Reding 94867bb17f6SThierry Reding sdmmc4: mmc@3460000 { 94999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 95099425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 95199425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 952baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 953baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 954baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 95598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 95698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 95798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 95999425dfdSThierry Reding reset-names = "sdhci"; 960954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 961954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 962954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9638589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 96441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 96541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 96641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 96741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9684e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9694e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 970e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 971e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 97222248e91SAapo Vienamo nvidia,dqs-trim = <63>; 973207f60baSAapo Vienamo mmc-hs400-1_8v; 974c4307836SSowjanya Komatineni supports-cqe; 97599425dfdSThierry Reding status = "disabled"; 97699425dfdSThierry Reding }; 97799425dfdSThierry Reding 978b066a310SThierry Reding hda@3510000 { 979b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 980b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 981b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 982b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 983b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 984b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 985b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 986b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 987b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 988b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 989b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 990b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 991954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 992954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 993954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 994dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 995b066a310SThierry Reding status = "disabled"; 996b066a310SThierry Reding }; 997b066a310SThierry Reding 9988bfde518SThierry Reding padctl: padctl@3520000 { 9998bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 10008bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 10018bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 10028bfde518SThierry Reding reg-names = "padctl", "ao"; 10036450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 10048bfde518SThierry Reding 10058bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 10068bfde518SThierry Reding reset-names = "padctl"; 10078bfde518SThierry Reding 10088bfde518SThierry Reding status = "disabled"; 10098bfde518SThierry Reding 10108bfde518SThierry Reding pads { 10118bfde518SThierry Reding usb2 { 10128bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 10138bfde518SThierry Reding clock-names = "trk"; 10148bfde518SThierry Reding status = "disabled"; 10158bfde518SThierry Reding 10168bfde518SThierry Reding lanes { 10178bfde518SThierry Reding usb2-0 { 10188bfde518SThierry Reding status = "disabled"; 10198bfde518SThierry Reding #phy-cells = <0>; 10208bfde518SThierry Reding }; 10218bfde518SThierry Reding 10228bfde518SThierry Reding usb2-1 { 10238bfde518SThierry Reding status = "disabled"; 10248bfde518SThierry Reding #phy-cells = <0>; 10258bfde518SThierry Reding }; 10268bfde518SThierry Reding 10278bfde518SThierry Reding usb2-2 { 10288bfde518SThierry Reding status = "disabled"; 10298bfde518SThierry Reding #phy-cells = <0>; 10308bfde518SThierry Reding }; 10318bfde518SThierry Reding }; 10328bfde518SThierry Reding }; 10338bfde518SThierry Reding 10348bfde518SThierry Reding hsic { 10358bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 10368bfde518SThierry Reding clock-names = "trk"; 10378bfde518SThierry Reding status = "disabled"; 10388bfde518SThierry Reding 10398bfde518SThierry Reding lanes { 10408bfde518SThierry Reding hsic-0 { 10418bfde518SThierry Reding status = "disabled"; 10428bfde518SThierry Reding #phy-cells = <0>; 10438bfde518SThierry Reding }; 10448bfde518SThierry Reding }; 10458bfde518SThierry Reding }; 10468bfde518SThierry Reding 10478bfde518SThierry Reding usb3 { 10488bfde518SThierry Reding status = "disabled"; 10498bfde518SThierry Reding 10508bfde518SThierry Reding lanes { 10518bfde518SThierry Reding usb3-0 { 10528bfde518SThierry Reding status = "disabled"; 10538bfde518SThierry Reding #phy-cells = <0>; 10548bfde518SThierry Reding }; 10558bfde518SThierry Reding 10568bfde518SThierry Reding usb3-1 { 10578bfde518SThierry Reding status = "disabled"; 10588bfde518SThierry Reding #phy-cells = <0>; 10598bfde518SThierry Reding }; 10608bfde518SThierry Reding 10618bfde518SThierry Reding usb3-2 { 10628bfde518SThierry Reding status = "disabled"; 10638bfde518SThierry Reding #phy-cells = <0>; 10648bfde518SThierry Reding }; 10658bfde518SThierry Reding }; 10668bfde518SThierry Reding }; 10678bfde518SThierry Reding }; 10688bfde518SThierry Reding 10698bfde518SThierry Reding ports { 10708bfde518SThierry Reding usb2-0 { 10718bfde518SThierry Reding status = "disabled"; 10728bfde518SThierry Reding }; 10738bfde518SThierry Reding 10748bfde518SThierry Reding usb2-1 { 10758bfde518SThierry Reding status = "disabled"; 10768bfde518SThierry Reding }; 10778bfde518SThierry Reding 10788bfde518SThierry Reding usb2-2 { 10798bfde518SThierry Reding status = "disabled"; 10808bfde518SThierry Reding }; 10818bfde518SThierry Reding 10828bfde518SThierry Reding hsic-0 { 10838bfde518SThierry Reding status = "disabled"; 10848bfde518SThierry Reding }; 10858bfde518SThierry Reding 10868bfde518SThierry Reding usb3-0 { 10878bfde518SThierry Reding status = "disabled"; 10888bfde518SThierry Reding }; 10898bfde518SThierry Reding 10908bfde518SThierry Reding usb3-1 { 10918bfde518SThierry Reding status = "disabled"; 10928bfde518SThierry Reding }; 10938bfde518SThierry Reding 10948bfde518SThierry Reding usb3-2 { 10958bfde518SThierry Reding status = "disabled"; 10968bfde518SThierry Reding }; 10978bfde518SThierry Reding }; 10988bfde518SThierry Reding }; 10998bfde518SThierry Reding 11008bfde518SThierry Reding usb@3530000 { 11018bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 11028bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 11038bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 11048bfde518SThierry Reding reg-names = "hcd", "fpci"; 11058bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1106a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11078bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 11088bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 11098bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 11108bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 11118bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11128bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 11138bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 11148bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11158bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 11168bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 11178bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 11188bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 11198bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 11208bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 11218bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1122954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1123954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1124954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 112506c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 11268bfde518SThierry Reding #address-cells = <1>; 11278bfde518SThierry Reding #size-cells = <0>; 112806c6b06fSThierry Reding status = "disabled"; 112906c6b06fSThierry Reding 113006c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 11318bfde518SThierry Reding }; 11328bfde518SThierry Reding 1133584f800cSNagarjuna Kristam usb@3550000 { 1134584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1135584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1136584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1137584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1138584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1139584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1140584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1141584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1142584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1143584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1144d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1145d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1146d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1147584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1148584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1149584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1150584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1151584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1152584f800cSNagarjuna Kristam status = "disabled"; 1153584f800cSNagarjuna Kristam }; 1154584f800cSNagarjuna Kristam 115585593b75SThierry Reding fuse@3820000 { 115685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 115785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 115885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 115985593b75SThierry Reding clock-names = "fuse"; 116085593b75SThierry Reding }; 116185593b75SThierry Reding 116239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 116339cb62cbSJoseph Lo compatible = "arm,gic-400"; 116439cb62cbSJoseph Lo #interrupt-cells = <3>; 116539cb62cbSJoseph Lo interrupt-controller; 116639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1167776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1168776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1169776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 117039cb62cbSJoseph Lo interrupts = <GIC_PPI 9 117139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 117239cb62cbSJoseph Lo interrupt-parent = <&gic>; 117339cb62cbSJoseph Lo }; 117439cb62cbSJoseph Lo 117597cf683cSThierry Reding cec@3960000 { 117697cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 117797cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 117897cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 117997cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 118097cf683cSThierry Reding clock-names = "cec"; 118197cf683cSThierry Reding status = "disabled"; 118297cf683cSThierry Reding }; 118397cf683cSThierry Reding 118439cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 118539cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 118639cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 118739cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 118839cb62cbSJoseph Lo interrupt-names = "doorbell"; 118939cb62cbSJoseph Lo #mbox-cells = <2>; 119039cb62cbSJoseph Lo status = "disabled"; 119139cb62cbSJoseph Lo }; 119239cb62cbSJoseph Lo 119340cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1194548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 119540cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 119640cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 119740cc83b3SThierry Reding #address-cells = <1>; 119840cc83b3SThierry Reding #size-cells = <0>; 1199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 120040cc83b3SThierry Reding clock-names = "div-clk"; 12017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 120240cc83b3SThierry Reding reset-names = "i2c"; 1203*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1204*8e442805SAkhil R dma-coherent; 1205*8e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 1206*8e442805SAkhil R dma-names = "rx", "tx"; 120740cc83b3SThierry Reding status = "disabled"; 120840cc83b3SThierry Reding }; 120940cc83b3SThierry Reding 121040cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1211548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 121240cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 121340cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 121440cc83b3SThierry Reding #address-cells = <1>; 121540cc83b3SThierry Reding #size-cells = <0>; 1216c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 121740cc83b3SThierry Reding clock-names = "div-clk"; 12187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 121940cc83b3SThierry Reding reset-names = "i2c"; 1220*8e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 1221*8e442805SAkhil R dma-coherent; 1222*8e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 1223*8e442805SAkhil R dma-names = "rx", "tx"; 122440cc83b3SThierry Reding status = "disabled"; 122540cc83b3SThierry Reding }; 122640cc83b3SThierry Reding 1227a7a77e2eSThierry Reding uartc: serial@c280000 { 1228a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1229a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1230a7a77e2eSThierry Reding reg-shift = <2>; 1231a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1232c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1233a7a77e2eSThierry Reding clock-names = "serial"; 12347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1235a7a77e2eSThierry Reding reset-names = "serial"; 1236a7a77e2eSThierry Reding status = "disabled"; 1237a7a77e2eSThierry Reding }; 1238a7a77e2eSThierry Reding 1239a7a77e2eSThierry Reding uartg: serial@c290000 { 1240a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1241a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1242a7a77e2eSThierry Reding reg-shift = <2>; 1243a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1244c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1245a7a77e2eSThierry Reding clock-names = "serial"; 12467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1247a7a77e2eSThierry Reding reset-names = "serial"; 1248a7a77e2eSThierry Reding status = "disabled"; 1249a7a77e2eSThierry Reding }; 1250a7a77e2eSThierry Reding 12519733a251SThierry Reding rtc: rtc@c2a0000 { 12529733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 12539733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 12549733a251SThierry Reding interrupt-parent = <&pmc>; 12559733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 12569733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 12579733a251SThierry Reding clock-names = "rtc"; 12589733a251SThierry Reding status = "disabled"; 12599733a251SThierry Reding }; 12609733a251SThierry Reding 1261fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1262fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1263fc4bb754SThierry Reding reg-names = "security", "gpio"; 1264fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1265fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1266fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1267fc4bb754SThierry Reding gpio-controller; 1268fc4bb754SThierry Reding #gpio-cells = <2>; 1269fc4bb754SThierry Reding interrupt-controller; 1270fc4bb754SThierry Reding #interrupt-cells = <2>; 1271fc4bb754SThierry Reding }; 1272fc4bb754SThierry Reding 1273913f8ad4SThierry Reding pwm4: pwm@c340000 { 1274913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1275913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1276913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1277913f8ad4SThierry Reding clock-names = "pwm"; 1278913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1279913f8ad4SThierry Reding reset-names = "pwm"; 1280913f8ad4SThierry Reding status = "disabled"; 1281913f8ad4SThierry Reding #pwm-cells = <2>; 1282913f8ad4SThierry Reding }; 1283913f8ad4SThierry Reding 128432e66e46SThierry Reding pmc: pmc@c360000 { 128573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 128673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 128773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 128873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 128973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 129073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 129124005fd1SAapo Vienamo 129232e66e46SThierry Reding #interrupt-cells = <2>; 129332e66e46SThierry Reding interrupt-controller; 129432e66e46SThierry Reding 129524005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 129624005fd1SAapo Vienamo pins = "sdmmc1-hv"; 129724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 129824005fd1SAapo Vienamo }; 129924005fd1SAapo Vienamo 130024005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 130124005fd1SAapo Vienamo pins = "sdmmc1-hv"; 130224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 130324005fd1SAapo Vienamo }; 130424005fd1SAapo Vienamo 130524005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 130624005fd1SAapo Vienamo pins = "sdmmc2-hv"; 130724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 130824005fd1SAapo Vienamo }; 130924005fd1SAapo Vienamo 131024005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 131124005fd1SAapo Vienamo pins = "sdmmc2-hv"; 131224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 131324005fd1SAapo Vienamo }; 131424005fd1SAapo Vienamo 131524005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 131624005fd1SAapo Vienamo pins = "sdmmc3-hv"; 131724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 131824005fd1SAapo Vienamo }; 131924005fd1SAapo Vienamo 132024005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 132124005fd1SAapo Vienamo pins = "sdmmc3-hv"; 132224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 132324005fd1SAapo Vienamo }; 132473bf90d4SThierry Reding }; 132573bf90d4SThierry Reding 13267b7ef494SMikko Perttunen ccplex@e000000 { 13277b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 13282b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 13297b7ef494SMikko Perttunen 13307b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 13317b7ef494SMikko Perttunen }; 13327b7ef494SMikko Perttunen 1333f8973cf4SManikanta Maddireddy pcie@10003000 { 1334f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1335f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1336f8973cf4SManikanta Maddireddy device_type = "pci"; 1337644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1338644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1339644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1340f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1341f8973cf4SManikanta Maddireddy 1342f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1343f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1344f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1345f8973cf4SManikanta Maddireddy 1346f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1347f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1348f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1349f8973cf4SManikanta Maddireddy 1350f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1351f8973cf4SManikanta Maddireddy #address-cells = <3>; 1352f8973cf4SManikanta Maddireddy #size-cells = <2>; 1353f8973cf4SManikanta Maddireddy 1354644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1355644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1356644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1357644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1358644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1359644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1360f8973cf4SManikanta Maddireddy 136178b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 136278b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1363f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 136478b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1365f8973cf4SManikanta Maddireddy 136678b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 136778b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1368f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 136978b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1370f8973cf4SManikanta Maddireddy 1371954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1372954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1373954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1374954490b3SThierry Reding 1375f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1376f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1377f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1378f2a465e7SThierry Reding 1379f8973cf4SManikanta Maddireddy status = "disabled"; 1380f8973cf4SManikanta Maddireddy 1381f8973cf4SManikanta Maddireddy pci@1,0 { 1382f8973cf4SManikanta Maddireddy device_type = "pci"; 1383f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1384f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1385f8973cf4SManikanta Maddireddy status = "disabled"; 1386f8973cf4SManikanta Maddireddy 1387f8973cf4SManikanta Maddireddy #address-cells = <3>; 1388f8973cf4SManikanta Maddireddy #size-cells = <2>; 1389f8973cf4SManikanta Maddireddy ranges; 1390f8973cf4SManikanta Maddireddy 1391f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1392f8973cf4SManikanta Maddireddy }; 1393f8973cf4SManikanta Maddireddy 1394f8973cf4SManikanta Maddireddy pci@2,0 { 1395f8973cf4SManikanta Maddireddy device_type = "pci"; 1396f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1397f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1398f8973cf4SManikanta Maddireddy status = "disabled"; 1399f8973cf4SManikanta Maddireddy 1400f8973cf4SManikanta Maddireddy #address-cells = <3>; 1401f8973cf4SManikanta Maddireddy #size-cells = <2>; 1402f8973cf4SManikanta Maddireddy ranges; 1403f8973cf4SManikanta Maddireddy 1404f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1405f8973cf4SManikanta Maddireddy }; 1406f8973cf4SManikanta Maddireddy 1407f8973cf4SManikanta Maddireddy pci@3,0 { 1408f8973cf4SManikanta Maddireddy device_type = "pci"; 1409f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1410f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1411f8973cf4SManikanta Maddireddy status = "disabled"; 1412f8973cf4SManikanta Maddireddy 1413f8973cf4SManikanta Maddireddy #address-cells = <3>; 1414f8973cf4SManikanta Maddireddy #size-cells = <2>; 1415f8973cf4SManikanta Maddireddy ranges; 1416f8973cf4SManikanta Maddireddy 1417f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1418f8973cf4SManikanta Maddireddy }; 1419f8973cf4SManikanta Maddireddy }; 1420f8973cf4SManikanta Maddireddy 1421b30a8e61SThierry Reding smmu: iommu@12000000 { 1422bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1423b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1424b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1489b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1490b30a8e61SThierry Reding #global-interrupts = <1>; 1491b30a8e61SThierry Reding #iommu-cells = <1>; 1492b966d2dbSThierry Reding 1493b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1494b30a8e61SThierry Reding }; 1495b30a8e61SThierry Reding 14965524c61fSMikko Perttunen host1x@13e00000 { 1497ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 14985524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 14995524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 15005524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 15015524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 15025524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1503052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 15045524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 15055524c61fSMikko Perttunen clock-names = "host1x"; 15065524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 15075524c61fSMikko Perttunen reset-names = "host1x"; 15085524c61fSMikko Perttunen 15095524c61fSMikko Perttunen #address-cells = <1>; 15105524c61fSMikko Perttunen #size-cells = <1>; 15115524c61fSMikko Perttunen 15125524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1513954490b3SThierry Reding 1514954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1515954490b3SThierry Reding interconnect-names = "dma-mem"; 1516954490b3SThierry Reding 1517c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1518c2599da7SThierry Reding 1519e30cf101SMikko Perttunen /* Context isolation domains */ 1520b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1521b0c1a994SThierry Reding <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1522b0c1a994SThierry Reding <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1523b0c1a994SThierry Reding <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1524b0c1a994SThierry Reding <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1525b0c1a994SThierry Reding <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1526b0c1a994SThierry Reding <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1527b0c1a994SThierry Reding <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1528e30cf101SMikko Perttunen 1529c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1530c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1531c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1532c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1533c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1534c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1535c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1536c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1537c2599da7SThierry Reding reset-names = "dpaux"; 1538c2599da7SThierry Reding status = "disabled"; 1539c2599da7SThierry Reding 1540c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1541c2599da7SThierry Reding 1542c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1543c2599da7SThierry Reding groups = "dpaux-io"; 1544c2599da7SThierry Reding function = "aux"; 1545c2599da7SThierry Reding }; 1546c2599da7SThierry Reding 1547c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1548c2599da7SThierry Reding groups = "dpaux-io"; 1549c2599da7SThierry Reding function = "i2c"; 1550c2599da7SThierry Reding }; 1551c2599da7SThierry Reding 1552c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1553c2599da7SThierry Reding groups = "dpaux-io"; 1554c2599da7SThierry Reding function = "off"; 1555c2599da7SThierry Reding }; 1556c2599da7SThierry Reding 1557c2599da7SThierry Reding i2c-bus { 1558c2599da7SThierry Reding #address-cells = <1>; 1559c2599da7SThierry Reding #size-cells = <0>; 1560c2599da7SThierry Reding }; 1561c2599da7SThierry Reding }; 1562c2599da7SThierry Reding 1563c2599da7SThierry Reding display-hub@15200000 { 1564aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1565ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1566c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1567c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1568c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1569c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1570c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1571c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1572c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1573c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1574c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1575c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1576c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1577c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1578c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1579c2599da7SThierry Reding status = "disabled"; 1580c2599da7SThierry Reding 1581c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1582c2599da7SThierry Reding 1583c2599da7SThierry Reding #address-cells = <1>; 1584c2599da7SThierry Reding #size-cells = <1>; 1585c2599da7SThierry Reding 1586c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1587c2599da7SThierry Reding 1588c2599da7SThierry Reding display@15200000 { 1589c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1590c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1591c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1592c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1593c2599da7SThierry Reding clock-names = "dc"; 1594c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1595c2599da7SThierry Reding reset-names = "dc"; 1596c2599da7SThierry Reding 1597c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1598954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1599954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1600954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1601c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1602c2599da7SThierry Reding 1603c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1604c2599da7SThierry Reding nvidia,head = <0>; 1605c2599da7SThierry Reding }; 1606c2599da7SThierry Reding 1607c2599da7SThierry Reding display@15210000 { 1608c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1609c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1610c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1611c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1612c2599da7SThierry Reding clock-names = "dc"; 1613c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1614c2599da7SThierry Reding reset-names = "dc"; 1615c2599da7SThierry Reding 1616c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1617954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1618954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1619954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1620c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1621c2599da7SThierry Reding 1622c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1623c2599da7SThierry Reding nvidia,head = <1>; 1624c2599da7SThierry Reding }; 1625c2599da7SThierry Reding 1626c2599da7SThierry Reding display@15220000 { 1627c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1628c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1629c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1630c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1631c2599da7SThierry Reding clock-names = "dc"; 1632c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1633c2599da7SThierry Reding reset-names = "dc"; 1634c2599da7SThierry Reding 1635c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1636954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1637954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1638954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1639c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1640c2599da7SThierry Reding 1641c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1642c2599da7SThierry Reding nvidia,head = <2>; 1643c2599da7SThierry Reding }; 1644c2599da7SThierry Reding }; 1645c2599da7SThierry Reding 1646c2599da7SThierry Reding dsia: dsi@15300000 { 1647c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1648c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1649c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1650c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1651c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1652c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1653c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1654c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1655c2599da7SThierry Reding reset-names = "dsi"; 1656c2599da7SThierry Reding status = "disabled"; 1657c2599da7SThierry Reding 1658c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1659c2599da7SThierry Reding }; 1660effc4b44SMikko Perttunen 1661effc4b44SMikko Perttunen vic@15340000 { 1662effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1663effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1664effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1665effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1666effc4b44SMikko Perttunen clock-names = "vic"; 1667effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1668effc4b44SMikko Perttunen reset-names = "vic"; 1669effc4b44SMikko Perttunen 1670effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1671954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1672954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1673954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 167429ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1675effc4b44SMikko Perttunen }; 1676c2599da7SThierry Reding 1677f7eb2785SJon Hunter nvjpg@15380000 { 1678f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1679f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1680f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1681f7eb2785SJon Hunter clock-names = "nvjpg"; 1682f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1683f7eb2785SJon Hunter reset-names = "nvjpg"; 1684f7eb2785SJon Hunter 1685f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1686f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1687f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1688f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1689f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1690f7eb2785SJon Hunter }; 1691f7eb2785SJon Hunter 1692c2599da7SThierry Reding dsib: dsi@15400000 { 1693c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1694c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1695c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1696c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1697c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1698c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1699c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1700c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1701c2599da7SThierry Reding reset-names = "dsi"; 1702c2599da7SThierry Reding status = "disabled"; 1703c2599da7SThierry Reding 1704c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1705c2599da7SThierry Reding }; 1706c2599da7SThierry Reding 170778a05873SMikko Perttunen nvdec@15480000 { 170878a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 170978a05873SMikko Perttunen reg = <0x15480000 0x40000>; 171078a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 171178a05873SMikko Perttunen clock-names = "nvdec"; 171278a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 171378a05873SMikko Perttunen reset-names = "nvdec"; 171478a05873SMikko Perttunen 171578a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 171678a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 171778a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 171878a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 171978a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 172078a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 172178a05873SMikko Perttunen }; 172278a05873SMikko Perttunen 1723f7eb2785SJon Hunter nvenc@154c0000 { 1724f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1725f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1726f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1727f7eb2785SJon Hunter clock-names = "nvenc"; 1728f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1729f7eb2785SJon Hunter reset-names = "nvenc"; 1730f7eb2785SJon Hunter 1731f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1732f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1733f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1734f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1735f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1736f7eb2785SJon Hunter }; 1737f7eb2785SJon Hunter 1738c2599da7SThierry Reding sor0: sor@15540000 { 1739c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1740c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1741c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1742c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1743c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1744c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1745c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1746c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1747c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1748c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1749c2599da7SThierry Reding "pad"; 1750c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1751c2599da7SThierry Reding reset-names = "sor"; 1752c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1753c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1754c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1755c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1756c2599da7SThierry Reding status = "disabled"; 1757c2599da7SThierry Reding 1758c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1759c2599da7SThierry Reding nvidia,interface = <0>; 1760c2599da7SThierry Reding }; 1761c2599da7SThierry Reding 1762c2599da7SThierry Reding sor1: sor@15580000 { 1763d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1764c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1765c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1766c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1767c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1768c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1769c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1770c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1771c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1772c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1773c2599da7SThierry Reding "pad"; 1774c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1775c2599da7SThierry Reding reset-names = "sor"; 1776c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1777c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1778c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1779c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1780c2599da7SThierry Reding status = "disabled"; 1781c2599da7SThierry Reding 1782c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1783c2599da7SThierry Reding nvidia,interface = <1>; 1784c2599da7SThierry Reding }; 1785c2599da7SThierry Reding 1786c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1787c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1788c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1789c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1790c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1791c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1792c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1793c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1794c2599da7SThierry Reding reset-names = "dpaux"; 1795c2599da7SThierry Reding status = "disabled"; 1796c2599da7SThierry Reding 1797c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1798c2599da7SThierry Reding 1799c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1800c2599da7SThierry Reding groups = "dpaux-io"; 1801c2599da7SThierry Reding function = "aux"; 1802c2599da7SThierry Reding }; 1803c2599da7SThierry Reding 1804c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1805c2599da7SThierry Reding groups = "dpaux-io"; 1806c2599da7SThierry Reding function = "i2c"; 1807c2599da7SThierry Reding }; 1808c2599da7SThierry Reding 1809c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1810c2599da7SThierry Reding groups = "dpaux-io"; 1811c2599da7SThierry Reding function = "off"; 1812c2599da7SThierry Reding }; 1813c2599da7SThierry Reding 1814c2599da7SThierry Reding i2c-bus { 1815c2599da7SThierry Reding #address-cells = <1>; 1816c2599da7SThierry Reding #size-cells = <0>; 1817c2599da7SThierry Reding }; 1818c2599da7SThierry Reding }; 1819c2599da7SThierry Reding 1820c2599da7SThierry Reding padctl@15880000 { 1821c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1822c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1823c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1824c2599da7SThierry Reding reset-names = "dsi"; 1825c2599da7SThierry Reding status = "disabled"; 1826c2599da7SThierry Reding }; 1827c2599da7SThierry Reding 1828c2599da7SThierry Reding dsic: dsi@15900000 { 1829c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1830c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1831c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1832c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1833c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1834c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1835c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1836c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1837c2599da7SThierry Reding reset-names = "dsi"; 1838c2599da7SThierry Reding status = "disabled"; 1839c2599da7SThierry Reding 1840c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1841c2599da7SThierry Reding }; 1842c2599da7SThierry Reding 1843c2599da7SThierry Reding dsid: dsi@15940000 { 1844c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1845c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1846c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1847c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1848c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1849c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1850c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1851c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1852c2599da7SThierry Reding reset-names = "dsi"; 1853c2599da7SThierry Reding status = "disabled"; 1854c2599da7SThierry Reding 1855c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1856c2599da7SThierry Reding }; 18575524c61fSMikko Perttunen }; 18585524c61fSMikko Perttunen 1859dfd7a384SAlexandre Courbot gpu@17000000 { 1860dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1861dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1862dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 186359a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 186459a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1865dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1866dfd7a384SAlexandre Courbot 1867dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1868dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1869dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1870dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1871dfd7a384SAlexandre Courbot reset-names = "gpu"; 1872dfd7a384SAlexandre Courbot status = "disabled"; 1873dfd7a384SAlexandre Courbot 1874dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1875954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1876954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1877954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1878954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1879954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1880dfd7a384SAlexandre Courbot }; 1881dfd7a384SAlexandre Courbot 1882e867fe41SThierry Reding sram@30000000 { 188339cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 188439cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1885aa78032cSThierry Reding #address-cells = <1>; 1886aa78032cSThierry Reding #size-cells = <1>; 1887aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 188861192a9dSMikko Perttunen no-memory-wc; 188939cb62cbSJoseph Lo 1890e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1891aa78032cSThierry Reding reg = <0x4e000 0x1000>; 189239cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 189339cb62cbSJoseph Lo pool; 189439cb62cbSJoseph Lo }; 189539cb62cbSJoseph Lo 1896e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1897aa78032cSThierry Reding reg = <0x4f000 0x1000>; 189839cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 189939cb62cbSJoseph Lo pool; 190039cb62cbSJoseph Lo }; 190139cb62cbSJoseph Lo }; 190239cb62cbSJoseph Lo 1903e061fbdfSSowjanya Komatineni sata@3507000 { 1904e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1905e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1906e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1907e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1908e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1909e061fbdfSSowjanya Komatineni 1910e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1911e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1912e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1913e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1914e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1915e061fbdfSSowjanya Komatineni 1916e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1917e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1918e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1919e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1920e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1921e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1922e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1923e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1924e061fbdfSSowjanya Komatineni <204000000>; 1925e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1926e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1927e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1928e061fbdfSSowjanya Komatineni status = "disabled"; 1929e061fbdfSSowjanya Komatineni }; 1930e061fbdfSSowjanya Komatineni 1931541d7c44SThierry Reding bpmp: bpmp { 1932541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1933954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1934954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1935954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1936954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1937954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1938541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1939541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1940541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 19417fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1942541d7c44SThierry Reding #clock-cells = <1>; 1943541d7c44SThierry Reding #reset-cells = <1>; 1944541d7c44SThierry Reding #power-domain-cells = <1>; 1945541d7c44SThierry Reding 1946541d7c44SThierry Reding bpmp_i2c: i2c { 1947541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1948541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1949541d7c44SThierry Reding #address-cells = <1>; 1950541d7c44SThierry Reding #size-cells = <0>; 1951541d7c44SThierry Reding status = "disabled"; 1952541d7c44SThierry Reding }; 1953541d7c44SThierry Reding 1954541d7c44SThierry Reding bpmp_thermal: thermal { 1955541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1956541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1957541d7c44SThierry Reding }; 1958541d7c44SThierry Reding }; 1959541d7c44SThierry Reding 1960cd6fe32eSThierry Reding cpus { 1961cd6fe32eSThierry Reding #address-cells = <1>; 1962cd6fe32eSThierry Reding #size-cells = <0>; 1963cd6fe32eSThierry Reding 19643b4c1378SMarc Zyngier denver_0: cpu@0 { 196531af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1966cd6fe32eSThierry Reding device_type = "cpu"; 19675298166dSJoseph Lo i-cache-size = <0x20000>; 19685298166dSJoseph Lo i-cache-line-size = <64>; 19695298166dSJoseph Lo i-cache-sets = <512>; 19705298166dSJoseph Lo d-cache-size = <0x10000>; 19715298166dSJoseph Lo d-cache-line-size = <64>; 19725298166dSJoseph Lo d-cache-sets = <256>; 19735298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1974cd6fe32eSThierry Reding reg = <0x000>; 1975cd6fe32eSThierry Reding }; 1976cd6fe32eSThierry Reding 19773b4c1378SMarc Zyngier denver_1: cpu@1 { 197831af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1979cd6fe32eSThierry Reding device_type = "cpu"; 19805298166dSJoseph Lo i-cache-size = <0x20000>; 19815298166dSJoseph Lo i-cache-line-size = <64>; 19825298166dSJoseph Lo i-cache-sets = <512>; 19835298166dSJoseph Lo d-cache-size = <0x10000>; 19845298166dSJoseph Lo d-cache-line-size = <64>; 19855298166dSJoseph Lo d-cache-sets = <256>; 19865298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1987cd6fe32eSThierry Reding reg = <0x001>; 1988cd6fe32eSThierry Reding }; 1989cd6fe32eSThierry Reding 19903b4c1378SMarc Zyngier ca57_0: cpu@2 { 199131af04cdSRob Herring compatible = "arm,cortex-a57"; 1992cd6fe32eSThierry Reding device_type = "cpu"; 19935298166dSJoseph Lo i-cache-size = <0xC000>; 19945298166dSJoseph Lo i-cache-line-size = <64>; 19955298166dSJoseph Lo i-cache-sets = <256>; 19965298166dSJoseph Lo d-cache-size = <0x8000>; 19975298166dSJoseph Lo d-cache-line-size = <64>; 19985298166dSJoseph Lo d-cache-sets = <256>; 19995298166dSJoseph Lo next-level-cache = <&L2_A57>; 2000cd6fe32eSThierry Reding reg = <0x100>; 2001cd6fe32eSThierry Reding }; 2002cd6fe32eSThierry Reding 20033b4c1378SMarc Zyngier ca57_1: cpu@3 { 200431af04cdSRob Herring compatible = "arm,cortex-a57"; 2005cd6fe32eSThierry Reding device_type = "cpu"; 20065298166dSJoseph Lo i-cache-size = <0xC000>; 20075298166dSJoseph Lo i-cache-line-size = <64>; 20085298166dSJoseph Lo i-cache-sets = <256>; 20095298166dSJoseph Lo d-cache-size = <0x8000>; 20105298166dSJoseph Lo d-cache-line-size = <64>; 20115298166dSJoseph Lo d-cache-sets = <256>; 20125298166dSJoseph Lo next-level-cache = <&L2_A57>; 2013cd6fe32eSThierry Reding reg = <0x101>; 2014cd6fe32eSThierry Reding }; 2015cd6fe32eSThierry Reding 20163b4c1378SMarc Zyngier ca57_2: cpu@4 { 201731af04cdSRob Herring compatible = "arm,cortex-a57"; 2018cd6fe32eSThierry Reding device_type = "cpu"; 20195298166dSJoseph Lo i-cache-size = <0xC000>; 20205298166dSJoseph Lo i-cache-line-size = <64>; 20215298166dSJoseph Lo i-cache-sets = <256>; 20225298166dSJoseph Lo d-cache-size = <0x8000>; 20235298166dSJoseph Lo d-cache-line-size = <64>; 20245298166dSJoseph Lo d-cache-sets = <256>; 20255298166dSJoseph Lo next-level-cache = <&L2_A57>; 2026cd6fe32eSThierry Reding reg = <0x102>; 2027cd6fe32eSThierry Reding }; 2028cd6fe32eSThierry Reding 20293b4c1378SMarc Zyngier ca57_3: cpu@5 { 203031af04cdSRob Herring compatible = "arm,cortex-a57"; 2031cd6fe32eSThierry Reding device_type = "cpu"; 20325298166dSJoseph Lo i-cache-size = <0xC000>; 20335298166dSJoseph Lo i-cache-line-size = <64>; 20345298166dSJoseph Lo i-cache-sets = <256>; 20355298166dSJoseph Lo d-cache-size = <0x8000>; 20365298166dSJoseph Lo d-cache-line-size = <64>; 20375298166dSJoseph Lo d-cache-sets = <256>; 20385298166dSJoseph Lo next-level-cache = <&L2_A57>; 2039cd6fe32eSThierry Reding reg = <0x103>; 2040cd6fe32eSThierry Reding }; 20415298166dSJoseph Lo 20425298166dSJoseph Lo L2_DENVER: l2-cache0 { 20435298166dSJoseph Lo compatible = "cache"; 20445298166dSJoseph Lo cache-unified; 20455298166dSJoseph Lo cache-level = <2>; 20465298166dSJoseph Lo cache-size = <0x200000>; 20475298166dSJoseph Lo cache-line-size = <64>; 20485298166dSJoseph Lo cache-sets = <2048>; 20495298166dSJoseph Lo }; 20505298166dSJoseph Lo 20515298166dSJoseph Lo L2_A57: l2-cache1 { 20525298166dSJoseph Lo compatible = "cache"; 20535298166dSJoseph Lo cache-unified; 20545298166dSJoseph Lo cache-level = <2>; 20555298166dSJoseph Lo cache-size = <0x200000>; 20565298166dSJoseph Lo cache-line-size = <64>; 20575298166dSJoseph Lo cache-sets = <2048>; 20585298166dSJoseph Lo }; 2059cd6fe32eSThierry Reding }; 2060cd6fe32eSThierry Reding 20613b4c1378SMarc Zyngier pmu_denver { 2062f0a48120SThierry Reding compatible = "nvidia,denver-pmu"; 20633b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 20643b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 20653b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 20663b4c1378SMarc Zyngier }; 20673b4c1378SMarc Zyngier 20683b4c1378SMarc Zyngier pmu_a57 { 2069f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 20703b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 20713b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20723b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20733b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20743b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20753b4c1378SMarc Zyngier }; 20763b4c1378SMarc Zyngier 2077e4710376SSameer Pujar sound { 2078e4710376SSameer Pujar status = "disabled"; 2079e4710376SSameer Pujar 2080e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2081e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2082e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2083e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2084e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2085e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2086e4710376SSameer Pujar assigned-clock-parents = <0>, 2087e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2088e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2089e4710376SSameer Pujar /* 2090e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2091e4710376SSameer Pujar * for this to work and oscillate between base rates required 2092e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2093e4710376SSameer Pujar */ 2094e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2095e4710376SSameer Pujar 2096e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2097e4710376SSameer Pujar }; 2098e4710376SSameer Pujar 209915274c23SMikko Perttunen thermal-zones { 2100fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2101fe57ff53SThierry Reding cpu-thermal { 210215274c23SMikko Perttunen polling-delay = <0>; 210315274c23SMikko Perttunen polling-delay-passive = <1000>; 210415274c23SMikko Perttunen 2105fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 210615274c23SMikko Perttunen 210715274c23SMikko Perttunen trips { 210815274c23SMikko Perttunen critical { 210915274c23SMikko Perttunen temperature = <101000>; 211015274c23SMikko Perttunen hysteresis = <0>; 211115274c23SMikko Perttunen type = "critical"; 211215274c23SMikko Perttunen }; 211315274c23SMikko Perttunen }; 211415274c23SMikko Perttunen 211515274c23SMikko Perttunen cooling-maps { 211615274c23SMikko Perttunen }; 211715274c23SMikko Perttunen }; 211815274c23SMikko Perttunen 2119fe57ff53SThierry Reding /* Denver cluster */ 2120fe57ff53SThierry Reding aux-thermal { 212115274c23SMikko Perttunen polling-delay = <0>; 212215274c23SMikko Perttunen polling-delay-passive = <1000>; 212315274c23SMikko Perttunen 2124fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 212515274c23SMikko Perttunen 212615274c23SMikko Perttunen trips { 212715274c23SMikko Perttunen critical { 212815274c23SMikko Perttunen temperature = <101000>; 212915274c23SMikko Perttunen hysteresis = <0>; 213015274c23SMikko Perttunen type = "critical"; 213115274c23SMikko Perttunen }; 213215274c23SMikko Perttunen }; 213315274c23SMikko Perttunen 213415274c23SMikko Perttunen cooling-maps { 213515274c23SMikko Perttunen }; 213615274c23SMikko Perttunen }; 213715274c23SMikko Perttunen 2138fe57ff53SThierry Reding gpu-thermal { 213915274c23SMikko Perttunen polling-delay = <0>; 214015274c23SMikko Perttunen polling-delay-passive = <1000>; 214115274c23SMikko Perttunen 2142fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 214315274c23SMikko Perttunen 214415274c23SMikko Perttunen trips { 214515274c23SMikko Perttunen critical { 214615274c23SMikko Perttunen temperature = <101000>; 214715274c23SMikko Perttunen hysteresis = <0>; 214815274c23SMikko Perttunen type = "critical"; 214915274c23SMikko Perttunen }; 215015274c23SMikko Perttunen }; 215115274c23SMikko Perttunen 215215274c23SMikko Perttunen cooling-maps { 215315274c23SMikko Perttunen }; 215415274c23SMikko Perttunen }; 215515274c23SMikko Perttunen 2156fe57ff53SThierry Reding pll-thermal { 215715274c23SMikko Perttunen polling-delay = <0>; 215815274c23SMikko Perttunen polling-delay-passive = <1000>; 215915274c23SMikko Perttunen 2160fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 216115274c23SMikko Perttunen 216215274c23SMikko Perttunen trips { 216315274c23SMikko Perttunen critical { 216415274c23SMikko Perttunen temperature = <101000>; 216515274c23SMikko Perttunen hysteresis = <0>; 216615274c23SMikko Perttunen type = "critical"; 216715274c23SMikko Perttunen }; 216815274c23SMikko Perttunen }; 216915274c23SMikko Perttunen 217015274c23SMikko Perttunen cooling-maps { 217115274c23SMikko Perttunen }; 217215274c23SMikko Perttunen }; 217315274c23SMikko Perttunen 2174fe57ff53SThierry Reding ao-thermal { 217515274c23SMikko Perttunen polling-delay = <0>; 217615274c23SMikko Perttunen polling-delay-passive = <1000>; 217715274c23SMikko Perttunen 2178fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 217915274c23SMikko Perttunen 218015274c23SMikko Perttunen trips { 218115274c23SMikko Perttunen critical { 218215274c23SMikko Perttunen temperature = <101000>; 218315274c23SMikko Perttunen hysteresis = <0>; 218415274c23SMikko Perttunen type = "critical"; 218515274c23SMikko Perttunen }; 218615274c23SMikko Perttunen }; 218715274c23SMikko Perttunen 218815274c23SMikko Perttunen cooling-maps { 218915274c23SMikko Perttunen }; 219015274c23SMikko Perttunen }; 219139cb62cbSJoseph Lo }; 219239cb62cbSJoseph Lo 219339cb62cbSJoseph Lo timer { 219439cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 219539cb62cbSJoseph Lo interrupts = <GIC_PPI 13 219639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 219739cb62cbSJoseph Lo <GIC_PPI 14 219839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 219939cb62cbSJoseph Lo <GIC_PPI 11 220039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 220139cb62cbSJoseph Lo <GIC_PPI 10 220239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 220339cb62cbSJoseph Lo interrupt-parent = <&gic>; 2204b30be673SThierry Reding always-on; 220539cb62cbSJoseph Lo }; 220639cb62cbSJoseph Lo}; 2207