1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 77bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 815274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 939cb62cbSJoseph Lo 1039cb62cbSJoseph Lo/ { 1139cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1239cb62cbSJoseph Lo interrupt-parent = <&gic>; 1339cb62cbSJoseph Lo #address-cells = <2>; 1439cb62cbSJoseph Lo #size-cells = <2>; 1539cb62cbSJoseph Lo 1694e25dc3SThierry Reding misc@100000 { 1794e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 1894e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 1994e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2094e25dc3SThierry Reding }; 2194e25dc3SThierry Reding 22fc4bb754SThierry Reding gpio: gpio@2200000 { 23fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 24fc4bb754SThierry Reding reg-names = "security", "gpio"; 25fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 26fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 27fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 28fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 29fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 33fc4bb754SThierry Reding #interrupt-cells = <2>; 34fc4bb754SThierry Reding interrupt-controller; 35fc4bb754SThierry Reding #gpio-cells = <2>; 36fc4bb754SThierry Reding gpio-controller; 37fc4bb754SThierry Reding }; 38fc4bb754SThierry Reding 390caafbdeSThierry Reding ethernet@2490000 { 400caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 410caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 420caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 430caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 440caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 450caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 460caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 470caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 480caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 490caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 500caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 510caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 520caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 530caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 540caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 550caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 580caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 590caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 600caafbdeSThierry Reding reset-names = "eqos"; 610caafbdeSThierry Reding status = "disabled"; 620caafbdeSThierry Reding 630caafbdeSThierry Reding snps,write-requests = <1>; 640caafbdeSThierry Reding snps,read-requests = <3>; 650caafbdeSThierry Reding snps,burst-map = <0x7>; 660caafbdeSThierry Reding snps,txpbl = <32>; 670caafbdeSThierry Reding snps,rxpbl = <8>; 680caafbdeSThierry Reding }; 690caafbdeSThierry Reding 7039cb62cbSJoseph Lo uarta: serial@3100000 { 7139cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 7239cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 7339cb62cbSJoseph Lo reg-shift = <2>; 7439cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 75c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 76a7a77e2eSThierry Reding clock-names = "serial"; 777bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 78a7a77e2eSThierry Reding reset-names = "serial"; 79a7a77e2eSThierry Reding status = "disabled"; 80a7a77e2eSThierry Reding }; 81a7a77e2eSThierry Reding 82a7a77e2eSThierry Reding uartb: serial@3110000 { 83a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 84a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 85a7a77e2eSThierry Reding reg-shift = <2>; 86a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 87c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 88a7a77e2eSThierry Reding clock-names = "serial"; 897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 90a7a77e2eSThierry Reding reset-names = "serial"; 91a7a77e2eSThierry Reding status = "disabled"; 92a7a77e2eSThierry Reding }; 93a7a77e2eSThierry Reding 94a7a77e2eSThierry Reding uartd: serial@3130000 { 95a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 96a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 97a7a77e2eSThierry Reding reg-shift = <2>; 98a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 99c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 100a7a77e2eSThierry Reding clock-names = "serial"; 1017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 102a7a77e2eSThierry Reding reset-names = "serial"; 103a7a77e2eSThierry Reding status = "disabled"; 104a7a77e2eSThierry Reding }; 105a7a77e2eSThierry Reding 106a7a77e2eSThierry Reding uarte: serial@3140000 { 107a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 108a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 109a7a77e2eSThierry Reding reg-shift = <2>; 110a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 111c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 112a7a77e2eSThierry Reding clock-names = "serial"; 1137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 114a7a77e2eSThierry Reding reset-names = "serial"; 115a7a77e2eSThierry Reding status = "disabled"; 116a7a77e2eSThierry Reding }; 117a7a77e2eSThierry Reding 118a7a77e2eSThierry Reding uartf: serial@3150000 { 119a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 120a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 121a7a77e2eSThierry Reding reg-shift = <2>; 122a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 123c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 124a7a77e2eSThierry Reding clock-names = "serial"; 1257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 126a7a77e2eSThierry Reding reset-names = "serial"; 12739cb62cbSJoseph Lo status = "disabled"; 12839cb62cbSJoseph Lo }; 12939cb62cbSJoseph Lo 13040cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13140cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13240cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 13340cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 13440cc83b3SThierry Reding #address-cells = <1>; 13540cc83b3SThierry Reding #size-cells = <0>; 136c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 13740cc83b3SThierry Reding clock-names = "div-clk"; 1387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 13940cc83b3SThierry Reding reset-names = "i2c"; 14040cc83b3SThierry Reding status = "disabled"; 14140cc83b3SThierry Reding }; 14240cc83b3SThierry Reding 14340cc83b3SThierry Reding cam_i2c: i2c@3180000 { 14440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14540cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 14640cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 14740cc83b3SThierry Reding #address-cells = <1>; 14840cc83b3SThierry Reding #size-cells = <0>; 149c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15040cc83b3SThierry Reding clock-names = "div-clk"; 1517bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 15240cc83b3SThierry Reding reset-names = "i2c"; 15340cc83b3SThierry Reding status = "disabled"; 15440cc83b3SThierry Reding }; 15540cc83b3SThierry Reding 15640cc83b3SThierry Reding /* shares pads with dpaux1 */ 15740cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 15840cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15940cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16040cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16140cc83b3SThierry Reding #address-cells = <1>; 16240cc83b3SThierry Reding #size-cells = <0>; 163c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 16440cc83b3SThierry Reding clock-names = "div-clk"; 1657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 16640cc83b3SThierry Reding reset-names = "i2c"; 16740cc83b3SThierry Reding status = "disabled"; 16840cc83b3SThierry Reding }; 16940cc83b3SThierry Reding 17040cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17140cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 17240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 17340cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 17440cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 17540cc83b3SThierry Reding #address-cells = <1>; 17640cc83b3SThierry Reding #size-cells = <0>; 177c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 17840cc83b3SThierry Reding clock-names = "div-clk"; 1797bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18040cc83b3SThierry Reding reset-names = "i2c"; 18140cc83b3SThierry Reding status = "disabled"; 18240cc83b3SThierry Reding }; 18340cc83b3SThierry Reding 18440cc83b3SThierry Reding /* shares pads with dpaux0 */ 18540cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 18640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18740cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 18840cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 18940cc83b3SThierry Reding #address-cells = <1>; 19040cc83b3SThierry Reding #size-cells = <0>; 191c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 19240cc83b3SThierry Reding clock-names = "div-clk"; 1937bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 19440cc83b3SThierry Reding reset-names = "i2c"; 19540cc83b3SThierry Reding status = "disabled"; 19640cc83b3SThierry Reding }; 19740cc83b3SThierry Reding 19840cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 19940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20040cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20140cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 20240cc83b3SThierry Reding #address-cells = <1>; 20340cc83b3SThierry Reding #size-cells = <0>; 204c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 20540cc83b3SThierry Reding clock-names = "div-clk"; 2067bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 20740cc83b3SThierry Reding reset-names = "i2c"; 20840cc83b3SThierry Reding status = "disabled"; 20940cc83b3SThierry Reding }; 21040cc83b3SThierry Reding 21140cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 21240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 21340cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 21440cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 21540cc83b3SThierry Reding #address-cells = <1>; 21640cc83b3SThierry Reding #size-cells = <0>; 217c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 21840cc83b3SThierry Reding clock-names = "div-clk"; 2197bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22040cc83b3SThierry Reding reset-names = "i2c"; 22140cc83b3SThierry Reding status = "disabled"; 22240cc83b3SThierry Reding }; 22340cc83b3SThierry Reding 22499425dfdSThierry Reding sdmmc1: sdhci@3400000 { 22599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 22699425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 22799425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 228c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 22999425dfdSThierry Reding clock-names = "sdhci"; 2307bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23199425dfdSThierry Reding reset-names = "sdhci"; 23299425dfdSThierry Reding status = "disabled"; 23399425dfdSThierry Reding }; 23499425dfdSThierry Reding 23599425dfdSThierry Reding sdmmc2: sdhci@3420000 { 23699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23799425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 23899425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 239c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 24099425dfdSThierry Reding clock-names = "sdhci"; 2417bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 24299425dfdSThierry Reding reset-names = "sdhci"; 24399425dfdSThierry Reding status = "disabled"; 24499425dfdSThierry Reding }; 24599425dfdSThierry Reding 24699425dfdSThierry Reding sdmmc3: sdhci@3440000 { 24799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24899425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 24999425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 250c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 25199425dfdSThierry Reding clock-names = "sdhci"; 2527bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 25399425dfdSThierry Reding reset-names = "sdhci"; 25499425dfdSThierry Reding status = "disabled"; 25599425dfdSThierry Reding }; 25699425dfdSThierry Reding 25799425dfdSThierry Reding sdmmc4: sdhci@3460000 { 25899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25999425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 26099425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 261c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 26299425dfdSThierry Reding clock-names = "sdhci"; 2637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 26499425dfdSThierry Reding reset-names = "sdhci"; 26599425dfdSThierry Reding status = "disabled"; 26699425dfdSThierry Reding }; 26799425dfdSThierry Reding 26885593b75SThierry Reding fuse@3820000 { 26985593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 27085593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 27185593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 27285593b75SThierry Reding clock-names = "fuse"; 27385593b75SThierry Reding }; 27485593b75SThierry Reding 27539cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 27639cb62cbSJoseph Lo compatible = "arm,gic-400"; 27739cb62cbSJoseph Lo #interrupt-cells = <3>; 27839cb62cbSJoseph Lo interrupt-controller; 27939cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 28039cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 28139cb62cbSJoseph Lo interrupts = <GIC_PPI 9 28239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 28339cb62cbSJoseph Lo interrupt-parent = <&gic>; 28439cb62cbSJoseph Lo }; 28539cb62cbSJoseph Lo 28639cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 28739cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 28839cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 28939cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 29039cb62cbSJoseph Lo interrupt-names = "doorbell"; 29139cb62cbSJoseph Lo #mbox-cells = <2>; 29239cb62cbSJoseph Lo status = "disabled"; 29339cb62cbSJoseph Lo }; 29439cb62cbSJoseph Lo 29540cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 29640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 29740cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 29840cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 29940cc83b3SThierry Reding #address-cells = <1>; 30040cc83b3SThierry Reding #size-cells = <0>; 301c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 30240cc83b3SThierry Reding clock-names = "div-clk"; 3037bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 30440cc83b3SThierry Reding reset-names = "i2c"; 30540cc83b3SThierry Reding status = "disabled"; 30640cc83b3SThierry Reding }; 30740cc83b3SThierry Reding 30840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 30940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 31040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 31140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 31240cc83b3SThierry Reding #address-cells = <1>; 31340cc83b3SThierry Reding #size-cells = <0>; 314c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 31540cc83b3SThierry Reding clock-names = "div-clk"; 3167bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 31740cc83b3SThierry Reding reset-names = "i2c"; 31840cc83b3SThierry Reding status = "disabled"; 31940cc83b3SThierry Reding }; 32040cc83b3SThierry Reding 321a7a77e2eSThierry Reding uartc: serial@c280000 { 322a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 323a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 324a7a77e2eSThierry Reding reg-shift = <2>; 325a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 326c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 327a7a77e2eSThierry Reding clock-names = "serial"; 3287bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 329a7a77e2eSThierry Reding reset-names = "serial"; 330a7a77e2eSThierry Reding status = "disabled"; 331a7a77e2eSThierry Reding }; 332a7a77e2eSThierry Reding 333a7a77e2eSThierry Reding uartg: serial@c290000 { 334a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 335a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 336a7a77e2eSThierry Reding reg-shift = <2>; 337a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 338c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 339a7a77e2eSThierry Reding clock-names = "serial"; 3407bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 341a7a77e2eSThierry Reding reset-names = "serial"; 342a7a77e2eSThierry Reding status = "disabled"; 343a7a77e2eSThierry Reding }; 344a7a77e2eSThierry Reding 345fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 346fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 347fc4bb754SThierry Reding reg-names = "security", "gpio"; 348fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 349fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 350fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 351fc4bb754SThierry Reding gpio-controller; 352fc4bb754SThierry Reding #gpio-cells = <2>; 353fc4bb754SThierry Reding interrupt-controller; 354fc4bb754SThierry Reding #interrupt-cells = <2>; 355fc4bb754SThierry Reding }; 356fc4bb754SThierry Reding 35773bf90d4SThierry Reding pmc@c360000 { 35873bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 35973bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 36073bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 36173bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 36273bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 36373bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 36473bf90d4SThierry Reding }; 36573bf90d4SThierry Reding 3667b7ef494SMikko Perttunen ccplex@e000000 { 3677b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 3687b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 3697b7ef494SMikko Perttunen 3707b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 3717b7ef494SMikko Perttunen }; 3727b7ef494SMikko Perttunen 373f8973cf4SManikanta Maddireddy pcie@10003000 { 374f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 375f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 376f8973cf4SManikanta Maddireddy device_type = "pci"; 377f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 378f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 379f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 380f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 381f8973cf4SManikanta Maddireddy 382f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 383f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 384f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 385f8973cf4SManikanta Maddireddy 386f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 387f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 388f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 389f8973cf4SManikanta Maddireddy 390f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 391f8973cf4SManikanta Maddireddy #address-cells = <3>; 392f8973cf4SManikanta Maddireddy #size-cells = <2>; 393f8973cf4SManikanta Maddireddy 394f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 395f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 396f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 397f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 398f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 399f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 400f8973cf4SManikanta Maddireddy 401f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 402f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 403f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 404f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 405f8973cf4SManikanta Maddireddy 406f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 407f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 408f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 409f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 410f8973cf4SManikanta Maddireddy 411f8973cf4SManikanta Maddireddy status = "disabled"; 412f8973cf4SManikanta Maddireddy 413f8973cf4SManikanta Maddireddy pci@1,0 { 414f8973cf4SManikanta Maddireddy device_type = "pci"; 415f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 416f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 417f8973cf4SManikanta Maddireddy status = "disabled"; 418f8973cf4SManikanta Maddireddy 419f8973cf4SManikanta Maddireddy #address-cells = <3>; 420f8973cf4SManikanta Maddireddy #size-cells = <2>; 421f8973cf4SManikanta Maddireddy ranges; 422f8973cf4SManikanta Maddireddy 423f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 424f8973cf4SManikanta Maddireddy }; 425f8973cf4SManikanta Maddireddy 426f8973cf4SManikanta Maddireddy pci@2,0 { 427f8973cf4SManikanta Maddireddy device_type = "pci"; 428f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 429f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 430f8973cf4SManikanta Maddireddy status = "disabled"; 431f8973cf4SManikanta Maddireddy 432f8973cf4SManikanta Maddireddy #address-cells = <3>; 433f8973cf4SManikanta Maddireddy #size-cells = <2>; 434f8973cf4SManikanta Maddireddy ranges; 435f8973cf4SManikanta Maddireddy 436f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 437f8973cf4SManikanta Maddireddy }; 438f8973cf4SManikanta Maddireddy 439f8973cf4SManikanta Maddireddy pci@3,0 { 440f8973cf4SManikanta Maddireddy device_type = "pci"; 441f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 442f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 443f8973cf4SManikanta Maddireddy status = "disabled"; 444f8973cf4SManikanta Maddireddy 445f8973cf4SManikanta Maddireddy #address-cells = <3>; 446f8973cf4SManikanta Maddireddy #size-cells = <2>; 447f8973cf4SManikanta Maddireddy ranges; 448f8973cf4SManikanta Maddireddy 449f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 450f8973cf4SManikanta Maddireddy }; 451f8973cf4SManikanta Maddireddy }; 452f8973cf4SManikanta Maddireddy 4535524c61fSMikko Perttunen host1x@13e00000 { 4545524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 4555524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 4565524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 4575524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 4585524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 4595524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4605524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 4615524c61fSMikko Perttunen clock-names = "host1x"; 4625524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 4635524c61fSMikko Perttunen reset-names = "host1x"; 4645524c61fSMikko Perttunen 4655524c61fSMikko Perttunen #address-cells = <1>; 4665524c61fSMikko Perttunen #size-cells = <1>; 4675524c61fSMikko Perttunen 4685524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 469effc4b44SMikko Perttunen 470effc4b44SMikko Perttunen vic@15340000 { 471effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 472effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 473effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 474effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 475effc4b44SMikko Perttunen clock-names = "vic"; 476effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 477effc4b44SMikko Perttunen reset-names = "vic"; 478effc4b44SMikko Perttunen 479effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 480effc4b44SMikko Perttunen }; 4815524c61fSMikko Perttunen }; 4825524c61fSMikko Perttunen 483dfd7a384SAlexandre Courbot gpu@17000000 { 484dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 485dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 486dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 487dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 488dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 489dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 490dfd7a384SAlexandre Courbot 491dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 492dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 493dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 494dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 495dfd7a384SAlexandre Courbot reset-names = "gpu"; 496dfd7a384SAlexandre Courbot status = "disabled"; 497dfd7a384SAlexandre Courbot 498dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 499dfd7a384SAlexandre Courbot }; 500dfd7a384SAlexandre Courbot 50139cb62cbSJoseph Lo sysram@30000000 { 50239cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 50339cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 50439cb62cbSJoseph Lo #address-cells = <2>; 50539cb62cbSJoseph Lo #size-cells = <2>; 50639cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 50739cb62cbSJoseph Lo 50839cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 50939cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 51039cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 51139cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 51239cb62cbSJoseph Lo pool; 51339cb62cbSJoseph Lo }; 51439cb62cbSJoseph Lo 51539cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 51639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 51739cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 51839cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 51939cb62cbSJoseph Lo pool; 52039cb62cbSJoseph Lo }; 52139cb62cbSJoseph Lo }; 52239cb62cbSJoseph Lo 523cd6fe32eSThierry Reding cpus { 524cd6fe32eSThierry Reding #address-cells = <1>; 525cd6fe32eSThierry Reding #size-cells = <0>; 526cd6fe32eSThierry Reding 527cd6fe32eSThierry Reding cpu@0 { 528cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 529cd6fe32eSThierry Reding device_type = "cpu"; 530cd6fe32eSThierry Reding reg = <0x000>; 531cd6fe32eSThierry Reding }; 532cd6fe32eSThierry Reding 533cd6fe32eSThierry Reding cpu@1 { 534cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 535cd6fe32eSThierry Reding device_type = "cpu"; 536cd6fe32eSThierry Reding reg = <0x001>; 537cd6fe32eSThierry Reding }; 538cd6fe32eSThierry Reding 539cd6fe32eSThierry Reding cpu@2 { 540cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 541cd6fe32eSThierry Reding device_type = "cpu"; 542cd6fe32eSThierry Reding reg = <0x100>; 543cd6fe32eSThierry Reding }; 544cd6fe32eSThierry Reding 545cd6fe32eSThierry Reding cpu@3 { 546cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 547cd6fe32eSThierry Reding device_type = "cpu"; 548cd6fe32eSThierry Reding reg = <0x101>; 549cd6fe32eSThierry Reding }; 550cd6fe32eSThierry Reding 551cd6fe32eSThierry Reding cpu@4 { 552cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 553cd6fe32eSThierry Reding device_type = "cpu"; 554cd6fe32eSThierry Reding reg = <0x102>; 555cd6fe32eSThierry Reding }; 556cd6fe32eSThierry Reding 557cd6fe32eSThierry Reding cpu@5 { 558cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 559cd6fe32eSThierry Reding device_type = "cpu"; 560cd6fe32eSThierry Reding reg = <0x103>; 561cd6fe32eSThierry Reding }; 562cd6fe32eSThierry Reding }; 563cd6fe32eSThierry Reding 56439cb62cbSJoseph Lo bpmp: bpmp { 56539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 5665edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5675edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 56839cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 56939cb62cbSJoseph Lo #clock-cells = <1>; 57039cb62cbSJoseph Lo #reset-cells = <1>; 571dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 57239cb62cbSJoseph Lo 57339cb62cbSJoseph Lo bpmp_i2c: i2c { 57439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 57539cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 57639cb62cbSJoseph Lo #address-cells = <1>; 57739cb62cbSJoseph Lo #size-cells = <0>; 57839cb62cbSJoseph Lo status = "disabled"; 57939cb62cbSJoseph Lo }; 58015274c23SMikko Perttunen 58115274c23SMikko Perttunen bpmp_thermal: thermal { 58215274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 58315274c23SMikko Perttunen #thermal-sensor-cells = <1>; 58415274c23SMikko Perttunen }; 58515274c23SMikko Perttunen }; 58615274c23SMikko Perttunen 58715274c23SMikko Perttunen thermal-zones { 58815274c23SMikko Perttunen a57 { 58915274c23SMikko Perttunen polling-delay = <0>; 59015274c23SMikko Perttunen polling-delay-passive = <1000>; 59115274c23SMikko Perttunen 59215274c23SMikko Perttunen thermal-sensors = 59315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 59415274c23SMikko Perttunen 59515274c23SMikko Perttunen trips { 59615274c23SMikko Perttunen critical { 59715274c23SMikko Perttunen temperature = <101000>; 59815274c23SMikko Perttunen hysteresis = <0>; 59915274c23SMikko Perttunen type = "critical"; 60015274c23SMikko Perttunen }; 60115274c23SMikko Perttunen }; 60215274c23SMikko Perttunen 60315274c23SMikko Perttunen cooling-maps { 60415274c23SMikko Perttunen }; 60515274c23SMikko Perttunen }; 60615274c23SMikko Perttunen 60715274c23SMikko Perttunen denver { 60815274c23SMikko Perttunen polling-delay = <0>; 60915274c23SMikko Perttunen polling-delay-passive = <1000>; 61015274c23SMikko Perttunen 61115274c23SMikko Perttunen thermal-sensors = 61215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 61315274c23SMikko Perttunen 61415274c23SMikko Perttunen trips { 61515274c23SMikko Perttunen critical { 61615274c23SMikko Perttunen temperature = <101000>; 61715274c23SMikko Perttunen hysteresis = <0>; 61815274c23SMikko Perttunen type = "critical"; 61915274c23SMikko Perttunen }; 62015274c23SMikko Perttunen }; 62115274c23SMikko Perttunen 62215274c23SMikko Perttunen cooling-maps { 62315274c23SMikko Perttunen }; 62415274c23SMikko Perttunen }; 62515274c23SMikko Perttunen 62615274c23SMikko Perttunen gpu { 62715274c23SMikko Perttunen polling-delay = <0>; 62815274c23SMikko Perttunen polling-delay-passive = <1000>; 62915274c23SMikko Perttunen 63015274c23SMikko Perttunen thermal-sensors = 63115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 63215274c23SMikko Perttunen 63315274c23SMikko Perttunen trips { 63415274c23SMikko Perttunen critical { 63515274c23SMikko Perttunen temperature = <101000>; 63615274c23SMikko Perttunen hysteresis = <0>; 63715274c23SMikko Perttunen type = "critical"; 63815274c23SMikko Perttunen }; 63915274c23SMikko Perttunen }; 64015274c23SMikko Perttunen 64115274c23SMikko Perttunen cooling-maps { 64215274c23SMikko Perttunen }; 64315274c23SMikko Perttunen }; 64415274c23SMikko Perttunen 64515274c23SMikko Perttunen pll { 64615274c23SMikko Perttunen polling-delay = <0>; 64715274c23SMikko Perttunen polling-delay-passive = <1000>; 64815274c23SMikko Perttunen 64915274c23SMikko Perttunen thermal-sensors = 65015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 65115274c23SMikko Perttunen 65215274c23SMikko Perttunen trips { 65315274c23SMikko Perttunen critical { 65415274c23SMikko Perttunen temperature = <101000>; 65515274c23SMikko Perttunen hysteresis = <0>; 65615274c23SMikko Perttunen type = "critical"; 65715274c23SMikko Perttunen }; 65815274c23SMikko Perttunen }; 65915274c23SMikko Perttunen 66015274c23SMikko Perttunen cooling-maps { 66115274c23SMikko Perttunen }; 66215274c23SMikko Perttunen }; 66315274c23SMikko Perttunen 66415274c23SMikko Perttunen always_on { 66515274c23SMikko Perttunen polling-delay = <0>; 66615274c23SMikko Perttunen polling-delay-passive = <1000>; 66715274c23SMikko Perttunen 66815274c23SMikko Perttunen thermal-sensors = 66915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 67015274c23SMikko Perttunen 67115274c23SMikko Perttunen trips { 67215274c23SMikko Perttunen critical { 67315274c23SMikko Perttunen temperature = <101000>; 67415274c23SMikko Perttunen hysteresis = <0>; 67515274c23SMikko Perttunen type = "critical"; 67615274c23SMikko Perttunen }; 67715274c23SMikko Perttunen }; 67815274c23SMikko Perttunen 67915274c23SMikko Perttunen cooling-maps { 68015274c23SMikko Perttunen }; 68115274c23SMikko Perttunen }; 68239cb62cbSJoseph Lo }; 68339cb62cbSJoseph Lo 68439cb62cbSJoseph Lo timer { 68539cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 68639cb62cbSJoseph Lo interrupts = <GIC_PPI 13 68739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68839cb62cbSJoseph Lo <GIC_PPI 14 68939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69039cb62cbSJoseph Lo <GIC_PPI 11 69139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69239cb62cbSJoseph Lo <GIC_PPI 10 69339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 69439cb62cbSJoseph Lo interrupt-parent = <&gic>; 69539cb62cbSJoseph Lo }; 69639cb62cbSJoseph Lo}; 697