1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 640caafbdeSThierry Reding status = "disabled"; 650caafbdeSThierry Reding 660caafbdeSThierry Reding snps,write-requests = <1>; 670caafbdeSThierry Reding snps,read-requests = <3>; 680caafbdeSThierry Reding snps,burst-map = <0x7>; 690caafbdeSThierry Reding snps,txpbl = <32>; 700caafbdeSThierry Reding snps,rxpbl = <8>; 710caafbdeSThierry Reding }; 720caafbdeSThierry Reding 73d25a3bf1SThierry Reding memory-controller@2c00000 { 74d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 75d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 76d25a3bf1SThierry Reding status = "disabled"; 77d25a3bf1SThierry Reding }; 78d25a3bf1SThierry Reding 7939cb62cbSJoseph Lo uarta: serial@3100000 { 8039cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8139cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8239cb62cbSJoseph Lo reg-shift = <2>; 8339cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 84c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 85a7a77e2eSThierry Reding clock-names = "serial"; 867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 87a7a77e2eSThierry Reding reset-names = "serial"; 88a7a77e2eSThierry Reding status = "disabled"; 89a7a77e2eSThierry Reding }; 90a7a77e2eSThierry Reding 91a7a77e2eSThierry Reding uartb: serial@3110000 { 92a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 93a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 94a7a77e2eSThierry Reding reg-shift = <2>; 95a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 96c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 97a7a77e2eSThierry Reding clock-names = "serial"; 987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 99a7a77e2eSThierry Reding reset-names = "serial"; 100a7a77e2eSThierry Reding status = "disabled"; 101a7a77e2eSThierry Reding }; 102a7a77e2eSThierry Reding 103a7a77e2eSThierry Reding uartd: serial@3130000 { 104a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 105a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 106a7a77e2eSThierry Reding reg-shift = <2>; 107a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 108c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 109a7a77e2eSThierry Reding clock-names = "serial"; 1107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 111a7a77e2eSThierry Reding reset-names = "serial"; 112a7a77e2eSThierry Reding status = "disabled"; 113a7a77e2eSThierry Reding }; 114a7a77e2eSThierry Reding 115a7a77e2eSThierry Reding uarte: serial@3140000 { 116a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 117a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 118a7a77e2eSThierry Reding reg-shift = <2>; 119a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 120c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 121a7a77e2eSThierry Reding clock-names = "serial"; 1227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 123a7a77e2eSThierry Reding reset-names = "serial"; 124a7a77e2eSThierry Reding status = "disabled"; 125a7a77e2eSThierry Reding }; 126a7a77e2eSThierry Reding 127a7a77e2eSThierry Reding uartf: serial@3150000 { 128a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 129a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 130a7a77e2eSThierry Reding reg-shift = <2>; 131a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 132c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 133a7a77e2eSThierry Reding clock-names = "serial"; 1347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 135a7a77e2eSThierry Reding reset-names = "serial"; 13639cb62cbSJoseph Lo status = "disabled"; 13739cb62cbSJoseph Lo }; 13839cb62cbSJoseph Lo 13940cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 140250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 14140cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14240cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14340cc83b3SThierry Reding #address-cells = <1>; 14440cc83b3SThierry Reding #size-cells = <0>; 145c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14640cc83b3SThierry Reding clock-names = "div-clk"; 1477bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14840cc83b3SThierry Reding reset-names = "i2c"; 14940cc83b3SThierry Reding status = "disabled"; 15040cc83b3SThierry Reding }; 15140cc83b3SThierry Reding 15240cc83b3SThierry Reding cam_i2c: i2c@3180000 { 153250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 15440cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15540cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15640cc83b3SThierry Reding #address-cells = <1>; 15740cc83b3SThierry Reding #size-cells = <0>; 158c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15940cc83b3SThierry Reding clock-names = "div-clk"; 1607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16140cc83b3SThierry Reding reset-names = "i2c"; 16240cc83b3SThierry Reding status = "disabled"; 16340cc83b3SThierry Reding }; 16440cc83b3SThierry Reding 16540cc83b3SThierry Reding /* shares pads with dpaux1 */ 16640cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 167250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 16840cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16940cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 17040cc83b3SThierry Reding #address-cells = <1>; 17140cc83b3SThierry Reding #size-cells = <0>; 172c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17340cc83b3SThierry Reding clock-names = "div-clk"; 1747bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17540cc83b3SThierry Reding reset-names = "i2c"; 176846137c6SThierry Reding pinctrl-names = "default", "idle"; 177846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 178846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 17940cc83b3SThierry Reding status = "disabled"; 18040cc83b3SThierry Reding }; 18140cc83b3SThierry Reding 18240cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 18340cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 184250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 18540cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18640cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18740cc83b3SThierry Reding #address-cells = <1>; 18840cc83b3SThierry Reding #size-cells = <0>; 189c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 19040cc83b3SThierry Reding clock-names = "div-clk"; 1917bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 19240cc83b3SThierry Reding reset-names = "i2c"; 19340cc83b3SThierry Reding status = "disabled"; 19440cc83b3SThierry Reding }; 19540cc83b3SThierry Reding 19640cc83b3SThierry Reding /* shares pads with dpaux0 */ 19740cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 198250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 19940cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 20040cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 20140cc83b3SThierry Reding #address-cells = <1>; 20240cc83b3SThierry Reding #size-cells = <0>; 203c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20440cc83b3SThierry Reding clock-names = "div-clk"; 2057bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20640cc83b3SThierry Reding reset-names = "i2c"; 207846137c6SThierry Reding pinctrl-names = "default", "idle"; 208846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 209846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 21040cc83b3SThierry Reding status = "disabled"; 21140cc83b3SThierry Reding }; 21240cc83b3SThierry Reding 21340cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 214250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 21540cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 21640cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21740cc83b3SThierry Reding #address-cells = <1>; 21840cc83b3SThierry Reding #size-cells = <0>; 219c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 22040cc83b3SThierry Reding clock-names = "div-clk"; 2217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 22240cc83b3SThierry Reding reset-names = "i2c"; 22340cc83b3SThierry Reding status = "disabled"; 22440cc83b3SThierry Reding }; 22540cc83b3SThierry Reding 22640cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 227250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 22840cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22940cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 23040cc83b3SThierry Reding #address-cells = <1>; 23140cc83b3SThierry Reding #size-cells = <0>; 232c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 23340cc83b3SThierry Reding clock-names = "div-clk"; 2347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 23540cc83b3SThierry Reding reset-names = "i2c"; 23640cc83b3SThierry Reding status = "disabled"; 23740cc83b3SThierry Reding }; 23840cc83b3SThierry Reding 23999425dfdSThierry Reding sdmmc1: sdhci@3400000 { 24099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24199425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 24299425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 243c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 24499425dfdSThierry Reding clock-names = "sdhci"; 2457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 24699425dfdSThierry Reding reset-names = "sdhci"; 2478589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 24824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 25024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 25141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 25241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 25341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 25441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 25541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 25641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 2576f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2586f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 25998a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 26098a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 26198a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 26299425dfdSThierry Reding status = "disabled"; 26399425dfdSThierry Reding }; 26499425dfdSThierry Reding 26599425dfdSThierry Reding sdmmc2: sdhci@3420000 { 26699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 26799425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 26899425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 269c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 27099425dfdSThierry Reding clock-names = "sdhci"; 2717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 27299425dfdSThierry Reding reset-names = "sdhci"; 2738589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 27424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 27524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 27624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 27741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 27841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 27941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 28041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 2816f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 2826f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 28399425dfdSThierry Reding status = "disabled"; 28499425dfdSThierry Reding }; 28599425dfdSThierry Reding 28699425dfdSThierry Reding sdmmc3: sdhci@3440000 { 28799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 28899425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 28999425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 290c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 29199425dfdSThierry Reding clock-names = "sdhci"; 2927bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 29399425dfdSThierry Reding reset-names = "sdhci"; 2948589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 29524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 29624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 29724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 29841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 29941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 30041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 30141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 30241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 30341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3046f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3056f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 30699425dfdSThierry Reding status = "disabled"; 30799425dfdSThierry Reding }; 30899425dfdSThierry Reding 30999425dfdSThierry Reding sdmmc4: sdhci@3460000 { 31099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 31199425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 31299425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 313c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 31499425dfdSThierry Reding clock-names = "sdhci"; 31598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 31698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 31798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 3187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 31999425dfdSThierry Reding reset-names = "sdhci"; 3208589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 32141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 32241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 32341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 32441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3254e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3264e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 327e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 328e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 32922248e91SAapo Vienamo nvidia,dqs-trim = <63>; 330207f60baSAapo Vienamo mmc-hs400-1_8v; 331c4307836SSowjanya Komatineni supports-cqe; 33299425dfdSThierry Reding status = "disabled"; 33399425dfdSThierry Reding }; 33499425dfdSThierry Reding 335b066a310SThierry Reding hda@3510000 { 336b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 337b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 338b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 339b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 340b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 341b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 342b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 343b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 344b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 345b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 346b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 347b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 348dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 349b066a310SThierry Reding status = "disabled"; 350b066a310SThierry Reding }; 351b066a310SThierry Reding 3528bfde518SThierry Reding padctl: padctl@3520000 { 3538bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 3548bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 3558bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 3568bfde518SThierry Reding reg-names = "padctl", "ao"; 3578bfde518SThierry Reding 3588bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 3598bfde518SThierry Reding reset-names = "padctl"; 3608bfde518SThierry Reding 3618bfde518SThierry Reding status = "disabled"; 3628bfde518SThierry Reding 3638bfde518SThierry Reding pads { 3648bfde518SThierry Reding usb2 { 3658bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 3668bfde518SThierry Reding clock-names = "trk"; 3678bfde518SThierry Reding status = "disabled"; 3688bfde518SThierry Reding 3698bfde518SThierry Reding lanes { 3708bfde518SThierry Reding usb2-0 { 3718bfde518SThierry Reding status = "disabled"; 3728bfde518SThierry Reding #phy-cells = <0>; 3738bfde518SThierry Reding }; 3748bfde518SThierry Reding 3758bfde518SThierry Reding usb2-1 { 3768bfde518SThierry Reding status = "disabled"; 3778bfde518SThierry Reding #phy-cells = <0>; 3788bfde518SThierry Reding }; 3798bfde518SThierry Reding 3808bfde518SThierry Reding usb2-2 { 3818bfde518SThierry Reding status = "disabled"; 3828bfde518SThierry Reding #phy-cells = <0>; 3838bfde518SThierry Reding }; 3848bfde518SThierry Reding }; 3858bfde518SThierry Reding }; 3868bfde518SThierry Reding 3878bfde518SThierry Reding hsic { 3888bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 3898bfde518SThierry Reding clock-names = "trk"; 3908bfde518SThierry Reding status = "disabled"; 3918bfde518SThierry Reding 3928bfde518SThierry Reding lanes { 3938bfde518SThierry Reding hsic-0 { 3948bfde518SThierry Reding status = "disabled"; 3958bfde518SThierry Reding #phy-cells = <0>; 3968bfde518SThierry Reding }; 3978bfde518SThierry Reding }; 3988bfde518SThierry Reding }; 3998bfde518SThierry Reding 4008bfde518SThierry Reding usb3 { 4018bfde518SThierry Reding status = "disabled"; 4028bfde518SThierry Reding 4038bfde518SThierry Reding lanes { 4048bfde518SThierry Reding usb3-0 { 4058bfde518SThierry Reding status = "disabled"; 4068bfde518SThierry Reding #phy-cells = <0>; 4078bfde518SThierry Reding }; 4088bfde518SThierry Reding 4098bfde518SThierry Reding usb3-1 { 4108bfde518SThierry Reding status = "disabled"; 4118bfde518SThierry Reding #phy-cells = <0>; 4128bfde518SThierry Reding }; 4138bfde518SThierry Reding 4148bfde518SThierry Reding usb3-2 { 4158bfde518SThierry Reding status = "disabled"; 4168bfde518SThierry Reding #phy-cells = <0>; 4178bfde518SThierry Reding }; 4188bfde518SThierry Reding }; 4198bfde518SThierry Reding }; 4208bfde518SThierry Reding }; 4218bfde518SThierry Reding 4228bfde518SThierry Reding ports { 4238bfde518SThierry Reding usb2-0 { 4248bfde518SThierry Reding status = "disabled"; 4258bfde518SThierry Reding }; 4268bfde518SThierry Reding 4278bfde518SThierry Reding usb2-1 { 4288bfde518SThierry Reding status = "disabled"; 4298bfde518SThierry Reding }; 4308bfde518SThierry Reding 4318bfde518SThierry Reding usb2-2 { 4328bfde518SThierry Reding status = "disabled"; 4338bfde518SThierry Reding }; 4348bfde518SThierry Reding 4358bfde518SThierry Reding hsic-0 { 4368bfde518SThierry Reding status = "disabled"; 4378bfde518SThierry Reding }; 4388bfde518SThierry Reding 4398bfde518SThierry Reding usb3-0 { 4408bfde518SThierry Reding status = "disabled"; 4418bfde518SThierry Reding }; 4428bfde518SThierry Reding 4438bfde518SThierry Reding usb3-1 { 4448bfde518SThierry Reding status = "disabled"; 4458bfde518SThierry Reding }; 4468bfde518SThierry Reding 4478bfde518SThierry Reding usb3-2 { 4488bfde518SThierry Reding status = "disabled"; 4498bfde518SThierry Reding }; 4508bfde518SThierry Reding }; 4518bfde518SThierry Reding }; 4528bfde518SThierry Reding 4538bfde518SThierry Reding usb@3530000 { 4548bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 4558bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 4568bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 4578bfde518SThierry Reding reg-names = "hcd", "fpci"; 4588bfde518SThierry Reding 4598bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4608bfde518SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 4618bfde518SThierry Reding <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 4628bfde518SThierry Reding 4638bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 4648bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 4658bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 4668bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 4678bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 4688bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 4698bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 4708bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 4718bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 4728bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 4738bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 4748bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 4758bfde518SThierry Reding 4768bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 4778bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 4788bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 4798bfde518SThierry Reding nvidia,xusb-padctl = <&padctl>; 4808bfde518SThierry Reding 4818bfde518SThierry Reding status = "disabled"; 4828bfde518SThierry Reding 4838bfde518SThierry Reding #address-cells = <1>; 4848bfde518SThierry Reding #size-cells = <0>; 4858bfde518SThierry Reding }; 4868bfde518SThierry Reding 48785593b75SThierry Reding fuse@3820000 { 48885593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 48985593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 49085593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 49185593b75SThierry Reding clock-names = "fuse"; 49285593b75SThierry Reding }; 49385593b75SThierry Reding 49439cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 49539cb62cbSJoseph Lo compatible = "arm,gic-400"; 49639cb62cbSJoseph Lo #interrupt-cells = <3>; 49739cb62cbSJoseph Lo interrupt-controller; 49839cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 49939cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 50039cb62cbSJoseph Lo interrupts = <GIC_PPI 9 50139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 50239cb62cbSJoseph Lo interrupt-parent = <&gic>; 50339cb62cbSJoseph Lo }; 50439cb62cbSJoseph Lo 50597cf683cSThierry Reding cec@3960000 { 50697cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 50797cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 50897cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 50997cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 51097cf683cSThierry Reding clock-names = "cec"; 51197cf683cSThierry Reding status = "disabled"; 51297cf683cSThierry Reding }; 51397cf683cSThierry Reding 51439cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 51539cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 51639cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 51739cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 51839cb62cbSJoseph Lo interrupt-names = "doorbell"; 51939cb62cbSJoseph Lo #mbox-cells = <2>; 52039cb62cbSJoseph Lo status = "disabled"; 52139cb62cbSJoseph Lo }; 52239cb62cbSJoseph Lo 52340cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 524250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 52540cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 52640cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 52740cc83b3SThierry Reding #address-cells = <1>; 52840cc83b3SThierry Reding #size-cells = <0>; 529c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 53040cc83b3SThierry Reding clock-names = "div-clk"; 5317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 53240cc83b3SThierry Reding reset-names = "i2c"; 53340cc83b3SThierry Reding status = "disabled"; 53440cc83b3SThierry Reding }; 53540cc83b3SThierry Reding 53640cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 537250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 53840cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 53940cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 54040cc83b3SThierry Reding #address-cells = <1>; 54140cc83b3SThierry Reding #size-cells = <0>; 542c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 54340cc83b3SThierry Reding clock-names = "div-clk"; 5447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 54540cc83b3SThierry Reding reset-names = "i2c"; 54640cc83b3SThierry Reding status = "disabled"; 54740cc83b3SThierry Reding }; 54840cc83b3SThierry Reding 549a7a77e2eSThierry Reding uartc: serial@c280000 { 550a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 551a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 552a7a77e2eSThierry Reding reg-shift = <2>; 553a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 554c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 555a7a77e2eSThierry Reding clock-names = "serial"; 5567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 557a7a77e2eSThierry Reding reset-names = "serial"; 558a7a77e2eSThierry Reding status = "disabled"; 559a7a77e2eSThierry Reding }; 560a7a77e2eSThierry Reding 561a7a77e2eSThierry Reding uartg: serial@c290000 { 562a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 563a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 564a7a77e2eSThierry Reding reg-shift = <2>; 565a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 566c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 567a7a77e2eSThierry Reding clock-names = "serial"; 5687bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 569a7a77e2eSThierry Reding reset-names = "serial"; 570a7a77e2eSThierry Reding status = "disabled"; 571a7a77e2eSThierry Reding }; 572a7a77e2eSThierry Reding 5739733a251SThierry Reding rtc: rtc@c2a0000 { 5749733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 5759733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 5769733a251SThierry Reding interrupt-parent = <&pmc>; 5779733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 5789733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 5799733a251SThierry Reding clock-names = "rtc"; 5809733a251SThierry Reding status = "disabled"; 5819733a251SThierry Reding }; 5829733a251SThierry Reding 583fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 584fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 585fc4bb754SThierry Reding reg-names = "security", "gpio"; 586fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 587fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 588fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 589fc4bb754SThierry Reding gpio-controller; 590fc4bb754SThierry Reding #gpio-cells = <2>; 591fc4bb754SThierry Reding interrupt-controller; 592fc4bb754SThierry Reding #interrupt-cells = <2>; 593fc4bb754SThierry Reding }; 594fc4bb754SThierry Reding 59532e66e46SThierry Reding pmc: pmc@c360000 { 59673bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 59773bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 59873bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 59973bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 60073bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 60173bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 60224005fd1SAapo Vienamo 60332e66e46SThierry Reding #interrupt-cells = <2>; 60432e66e46SThierry Reding interrupt-controller; 60532e66e46SThierry Reding 60624005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 60724005fd1SAapo Vienamo pins = "sdmmc1-hv"; 60824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 60924005fd1SAapo Vienamo }; 61024005fd1SAapo Vienamo 61124005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 61224005fd1SAapo Vienamo pins = "sdmmc1-hv"; 61324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 61424005fd1SAapo Vienamo }; 61524005fd1SAapo Vienamo 61624005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 61724005fd1SAapo Vienamo pins = "sdmmc2-hv"; 61824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 61924005fd1SAapo Vienamo }; 62024005fd1SAapo Vienamo 62124005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 62224005fd1SAapo Vienamo pins = "sdmmc2-hv"; 62324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 62424005fd1SAapo Vienamo }; 62524005fd1SAapo Vienamo 62624005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 62724005fd1SAapo Vienamo pins = "sdmmc3-hv"; 62824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 62924005fd1SAapo Vienamo }; 63024005fd1SAapo Vienamo 63124005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 63224005fd1SAapo Vienamo pins = "sdmmc3-hv"; 63324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 63424005fd1SAapo Vienamo }; 63573bf90d4SThierry Reding }; 63673bf90d4SThierry Reding 6377b7ef494SMikko Perttunen ccplex@e000000 { 6387b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 6397b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 6407b7ef494SMikko Perttunen 6417b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 6427b7ef494SMikko Perttunen }; 6437b7ef494SMikko Perttunen 644f8973cf4SManikanta Maddireddy pcie@10003000 { 645f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 646f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 647f8973cf4SManikanta Maddireddy device_type = "pci"; 648f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 649f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 650f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 651f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 652f8973cf4SManikanta Maddireddy 653f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 654f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 655f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 656f8973cf4SManikanta Maddireddy 657f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 658f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 659f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 660f8973cf4SManikanta Maddireddy 661f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 662f8973cf4SManikanta Maddireddy #address-cells = <3>; 663f8973cf4SManikanta Maddireddy #size-cells = <2>; 664f8973cf4SManikanta Maddireddy 665f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 666f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 667f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 668f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 669f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 670f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 671f8973cf4SManikanta Maddireddy 672f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 673f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 674f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 675f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 676f8973cf4SManikanta Maddireddy 677f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 678f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 679f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 680f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 681f8973cf4SManikanta Maddireddy 682f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 683f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 684f2a465e7SThierry Reding iommu-map-mask = <0x0>; 685f2a465e7SThierry Reding 686f8973cf4SManikanta Maddireddy status = "disabled"; 687f8973cf4SManikanta Maddireddy 688f8973cf4SManikanta Maddireddy pci@1,0 { 689f8973cf4SManikanta Maddireddy device_type = "pci"; 690f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 691f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 692f8973cf4SManikanta Maddireddy status = "disabled"; 693f8973cf4SManikanta Maddireddy 694f8973cf4SManikanta Maddireddy #address-cells = <3>; 695f8973cf4SManikanta Maddireddy #size-cells = <2>; 696f8973cf4SManikanta Maddireddy ranges; 697f8973cf4SManikanta Maddireddy 698f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 699f8973cf4SManikanta Maddireddy }; 700f8973cf4SManikanta Maddireddy 701f8973cf4SManikanta Maddireddy pci@2,0 { 702f8973cf4SManikanta Maddireddy device_type = "pci"; 703f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 704f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 705f8973cf4SManikanta Maddireddy status = "disabled"; 706f8973cf4SManikanta Maddireddy 707f8973cf4SManikanta Maddireddy #address-cells = <3>; 708f8973cf4SManikanta Maddireddy #size-cells = <2>; 709f8973cf4SManikanta Maddireddy ranges; 710f8973cf4SManikanta Maddireddy 711f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 712f8973cf4SManikanta Maddireddy }; 713f8973cf4SManikanta Maddireddy 714f8973cf4SManikanta Maddireddy pci@3,0 { 715f8973cf4SManikanta Maddireddy device_type = "pci"; 716f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 717f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 718f8973cf4SManikanta Maddireddy status = "disabled"; 719f8973cf4SManikanta Maddireddy 720f8973cf4SManikanta Maddireddy #address-cells = <3>; 721f8973cf4SManikanta Maddireddy #size-cells = <2>; 722f8973cf4SManikanta Maddireddy ranges; 723f8973cf4SManikanta Maddireddy 724f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 725f8973cf4SManikanta Maddireddy }; 726f8973cf4SManikanta Maddireddy }; 727f8973cf4SManikanta Maddireddy 728b30a8e61SThierry Reding smmu: iommu@12000000 { 729b30a8e61SThierry Reding compatible = "arm,mmu-500"; 730b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 731b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 732b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 733b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 734b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 735b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 736b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 737b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 738b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 739b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 740b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 741b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 742b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 743b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 744b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 745b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 746b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 747b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 748b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 749b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 750b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 751b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 752b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 753b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 754b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 755b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 756b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 757b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 758b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 759b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 760b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 761b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 762b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 763b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 764b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 765b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 766b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 767b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 768b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 769b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 770b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 771b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 772b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 773b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 774b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 775b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 776b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 777b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 778b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 779b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 780b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 781b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 782b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 783b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 784b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 785b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 786b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 787b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 788b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 789b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 790b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 791b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 792b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 793b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 794b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 795b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 796b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 797b30a8e61SThierry Reding #global-interrupts = <1>; 798b30a8e61SThierry Reding #iommu-cells = <1>; 799b30a8e61SThierry Reding }; 800b30a8e61SThierry Reding 8015524c61fSMikko Perttunen host1x@13e00000 { 8025524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 8035524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 8045524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 8055524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 8065524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 8075524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 8085524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 8095524c61fSMikko Perttunen clock-names = "host1x"; 8105524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 8115524c61fSMikko Perttunen reset-names = "host1x"; 8125524c61fSMikko Perttunen 8135524c61fSMikko Perttunen #address-cells = <1>; 8145524c61fSMikko Perttunen #size-cells = <1>; 8155524c61fSMikko Perttunen 8165524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 817c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 818c2599da7SThierry Reding 819c2599da7SThierry Reding dpaux1: dpaux@15040000 { 820c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 821c2599da7SThierry Reding reg = <0x15040000 0x10000>; 822c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 823c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 824c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 825c2599da7SThierry Reding clock-names = "dpaux", "parent"; 826c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 827c2599da7SThierry Reding reset-names = "dpaux"; 828c2599da7SThierry Reding status = "disabled"; 829c2599da7SThierry Reding 830c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 831c2599da7SThierry Reding 832c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 833c2599da7SThierry Reding groups = "dpaux-io"; 834c2599da7SThierry Reding function = "aux"; 835c2599da7SThierry Reding }; 836c2599da7SThierry Reding 837c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 838c2599da7SThierry Reding groups = "dpaux-io"; 839c2599da7SThierry Reding function = "i2c"; 840c2599da7SThierry Reding }; 841c2599da7SThierry Reding 842c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 843c2599da7SThierry Reding groups = "dpaux-io"; 844c2599da7SThierry Reding function = "off"; 845c2599da7SThierry Reding }; 846c2599da7SThierry Reding 847c2599da7SThierry Reding i2c-bus { 848c2599da7SThierry Reding #address-cells = <1>; 849c2599da7SThierry Reding #size-cells = <0>; 850c2599da7SThierry Reding }; 851c2599da7SThierry Reding }; 852c2599da7SThierry Reding 853c2599da7SThierry Reding display-hub@15200000 { 854c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 855ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 856c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 857c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 858c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 859c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 860c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 861c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 862c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 863c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 864c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 865c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 866c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 867c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 868c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 869c2599da7SThierry Reding status = "disabled"; 870c2599da7SThierry Reding 871c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 872c2599da7SThierry Reding 873c2599da7SThierry Reding #address-cells = <1>; 874c2599da7SThierry Reding #size-cells = <1>; 875c2599da7SThierry Reding 876c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 877c2599da7SThierry Reding 878c2599da7SThierry Reding display@15200000 { 879c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 880c2599da7SThierry Reding reg = <0x15200000 0x10000>; 881c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 882c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 883c2599da7SThierry Reding clock-names = "dc"; 884c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 885c2599da7SThierry Reding reset-names = "dc"; 886c2599da7SThierry Reding 887c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 888c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 889c2599da7SThierry Reding 890c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 891c2599da7SThierry Reding nvidia,head = <0>; 892c2599da7SThierry Reding }; 893c2599da7SThierry Reding 894c2599da7SThierry Reding display@15210000 { 895c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 896c2599da7SThierry Reding reg = <0x15210000 0x10000>; 897c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 898c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 899c2599da7SThierry Reding clock-names = "dc"; 900c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 901c2599da7SThierry Reding reset-names = "dc"; 902c2599da7SThierry Reding 903c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 904c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 905c2599da7SThierry Reding 906c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 907c2599da7SThierry Reding nvidia,head = <1>; 908c2599da7SThierry Reding }; 909c2599da7SThierry Reding 910c2599da7SThierry Reding display@15220000 { 911c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 912c2599da7SThierry Reding reg = <0x15220000 0x10000>; 913c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 914c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 915c2599da7SThierry Reding clock-names = "dc"; 916c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 917c2599da7SThierry Reding reset-names = "dc"; 918c2599da7SThierry Reding 919c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 920c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 921c2599da7SThierry Reding 922c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 923c2599da7SThierry Reding nvidia,head = <2>; 924c2599da7SThierry Reding }; 925c2599da7SThierry Reding }; 926c2599da7SThierry Reding 927c2599da7SThierry Reding dsia: dsi@15300000 { 928c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 929c2599da7SThierry Reding reg = <0x15300000 0x10000>; 930c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 931c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 932c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 933c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 934c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 935c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 936c2599da7SThierry Reding reset-names = "dsi"; 937c2599da7SThierry Reding status = "disabled"; 938c2599da7SThierry Reding 939c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 940c2599da7SThierry Reding }; 941effc4b44SMikko Perttunen 942effc4b44SMikko Perttunen vic@15340000 { 943effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 944effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 945effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 946effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 947effc4b44SMikko Perttunen clock-names = "vic"; 948effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 949effc4b44SMikko Perttunen reset-names = "vic"; 950effc4b44SMikko Perttunen 951effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 952effc4b44SMikko Perttunen }; 953c2599da7SThierry Reding 954c2599da7SThierry Reding dsib: dsi@15400000 { 955c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 956c2599da7SThierry Reding reg = <0x15400000 0x10000>; 957c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 958c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 959c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 960c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 961c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 962c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 963c2599da7SThierry Reding reset-names = "dsi"; 964c2599da7SThierry Reding status = "disabled"; 965c2599da7SThierry Reding 966c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 967c2599da7SThierry Reding }; 968c2599da7SThierry Reding 969c2599da7SThierry Reding sor0: sor@15540000 { 970c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 971c2599da7SThierry Reding reg = <0x15540000 0x10000>; 972c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 973c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 974c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 975c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 976c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 977c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 978c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 979c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 980c2599da7SThierry Reding "pad"; 981c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 982c2599da7SThierry Reding reset-names = "sor"; 983c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 984c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 985c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 986c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 987c2599da7SThierry Reding status = "disabled"; 988c2599da7SThierry Reding 989c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 990c2599da7SThierry Reding nvidia,interface = <0>; 991c2599da7SThierry Reding }; 992c2599da7SThierry Reding 993c2599da7SThierry Reding sor1: sor@15580000 { 994c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 995c2599da7SThierry Reding reg = <0x15580000 0x10000>; 996c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 997c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 998c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 999c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1000c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1001c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1002c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1003c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1004c2599da7SThierry Reding "pad"; 1005c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1006c2599da7SThierry Reding reset-names = "sor"; 1007c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1008c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1009c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1010c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1011c2599da7SThierry Reding status = "disabled"; 1012c2599da7SThierry Reding 1013c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1014c2599da7SThierry Reding nvidia,interface = <1>; 1015c2599da7SThierry Reding }; 1016c2599da7SThierry Reding 1017c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1018c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1019c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1020c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1021c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1022c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1023c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1024c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1025c2599da7SThierry Reding reset-names = "dpaux"; 1026c2599da7SThierry Reding status = "disabled"; 1027c2599da7SThierry Reding 1028c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1029c2599da7SThierry Reding 1030c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1031c2599da7SThierry Reding groups = "dpaux-io"; 1032c2599da7SThierry Reding function = "aux"; 1033c2599da7SThierry Reding }; 1034c2599da7SThierry Reding 1035c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1036c2599da7SThierry Reding groups = "dpaux-io"; 1037c2599da7SThierry Reding function = "i2c"; 1038c2599da7SThierry Reding }; 1039c2599da7SThierry Reding 1040c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1041c2599da7SThierry Reding groups = "dpaux-io"; 1042c2599da7SThierry Reding function = "off"; 1043c2599da7SThierry Reding }; 1044c2599da7SThierry Reding 1045c2599da7SThierry Reding i2c-bus { 1046c2599da7SThierry Reding #address-cells = <1>; 1047c2599da7SThierry Reding #size-cells = <0>; 1048c2599da7SThierry Reding }; 1049c2599da7SThierry Reding }; 1050c2599da7SThierry Reding 1051c2599da7SThierry Reding padctl@15880000 { 1052c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1053c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1054c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1055c2599da7SThierry Reding reset-names = "dsi"; 1056c2599da7SThierry Reding status = "disabled"; 1057c2599da7SThierry Reding }; 1058c2599da7SThierry Reding 1059c2599da7SThierry Reding dsic: dsi@15900000 { 1060c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1061c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1062c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1063c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1064c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1065c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1066c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1067c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1068c2599da7SThierry Reding reset-names = "dsi"; 1069c2599da7SThierry Reding status = "disabled"; 1070c2599da7SThierry Reding 1071c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1072c2599da7SThierry Reding }; 1073c2599da7SThierry Reding 1074c2599da7SThierry Reding dsid: dsi@15940000 { 1075c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1076c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1077c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1078c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1079c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1080c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1081c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1082c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1083c2599da7SThierry Reding reset-names = "dsi"; 1084c2599da7SThierry Reding status = "disabled"; 1085c2599da7SThierry Reding 1086c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1087c2599da7SThierry Reding }; 10885524c61fSMikko Perttunen }; 10895524c61fSMikko Perttunen 1090dfd7a384SAlexandre Courbot gpu@17000000 { 1091dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1092dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1093dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 1094dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1095dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1096dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1097dfd7a384SAlexandre Courbot 1098dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1099dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1100dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1101dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1102dfd7a384SAlexandre Courbot reset-names = "gpu"; 1103dfd7a384SAlexandre Courbot status = "disabled"; 1104dfd7a384SAlexandre Courbot 1105dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1106dfd7a384SAlexandre Courbot }; 1107dfd7a384SAlexandre Courbot 110839cb62cbSJoseph Lo sysram@30000000 { 110939cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 111039cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 111139cb62cbSJoseph Lo #address-cells = <2>; 111239cb62cbSJoseph Lo #size-cells = <2>; 111339cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 111439cb62cbSJoseph Lo 111539cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 111639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 111739cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 111839cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 111939cb62cbSJoseph Lo pool; 112039cb62cbSJoseph Lo }; 112139cb62cbSJoseph Lo 112239cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 112339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 112439cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 112539cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 112639cb62cbSJoseph Lo pool; 112739cb62cbSJoseph Lo }; 112839cb62cbSJoseph Lo }; 112939cb62cbSJoseph Lo 1130cd6fe32eSThierry Reding cpus { 1131cd6fe32eSThierry Reding #address-cells = <1>; 1132cd6fe32eSThierry Reding #size-cells = <0>; 1133cd6fe32eSThierry Reding 1134cd6fe32eSThierry Reding cpu@0 { 113531af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1136cd6fe32eSThierry Reding device_type = "cpu"; 11375298166dSJoseph Lo i-cache-size = <0x20000>; 11385298166dSJoseph Lo i-cache-line-size = <64>; 11395298166dSJoseph Lo i-cache-sets = <512>; 11405298166dSJoseph Lo d-cache-size = <0x10000>; 11415298166dSJoseph Lo d-cache-line-size = <64>; 11425298166dSJoseph Lo d-cache-sets = <256>; 11435298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1144cd6fe32eSThierry Reding reg = <0x000>; 1145cd6fe32eSThierry Reding }; 1146cd6fe32eSThierry Reding 1147cd6fe32eSThierry Reding cpu@1 { 114831af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1149cd6fe32eSThierry Reding device_type = "cpu"; 11505298166dSJoseph Lo i-cache-size = <0x20000>; 11515298166dSJoseph Lo i-cache-line-size = <64>; 11525298166dSJoseph Lo i-cache-sets = <512>; 11535298166dSJoseph Lo d-cache-size = <0x10000>; 11545298166dSJoseph Lo d-cache-line-size = <64>; 11555298166dSJoseph Lo d-cache-sets = <256>; 11565298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1157cd6fe32eSThierry Reding reg = <0x001>; 1158cd6fe32eSThierry Reding }; 1159cd6fe32eSThierry Reding 1160cd6fe32eSThierry Reding cpu@2 { 116131af04cdSRob Herring compatible = "arm,cortex-a57"; 1162cd6fe32eSThierry Reding device_type = "cpu"; 11635298166dSJoseph Lo i-cache-size = <0xC000>; 11645298166dSJoseph Lo i-cache-line-size = <64>; 11655298166dSJoseph Lo i-cache-sets = <256>; 11665298166dSJoseph Lo d-cache-size = <0x8000>; 11675298166dSJoseph Lo d-cache-line-size = <64>; 11685298166dSJoseph Lo d-cache-sets = <256>; 11695298166dSJoseph Lo next-level-cache = <&L2_A57>; 1170cd6fe32eSThierry Reding reg = <0x100>; 1171cd6fe32eSThierry Reding }; 1172cd6fe32eSThierry Reding 1173cd6fe32eSThierry Reding cpu@3 { 117431af04cdSRob Herring compatible = "arm,cortex-a57"; 1175cd6fe32eSThierry Reding device_type = "cpu"; 11765298166dSJoseph Lo i-cache-size = <0xC000>; 11775298166dSJoseph Lo i-cache-line-size = <64>; 11785298166dSJoseph Lo i-cache-sets = <256>; 11795298166dSJoseph Lo d-cache-size = <0x8000>; 11805298166dSJoseph Lo d-cache-line-size = <64>; 11815298166dSJoseph Lo d-cache-sets = <256>; 11825298166dSJoseph Lo next-level-cache = <&L2_A57>; 1183cd6fe32eSThierry Reding reg = <0x101>; 1184cd6fe32eSThierry Reding }; 1185cd6fe32eSThierry Reding 1186cd6fe32eSThierry Reding cpu@4 { 118731af04cdSRob Herring compatible = "arm,cortex-a57"; 1188cd6fe32eSThierry Reding device_type = "cpu"; 11895298166dSJoseph Lo i-cache-size = <0xC000>; 11905298166dSJoseph Lo i-cache-line-size = <64>; 11915298166dSJoseph Lo i-cache-sets = <256>; 11925298166dSJoseph Lo d-cache-size = <0x8000>; 11935298166dSJoseph Lo d-cache-line-size = <64>; 11945298166dSJoseph Lo d-cache-sets = <256>; 11955298166dSJoseph Lo next-level-cache = <&L2_A57>; 1196cd6fe32eSThierry Reding reg = <0x102>; 1197cd6fe32eSThierry Reding }; 1198cd6fe32eSThierry Reding 1199cd6fe32eSThierry Reding cpu@5 { 120031af04cdSRob Herring compatible = "arm,cortex-a57"; 1201cd6fe32eSThierry Reding device_type = "cpu"; 12025298166dSJoseph Lo i-cache-size = <0xC000>; 12035298166dSJoseph Lo i-cache-line-size = <64>; 12045298166dSJoseph Lo i-cache-sets = <256>; 12055298166dSJoseph Lo d-cache-size = <0x8000>; 12065298166dSJoseph Lo d-cache-line-size = <64>; 12075298166dSJoseph Lo d-cache-sets = <256>; 12085298166dSJoseph Lo next-level-cache = <&L2_A57>; 1209cd6fe32eSThierry Reding reg = <0x103>; 1210cd6fe32eSThierry Reding }; 12115298166dSJoseph Lo 12125298166dSJoseph Lo L2_DENVER: l2-cache0 { 12135298166dSJoseph Lo compatible = "cache"; 12145298166dSJoseph Lo cache-unified; 12155298166dSJoseph Lo cache-level = <2>; 12165298166dSJoseph Lo cache-size = <0x200000>; 12175298166dSJoseph Lo cache-line-size = <64>; 12185298166dSJoseph Lo cache-sets = <2048>; 12195298166dSJoseph Lo }; 12205298166dSJoseph Lo 12215298166dSJoseph Lo L2_A57: l2-cache1 { 12225298166dSJoseph Lo compatible = "cache"; 12235298166dSJoseph Lo cache-unified; 12245298166dSJoseph Lo cache-level = <2>; 12255298166dSJoseph Lo cache-size = <0x200000>; 12265298166dSJoseph Lo cache-line-size = <64>; 12275298166dSJoseph Lo cache-sets = <2048>; 12285298166dSJoseph Lo }; 1229cd6fe32eSThierry Reding }; 1230cd6fe32eSThierry Reding 123139cb62cbSJoseph Lo bpmp: bpmp { 123239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 1233dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_BPMP>; 12345edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 12355edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 123639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 123739cb62cbSJoseph Lo #clock-cells = <1>; 123839cb62cbSJoseph Lo #reset-cells = <1>; 1239dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 124039cb62cbSJoseph Lo 124139cb62cbSJoseph Lo bpmp_i2c: i2c { 124239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 124339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 124439cb62cbSJoseph Lo #address-cells = <1>; 124539cb62cbSJoseph Lo #size-cells = <0>; 124639cb62cbSJoseph Lo status = "disabled"; 124739cb62cbSJoseph Lo }; 124815274c23SMikko Perttunen 124915274c23SMikko Perttunen bpmp_thermal: thermal { 125015274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 125115274c23SMikko Perttunen #thermal-sensor-cells = <1>; 125215274c23SMikko Perttunen }; 125315274c23SMikko Perttunen }; 125415274c23SMikko Perttunen 125515274c23SMikko Perttunen thermal-zones { 125615274c23SMikko Perttunen a57 { 125715274c23SMikko Perttunen polling-delay = <0>; 125815274c23SMikko Perttunen polling-delay-passive = <1000>; 125915274c23SMikko Perttunen 126015274c23SMikko Perttunen thermal-sensors = 126115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 126215274c23SMikko Perttunen 126315274c23SMikko Perttunen trips { 126415274c23SMikko Perttunen critical { 126515274c23SMikko Perttunen temperature = <101000>; 126615274c23SMikko Perttunen hysteresis = <0>; 126715274c23SMikko Perttunen type = "critical"; 126815274c23SMikko Perttunen }; 126915274c23SMikko Perttunen }; 127015274c23SMikko Perttunen 127115274c23SMikko Perttunen cooling-maps { 127215274c23SMikko Perttunen }; 127315274c23SMikko Perttunen }; 127415274c23SMikko Perttunen 127515274c23SMikko Perttunen denver { 127615274c23SMikko Perttunen polling-delay = <0>; 127715274c23SMikko Perttunen polling-delay-passive = <1000>; 127815274c23SMikko Perttunen 127915274c23SMikko Perttunen thermal-sensors = 128015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 128115274c23SMikko Perttunen 128215274c23SMikko Perttunen trips { 128315274c23SMikko Perttunen critical { 128415274c23SMikko Perttunen temperature = <101000>; 128515274c23SMikko Perttunen hysteresis = <0>; 128615274c23SMikko Perttunen type = "critical"; 128715274c23SMikko Perttunen }; 128815274c23SMikko Perttunen }; 128915274c23SMikko Perttunen 129015274c23SMikko Perttunen cooling-maps { 129115274c23SMikko Perttunen }; 129215274c23SMikko Perttunen }; 129315274c23SMikko Perttunen 129415274c23SMikko Perttunen gpu { 129515274c23SMikko Perttunen polling-delay = <0>; 129615274c23SMikko Perttunen polling-delay-passive = <1000>; 129715274c23SMikko Perttunen 129815274c23SMikko Perttunen thermal-sensors = 129915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 130015274c23SMikko Perttunen 130115274c23SMikko Perttunen trips { 130215274c23SMikko Perttunen critical { 130315274c23SMikko Perttunen temperature = <101000>; 130415274c23SMikko Perttunen hysteresis = <0>; 130515274c23SMikko Perttunen type = "critical"; 130615274c23SMikko Perttunen }; 130715274c23SMikko Perttunen }; 130815274c23SMikko Perttunen 130915274c23SMikko Perttunen cooling-maps { 131015274c23SMikko Perttunen }; 131115274c23SMikko Perttunen }; 131215274c23SMikko Perttunen 131315274c23SMikko Perttunen pll { 131415274c23SMikko Perttunen polling-delay = <0>; 131515274c23SMikko Perttunen polling-delay-passive = <1000>; 131615274c23SMikko Perttunen 131715274c23SMikko Perttunen thermal-sensors = 131815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 131915274c23SMikko Perttunen 132015274c23SMikko Perttunen trips { 132115274c23SMikko Perttunen critical { 132215274c23SMikko Perttunen temperature = <101000>; 132315274c23SMikko Perttunen hysteresis = <0>; 132415274c23SMikko Perttunen type = "critical"; 132515274c23SMikko Perttunen }; 132615274c23SMikko Perttunen }; 132715274c23SMikko Perttunen 132815274c23SMikko Perttunen cooling-maps { 132915274c23SMikko Perttunen }; 133015274c23SMikko Perttunen }; 133115274c23SMikko Perttunen 133215274c23SMikko Perttunen always_on { 133315274c23SMikko Perttunen polling-delay = <0>; 133415274c23SMikko Perttunen polling-delay-passive = <1000>; 133515274c23SMikko Perttunen 133615274c23SMikko Perttunen thermal-sensors = 133715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 133815274c23SMikko Perttunen 133915274c23SMikko Perttunen trips { 134015274c23SMikko Perttunen critical { 134115274c23SMikko Perttunen temperature = <101000>; 134215274c23SMikko Perttunen hysteresis = <0>; 134315274c23SMikko Perttunen type = "critical"; 134415274c23SMikko Perttunen }; 134515274c23SMikko Perttunen }; 134615274c23SMikko Perttunen 134715274c23SMikko Perttunen cooling-maps { 134815274c23SMikko Perttunen }; 134915274c23SMikko Perttunen }; 135039cb62cbSJoseph Lo }; 135139cb62cbSJoseph Lo 135239cb62cbSJoseph Lo timer { 135339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 135439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 135539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135639cb62cbSJoseph Lo <GIC_PPI 14 135739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135839cb62cbSJoseph Lo <GIC_PPI 11 135939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 136039cb62cbSJoseph Lo <GIC_PPI 10 136139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 136239cb62cbSJoseph Lo interrupt-parent = <&gic>; 136339cb62cbSJoseph Lo }; 136439cb62cbSJoseph Lo}; 1365