1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 764b154b94SThierry Reding aconnect@2900000 { 775d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 785d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 795d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 805d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 815d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 825d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 835d2249ddSSameer Pujar #address-cells = <1>; 845d2249ddSSameer Pujar #size-cells = <1>; 855d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 865d2249ddSSameer Pujar status = "disabled"; 875d2249ddSSameer Pujar 88177208f7SSameer Pujar adma: dma-controller@2930000 { 895d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 146177208f7SSameer Pujar reg = <0x02900800 0x800>; 147177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 148177208f7SSameer Pujar clock-names = "ahub"; 149177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151177208f7SSameer Pujar #address-cells = <1>; 152177208f7SSameer Pujar #size-cells = <1>; 153177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 154177208f7SSameer Pujar status = "disabled"; 155177208f7SSameer Pujar 156177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 157177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 158177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 159177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 160177208f7SSameer Pujar <&adma 2>, <&adma 2>, 161177208f7SSameer Pujar <&adma 3>, <&adma 3>, 162177208f7SSameer Pujar <&adma 4>, <&adma 4>, 163177208f7SSameer Pujar <&adma 5>, <&adma 5>, 164177208f7SSameer Pujar <&adma 6>, <&adma 6>, 165177208f7SSameer Pujar <&adma 7>, <&adma 7>, 166177208f7SSameer Pujar <&adma 8>, <&adma 8>, 167177208f7SSameer Pujar <&adma 9>, <&adma 9>, 168177208f7SSameer Pujar <&adma 10>, <&adma 10>, 169177208f7SSameer Pujar <&adma 11>, <&adma 11>, 170177208f7SSameer Pujar <&adma 12>, <&adma 12>, 171177208f7SSameer Pujar <&adma 13>, <&adma 13>, 172177208f7SSameer Pujar <&adma 14>, <&adma 14>, 173177208f7SSameer Pujar <&adma 15>, <&adma 15>, 174177208f7SSameer Pujar <&adma 16>, <&adma 16>, 175177208f7SSameer Pujar <&adma 17>, <&adma 17>, 176177208f7SSameer Pujar <&adma 18>, <&adma 18>, 177177208f7SSameer Pujar <&adma 19>, <&adma 19>, 178177208f7SSameer Pujar <&adma 20>, <&adma 20>; 179177208f7SSameer Pujar dma-names = "rx1", "tx1", 180177208f7SSameer Pujar "rx2", "tx2", 181177208f7SSameer Pujar "rx3", "tx3", 182177208f7SSameer Pujar "rx4", "tx4", 183177208f7SSameer Pujar "rx5", "tx5", 184177208f7SSameer Pujar "rx6", "tx6", 185177208f7SSameer Pujar "rx7", "tx7", 186177208f7SSameer Pujar "rx8", "tx8", 187177208f7SSameer Pujar "rx9", "tx9", 188177208f7SSameer Pujar "rx10", "tx10", 189177208f7SSameer Pujar "rx11", "tx11", 190177208f7SSameer Pujar "rx12", "tx12", 191177208f7SSameer Pujar "rx13", "tx13", 192177208f7SSameer Pujar "rx14", "tx14", 193177208f7SSameer Pujar "rx15", "tx15", 194177208f7SSameer Pujar "rx16", "tx16", 195177208f7SSameer Pujar "rx17", "tx17", 196177208f7SSameer Pujar "rx18", "tx18", 197177208f7SSameer Pujar "rx19", "tx19", 198177208f7SSameer Pujar "rx20", "tx20"; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar }; 201177208f7SSameer Pujar 202177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 203177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 204177208f7SSameer Pujar "nvidia,tegra210-i2s"; 205177208f7SSameer Pujar reg = <0x2901000 0x100>; 206177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 207177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 209177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211177208f7SSameer Pujar assigned-clock-rates = <1536000>; 212177208f7SSameer Pujar sound-name-prefix = "I2S1"; 213177208f7SSameer Pujar status = "disabled"; 214177208f7SSameer Pujar }; 215177208f7SSameer Pujar 216177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 217177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 218177208f7SSameer Pujar "nvidia,tegra210-i2s"; 219177208f7SSameer Pujar reg = <0x2901100 0x100>; 220177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 221177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 223177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225177208f7SSameer Pujar assigned-clock-rates = <1536000>; 226177208f7SSameer Pujar sound-name-prefix = "I2S2"; 227177208f7SSameer Pujar status = "disabled"; 228177208f7SSameer Pujar }; 229177208f7SSameer Pujar 230177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 231177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 232177208f7SSameer Pujar "nvidia,tegra210-i2s"; 233177208f7SSameer Pujar reg = <0x2901200 0x100>; 234177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 235177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239177208f7SSameer Pujar assigned-clock-rates = <1536000>; 240177208f7SSameer Pujar sound-name-prefix = "I2S3"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901300 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S4"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901400 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S5"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901500 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S6"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 287177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 288177208f7SSameer Pujar reg = <0x2904000 0x100>; 289177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290177208f7SSameer Pujar clock-names = "dmic"; 291177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293177208f7SSameer Pujar assigned-clock-rates = <3072000>; 294177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 295177208f7SSameer Pujar status = "disabled"; 296177208f7SSameer Pujar }; 297177208f7SSameer Pujar 298177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 299177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 300177208f7SSameer Pujar reg = <0x2904100 0x100>; 301177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302177208f7SSameer Pujar clock-names = "dmic"; 303177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305177208f7SSameer Pujar assigned-clock-rates = <3072000>; 306177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 307177208f7SSameer Pujar status = "disabled"; 308177208f7SSameer Pujar }; 309177208f7SSameer Pujar 310177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 311177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 312177208f7SSameer Pujar reg = <0x2904200 0x100>; 313177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314177208f7SSameer Pujar clock-names = "dmic"; 315177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317177208f7SSameer Pujar assigned-clock-rates = <3072000>; 318177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 319177208f7SSameer Pujar status = "disabled"; 320177208f7SSameer Pujar }; 321177208f7SSameer Pujar 322177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 323177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 324177208f7SSameer Pujar reg = <0x2904300 0x100>; 325177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326177208f7SSameer Pujar clock-names = "dmic"; 327177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329177208f7SSameer Pujar assigned-clock-rates = <3072000>; 330177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 331177208f7SSameer Pujar status = "disabled"; 332177208f7SSameer Pujar }; 333177208f7SSameer Pujar 334177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 335177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 336177208f7SSameer Pujar reg = <0x2905000 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338177208f7SSameer Pujar clock-names = "dspk"; 339177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341177208f7SSameer Pujar assigned-clock-rates = <12288000>; 342177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 343177208f7SSameer Pujar status = "disabled"; 344177208f7SSameer Pujar }; 345177208f7SSameer Pujar 346177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 347177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 348177208f7SSameer Pujar reg = <0x2905100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350177208f7SSameer Pujar clock-names = "dspk"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <12288000>; 354177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357848f3290SSameer Pujar 358848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 359848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 360848f3290SSameer Pujar "nvidia,tegra210-sfc"; 361848f3290SSameer Pujar reg = <0x2902000 0x200>; 362848f3290SSameer Pujar sound-name-prefix = "SFC1"; 363848f3290SSameer Pujar status = "disabled"; 364848f3290SSameer Pujar }; 365848f3290SSameer Pujar 366848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 367848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 368848f3290SSameer Pujar "nvidia,tegra210-sfc"; 369848f3290SSameer Pujar reg = <0x2902200 0x200>; 370848f3290SSameer Pujar sound-name-prefix = "SFC2"; 371848f3290SSameer Pujar status = "disabled"; 372848f3290SSameer Pujar }; 373848f3290SSameer Pujar 374848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 375848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 376848f3290SSameer Pujar "nvidia,tegra210-sfc"; 377848f3290SSameer Pujar reg = <0x2902400 0x200>; 378848f3290SSameer Pujar sound-name-prefix = "SFC3"; 379848f3290SSameer Pujar status = "disabled"; 380848f3290SSameer Pujar }; 381848f3290SSameer Pujar 382848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 383848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 384848f3290SSameer Pujar "nvidia,tegra210-sfc"; 385848f3290SSameer Pujar reg = <0x2902600 0x200>; 386848f3290SSameer Pujar sound-name-prefix = "SFC4"; 387848f3290SSameer Pujar status = "disabled"; 388848f3290SSameer Pujar }; 389848f3290SSameer Pujar 390848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 391848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 392848f3290SSameer Pujar "nvidia,tegra210-mvc"; 393848f3290SSameer Pujar reg = <0x290a000 0x200>; 394848f3290SSameer Pujar sound-name-prefix = "MVC1"; 395848f3290SSameer Pujar status = "disabled"; 396848f3290SSameer Pujar }; 397848f3290SSameer Pujar 398848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 399848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 400848f3290SSameer Pujar "nvidia,tegra210-mvc"; 401848f3290SSameer Pujar reg = <0x290a200 0x200>; 402848f3290SSameer Pujar sound-name-prefix = "MVC2"; 403848f3290SSameer Pujar status = "disabled"; 404848f3290SSameer Pujar }; 405848f3290SSameer Pujar 406848f3290SSameer Pujar tegra_amx1: amx@2903000 { 407848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 408848f3290SSameer Pujar "nvidia,tegra210-amx"; 409848f3290SSameer Pujar reg = <0x2903000 0x100>; 410848f3290SSameer Pujar sound-name-prefix = "AMX1"; 411848f3290SSameer Pujar status = "disabled"; 412848f3290SSameer Pujar }; 413848f3290SSameer Pujar 414848f3290SSameer Pujar tegra_amx2: amx@2903100 { 415848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 416848f3290SSameer Pujar "nvidia,tegra210-amx"; 417848f3290SSameer Pujar reg = <0x2903100 0x100>; 418848f3290SSameer Pujar sound-name-prefix = "AMX2"; 419848f3290SSameer Pujar status = "disabled"; 420848f3290SSameer Pujar }; 421848f3290SSameer Pujar 422848f3290SSameer Pujar tegra_amx3: amx@2903200 { 423848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 424848f3290SSameer Pujar "nvidia,tegra210-amx"; 425848f3290SSameer Pujar reg = <0x2903200 0x100>; 426848f3290SSameer Pujar sound-name-prefix = "AMX3"; 427848f3290SSameer Pujar status = "disabled"; 428848f3290SSameer Pujar }; 429848f3290SSameer Pujar 430848f3290SSameer Pujar tegra_amx4: amx@2903300 { 431848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 432848f3290SSameer Pujar "nvidia,tegra210-amx"; 433848f3290SSameer Pujar reg = <0x2903300 0x100>; 434848f3290SSameer Pujar sound-name-prefix = "AMX4"; 435848f3290SSameer Pujar status = "disabled"; 436848f3290SSameer Pujar }; 437848f3290SSameer Pujar 438848f3290SSameer Pujar tegra_adx1: adx@2903800 { 439848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 440848f3290SSameer Pujar "nvidia,tegra210-adx"; 441848f3290SSameer Pujar reg = <0x2903800 0x100>; 442848f3290SSameer Pujar sound-name-prefix = "ADX1"; 443848f3290SSameer Pujar status = "disabled"; 444848f3290SSameer Pujar }; 445848f3290SSameer Pujar 446848f3290SSameer Pujar tegra_adx2: adx@2903900 { 447848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 448848f3290SSameer Pujar "nvidia,tegra210-adx"; 449848f3290SSameer Pujar reg = <0x2903900 0x100>; 450848f3290SSameer Pujar sound-name-prefix = "ADX2"; 451848f3290SSameer Pujar status = "disabled"; 452848f3290SSameer Pujar }; 453848f3290SSameer Pujar 454848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 455848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 456848f3290SSameer Pujar "nvidia,tegra210-adx"; 457848f3290SSameer Pujar reg = <0x2903a00 0x100>; 458848f3290SSameer Pujar sound-name-prefix = "ADX3"; 459848f3290SSameer Pujar status = "disabled"; 460848f3290SSameer Pujar }; 461848f3290SSameer Pujar 462848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 463848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 464848f3290SSameer Pujar "nvidia,tegra210-adx"; 465848f3290SSameer Pujar reg = <0x2903b00 0x100>; 466848f3290SSameer Pujar sound-name-prefix = "ADX4"; 467848f3290SSameer Pujar status = "disabled"; 468848f3290SSameer Pujar }; 469848f3290SSameer Pujar 470848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 471848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 472848f3290SSameer Pujar "nvidia,tegra210-amixer"; 473848f3290SSameer Pujar reg = <0x290bb00 0x800>; 474848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 475848f3290SSameer Pujar status = "disabled"; 476848f3290SSameer Pujar }; 477177208f7SSameer Pujar }; 4785d2249ddSSameer Pujar }; 4795d2249ddSSameer Pujar 480954490b3SThierry Reding mc: memory-controller@2c00000 { 481d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 482d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 483b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 484d25a3bf1SThierry Reding status = "disabled"; 4853f6eaef9SThierry Reding 486954490b3SThierry Reding #interconnect-cells = <1>; 4873f6eaef9SThierry Reding #address-cells = <2>; 4883f6eaef9SThierry Reding #size-cells = <2>; 4893f6eaef9SThierry Reding 4903f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 4913f6eaef9SThierry Reding 4923f6eaef9SThierry Reding /* 4933f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 4943f6eaef9SThierry Reding * controller can address. 4953f6eaef9SThierry Reding */ 4963f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 4973f6eaef9SThierry Reding 4983f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 4993f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5003f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5013f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5023f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5033f6eaef9SThierry Reding clock-names = "emc"; 5043f6eaef9SThierry Reding 505954490b3SThierry Reding #interconnect-cells = <0>; 506954490b3SThierry Reding 5073f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5083f6eaef9SThierry Reding }; 509d25a3bf1SThierry Reding }; 510d25a3bf1SThierry Reding 51139cb62cbSJoseph Lo uarta: serial@3100000 { 51239cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 51339cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 51439cb62cbSJoseph Lo reg-shift = <2>; 51539cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 516c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 517a7a77e2eSThierry Reding clock-names = "serial"; 5187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 519a7a77e2eSThierry Reding reset-names = "serial"; 520a7a77e2eSThierry Reding status = "disabled"; 521a7a77e2eSThierry Reding }; 522a7a77e2eSThierry Reding 523a7a77e2eSThierry Reding uartb: serial@3110000 { 524a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 525a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 526a7a77e2eSThierry Reding reg-shift = <2>; 527a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 528c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 529a7a77e2eSThierry Reding clock-names = "serial"; 5307bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 531a7a77e2eSThierry Reding reset-names = "serial"; 532a7a77e2eSThierry Reding status = "disabled"; 533a7a77e2eSThierry Reding }; 534a7a77e2eSThierry Reding 535a7a77e2eSThierry Reding uartd: serial@3130000 { 536a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 537a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 538a7a77e2eSThierry Reding reg-shift = <2>; 539a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 540c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 541a7a77e2eSThierry Reding clock-names = "serial"; 5427bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 543a7a77e2eSThierry Reding reset-names = "serial"; 544a7a77e2eSThierry Reding status = "disabled"; 545a7a77e2eSThierry Reding }; 546a7a77e2eSThierry Reding 547a7a77e2eSThierry Reding uarte: serial@3140000 { 548a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 549a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 550a7a77e2eSThierry Reding reg-shift = <2>; 551a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 552c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 553a7a77e2eSThierry Reding clock-names = "serial"; 5547bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 555a7a77e2eSThierry Reding reset-names = "serial"; 556a7a77e2eSThierry Reding status = "disabled"; 557a7a77e2eSThierry Reding }; 558a7a77e2eSThierry Reding 559a7a77e2eSThierry Reding uartf: serial@3150000 { 560a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 561a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 562a7a77e2eSThierry Reding reg-shift = <2>; 563a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 564c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 565a7a77e2eSThierry Reding clock-names = "serial"; 5667bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 567a7a77e2eSThierry Reding reset-names = "serial"; 56839cb62cbSJoseph Lo status = "disabled"; 56939cb62cbSJoseph Lo }; 57039cb62cbSJoseph Lo 57140cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 572250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 57340cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 57440cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 57540cc83b3SThierry Reding #address-cells = <1>; 57640cc83b3SThierry Reding #size-cells = <0>; 577c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 57840cc83b3SThierry Reding clock-names = "div-clk"; 5797bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 58040cc83b3SThierry Reding reset-names = "i2c"; 58140cc83b3SThierry Reding status = "disabled"; 58240cc83b3SThierry Reding }; 58340cc83b3SThierry Reding 58440cc83b3SThierry Reding cam_i2c: i2c@3180000 { 585250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 58640cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 58740cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 58840cc83b3SThierry Reding #address-cells = <1>; 58940cc83b3SThierry Reding #size-cells = <0>; 590c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 59140cc83b3SThierry Reding clock-names = "div-clk"; 5927bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 59340cc83b3SThierry Reding reset-names = "i2c"; 59440cc83b3SThierry Reding status = "disabled"; 59540cc83b3SThierry Reding }; 59640cc83b3SThierry Reding 59740cc83b3SThierry Reding /* shares pads with dpaux1 */ 59840cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 599250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 60040cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 60140cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 60240cc83b3SThierry Reding #address-cells = <1>; 60340cc83b3SThierry Reding #size-cells = <0>; 604c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 60540cc83b3SThierry Reding clock-names = "div-clk"; 6067bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 60740cc83b3SThierry Reding reset-names = "i2c"; 608846137c6SThierry Reding pinctrl-names = "default", "idle"; 609846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 610846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 61140cc83b3SThierry Reding status = "disabled"; 61240cc83b3SThierry Reding }; 61340cc83b3SThierry Reding 61440cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 61540cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 616250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 61740cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 61840cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 61940cc83b3SThierry Reding #address-cells = <1>; 62040cc83b3SThierry Reding #size-cells = <0>; 621c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 62240cc83b3SThierry Reding clock-names = "div-clk"; 6237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 62440cc83b3SThierry Reding reset-names = "i2c"; 62540cc83b3SThierry Reding status = "disabled"; 62640cc83b3SThierry Reding }; 62740cc83b3SThierry Reding 62840cc83b3SThierry Reding /* shares pads with dpaux0 */ 62940cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 630250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 63140cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 63240cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 63340cc83b3SThierry Reding #address-cells = <1>; 63440cc83b3SThierry Reding #size-cells = <0>; 635c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 63640cc83b3SThierry Reding clock-names = "div-clk"; 6377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 63840cc83b3SThierry Reding reset-names = "i2c"; 639846137c6SThierry Reding pinctrl-names = "default", "idle"; 640846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 641846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 64240cc83b3SThierry Reding status = "disabled"; 64340cc83b3SThierry Reding }; 64440cc83b3SThierry Reding 64540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 646250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 64740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 64840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 64940cc83b3SThierry Reding #address-cells = <1>; 65040cc83b3SThierry Reding #size-cells = <0>; 651c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 65240cc83b3SThierry Reding clock-names = "div-clk"; 6537bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 65440cc83b3SThierry Reding reset-names = "i2c"; 65540cc83b3SThierry Reding status = "disabled"; 65640cc83b3SThierry Reding }; 65740cc83b3SThierry Reding 65840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 659250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 66040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 66140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 66240cc83b3SThierry Reding #address-cells = <1>; 66340cc83b3SThierry Reding #size-cells = <0>; 664c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 66540cc83b3SThierry Reding clock-names = "div-clk"; 6667bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 66740cc83b3SThierry Reding reset-names = "i2c"; 66840cc83b3SThierry Reding status = "disabled"; 66940cc83b3SThierry Reding }; 67040cc83b3SThierry Reding 671913f8ad4SThierry Reding pwm1: pwm@3280000 { 672913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 673913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 674913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 675913f8ad4SThierry Reding clock-names = "pwm"; 676913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 677913f8ad4SThierry Reding reset-names = "pwm"; 678913f8ad4SThierry Reding status = "disabled"; 679913f8ad4SThierry Reding #pwm-cells = <2>; 680913f8ad4SThierry Reding }; 681913f8ad4SThierry Reding 682913f8ad4SThierry Reding pwm2: pwm@3290000 { 683913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 684913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 685913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 686913f8ad4SThierry Reding clock-names = "pwm"; 687913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 688913f8ad4SThierry Reding reset-names = "pwm"; 689913f8ad4SThierry Reding status = "disabled"; 690913f8ad4SThierry Reding #pwm-cells = <2>; 691913f8ad4SThierry Reding }; 692913f8ad4SThierry Reding 693913f8ad4SThierry Reding pwm3: pwm@32a0000 { 694913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 695913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 696913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 697913f8ad4SThierry Reding clock-names = "pwm"; 698913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 699913f8ad4SThierry Reding reset-names = "pwm"; 700913f8ad4SThierry Reding status = "disabled"; 701913f8ad4SThierry Reding #pwm-cells = <2>; 702913f8ad4SThierry Reding }; 703913f8ad4SThierry Reding 704913f8ad4SThierry Reding pwm5: pwm@32c0000 { 705913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 706913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 707913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 708913f8ad4SThierry Reding clock-names = "pwm"; 709913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 710913f8ad4SThierry Reding reset-names = "pwm"; 711913f8ad4SThierry Reding status = "disabled"; 712913f8ad4SThierry Reding #pwm-cells = <2>; 713913f8ad4SThierry Reding }; 714913f8ad4SThierry Reding 715913f8ad4SThierry Reding pwm6: pwm@32d0000 { 716913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 717913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 718913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 719913f8ad4SThierry Reding clock-names = "pwm"; 720913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 721913f8ad4SThierry Reding reset-names = "pwm"; 722913f8ad4SThierry Reding status = "disabled"; 723913f8ad4SThierry Reding #pwm-cells = <2>; 724913f8ad4SThierry Reding }; 725913f8ad4SThierry Reding 726913f8ad4SThierry Reding pwm7: pwm@32e0000 { 727913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 728913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 729913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 730913f8ad4SThierry Reding clock-names = "pwm"; 731913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 732913f8ad4SThierry Reding reset-names = "pwm"; 733913f8ad4SThierry Reding status = "disabled"; 734913f8ad4SThierry Reding #pwm-cells = <2>; 735913f8ad4SThierry Reding }; 736913f8ad4SThierry Reding 737913f8ad4SThierry Reding pwm8: pwm@32f0000 { 738913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 739913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 740913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 741913f8ad4SThierry Reding clock-names = "pwm"; 742913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 743913f8ad4SThierry Reding reset-names = "pwm"; 744913f8ad4SThierry Reding status = "disabled"; 745913f8ad4SThierry Reding #pwm-cells = <2>; 746913f8ad4SThierry Reding }; 747913f8ad4SThierry Reding 74867bb17f6SThierry Reding sdmmc1: mmc@3400000 { 74999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 75099425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 75199425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 752baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 753baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 754baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7557bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 75699425dfdSThierry Reding reset-names = "sdhci"; 757954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 758954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 759954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 7608589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 76124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 76224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 76324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 76441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 76541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 76641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 76741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 76841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 76941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 7706f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 7716f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 77298a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 77398a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 77498a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 77599425dfdSThierry Reding status = "disabled"; 77699425dfdSThierry Reding }; 77799425dfdSThierry Reding 77867bb17f6SThierry Reding sdmmc2: mmc@3420000 { 77999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 78099425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 78199425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 782baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 783baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 784baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 7857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 78699425dfdSThierry Reding reset-names = "sdhci"; 787954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 788954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 789954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 7908589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 79124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 79224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 79324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 79441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 79541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 79641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 79741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 7986f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 7996f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 80099425dfdSThierry Reding status = "disabled"; 80199425dfdSThierry Reding }; 80299425dfdSThierry Reding 80367bb17f6SThierry Reding sdmmc3: mmc@3440000 { 80499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 80599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 80699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 807baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 808baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 809baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 81199425dfdSThierry Reding reset-names = "sdhci"; 812954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 813954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 814954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8158589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 81624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 81724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 81824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 81941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 82041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 82141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 82241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 82341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 82441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8256f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8266f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 82799425dfdSThierry Reding status = "disabled"; 82899425dfdSThierry Reding }; 82999425dfdSThierry Reding 83067bb17f6SThierry Reding sdmmc4: mmc@3460000 { 83199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 83299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 83399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 834baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 835baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 836baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 83798a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 83898a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 83998a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 8407bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 84199425dfdSThierry Reding reset-names = "sdhci"; 842954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 843954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 844954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8458589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 84641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 84741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 84841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 84941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 8504e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 8514e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 852e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 853e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 85422248e91SAapo Vienamo nvidia,dqs-trim = <63>; 855207f60baSAapo Vienamo mmc-hs400-1_8v; 856c4307836SSowjanya Komatineni supports-cqe; 85799425dfdSThierry Reding status = "disabled"; 85899425dfdSThierry Reding }; 85999425dfdSThierry Reding 860b066a310SThierry Reding hda@3510000 { 861b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 862b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 863b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 864b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 865b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 866b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 867b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 868b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 869b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 870b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 871b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 872b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 873954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 874954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 875954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 876dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 877b066a310SThierry Reding status = "disabled"; 878b066a310SThierry Reding }; 879b066a310SThierry Reding 8808bfde518SThierry Reding padctl: padctl@3520000 { 8818bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 8828bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 8838bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 8848bfde518SThierry Reding reg-names = "padctl", "ao"; 8856450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 8868bfde518SThierry Reding 8878bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 8888bfde518SThierry Reding reset-names = "padctl"; 8898bfde518SThierry Reding 8908bfde518SThierry Reding status = "disabled"; 8918bfde518SThierry Reding 8928bfde518SThierry Reding pads { 8938bfde518SThierry Reding usb2 { 8948bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 8958bfde518SThierry Reding clock-names = "trk"; 8968bfde518SThierry Reding status = "disabled"; 8978bfde518SThierry Reding 8988bfde518SThierry Reding lanes { 8998bfde518SThierry Reding usb2-0 { 9008bfde518SThierry Reding status = "disabled"; 9018bfde518SThierry Reding #phy-cells = <0>; 9028bfde518SThierry Reding }; 9038bfde518SThierry Reding 9048bfde518SThierry Reding usb2-1 { 9058bfde518SThierry Reding status = "disabled"; 9068bfde518SThierry Reding #phy-cells = <0>; 9078bfde518SThierry Reding }; 9088bfde518SThierry Reding 9098bfde518SThierry Reding usb2-2 { 9108bfde518SThierry Reding status = "disabled"; 9118bfde518SThierry Reding #phy-cells = <0>; 9128bfde518SThierry Reding }; 9138bfde518SThierry Reding }; 9148bfde518SThierry Reding }; 9158bfde518SThierry Reding 9168bfde518SThierry Reding hsic { 9178bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 9188bfde518SThierry Reding clock-names = "trk"; 9198bfde518SThierry Reding status = "disabled"; 9208bfde518SThierry Reding 9218bfde518SThierry Reding lanes { 9228bfde518SThierry Reding hsic-0 { 9238bfde518SThierry Reding status = "disabled"; 9248bfde518SThierry Reding #phy-cells = <0>; 9258bfde518SThierry Reding }; 9268bfde518SThierry Reding }; 9278bfde518SThierry Reding }; 9288bfde518SThierry Reding 9298bfde518SThierry Reding usb3 { 9308bfde518SThierry Reding status = "disabled"; 9318bfde518SThierry Reding 9328bfde518SThierry Reding lanes { 9338bfde518SThierry Reding usb3-0 { 9348bfde518SThierry Reding status = "disabled"; 9358bfde518SThierry Reding #phy-cells = <0>; 9368bfde518SThierry Reding }; 9378bfde518SThierry Reding 9388bfde518SThierry Reding usb3-1 { 9398bfde518SThierry Reding status = "disabled"; 9408bfde518SThierry Reding #phy-cells = <0>; 9418bfde518SThierry Reding }; 9428bfde518SThierry Reding 9438bfde518SThierry Reding usb3-2 { 9448bfde518SThierry Reding status = "disabled"; 9458bfde518SThierry Reding #phy-cells = <0>; 9468bfde518SThierry Reding }; 9478bfde518SThierry Reding }; 9488bfde518SThierry Reding }; 9498bfde518SThierry Reding }; 9508bfde518SThierry Reding 9518bfde518SThierry Reding ports { 9528bfde518SThierry Reding usb2-0 { 9538bfde518SThierry Reding status = "disabled"; 9548bfde518SThierry Reding }; 9558bfde518SThierry Reding 9568bfde518SThierry Reding usb2-1 { 9578bfde518SThierry Reding status = "disabled"; 9588bfde518SThierry Reding }; 9598bfde518SThierry Reding 9608bfde518SThierry Reding usb2-2 { 9618bfde518SThierry Reding status = "disabled"; 9628bfde518SThierry Reding }; 9638bfde518SThierry Reding 9648bfde518SThierry Reding hsic-0 { 9658bfde518SThierry Reding status = "disabled"; 9668bfde518SThierry Reding }; 9678bfde518SThierry Reding 9688bfde518SThierry Reding usb3-0 { 9698bfde518SThierry Reding status = "disabled"; 9708bfde518SThierry Reding }; 9718bfde518SThierry Reding 9728bfde518SThierry Reding usb3-1 { 9738bfde518SThierry Reding status = "disabled"; 9748bfde518SThierry Reding }; 9758bfde518SThierry Reding 9768bfde518SThierry Reding usb3-2 { 9778bfde518SThierry Reding status = "disabled"; 9788bfde518SThierry Reding }; 9798bfde518SThierry Reding }; 9808bfde518SThierry Reding }; 9818bfde518SThierry Reding 9828bfde518SThierry Reding usb@3530000 { 9838bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 9848bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 9858bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 9868bfde518SThierry Reding reg-names = "hcd", "fpci"; 9878bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 988a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 9898bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 9908bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 9918bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 9928bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 9938bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 9948bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 9958bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 9968bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 9978bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 9988bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 9998bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 10008bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 10018bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 10028bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 10038bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1004954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1005954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1006954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 100706c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 10088bfde518SThierry Reding #address-cells = <1>; 10098bfde518SThierry Reding #size-cells = <0>; 101006c6b06fSThierry Reding status = "disabled"; 101106c6b06fSThierry Reding 101206c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 10138bfde518SThierry Reding }; 10148bfde518SThierry Reding 1015584f800cSNagarjuna Kristam usb@3550000 { 1016584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1017584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1018584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1019584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1020584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1021584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1022584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1023584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1024584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1025584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1026d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1027d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1028d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1029584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1030584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1031584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1032584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1033584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1034584f800cSNagarjuna Kristam status = "disabled"; 1035584f800cSNagarjuna Kristam }; 1036584f800cSNagarjuna Kristam 103785593b75SThierry Reding fuse@3820000 { 103885593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 103985593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 104085593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 104185593b75SThierry Reding clock-names = "fuse"; 104285593b75SThierry Reding }; 104385593b75SThierry Reding 104439cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 104539cb62cbSJoseph Lo compatible = "arm,gic-400"; 104639cb62cbSJoseph Lo #interrupt-cells = <3>; 104739cb62cbSJoseph Lo interrupt-controller; 104839cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1049776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1050776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1051776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 105239cb62cbSJoseph Lo interrupts = <GIC_PPI 9 105339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 105439cb62cbSJoseph Lo interrupt-parent = <&gic>; 105539cb62cbSJoseph Lo }; 105639cb62cbSJoseph Lo 105797cf683cSThierry Reding cec@3960000 { 105897cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 105997cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 106097cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 106197cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 106297cf683cSThierry Reding clock-names = "cec"; 106397cf683cSThierry Reding status = "disabled"; 106497cf683cSThierry Reding }; 106597cf683cSThierry Reding 106639cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 106739cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 106839cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 106939cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 107039cb62cbSJoseph Lo interrupt-names = "doorbell"; 107139cb62cbSJoseph Lo #mbox-cells = <2>; 107239cb62cbSJoseph Lo status = "disabled"; 107339cb62cbSJoseph Lo }; 107439cb62cbSJoseph Lo 107540cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1076250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 107740cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 107840cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 107940cc83b3SThierry Reding #address-cells = <1>; 108040cc83b3SThierry Reding #size-cells = <0>; 1081c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 108240cc83b3SThierry Reding clock-names = "div-clk"; 10837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 108440cc83b3SThierry Reding reset-names = "i2c"; 108540cc83b3SThierry Reding status = "disabled"; 108640cc83b3SThierry Reding }; 108740cc83b3SThierry Reding 108840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1089250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 109040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 109140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 109240cc83b3SThierry Reding #address-cells = <1>; 109340cc83b3SThierry Reding #size-cells = <0>; 1094c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 109540cc83b3SThierry Reding clock-names = "div-clk"; 10967bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 109740cc83b3SThierry Reding reset-names = "i2c"; 109840cc83b3SThierry Reding status = "disabled"; 109940cc83b3SThierry Reding }; 110040cc83b3SThierry Reding 1101a7a77e2eSThierry Reding uartc: serial@c280000 { 1102a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1103a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1104a7a77e2eSThierry Reding reg-shift = <2>; 1105a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1106c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1107a7a77e2eSThierry Reding clock-names = "serial"; 11087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1109a7a77e2eSThierry Reding reset-names = "serial"; 1110a7a77e2eSThierry Reding status = "disabled"; 1111a7a77e2eSThierry Reding }; 1112a7a77e2eSThierry Reding 1113a7a77e2eSThierry Reding uartg: serial@c290000 { 1114a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1115a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1116a7a77e2eSThierry Reding reg-shift = <2>; 1117a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1118c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1119a7a77e2eSThierry Reding clock-names = "serial"; 11207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1121a7a77e2eSThierry Reding reset-names = "serial"; 1122a7a77e2eSThierry Reding status = "disabled"; 1123a7a77e2eSThierry Reding }; 1124a7a77e2eSThierry Reding 11259733a251SThierry Reding rtc: rtc@c2a0000 { 11269733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 11279733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 11289733a251SThierry Reding interrupt-parent = <&pmc>; 11299733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 11309733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 11319733a251SThierry Reding clock-names = "rtc"; 11329733a251SThierry Reding status = "disabled"; 11339733a251SThierry Reding }; 11349733a251SThierry Reding 1135fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1136fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1137fc4bb754SThierry Reding reg-names = "security", "gpio"; 1138fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1139fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1140fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1141fc4bb754SThierry Reding gpio-controller; 1142fc4bb754SThierry Reding #gpio-cells = <2>; 1143fc4bb754SThierry Reding interrupt-controller; 1144fc4bb754SThierry Reding #interrupt-cells = <2>; 1145fc4bb754SThierry Reding }; 1146fc4bb754SThierry Reding 1147913f8ad4SThierry Reding pwm4: pwm@c340000 { 1148913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1149913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1150913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1151913f8ad4SThierry Reding clock-names = "pwm"; 1152913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1153913f8ad4SThierry Reding reset-names = "pwm"; 1154913f8ad4SThierry Reding status = "disabled"; 1155913f8ad4SThierry Reding #pwm-cells = <2>; 1156913f8ad4SThierry Reding }; 1157913f8ad4SThierry Reding 115832e66e46SThierry Reding pmc: pmc@c360000 { 115973bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 116073bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 116173bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 116273bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 116373bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 116473bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 116524005fd1SAapo Vienamo 116632e66e46SThierry Reding #interrupt-cells = <2>; 116732e66e46SThierry Reding interrupt-controller; 116832e66e46SThierry Reding 116924005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 117024005fd1SAapo Vienamo pins = "sdmmc1-hv"; 117124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 117224005fd1SAapo Vienamo }; 117324005fd1SAapo Vienamo 117424005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 117524005fd1SAapo Vienamo pins = "sdmmc1-hv"; 117624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 117724005fd1SAapo Vienamo }; 117824005fd1SAapo Vienamo 117924005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 118024005fd1SAapo Vienamo pins = "sdmmc2-hv"; 118124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 118224005fd1SAapo Vienamo }; 118324005fd1SAapo Vienamo 118424005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 118524005fd1SAapo Vienamo pins = "sdmmc2-hv"; 118624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 118724005fd1SAapo Vienamo }; 118824005fd1SAapo Vienamo 118924005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 119024005fd1SAapo Vienamo pins = "sdmmc3-hv"; 119124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 119224005fd1SAapo Vienamo }; 119324005fd1SAapo Vienamo 119424005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 119524005fd1SAapo Vienamo pins = "sdmmc3-hv"; 119624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 119724005fd1SAapo Vienamo }; 119873bf90d4SThierry Reding }; 119973bf90d4SThierry Reding 12007b7ef494SMikko Perttunen ccplex@e000000 { 12017b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 12027b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 12037b7ef494SMikko Perttunen 12047b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 12057b7ef494SMikko Perttunen }; 12067b7ef494SMikko Perttunen 1207f8973cf4SManikanta Maddireddy pcie@10003000 { 1208f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1209f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1210f8973cf4SManikanta Maddireddy device_type = "pci"; 1211644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1212644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1213644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1214f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1215f8973cf4SManikanta Maddireddy 1216f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1217f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1218f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1219f8973cf4SManikanta Maddireddy 1220f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1221f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1222f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1223f8973cf4SManikanta Maddireddy 1224f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1225f8973cf4SManikanta Maddireddy #address-cells = <3>; 1226f8973cf4SManikanta Maddireddy #size-cells = <2>; 1227f8973cf4SManikanta Maddireddy 1228644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1229644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1230644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1231644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1232644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1233644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1234f8973cf4SManikanta Maddireddy 123578b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 123678b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1237f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 123878b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1239f8973cf4SManikanta Maddireddy 124078b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 124178b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1242f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 124378b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1244f8973cf4SManikanta Maddireddy 1245954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1246954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1247954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1248954490b3SThierry Reding 1249f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1250f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1251f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1252f2a465e7SThierry Reding 1253f8973cf4SManikanta Maddireddy status = "disabled"; 1254f8973cf4SManikanta Maddireddy 1255f8973cf4SManikanta Maddireddy pci@1,0 { 1256f8973cf4SManikanta Maddireddy device_type = "pci"; 1257f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1258f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1259f8973cf4SManikanta Maddireddy status = "disabled"; 1260f8973cf4SManikanta Maddireddy 1261f8973cf4SManikanta Maddireddy #address-cells = <3>; 1262f8973cf4SManikanta Maddireddy #size-cells = <2>; 1263f8973cf4SManikanta Maddireddy ranges; 1264f8973cf4SManikanta Maddireddy 1265f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1266f8973cf4SManikanta Maddireddy }; 1267f8973cf4SManikanta Maddireddy 1268f8973cf4SManikanta Maddireddy pci@2,0 { 1269f8973cf4SManikanta Maddireddy device_type = "pci"; 1270f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1271f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1272f8973cf4SManikanta Maddireddy status = "disabled"; 1273f8973cf4SManikanta Maddireddy 1274f8973cf4SManikanta Maddireddy #address-cells = <3>; 1275f8973cf4SManikanta Maddireddy #size-cells = <2>; 1276f8973cf4SManikanta Maddireddy ranges; 1277f8973cf4SManikanta Maddireddy 1278f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1279f8973cf4SManikanta Maddireddy }; 1280f8973cf4SManikanta Maddireddy 1281f8973cf4SManikanta Maddireddy pci@3,0 { 1282f8973cf4SManikanta Maddireddy device_type = "pci"; 1283f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1284f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1285f8973cf4SManikanta Maddireddy status = "disabled"; 1286f8973cf4SManikanta Maddireddy 1287f8973cf4SManikanta Maddireddy #address-cells = <3>; 1288f8973cf4SManikanta Maddireddy #size-cells = <2>; 1289f8973cf4SManikanta Maddireddy ranges; 1290f8973cf4SManikanta Maddireddy 1291f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1292f8973cf4SManikanta Maddireddy }; 1293f8973cf4SManikanta Maddireddy }; 1294f8973cf4SManikanta Maddireddy 1295b30a8e61SThierry Reding smmu: iommu@12000000 { 1296bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1297b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1298b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1299b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1300b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1301b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1302b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1303b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1304b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1305b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1306b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1307b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1308b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1309b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1310b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1311b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1312b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1313b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1314b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1315b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1316b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1317b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1318b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1319b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1320b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1321b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1322b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1323b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1324b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1325b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1326b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1327b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1328b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1329b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1330b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1331b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1332b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1333b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1334b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1335b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1336b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1337b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1338b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1339b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1340b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1341b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1342b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1343b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1344b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1345b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1346b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1347b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1348b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1349b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1350b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1351b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1352b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1353b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1354b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1355b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1356b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1357b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1358b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1359b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1360b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1361b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1362b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1363b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1364b30a8e61SThierry Reding #global-interrupts = <1>; 1365b30a8e61SThierry Reding #iommu-cells = <1>; 1366b966d2dbSThierry Reding 1367b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1368b30a8e61SThierry Reding }; 1369b30a8e61SThierry Reding 13705524c61fSMikko Perttunen host1x@13e00000 { 1371ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 13725524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 13735524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 13745524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 13755524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 13765524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1377052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 13785524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 13795524c61fSMikko Perttunen clock-names = "host1x"; 13805524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 13815524c61fSMikko Perttunen reset-names = "host1x"; 13825524c61fSMikko Perttunen 13835524c61fSMikko Perttunen #address-cells = <1>; 13845524c61fSMikko Perttunen #size-cells = <1>; 13855524c61fSMikko Perttunen 13865524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1387954490b3SThierry Reding 1388954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1389954490b3SThierry Reding interconnect-names = "dma-mem"; 1390954490b3SThierry Reding 1391c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1392c2599da7SThierry Reding 1393c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1394c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1395c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1396c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1397c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1398c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1399c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1400c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1401c2599da7SThierry Reding reset-names = "dpaux"; 1402c2599da7SThierry Reding status = "disabled"; 1403c2599da7SThierry Reding 1404c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1405c2599da7SThierry Reding 1406c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1407c2599da7SThierry Reding groups = "dpaux-io"; 1408c2599da7SThierry Reding function = "aux"; 1409c2599da7SThierry Reding }; 1410c2599da7SThierry Reding 1411c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1412c2599da7SThierry Reding groups = "dpaux-io"; 1413c2599da7SThierry Reding function = "i2c"; 1414c2599da7SThierry Reding }; 1415c2599da7SThierry Reding 1416c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1417c2599da7SThierry Reding groups = "dpaux-io"; 1418c2599da7SThierry Reding function = "off"; 1419c2599da7SThierry Reding }; 1420c2599da7SThierry Reding 1421c2599da7SThierry Reding i2c-bus { 1422c2599da7SThierry Reding #address-cells = <1>; 1423c2599da7SThierry Reding #size-cells = <0>; 1424c2599da7SThierry Reding }; 1425c2599da7SThierry Reding }; 1426c2599da7SThierry Reding 1427c2599da7SThierry Reding display-hub@15200000 { 1428aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1429ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1430c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1431c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1432c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1433c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1434c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1435c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1436c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1437c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1438c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1439c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1440c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1441c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1442c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1443c2599da7SThierry Reding status = "disabled"; 1444c2599da7SThierry Reding 1445c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1446c2599da7SThierry Reding 1447c2599da7SThierry Reding #address-cells = <1>; 1448c2599da7SThierry Reding #size-cells = <1>; 1449c2599da7SThierry Reding 1450c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1451c2599da7SThierry Reding 1452c2599da7SThierry Reding display@15200000 { 1453c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1454c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1455c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1456c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1457c2599da7SThierry Reding clock-names = "dc"; 1458c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1459c2599da7SThierry Reding reset-names = "dc"; 1460c2599da7SThierry Reding 1461c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1462954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1463954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1464954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1465c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1466c2599da7SThierry Reding 1467c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1468c2599da7SThierry Reding nvidia,head = <0>; 1469c2599da7SThierry Reding }; 1470c2599da7SThierry Reding 1471c2599da7SThierry Reding display@15210000 { 1472c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1473c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1474c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1475c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1476c2599da7SThierry Reding clock-names = "dc"; 1477c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1478c2599da7SThierry Reding reset-names = "dc"; 1479c2599da7SThierry Reding 1480c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1481954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1482954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1483954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1484c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1485c2599da7SThierry Reding 1486c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1487c2599da7SThierry Reding nvidia,head = <1>; 1488c2599da7SThierry Reding }; 1489c2599da7SThierry Reding 1490c2599da7SThierry Reding display@15220000 { 1491c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1492c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1493c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1494c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1495c2599da7SThierry Reding clock-names = "dc"; 1496c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1497c2599da7SThierry Reding reset-names = "dc"; 1498c2599da7SThierry Reding 1499c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1500954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1501954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1502954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1503c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1504c2599da7SThierry Reding 1505c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1506c2599da7SThierry Reding nvidia,head = <2>; 1507c2599da7SThierry Reding }; 1508c2599da7SThierry Reding }; 1509c2599da7SThierry Reding 1510c2599da7SThierry Reding dsia: dsi@15300000 { 1511c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1512c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1513c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1514c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1515c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1516c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1517c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1518c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1519c2599da7SThierry Reding reset-names = "dsi"; 1520c2599da7SThierry Reding status = "disabled"; 1521c2599da7SThierry Reding 1522c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1523c2599da7SThierry Reding }; 1524effc4b44SMikko Perttunen 1525effc4b44SMikko Perttunen vic@15340000 { 1526effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1527effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1528effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1529effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1530effc4b44SMikko Perttunen clock-names = "vic"; 1531effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1532effc4b44SMikko Perttunen reset-names = "vic"; 1533effc4b44SMikko Perttunen 1534effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1535954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1536954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1537954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 153829ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1539effc4b44SMikko Perttunen }; 1540c2599da7SThierry Reding 1541c2599da7SThierry Reding dsib: dsi@15400000 { 1542c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1543c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1544c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1545c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1546c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1547c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1548c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1549c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1550c2599da7SThierry Reding reset-names = "dsi"; 1551c2599da7SThierry Reding status = "disabled"; 1552c2599da7SThierry Reding 1553c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1554c2599da7SThierry Reding }; 1555c2599da7SThierry Reding 155678a05873SMikko Perttunen nvdec@15480000 { 155778a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 155878a05873SMikko Perttunen reg = <0x15480000 0x40000>; 155978a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 156078a05873SMikko Perttunen clock-names = "nvdec"; 156178a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 156278a05873SMikko Perttunen reset-names = "nvdec"; 156378a05873SMikko Perttunen 156478a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 156578a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 156678a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 156778a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 156878a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 156978a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 157078a05873SMikko Perttunen }; 157178a05873SMikko Perttunen 1572c2599da7SThierry Reding sor0: sor@15540000 { 1573c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1574c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1575c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1576c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1577c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1578c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1579c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1580c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1581c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1582c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1583c2599da7SThierry Reding "pad"; 1584c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1585c2599da7SThierry Reding reset-names = "sor"; 1586c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1587c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1588c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1589c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1590c2599da7SThierry Reding status = "disabled"; 1591c2599da7SThierry Reding 1592c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1593c2599da7SThierry Reding nvidia,interface = <0>; 1594c2599da7SThierry Reding }; 1595c2599da7SThierry Reding 1596c2599da7SThierry Reding sor1: sor@15580000 { 1597d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1598c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1599c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1600c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1601c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1602c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1603c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1604c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1605c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1606c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1607c2599da7SThierry Reding "pad"; 1608c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1609c2599da7SThierry Reding reset-names = "sor"; 1610c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1611c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1612c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1613c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1614c2599da7SThierry Reding status = "disabled"; 1615c2599da7SThierry Reding 1616c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1617c2599da7SThierry Reding nvidia,interface = <1>; 1618c2599da7SThierry Reding }; 1619c2599da7SThierry Reding 1620c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1621c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1622c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1623c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1624c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1625c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1626c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1627c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1628c2599da7SThierry Reding reset-names = "dpaux"; 1629c2599da7SThierry Reding status = "disabled"; 1630c2599da7SThierry Reding 1631c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1632c2599da7SThierry Reding 1633c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1634c2599da7SThierry Reding groups = "dpaux-io"; 1635c2599da7SThierry Reding function = "aux"; 1636c2599da7SThierry Reding }; 1637c2599da7SThierry Reding 1638c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1639c2599da7SThierry Reding groups = "dpaux-io"; 1640c2599da7SThierry Reding function = "i2c"; 1641c2599da7SThierry Reding }; 1642c2599da7SThierry Reding 1643c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1644c2599da7SThierry Reding groups = "dpaux-io"; 1645c2599da7SThierry Reding function = "off"; 1646c2599da7SThierry Reding }; 1647c2599da7SThierry Reding 1648c2599da7SThierry Reding i2c-bus { 1649c2599da7SThierry Reding #address-cells = <1>; 1650c2599da7SThierry Reding #size-cells = <0>; 1651c2599da7SThierry Reding }; 1652c2599da7SThierry Reding }; 1653c2599da7SThierry Reding 1654c2599da7SThierry Reding padctl@15880000 { 1655c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1656c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1657c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1658c2599da7SThierry Reding reset-names = "dsi"; 1659c2599da7SThierry Reding status = "disabled"; 1660c2599da7SThierry Reding }; 1661c2599da7SThierry Reding 1662c2599da7SThierry Reding dsic: dsi@15900000 { 1663c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1664c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1665c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1666c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1667c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1668c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1669c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1670c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1671c2599da7SThierry Reding reset-names = "dsi"; 1672c2599da7SThierry Reding status = "disabled"; 1673c2599da7SThierry Reding 1674c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1675c2599da7SThierry Reding }; 1676c2599da7SThierry Reding 1677c2599da7SThierry Reding dsid: dsi@15940000 { 1678c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1679c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1680c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1681c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1682c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1683c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1684c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1685c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1686c2599da7SThierry Reding reset-names = "dsi"; 1687c2599da7SThierry Reding status = "disabled"; 1688c2599da7SThierry Reding 1689c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1690c2599da7SThierry Reding }; 16915524c61fSMikko Perttunen }; 16925524c61fSMikko Perttunen 1693dfd7a384SAlexandre Courbot gpu@17000000 { 1694dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1695dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1696dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 169759a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 169859a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1699dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1700dfd7a384SAlexandre Courbot 1701dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1702dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1703dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1704dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1705dfd7a384SAlexandre Courbot reset-names = "gpu"; 1706dfd7a384SAlexandre Courbot status = "disabled"; 1707dfd7a384SAlexandre Courbot 1708dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1709954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1710954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1711954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1712954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1713954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1714dfd7a384SAlexandre Courbot }; 1715dfd7a384SAlexandre Courbot 1716e867fe41SThierry Reding sram@30000000 { 171739cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 171839cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1719aa78032cSThierry Reding #address-cells = <1>; 1720aa78032cSThierry Reding #size-cells = <1>; 1721aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 172239cb62cbSJoseph Lo 1723e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1724aa78032cSThierry Reding reg = <0x4e000 0x1000>; 172539cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 172639cb62cbSJoseph Lo pool; 172739cb62cbSJoseph Lo }; 172839cb62cbSJoseph Lo 1729e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1730aa78032cSThierry Reding reg = <0x4f000 0x1000>; 173139cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 173239cb62cbSJoseph Lo pool; 173339cb62cbSJoseph Lo }; 173439cb62cbSJoseph Lo }; 173539cb62cbSJoseph Lo 1736e061fbdfSSowjanya Komatineni sata@3507000 { 1737e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1738e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1739e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1740e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1741e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1742e061fbdfSSowjanya Komatineni 1743e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1744e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1745e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1746e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1747e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1748e061fbdfSSowjanya Komatineni 1749e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1750e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1751e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1752e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1753e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1754e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1755e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1756e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1757e061fbdfSSowjanya Komatineni <204000000>; 1758e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1759e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1760e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1761e061fbdfSSowjanya Komatineni status = "disabled"; 1762e061fbdfSSowjanya Komatineni }; 1763e061fbdfSSowjanya Komatineni 1764541d7c44SThierry Reding bpmp: bpmp { 1765541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1766954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1767954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1768954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1769954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1770954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1771541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1772541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1773541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1774*7fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1775541d7c44SThierry Reding #clock-cells = <1>; 1776541d7c44SThierry Reding #reset-cells = <1>; 1777541d7c44SThierry Reding #power-domain-cells = <1>; 1778541d7c44SThierry Reding 1779541d7c44SThierry Reding bpmp_i2c: i2c { 1780541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1781541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1782541d7c44SThierry Reding #address-cells = <1>; 1783541d7c44SThierry Reding #size-cells = <0>; 1784541d7c44SThierry Reding status = "disabled"; 1785541d7c44SThierry Reding }; 1786541d7c44SThierry Reding 1787541d7c44SThierry Reding bpmp_thermal: thermal { 1788541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1789541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1790541d7c44SThierry Reding }; 1791541d7c44SThierry Reding }; 1792541d7c44SThierry Reding 1793cd6fe32eSThierry Reding cpus { 1794cd6fe32eSThierry Reding #address-cells = <1>; 1795cd6fe32eSThierry Reding #size-cells = <0>; 1796cd6fe32eSThierry Reding 17973b4c1378SMarc Zyngier denver_0: cpu@0 { 179831af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1799cd6fe32eSThierry Reding device_type = "cpu"; 18005298166dSJoseph Lo i-cache-size = <0x20000>; 18015298166dSJoseph Lo i-cache-line-size = <64>; 18025298166dSJoseph Lo i-cache-sets = <512>; 18035298166dSJoseph Lo d-cache-size = <0x10000>; 18045298166dSJoseph Lo d-cache-line-size = <64>; 18055298166dSJoseph Lo d-cache-sets = <256>; 18065298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1807cd6fe32eSThierry Reding reg = <0x000>; 1808cd6fe32eSThierry Reding }; 1809cd6fe32eSThierry Reding 18103b4c1378SMarc Zyngier denver_1: cpu@1 { 181131af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1812cd6fe32eSThierry Reding device_type = "cpu"; 18135298166dSJoseph Lo i-cache-size = <0x20000>; 18145298166dSJoseph Lo i-cache-line-size = <64>; 18155298166dSJoseph Lo i-cache-sets = <512>; 18165298166dSJoseph Lo d-cache-size = <0x10000>; 18175298166dSJoseph Lo d-cache-line-size = <64>; 18185298166dSJoseph Lo d-cache-sets = <256>; 18195298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1820cd6fe32eSThierry Reding reg = <0x001>; 1821cd6fe32eSThierry Reding }; 1822cd6fe32eSThierry Reding 18233b4c1378SMarc Zyngier ca57_0: cpu@2 { 182431af04cdSRob Herring compatible = "arm,cortex-a57"; 1825cd6fe32eSThierry Reding device_type = "cpu"; 18265298166dSJoseph Lo i-cache-size = <0xC000>; 18275298166dSJoseph Lo i-cache-line-size = <64>; 18285298166dSJoseph Lo i-cache-sets = <256>; 18295298166dSJoseph Lo d-cache-size = <0x8000>; 18305298166dSJoseph Lo d-cache-line-size = <64>; 18315298166dSJoseph Lo d-cache-sets = <256>; 18325298166dSJoseph Lo next-level-cache = <&L2_A57>; 1833cd6fe32eSThierry Reding reg = <0x100>; 1834cd6fe32eSThierry Reding }; 1835cd6fe32eSThierry Reding 18363b4c1378SMarc Zyngier ca57_1: cpu@3 { 183731af04cdSRob Herring compatible = "arm,cortex-a57"; 1838cd6fe32eSThierry Reding device_type = "cpu"; 18395298166dSJoseph Lo i-cache-size = <0xC000>; 18405298166dSJoseph Lo i-cache-line-size = <64>; 18415298166dSJoseph Lo i-cache-sets = <256>; 18425298166dSJoseph Lo d-cache-size = <0x8000>; 18435298166dSJoseph Lo d-cache-line-size = <64>; 18445298166dSJoseph Lo d-cache-sets = <256>; 18455298166dSJoseph Lo next-level-cache = <&L2_A57>; 1846cd6fe32eSThierry Reding reg = <0x101>; 1847cd6fe32eSThierry Reding }; 1848cd6fe32eSThierry Reding 18493b4c1378SMarc Zyngier ca57_2: cpu@4 { 185031af04cdSRob Herring compatible = "arm,cortex-a57"; 1851cd6fe32eSThierry Reding device_type = "cpu"; 18525298166dSJoseph Lo i-cache-size = <0xC000>; 18535298166dSJoseph Lo i-cache-line-size = <64>; 18545298166dSJoseph Lo i-cache-sets = <256>; 18555298166dSJoseph Lo d-cache-size = <0x8000>; 18565298166dSJoseph Lo d-cache-line-size = <64>; 18575298166dSJoseph Lo d-cache-sets = <256>; 18585298166dSJoseph Lo next-level-cache = <&L2_A57>; 1859cd6fe32eSThierry Reding reg = <0x102>; 1860cd6fe32eSThierry Reding }; 1861cd6fe32eSThierry Reding 18623b4c1378SMarc Zyngier ca57_3: cpu@5 { 186331af04cdSRob Herring compatible = "arm,cortex-a57"; 1864cd6fe32eSThierry Reding device_type = "cpu"; 18655298166dSJoseph Lo i-cache-size = <0xC000>; 18665298166dSJoseph Lo i-cache-line-size = <64>; 18675298166dSJoseph Lo i-cache-sets = <256>; 18685298166dSJoseph Lo d-cache-size = <0x8000>; 18695298166dSJoseph Lo d-cache-line-size = <64>; 18705298166dSJoseph Lo d-cache-sets = <256>; 18715298166dSJoseph Lo next-level-cache = <&L2_A57>; 1872cd6fe32eSThierry Reding reg = <0x103>; 1873cd6fe32eSThierry Reding }; 18745298166dSJoseph Lo 18755298166dSJoseph Lo L2_DENVER: l2-cache0 { 18765298166dSJoseph Lo compatible = "cache"; 18775298166dSJoseph Lo cache-unified; 18785298166dSJoseph Lo cache-level = <2>; 18795298166dSJoseph Lo cache-size = <0x200000>; 18805298166dSJoseph Lo cache-line-size = <64>; 18815298166dSJoseph Lo cache-sets = <2048>; 18825298166dSJoseph Lo }; 18835298166dSJoseph Lo 18845298166dSJoseph Lo L2_A57: l2-cache1 { 18855298166dSJoseph Lo compatible = "cache"; 18865298166dSJoseph Lo cache-unified; 18875298166dSJoseph Lo cache-level = <2>; 18885298166dSJoseph Lo cache-size = <0x200000>; 18895298166dSJoseph Lo cache-line-size = <64>; 18905298166dSJoseph Lo cache-sets = <2048>; 18915298166dSJoseph Lo }; 1892cd6fe32eSThierry Reding }; 1893cd6fe32eSThierry Reding 18943b4c1378SMarc Zyngier pmu_denver { 18953b4c1378SMarc Zyngier compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; 18963b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 18973b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 18983b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 18993b4c1378SMarc Zyngier }; 19003b4c1378SMarc Zyngier 19013b4c1378SMarc Zyngier pmu_a57 { 19023b4c1378SMarc Zyngier compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 19033b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 19043b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 19053b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 19063b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 19073b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 19083b4c1378SMarc Zyngier }; 19093b4c1378SMarc Zyngier 1910e4710376SSameer Pujar sound { 1911e4710376SSameer Pujar status = "disabled"; 1912e4710376SSameer Pujar 1913e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 1914e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1915e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 1916e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 1917e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 1918e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 1919e4710376SSameer Pujar assigned-clock-parents = <0>, 1920e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 1921e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1922e4710376SSameer Pujar /* 1923e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 1924e4710376SSameer Pujar * for this to work and oscillate between base rates required 1925e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 1926e4710376SSameer Pujar */ 1927e4710376SSameer Pujar assigned-clock-rates = <258000000>; 1928e4710376SSameer Pujar 1929e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 1930e4710376SSameer Pujar }; 1931e4710376SSameer Pujar 193215274c23SMikko Perttunen thermal-zones { 193315274c23SMikko Perttunen a57 { 193415274c23SMikko Perttunen polling-delay = <0>; 193515274c23SMikko Perttunen polling-delay-passive = <1000>; 193615274c23SMikko Perttunen 193715274c23SMikko Perttunen thermal-sensors = 193815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 193915274c23SMikko Perttunen 194015274c23SMikko Perttunen trips { 194115274c23SMikko Perttunen critical { 194215274c23SMikko Perttunen temperature = <101000>; 194315274c23SMikko Perttunen hysteresis = <0>; 194415274c23SMikko Perttunen type = "critical"; 194515274c23SMikko Perttunen }; 194615274c23SMikko Perttunen }; 194715274c23SMikko Perttunen 194815274c23SMikko Perttunen cooling-maps { 194915274c23SMikko Perttunen }; 195015274c23SMikko Perttunen }; 195115274c23SMikko Perttunen 195215274c23SMikko Perttunen denver { 195315274c23SMikko Perttunen polling-delay = <0>; 195415274c23SMikko Perttunen polling-delay-passive = <1000>; 195515274c23SMikko Perttunen 195615274c23SMikko Perttunen thermal-sensors = 195715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 195815274c23SMikko Perttunen 195915274c23SMikko Perttunen trips { 196015274c23SMikko Perttunen critical { 196115274c23SMikko Perttunen temperature = <101000>; 196215274c23SMikko Perttunen hysteresis = <0>; 196315274c23SMikko Perttunen type = "critical"; 196415274c23SMikko Perttunen }; 196515274c23SMikko Perttunen }; 196615274c23SMikko Perttunen 196715274c23SMikko Perttunen cooling-maps { 196815274c23SMikko Perttunen }; 196915274c23SMikko Perttunen }; 197015274c23SMikko Perttunen 197115274c23SMikko Perttunen gpu { 197215274c23SMikko Perttunen polling-delay = <0>; 197315274c23SMikko Perttunen polling-delay-passive = <1000>; 197415274c23SMikko Perttunen 197515274c23SMikko Perttunen thermal-sensors = 197615274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 197715274c23SMikko Perttunen 197815274c23SMikko Perttunen trips { 197915274c23SMikko Perttunen critical { 198015274c23SMikko Perttunen temperature = <101000>; 198115274c23SMikko Perttunen hysteresis = <0>; 198215274c23SMikko Perttunen type = "critical"; 198315274c23SMikko Perttunen }; 198415274c23SMikko Perttunen }; 198515274c23SMikko Perttunen 198615274c23SMikko Perttunen cooling-maps { 198715274c23SMikko Perttunen }; 198815274c23SMikko Perttunen }; 198915274c23SMikko Perttunen 199015274c23SMikko Perttunen pll { 199115274c23SMikko Perttunen polling-delay = <0>; 199215274c23SMikko Perttunen polling-delay-passive = <1000>; 199315274c23SMikko Perttunen 199415274c23SMikko Perttunen thermal-sensors = 199515274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 199615274c23SMikko Perttunen 199715274c23SMikko Perttunen trips { 199815274c23SMikko Perttunen critical { 199915274c23SMikko Perttunen temperature = <101000>; 200015274c23SMikko Perttunen hysteresis = <0>; 200115274c23SMikko Perttunen type = "critical"; 200215274c23SMikko Perttunen }; 200315274c23SMikko Perttunen }; 200415274c23SMikko Perttunen 200515274c23SMikko Perttunen cooling-maps { 200615274c23SMikko Perttunen }; 200715274c23SMikko Perttunen }; 200815274c23SMikko Perttunen 200915274c23SMikko Perttunen always_on { 201015274c23SMikko Perttunen polling-delay = <0>; 201115274c23SMikko Perttunen polling-delay-passive = <1000>; 201215274c23SMikko Perttunen 201315274c23SMikko Perttunen thermal-sensors = 201415274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 201515274c23SMikko Perttunen 201615274c23SMikko Perttunen trips { 201715274c23SMikko Perttunen critical { 201815274c23SMikko Perttunen temperature = <101000>; 201915274c23SMikko Perttunen hysteresis = <0>; 202015274c23SMikko Perttunen type = "critical"; 202115274c23SMikko Perttunen }; 202215274c23SMikko Perttunen }; 202315274c23SMikko Perttunen 202415274c23SMikko Perttunen cooling-maps { 202515274c23SMikko Perttunen }; 202615274c23SMikko Perttunen }; 202739cb62cbSJoseph Lo }; 202839cb62cbSJoseph Lo 202939cb62cbSJoseph Lo timer { 203039cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 203139cb62cbSJoseph Lo interrupts = <GIC_PPI 13 203239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203339cb62cbSJoseph Lo <GIC_PPI 14 203439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203539cb62cbSJoseph Lo <GIC_PPI 11 203639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203739cb62cbSJoseph Lo <GIC_PPI 10 203839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 203939cb62cbSJoseph Lo interrupt-parent = <&gic>; 2040b30be673SThierry Reding always-on; 204139cb62cbSJoseph Lo }; 204239cb62cbSJoseph Lo}; 2043