1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81dd0be827SAkhil R interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 82dd0be827SAkhil R <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 112835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 113835553b3SAkhil R #dma-cells = <1>; 114835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 115835553b3SAkhil R dma-coherent; 116dd0be827SAkhil R dma-channel-mask = <0xfffffffe>; 117835553b3SAkhil R status = "okay"; 118835553b3SAkhil R }; 119835553b3SAkhil R 1204b154b94SThierry Reding aconnect@2900000 { 1215d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1225d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1235d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1245d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1255d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1265d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1275d2249ddSSameer Pujar #address-cells = <1>; 1285d2249ddSSameer Pujar #size-cells = <1>; 1295d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1305d2249ddSSameer Pujar status = "disabled"; 1315d2249ddSSameer Pujar 132177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 133177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 134177208f7SSameer Pujar reg = <0x02900800 0x800>; 135177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 136177208f7SSameer Pujar clock-names = "ahub"; 137177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 138177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 139177208f7SSameer Pujar #address-cells = <1>; 140177208f7SSameer Pujar #size-cells = <1>; 141177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 142177208f7SSameer Pujar status = "disabled"; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 145177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 146177208f7SSameer Pujar "nvidia,tegra210-i2s"; 147177208f7SSameer Pujar reg = <0x2901000 0x100>; 148177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 149177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 150177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 151177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 152177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 153177208f7SSameer Pujar assigned-clock-rates = <1536000>; 154177208f7SSameer Pujar sound-name-prefix = "I2S1"; 155177208f7SSameer Pujar status = "disabled"; 156177208f7SSameer Pujar }; 157177208f7SSameer Pujar 158177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 159177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 160177208f7SSameer Pujar "nvidia,tegra210-i2s"; 161177208f7SSameer Pujar reg = <0x2901100 0x100>; 162177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 163177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 164177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 165177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 166177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 167177208f7SSameer Pujar assigned-clock-rates = <1536000>; 168177208f7SSameer Pujar sound-name-prefix = "I2S2"; 169177208f7SSameer Pujar status = "disabled"; 170177208f7SSameer Pujar }; 171177208f7SSameer Pujar 172177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 173177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 174177208f7SSameer Pujar "nvidia,tegra210-i2s"; 175177208f7SSameer Pujar reg = <0x2901200 0x100>; 176177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 177177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 178177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 179177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 180177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 181177208f7SSameer Pujar assigned-clock-rates = <1536000>; 182177208f7SSameer Pujar sound-name-prefix = "I2S3"; 183177208f7SSameer Pujar status = "disabled"; 184177208f7SSameer Pujar }; 185177208f7SSameer Pujar 186177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 187177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 188177208f7SSameer Pujar "nvidia,tegra210-i2s"; 189177208f7SSameer Pujar reg = <0x2901300 0x100>; 190177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 191177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 192177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 193177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 194177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 195177208f7SSameer Pujar assigned-clock-rates = <1536000>; 196177208f7SSameer Pujar sound-name-prefix = "I2S4"; 197177208f7SSameer Pujar status = "disabled"; 198177208f7SSameer Pujar }; 199177208f7SSameer Pujar 200177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 201177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 202177208f7SSameer Pujar "nvidia,tegra210-i2s"; 203177208f7SSameer Pujar reg = <0x2901400 0x100>; 204177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 205177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 206177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 207177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 208177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 209177208f7SSameer Pujar assigned-clock-rates = <1536000>; 210177208f7SSameer Pujar sound-name-prefix = "I2S5"; 211177208f7SSameer Pujar status = "disabled"; 212177208f7SSameer Pujar }; 213177208f7SSameer Pujar 214177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 215177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 216177208f7SSameer Pujar "nvidia,tegra210-i2s"; 217177208f7SSameer Pujar reg = <0x2901500 0x100>; 218177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 219177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 220177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 221177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 222177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 223177208f7SSameer Pujar assigned-clock-rates = <1536000>; 224177208f7SSameer Pujar sound-name-prefix = "I2S6"; 225177208f7SSameer Pujar status = "disabled"; 226177208f7SSameer Pujar }; 227177208f7SSameer Pujar 228*79ed18d9SThierry Reding tegra_sfc1: sfc@2902000 { 229*79ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 230*79ed18d9SThierry Reding "nvidia,tegra210-sfc"; 231*79ed18d9SThierry Reding reg = <0x2902000 0x200>; 232*79ed18d9SThierry Reding sound-name-prefix = "SFC1"; 233*79ed18d9SThierry Reding status = "disabled"; 234*79ed18d9SThierry Reding }; 235*79ed18d9SThierry Reding 236*79ed18d9SThierry Reding tegra_sfc2: sfc@2902200 { 237*79ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 238*79ed18d9SThierry Reding "nvidia,tegra210-sfc"; 239*79ed18d9SThierry Reding reg = <0x2902200 0x200>; 240*79ed18d9SThierry Reding sound-name-prefix = "SFC2"; 241*79ed18d9SThierry Reding status = "disabled"; 242*79ed18d9SThierry Reding }; 243*79ed18d9SThierry Reding 244*79ed18d9SThierry Reding tegra_sfc3: sfc@2902400 { 245*79ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 246*79ed18d9SThierry Reding "nvidia,tegra210-sfc"; 247*79ed18d9SThierry Reding reg = <0x2902400 0x200>; 248*79ed18d9SThierry Reding sound-name-prefix = "SFC3"; 249*79ed18d9SThierry Reding status = "disabled"; 250*79ed18d9SThierry Reding }; 251*79ed18d9SThierry Reding 252*79ed18d9SThierry Reding tegra_sfc4: sfc@2902600 { 253*79ed18d9SThierry Reding compatible = "nvidia,tegra186-sfc", 254*79ed18d9SThierry Reding "nvidia,tegra210-sfc"; 255*79ed18d9SThierry Reding reg = <0x2902600 0x200>; 256*79ed18d9SThierry Reding sound-name-prefix = "SFC4"; 257*79ed18d9SThierry Reding status = "disabled"; 258*79ed18d9SThierry Reding }; 259*79ed18d9SThierry Reding 260*79ed18d9SThierry Reding tegra_amx1: amx@2903000 { 261*79ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 262*79ed18d9SThierry Reding "nvidia,tegra210-amx"; 263*79ed18d9SThierry Reding reg = <0x2903000 0x100>; 264*79ed18d9SThierry Reding sound-name-prefix = "AMX1"; 265*79ed18d9SThierry Reding status = "disabled"; 266*79ed18d9SThierry Reding }; 267*79ed18d9SThierry Reding 268*79ed18d9SThierry Reding tegra_amx2: amx@2903100 { 269*79ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 270*79ed18d9SThierry Reding "nvidia,tegra210-amx"; 271*79ed18d9SThierry Reding reg = <0x2903100 0x100>; 272*79ed18d9SThierry Reding sound-name-prefix = "AMX2"; 273*79ed18d9SThierry Reding status = "disabled"; 274*79ed18d9SThierry Reding }; 275*79ed18d9SThierry Reding 276*79ed18d9SThierry Reding tegra_amx3: amx@2903200 { 277*79ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 278*79ed18d9SThierry Reding "nvidia,tegra210-amx"; 279*79ed18d9SThierry Reding reg = <0x2903200 0x100>; 280*79ed18d9SThierry Reding sound-name-prefix = "AMX3"; 281*79ed18d9SThierry Reding status = "disabled"; 282*79ed18d9SThierry Reding }; 283*79ed18d9SThierry Reding 284*79ed18d9SThierry Reding tegra_amx4: amx@2903300 { 285*79ed18d9SThierry Reding compatible = "nvidia,tegra186-amx", 286*79ed18d9SThierry Reding "nvidia,tegra210-amx"; 287*79ed18d9SThierry Reding reg = <0x2903300 0x100>; 288*79ed18d9SThierry Reding sound-name-prefix = "AMX4"; 289*79ed18d9SThierry Reding status = "disabled"; 290*79ed18d9SThierry Reding }; 291*79ed18d9SThierry Reding 292*79ed18d9SThierry Reding tegra_adx1: adx@2903800 { 293*79ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 294*79ed18d9SThierry Reding "nvidia,tegra210-adx"; 295*79ed18d9SThierry Reding reg = <0x2903800 0x100>; 296*79ed18d9SThierry Reding sound-name-prefix = "ADX1"; 297*79ed18d9SThierry Reding status = "disabled"; 298*79ed18d9SThierry Reding }; 299*79ed18d9SThierry Reding 300*79ed18d9SThierry Reding tegra_adx2: adx@2903900 { 301*79ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 302*79ed18d9SThierry Reding "nvidia,tegra210-adx"; 303*79ed18d9SThierry Reding reg = <0x2903900 0x100>; 304*79ed18d9SThierry Reding sound-name-prefix = "ADX2"; 305*79ed18d9SThierry Reding status = "disabled"; 306*79ed18d9SThierry Reding }; 307*79ed18d9SThierry Reding 308*79ed18d9SThierry Reding tegra_adx3: adx@2903a00 { 309*79ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 310*79ed18d9SThierry Reding "nvidia,tegra210-adx"; 311*79ed18d9SThierry Reding reg = <0x2903a00 0x100>; 312*79ed18d9SThierry Reding sound-name-prefix = "ADX3"; 313*79ed18d9SThierry Reding status = "disabled"; 314*79ed18d9SThierry Reding }; 315*79ed18d9SThierry Reding 316*79ed18d9SThierry Reding tegra_adx4: adx@2903b00 { 317*79ed18d9SThierry Reding compatible = "nvidia,tegra186-adx", 318*79ed18d9SThierry Reding "nvidia,tegra210-adx"; 319*79ed18d9SThierry Reding reg = <0x2903b00 0x100>; 320*79ed18d9SThierry Reding sound-name-prefix = "ADX4"; 321*79ed18d9SThierry Reding status = "disabled"; 322*79ed18d9SThierry Reding }; 323*79ed18d9SThierry Reding 324177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 325177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 326177208f7SSameer Pujar reg = <0x2904000 0x100>; 327177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 328177208f7SSameer Pujar clock-names = "dmic"; 329177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 330177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 331177208f7SSameer Pujar assigned-clock-rates = <3072000>; 332177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 333177208f7SSameer Pujar status = "disabled"; 334177208f7SSameer Pujar }; 335177208f7SSameer Pujar 336177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 337177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 338177208f7SSameer Pujar reg = <0x2904100 0x100>; 339177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 340177208f7SSameer Pujar clock-names = "dmic"; 341177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 342177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 343177208f7SSameer Pujar assigned-clock-rates = <3072000>; 344177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 345177208f7SSameer Pujar status = "disabled"; 346177208f7SSameer Pujar }; 347177208f7SSameer Pujar 348177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 349177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 350177208f7SSameer Pujar reg = <0x2904200 0x100>; 351177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 352177208f7SSameer Pujar clock-names = "dmic"; 353177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 354177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 355177208f7SSameer Pujar assigned-clock-rates = <3072000>; 356177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 357177208f7SSameer Pujar status = "disabled"; 358177208f7SSameer Pujar }; 359177208f7SSameer Pujar 360177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 361177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 362177208f7SSameer Pujar reg = <0x2904300 0x100>; 363177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 364177208f7SSameer Pujar clock-names = "dmic"; 365177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 366177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 367177208f7SSameer Pujar assigned-clock-rates = <3072000>; 368177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 369177208f7SSameer Pujar status = "disabled"; 370177208f7SSameer Pujar }; 371177208f7SSameer Pujar 372177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 373177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 374177208f7SSameer Pujar reg = <0x2905000 0x100>; 375177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 376177208f7SSameer Pujar clock-names = "dspk"; 377177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 378177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 379177208f7SSameer Pujar assigned-clock-rates = <12288000>; 380177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 381177208f7SSameer Pujar status = "disabled"; 382177208f7SSameer Pujar }; 383177208f7SSameer Pujar 384177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 385177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 386177208f7SSameer Pujar reg = <0x2905100 0x100>; 387177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 388177208f7SSameer Pujar clock-names = "dspk"; 389177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 390177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 391177208f7SSameer Pujar assigned-clock-rates = <12288000>; 392177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 393177208f7SSameer Pujar status = "disabled"; 394177208f7SSameer Pujar }; 395848f3290SSameer Pujar 3964b6a1b7cSSameer Pujar tegra_ope1: processing-engine@2908000 { 3974b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-ope", 3984b6a1b7cSSameer Pujar "nvidia,tegra210-ope"; 3994b6a1b7cSSameer Pujar reg = <0x2908000 0x100>; 4004b6a1b7cSSameer Pujar #address-cells = <1>; 4014b6a1b7cSSameer Pujar #size-cells = <1>; 4024b6a1b7cSSameer Pujar ranges; 4034b6a1b7cSSameer Pujar sound-name-prefix = "OPE1"; 4044b6a1b7cSSameer Pujar status = "disabled"; 4054b6a1b7cSSameer Pujar 4064b6a1b7cSSameer Pujar equalizer@2908100 { 4074b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-peq", 4084b6a1b7cSSameer Pujar "nvidia,tegra210-peq"; 4094b6a1b7cSSameer Pujar reg = <0x2908100 0x100>; 4104b6a1b7cSSameer Pujar }; 4114b6a1b7cSSameer Pujar 4124b6a1b7cSSameer Pujar dynamic-range-compressor@2908200 { 4134b6a1b7cSSameer Pujar compatible = "nvidia,tegra186-mbdrc", 4144b6a1b7cSSameer Pujar "nvidia,tegra210-mbdrc"; 4154b6a1b7cSSameer Pujar reg = <0x2908200 0x200>; 4164b6a1b7cSSameer Pujar }; 4174b6a1b7cSSameer Pujar }; 4184b6a1b7cSSameer Pujar 419*79ed18d9SThierry Reding tegra_mvc1: mvc@290a000 { 420*79ed18d9SThierry Reding compatible = "nvidia,tegra186-mvc", 421*79ed18d9SThierry Reding "nvidia,tegra210-mvc"; 422*79ed18d9SThierry Reding reg = <0x290a000 0x200>; 423*79ed18d9SThierry Reding sound-name-prefix = "MVC1"; 424*79ed18d9SThierry Reding status = "disabled"; 425*79ed18d9SThierry Reding }; 426*79ed18d9SThierry Reding 427*79ed18d9SThierry Reding tegra_mvc2: mvc@290a200 { 428*79ed18d9SThierry Reding compatible = "nvidia,tegra186-mvc", 429*79ed18d9SThierry Reding "nvidia,tegra210-mvc"; 430*79ed18d9SThierry Reding reg = <0x290a200 0x200>; 431*79ed18d9SThierry Reding sound-name-prefix = "MVC2"; 432*79ed18d9SThierry Reding status = "disabled"; 433*79ed18d9SThierry Reding }; 434*79ed18d9SThierry Reding 435848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 436848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 437848f3290SSameer Pujar "nvidia,tegra210-amixer"; 438848f3290SSameer Pujar reg = <0x290bb00 0x800>; 439848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 440848f3290SSameer Pujar status = "disabled"; 441848f3290SSameer Pujar }; 44247a08153SSameer Pujar 443*79ed18d9SThierry Reding tegra_admaif: admaif@290f000 { 444*79ed18d9SThierry Reding compatible = "nvidia,tegra186-admaif"; 445*79ed18d9SThierry Reding reg = <0x0290f000 0x1000>; 446*79ed18d9SThierry Reding dmas = <&adma 1>, <&adma 1>, 447*79ed18d9SThierry Reding <&adma 2>, <&adma 2>, 448*79ed18d9SThierry Reding <&adma 3>, <&adma 3>, 449*79ed18d9SThierry Reding <&adma 4>, <&adma 4>, 450*79ed18d9SThierry Reding <&adma 5>, <&adma 5>, 451*79ed18d9SThierry Reding <&adma 6>, <&adma 6>, 452*79ed18d9SThierry Reding <&adma 7>, <&adma 7>, 453*79ed18d9SThierry Reding <&adma 8>, <&adma 8>, 454*79ed18d9SThierry Reding <&adma 9>, <&adma 9>, 455*79ed18d9SThierry Reding <&adma 10>, <&adma 10>, 456*79ed18d9SThierry Reding <&adma 11>, <&adma 11>, 457*79ed18d9SThierry Reding <&adma 12>, <&adma 12>, 458*79ed18d9SThierry Reding <&adma 13>, <&adma 13>, 459*79ed18d9SThierry Reding <&adma 14>, <&adma 14>, 460*79ed18d9SThierry Reding <&adma 15>, <&adma 15>, 461*79ed18d9SThierry Reding <&adma 16>, <&adma 16>, 462*79ed18d9SThierry Reding <&adma 17>, <&adma 17>, 463*79ed18d9SThierry Reding <&adma 18>, <&adma 18>, 464*79ed18d9SThierry Reding <&adma 19>, <&adma 19>, 465*79ed18d9SThierry Reding <&adma 20>, <&adma 20>; 466*79ed18d9SThierry Reding dma-names = "rx1", "tx1", 467*79ed18d9SThierry Reding "rx2", "tx2", 468*79ed18d9SThierry Reding "rx3", "tx3", 469*79ed18d9SThierry Reding "rx4", "tx4", 470*79ed18d9SThierry Reding "rx5", "tx5", 471*79ed18d9SThierry Reding "rx6", "tx6", 472*79ed18d9SThierry Reding "rx7", "tx7", 473*79ed18d9SThierry Reding "rx8", "tx8", 474*79ed18d9SThierry Reding "rx9", "tx9", 475*79ed18d9SThierry Reding "rx10", "tx10", 476*79ed18d9SThierry Reding "rx11", "tx11", 477*79ed18d9SThierry Reding "rx12", "tx12", 478*79ed18d9SThierry Reding "rx13", "tx13", 479*79ed18d9SThierry Reding "rx14", "tx14", 480*79ed18d9SThierry Reding "rx15", "tx15", 481*79ed18d9SThierry Reding "rx16", "tx16", 482*79ed18d9SThierry Reding "rx17", "tx17", 483*79ed18d9SThierry Reding "rx18", "tx18", 484*79ed18d9SThierry Reding "rx19", "tx19", 485*79ed18d9SThierry Reding "rx20", "tx20"; 486*79ed18d9SThierry Reding status = "disabled"; 487*79ed18d9SThierry Reding }; 488*79ed18d9SThierry Reding 48947a08153SSameer Pujar tegra_asrc: asrc@2910000 { 49047a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 49147a08153SSameer Pujar reg = <0x2910000 0x2000>; 49247a08153SSameer Pujar sound-name-prefix = "ASRC1"; 49347a08153SSameer Pujar status = "disabled"; 49447a08153SSameer Pujar }; 495177208f7SSameer Pujar }; 496*79ed18d9SThierry Reding 497*79ed18d9SThierry Reding adma: dma-controller@2930000 { 498*79ed18d9SThierry Reding compatible = "nvidia,tegra186-adma"; 499*79ed18d9SThierry Reding reg = <0x02930000 0x20000>; 500*79ed18d9SThierry Reding interrupt-parent = <&agic>; 501*79ed18d9SThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 502*79ed18d9SThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 503*79ed18d9SThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 504*79ed18d9SThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 505*79ed18d9SThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 506*79ed18d9SThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 507*79ed18d9SThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 508*79ed18d9SThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 509*79ed18d9SThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 510*79ed18d9SThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 511*79ed18d9SThierry Reding <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 512*79ed18d9SThierry Reding <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 513*79ed18d9SThierry Reding <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 514*79ed18d9SThierry Reding <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 515*79ed18d9SThierry Reding <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 516*79ed18d9SThierry Reding <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 517*79ed18d9SThierry Reding <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 518*79ed18d9SThierry Reding <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 519*79ed18d9SThierry Reding <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 520*79ed18d9SThierry Reding <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 521*79ed18d9SThierry Reding <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 522*79ed18d9SThierry Reding <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 523*79ed18d9SThierry Reding <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 524*79ed18d9SThierry Reding <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 525*79ed18d9SThierry Reding <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 526*79ed18d9SThierry Reding <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 527*79ed18d9SThierry Reding <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 528*79ed18d9SThierry Reding <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 529*79ed18d9SThierry Reding <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 530*79ed18d9SThierry Reding <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 531*79ed18d9SThierry Reding <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 532*79ed18d9SThierry Reding <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 533*79ed18d9SThierry Reding #dma-cells = <1>; 534*79ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_AHUB>; 535*79ed18d9SThierry Reding clock-names = "d_audio"; 536*79ed18d9SThierry Reding status = "disabled"; 537*79ed18d9SThierry Reding }; 538*79ed18d9SThierry Reding 539*79ed18d9SThierry Reding agic: interrupt-controller@2a40000 { 540*79ed18d9SThierry Reding compatible = "nvidia,tegra186-agic", 541*79ed18d9SThierry Reding "nvidia,tegra210-agic"; 542*79ed18d9SThierry Reding #interrupt-cells = <3>; 543*79ed18d9SThierry Reding interrupt-controller; 544*79ed18d9SThierry Reding reg = <0x02a41000 0x1000>, 545*79ed18d9SThierry Reding <0x02a42000 0x2000>; 546*79ed18d9SThierry Reding interrupts = <GIC_SPI 145 547*79ed18d9SThierry Reding (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 548*79ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_APE>; 549*79ed18d9SThierry Reding clock-names = "clk"; 550*79ed18d9SThierry Reding status = "disabled"; 551*79ed18d9SThierry Reding }; 5525d2249ddSSameer Pujar }; 5535d2249ddSSameer Pujar 554954490b3SThierry Reding mc: memory-controller@2c00000 { 555d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 556000b99e5SAshish Mhetre reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 557000b99e5SAshish Mhetre <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 558000b99e5SAshish Mhetre <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 559000b99e5SAshish Mhetre <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 560000b99e5SAshish Mhetre <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 561000b99e5SAshish Mhetre <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 562000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 563b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 564d25a3bf1SThierry Reding status = "disabled"; 5653f6eaef9SThierry Reding 566954490b3SThierry Reding #interconnect-cells = <1>; 5673f6eaef9SThierry Reding #address-cells = <2>; 5683f6eaef9SThierry Reding #size-cells = <2>; 5693f6eaef9SThierry Reding 5703f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5713f6eaef9SThierry Reding 5723f6eaef9SThierry Reding /* 5733f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5743f6eaef9SThierry Reding * controller can address. 5753f6eaef9SThierry Reding */ 5763f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5773f6eaef9SThierry Reding 5783f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5793f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5803f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5813f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5823f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5833f6eaef9SThierry Reding clock-names = "emc"; 5843f6eaef9SThierry Reding 585954490b3SThierry Reding #interconnect-cells = <0>; 586954490b3SThierry Reding 5873f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5883f6eaef9SThierry Reding }; 589d25a3bf1SThierry Reding }; 590d25a3bf1SThierry Reding 591bd1fefcbSThierry Reding timer@3010000 { 592bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 593bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 594bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 595bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 596bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 597bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 598bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 599bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 600bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 601bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 602bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 603bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604c710ac0bSKartik status = "okay"; 605bd1fefcbSThierry Reding }; 606bd1fefcbSThierry Reding 60739cb62cbSJoseph Lo uarta: serial@3100000 { 60839cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 60939cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 61039cb62cbSJoseph Lo reg-shift = <2>; 61139cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 612c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 613a7a77e2eSThierry Reding clock-names = "serial"; 6147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 615a7a77e2eSThierry Reding reset-names = "serial"; 616a7a77e2eSThierry Reding status = "disabled"; 617a7a77e2eSThierry Reding }; 618a7a77e2eSThierry Reding 619a7a77e2eSThierry Reding uartb: serial@3110000 { 620a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 621a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 622a7a77e2eSThierry Reding reg-shift = <2>; 623a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 624c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 625a7a77e2eSThierry Reding clock-names = "serial"; 6267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 627a7a77e2eSThierry Reding reset-names = "serial"; 628a7a77e2eSThierry Reding status = "disabled"; 629a7a77e2eSThierry Reding }; 630a7a77e2eSThierry Reding 631a7a77e2eSThierry Reding uartd: serial@3130000 { 632a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 633a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 634a7a77e2eSThierry Reding reg-shift = <2>; 635a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 636c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 637a7a77e2eSThierry Reding clock-names = "serial"; 6387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 639a7a77e2eSThierry Reding reset-names = "serial"; 640a7a77e2eSThierry Reding status = "disabled"; 641a7a77e2eSThierry Reding }; 642a7a77e2eSThierry Reding 643a7a77e2eSThierry Reding uarte: serial@3140000 { 644a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 645a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 646a7a77e2eSThierry Reding reg-shift = <2>; 647a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 648c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 649a7a77e2eSThierry Reding clock-names = "serial"; 6507bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 651a7a77e2eSThierry Reding reset-names = "serial"; 652a7a77e2eSThierry Reding status = "disabled"; 653a7a77e2eSThierry Reding }; 654a7a77e2eSThierry Reding 655a7a77e2eSThierry Reding uartf: serial@3150000 { 656a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 657a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 658a7a77e2eSThierry Reding reg-shift = <2>; 659a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 660c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 661a7a77e2eSThierry Reding clock-names = "serial"; 6627bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 663a7a77e2eSThierry Reding reset-names = "serial"; 66439cb62cbSJoseph Lo status = "disabled"; 66539cb62cbSJoseph Lo }; 66639cb62cbSJoseph Lo 66740cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 668548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 66940cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 67040cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 67140cc83b3SThierry Reding #address-cells = <1>; 67240cc83b3SThierry Reding #size-cells = <0>; 673c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 67440cc83b3SThierry Reding clock-names = "div-clk"; 6757bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 67640cc83b3SThierry Reding reset-names = "i2c"; 6778e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 6788e442805SAkhil R dma-coherent; 6798e442805SAkhil R dmas = <&gpcdma 21>, <&gpcdma 21>; 6808e442805SAkhil R dma-names = "rx", "tx"; 68140cc83b3SThierry Reding status = "disabled"; 68240cc83b3SThierry Reding }; 68340cc83b3SThierry Reding 68440cc83b3SThierry Reding cam_i2c: i2c@3180000 { 685548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68640cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 68740cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 68840cc83b3SThierry Reding #address-cells = <1>; 68940cc83b3SThierry Reding #size-cells = <0>; 690c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 69140cc83b3SThierry Reding clock-names = "div-clk"; 6927bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 69340cc83b3SThierry Reding reset-names = "i2c"; 6948e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 6958e442805SAkhil R dma-coherent; 6968e442805SAkhil R dmas = <&gpcdma 23>, <&gpcdma 23>; 6978e442805SAkhil R dma-names = "rx", "tx"; 69840cc83b3SThierry Reding status = "disabled"; 69940cc83b3SThierry Reding }; 70040cc83b3SThierry Reding 70140cc83b3SThierry Reding /* shares pads with dpaux1 */ 70240cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 703548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 70440cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 70540cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 70640cc83b3SThierry Reding #address-cells = <1>; 70740cc83b3SThierry Reding #size-cells = <0>; 708c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 70940cc83b3SThierry Reding clock-names = "div-clk"; 7107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 71140cc83b3SThierry Reding reset-names = "i2c"; 712846137c6SThierry Reding pinctrl-names = "default", "idle"; 713846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 714846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 7158e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 7168e442805SAkhil R dma-coherent; 7178e442805SAkhil R dmas = <&gpcdma 26>, <&gpcdma 26>; 7188e442805SAkhil R dma-names = "rx", "tx"; 71940cc83b3SThierry Reding status = "disabled"; 72040cc83b3SThierry Reding }; 72140cc83b3SThierry Reding 72240cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 72340cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 724548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 72540cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 72640cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 72740cc83b3SThierry Reding #address-cells = <1>; 72840cc83b3SThierry Reding #size-cells = <0>; 729c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 73040cc83b3SThierry Reding clock-names = "div-clk"; 7317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 73240cc83b3SThierry Reding reset-names = "i2c"; 73340cc83b3SThierry Reding status = "disabled"; 73440cc83b3SThierry Reding }; 73540cc83b3SThierry Reding 73640cc83b3SThierry Reding /* shares pads with dpaux0 */ 73740cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 738548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 73940cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 74040cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 74140cc83b3SThierry Reding #address-cells = <1>; 74240cc83b3SThierry Reding #size-cells = <0>; 743c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 74440cc83b3SThierry Reding clock-names = "div-clk"; 7457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 74640cc83b3SThierry Reding reset-names = "i2c"; 747846137c6SThierry Reding pinctrl-names = "default", "idle"; 748846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 749846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 7508e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 7518e442805SAkhil R dma-coherent; 7528e442805SAkhil R dmas = <&gpcdma 30>, <&gpcdma 30>; 7538e442805SAkhil R dma-names = "rx", "tx"; 75440cc83b3SThierry Reding status = "disabled"; 75540cc83b3SThierry Reding }; 75640cc83b3SThierry Reding 75740cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 758548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 75940cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 76040cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 76140cc83b3SThierry Reding #address-cells = <1>; 76240cc83b3SThierry Reding #size-cells = <0>; 763c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 76440cc83b3SThierry Reding clock-names = "div-clk"; 7657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 76640cc83b3SThierry Reding reset-names = "i2c"; 7678e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 7688e442805SAkhil R dma-coherent; 7698e442805SAkhil R dmas = <&gpcdma 27>, <&gpcdma 27>; 7708e442805SAkhil R dma-names = "rx", "tx"; 77140cc83b3SThierry Reding status = "disabled"; 77240cc83b3SThierry Reding }; 77340cc83b3SThierry Reding 77440cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 775548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 77640cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 77740cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 77840cc83b3SThierry Reding #address-cells = <1>; 77940cc83b3SThierry Reding #size-cells = <0>; 780c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 78140cc83b3SThierry Reding clock-names = "div-clk"; 7827bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 78340cc83b3SThierry Reding reset-names = "i2c"; 7848e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 7858e442805SAkhil R dma-coherent; 7868e442805SAkhil R dmas = <&gpcdma 31>, <&gpcdma 31>; 7878e442805SAkhil R dma-names = "rx", "tx"; 78840cc83b3SThierry Reding status = "disabled"; 78940cc83b3SThierry Reding }; 79040cc83b3SThierry Reding 791913f8ad4SThierry Reding pwm1: pwm@3280000 { 792913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 793913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 794913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 795913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 796913f8ad4SThierry Reding reset-names = "pwm"; 797913f8ad4SThierry Reding status = "disabled"; 798913f8ad4SThierry Reding #pwm-cells = <2>; 799913f8ad4SThierry Reding }; 800913f8ad4SThierry Reding 801913f8ad4SThierry Reding pwm2: pwm@3290000 { 802913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 803913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 804913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 805913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 806913f8ad4SThierry Reding reset-names = "pwm"; 807913f8ad4SThierry Reding status = "disabled"; 808913f8ad4SThierry Reding #pwm-cells = <2>; 809913f8ad4SThierry Reding }; 810913f8ad4SThierry Reding 811913f8ad4SThierry Reding pwm3: pwm@32a0000 { 812913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 813913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 814913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 815913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 816913f8ad4SThierry Reding reset-names = "pwm"; 817913f8ad4SThierry Reding status = "disabled"; 818913f8ad4SThierry Reding #pwm-cells = <2>; 819913f8ad4SThierry Reding }; 820913f8ad4SThierry Reding 821913f8ad4SThierry Reding pwm5: pwm@32c0000 { 822913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 823913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 824913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 825913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 826913f8ad4SThierry Reding reset-names = "pwm"; 827913f8ad4SThierry Reding status = "disabled"; 828913f8ad4SThierry Reding #pwm-cells = <2>; 829913f8ad4SThierry Reding }; 830913f8ad4SThierry Reding 831913f8ad4SThierry Reding pwm6: pwm@32d0000 { 832913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 833913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 834913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 835913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 836913f8ad4SThierry Reding reset-names = "pwm"; 837913f8ad4SThierry Reding status = "disabled"; 838913f8ad4SThierry Reding #pwm-cells = <2>; 839913f8ad4SThierry Reding }; 840913f8ad4SThierry Reding 841913f8ad4SThierry Reding pwm7: pwm@32e0000 { 842913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 843913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 844913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 845913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 846913f8ad4SThierry Reding reset-names = "pwm"; 847913f8ad4SThierry Reding status = "disabled"; 848913f8ad4SThierry Reding #pwm-cells = <2>; 849913f8ad4SThierry Reding }; 850913f8ad4SThierry Reding 851913f8ad4SThierry Reding pwm8: pwm@32f0000 { 852913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 853913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 854913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 855913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 856913f8ad4SThierry Reding reset-names = "pwm"; 857913f8ad4SThierry Reding status = "disabled"; 858913f8ad4SThierry Reding #pwm-cells = <2>; 859913f8ad4SThierry Reding }; 860913f8ad4SThierry Reding 86167bb17f6SThierry Reding sdmmc1: mmc@3400000 { 86299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 86399425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 86499425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 865baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 866baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 867baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8687bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 86999425dfdSThierry Reding reset-names = "sdhci"; 870954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 871954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 872954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8738589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 87424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 87524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 87624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 87741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 87841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 87941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 88041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 88141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 88241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8836f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8846f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 88598a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 88698a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 88798a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 88899425dfdSThierry Reding status = "disabled"; 88999425dfdSThierry Reding }; 89099425dfdSThierry Reding 89167bb17f6SThierry Reding sdmmc2: mmc@3420000 { 89299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 89399425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 89499425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 895baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 896baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 897baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 89999425dfdSThierry Reding reset-names = "sdhci"; 900954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 901954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 902954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9038589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 90424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 90524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 90624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 90741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 90841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 90941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 91041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9116f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9126f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 91399425dfdSThierry Reding status = "disabled"; 91499425dfdSThierry Reding }; 91599425dfdSThierry Reding 91667bb17f6SThierry Reding sdmmc3: mmc@3440000 { 91799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 91899425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 91999425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 920baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 921baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 922baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 9237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 92499425dfdSThierry Reding reset-names = "sdhci"; 925954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 926954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 927954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9288589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 92924005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 93024005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 93124005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 93241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 93341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 93441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 93541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 93641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 93741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 9386f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 9396f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 94099425dfdSThierry Reding status = "disabled"; 94199425dfdSThierry Reding }; 94299425dfdSThierry Reding 94367bb17f6SThierry Reding sdmmc4: mmc@3460000 { 94499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 94599425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 94699425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 948baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 949baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 95098a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 95198a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 95298a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9537bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 95499425dfdSThierry Reding reset-names = "sdhci"; 955954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 956954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 957954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9588589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 95941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 96041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 96141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 96241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9634e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9644e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 965e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 966e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 96722248e91SAapo Vienamo nvidia,dqs-trim = <63>; 968207f60baSAapo Vienamo mmc-hs400-1_8v; 969c4307836SSowjanya Komatineni supports-cqe; 97099425dfdSThierry Reding status = "disabled"; 97199425dfdSThierry Reding }; 97299425dfdSThierry Reding 973*79ed18d9SThierry Reding sata@3507000 { 974*79ed18d9SThierry Reding compatible = "nvidia,tegra186-ahci"; 975*79ed18d9SThierry Reding reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 976*79ed18d9SThierry Reding <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 977*79ed18d9SThierry Reding <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 978*79ed18d9SThierry Reding interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 979*79ed18d9SThierry Reding 980*79ed18d9SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 981*79ed18d9SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 982*79ed18d9SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 983*79ed18d9SThierry Reding interconnect-names = "dma-mem", "write"; 984*79ed18d9SThierry Reding iommus = <&smmu TEGRA186_SID_SATA>; 985*79ed18d9SThierry Reding 986*79ed18d9SThierry Reding clocks = <&bpmp TEGRA186_CLK_SATA>, 987*79ed18d9SThierry Reding <&bpmp TEGRA186_CLK_SATA_OOB>; 988*79ed18d9SThierry Reding clock-names = "sata", "sata-oob"; 989*79ed18d9SThierry Reding assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 990*79ed18d9SThierry Reding <&bpmp TEGRA186_CLK_SATA_OOB>; 991*79ed18d9SThierry Reding assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 992*79ed18d9SThierry Reding <&bpmp TEGRA186_CLK_PLLP>; 993*79ed18d9SThierry Reding assigned-clock-rates = <102000000>, 994*79ed18d9SThierry Reding <204000000>; 995*79ed18d9SThierry Reding resets = <&bpmp TEGRA186_RESET_SATA>, 996*79ed18d9SThierry Reding <&bpmp TEGRA186_RESET_SATACOLD>; 997*79ed18d9SThierry Reding reset-names = "sata", "sata-cold"; 998*79ed18d9SThierry Reding status = "disabled"; 999*79ed18d9SThierry Reding }; 1000*79ed18d9SThierry Reding 1001b066a310SThierry Reding hda@3510000 { 1002b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 1003b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 1004b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1005b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 1006b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 1007b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 1008b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1009b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 1010b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 1011b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 1012b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1013b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1014954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 1015954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 1016954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1017dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 1018b066a310SThierry Reding status = "disabled"; 1019b066a310SThierry Reding }; 1020b066a310SThierry Reding 10218bfde518SThierry Reding padctl: padctl@3520000 { 10228bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 10238bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 10248bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 10258bfde518SThierry Reding reg-names = "padctl", "ao"; 10266450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 10278bfde518SThierry Reding 10288bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 10298bfde518SThierry Reding reset-names = "padctl"; 10308bfde518SThierry Reding 10318bfde518SThierry Reding status = "disabled"; 10328bfde518SThierry Reding 10338bfde518SThierry Reding pads { 10348bfde518SThierry Reding usb2 { 10358bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 10368bfde518SThierry Reding clock-names = "trk"; 10378bfde518SThierry Reding status = "disabled"; 10388bfde518SThierry Reding 10398bfde518SThierry Reding lanes { 10408bfde518SThierry Reding usb2-0 { 10418bfde518SThierry Reding status = "disabled"; 10428bfde518SThierry Reding #phy-cells = <0>; 10438bfde518SThierry Reding }; 10448bfde518SThierry Reding 10458bfde518SThierry Reding usb2-1 { 10468bfde518SThierry Reding status = "disabled"; 10478bfde518SThierry Reding #phy-cells = <0>; 10488bfde518SThierry Reding }; 10498bfde518SThierry Reding 10508bfde518SThierry Reding usb2-2 { 10518bfde518SThierry Reding status = "disabled"; 10528bfde518SThierry Reding #phy-cells = <0>; 10538bfde518SThierry Reding }; 10548bfde518SThierry Reding }; 10558bfde518SThierry Reding }; 10568bfde518SThierry Reding 10578bfde518SThierry Reding hsic { 10588bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 10598bfde518SThierry Reding clock-names = "trk"; 10608bfde518SThierry Reding status = "disabled"; 10618bfde518SThierry Reding 10628bfde518SThierry Reding lanes { 10638bfde518SThierry Reding hsic-0 { 10648bfde518SThierry Reding status = "disabled"; 10658bfde518SThierry Reding #phy-cells = <0>; 10668bfde518SThierry Reding }; 10678bfde518SThierry Reding }; 10688bfde518SThierry Reding }; 10698bfde518SThierry Reding 10708bfde518SThierry Reding usb3 { 10718bfde518SThierry Reding status = "disabled"; 10728bfde518SThierry Reding 10738bfde518SThierry Reding lanes { 10748bfde518SThierry Reding usb3-0 { 10758bfde518SThierry Reding status = "disabled"; 10768bfde518SThierry Reding #phy-cells = <0>; 10778bfde518SThierry Reding }; 10788bfde518SThierry Reding 10798bfde518SThierry Reding usb3-1 { 10808bfde518SThierry Reding status = "disabled"; 10818bfde518SThierry Reding #phy-cells = <0>; 10828bfde518SThierry Reding }; 10838bfde518SThierry Reding 10848bfde518SThierry Reding usb3-2 { 10858bfde518SThierry Reding status = "disabled"; 10868bfde518SThierry Reding #phy-cells = <0>; 10878bfde518SThierry Reding }; 10888bfde518SThierry Reding }; 10898bfde518SThierry Reding }; 10908bfde518SThierry Reding }; 10918bfde518SThierry Reding 10928bfde518SThierry Reding ports { 10938bfde518SThierry Reding usb2-0 { 10948bfde518SThierry Reding status = "disabled"; 10958bfde518SThierry Reding }; 10968bfde518SThierry Reding 10978bfde518SThierry Reding usb2-1 { 10988bfde518SThierry Reding status = "disabled"; 10998bfde518SThierry Reding }; 11008bfde518SThierry Reding 11018bfde518SThierry Reding usb2-2 { 11028bfde518SThierry Reding status = "disabled"; 11038bfde518SThierry Reding }; 11048bfde518SThierry Reding 11058bfde518SThierry Reding hsic-0 { 11068bfde518SThierry Reding status = "disabled"; 11078bfde518SThierry Reding }; 11088bfde518SThierry Reding 11098bfde518SThierry Reding usb3-0 { 11108bfde518SThierry Reding status = "disabled"; 11118bfde518SThierry Reding }; 11128bfde518SThierry Reding 11138bfde518SThierry Reding usb3-1 { 11148bfde518SThierry Reding status = "disabled"; 11158bfde518SThierry Reding }; 11168bfde518SThierry Reding 11178bfde518SThierry Reding usb3-2 { 11188bfde518SThierry Reding status = "disabled"; 11198bfde518SThierry Reding }; 11208bfde518SThierry Reding }; 11218bfde518SThierry Reding }; 11228bfde518SThierry Reding 11238bfde518SThierry Reding usb@3530000 { 11248bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 11258bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 11268bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 11278bfde518SThierry Reding reg-names = "hcd", "fpci"; 11288bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1129a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 11308bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 11318bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 11328bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 11338bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 11348bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11358bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 11368bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 11378bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 11388bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 11398bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 11408bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 11418bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 11428bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 11438bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 11448bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1145954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1146954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1147954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 114806c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 11498bfde518SThierry Reding #address-cells = <1>; 11508bfde518SThierry Reding #size-cells = <0>; 115106c6b06fSThierry Reding status = "disabled"; 115206c6b06fSThierry Reding 115306c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 11548bfde518SThierry Reding }; 11558bfde518SThierry Reding 1156584f800cSNagarjuna Kristam usb@3550000 { 1157584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1158584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1159584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1160584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1161584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1162584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1163584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1164584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1165584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1166584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1167d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1168d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1169d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1170584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1171584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1172584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1173584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1174584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1175584f800cSNagarjuna Kristam status = "disabled"; 1176584f800cSNagarjuna Kristam }; 1177584f800cSNagarjuna Kristam 117885593b75SThierry Reding fuse@3820000 { 117985593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 118085593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 118185593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 118285593b75SThierry Reding clock-names = "fuse"; 118385593b75SThierry Reding }; 118485593b75SThierry Reding 118539cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 118639cb62cbSJoseph Lo compatible = "arm,gic-400"; 118739cb62cbSJoseph Lo #interrupt-cells = <3>; 118839cb62cbSJoseph Lo interrupt-controller; 118939cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1190776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1191776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1192776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 119339cb62cbSJoseph Lo interrupts = <GIC_PPI 9 119439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 119539cb62cbSJoseph Lo interrupt-parent = <&gic>; 119639cb62cbSJoseph Lo }; 119739cb62cbSJoseph Lo 119897cf683cSThierry Reding cec@3960000 { 119997cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 120097cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 120197cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 120297cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 120397cf683cSThierry Reding clock-names = "cec"; 120497cf683cSThierry Reding status = "disabled"; 120597cf683cSThierry Reding }; 120697cf683cSThierry Reding 120739cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 120839cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 120939cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 121039cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 121139cb62cbSJoseph Lo interrupt-names = "doorbell"; 121239cb62cbSJoseph Lo #mbox-cells = <2>; 121339cb62cbSJoseph Lo status = "disabled"; 121439cb62cbSJoseph Lo }; 121539cb62cbSJoseph Lo 121640cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1217548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 121840cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 121940cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 122040cc83b3SThierry Reding #address-cells = <1>; 122140cc83b3SThierry Reding #size-cells = <0>; 1222c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 122340cc83b3SThierry Reding clock-names = "div-clk"; 12247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 122540cc83b3SThierry Reding reset-names = "i2c"; 12268e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 12278e442805SAkhil R dma-coherent; 12288e442805SAkhil R dmas = <&gpcdma 22>, <&gpcdma 22>; 12298e442805SAkhil R dma-names = "rx", "tx"; 123040cc83b3SThierry Reding status = "disabled"; 123140cc83b3SThierry Reding }; 123240cc83b3SThierry Reding 123340cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1234548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 123540cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 123640cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 123740cc83b3SThierry Reding #address-cells = <1>; 123840cc83b3SThierry Reding #size-cells = <0>; 1239c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 124040cc83b3SThierry Reding clock-names = "div-clk"; 12417bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 124240cc83b3SThierry Reding reset-names = "i2c"; 12438e442805SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 12448e442805SAkhil R dma-coherent; 12458e442805SAkhil R dmas = <&gpcdma 0>, <&gpcdma 0>; 12468e442805SAkhil R dma-names = "rx", "tx"; 124740cc83b3SThierry Reding status = "disabled"; 124840cc83b3SThierry Reding }; 124940cc83b3SThierry Reding 1250a7a77e2eSThierry Reding uartc: serial@c280000 { 1251a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1252a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1253a7a77e2eSThierry Reding reg-shift = <2>; 1254a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1255c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1256a7a77e2eSThierry Reding clock-names = "serial"; 12577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1258a7a77e2eSThierry Reding reset-names = "serial"; 1259a7a77e2eSThierry Reding status = "disabled"; 1260a7a77e2eSThierry Reding }; 1261a7a77e2eSThierry Reding 1262a7a77e2eSThierry Reding uartg: serial@c290000 { 1263a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1264a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1265a7a77e2eSThierry Reding reg-shift = <2>; 1266a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1267c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1268a7a77e2eSThierry Reding clock-names = "serial"; 12697bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1270a7a77e2eSThierry Reding reset-names = "serial"; 1271a7a77e2eSThierry Reding status = "disabled"; 1272a7a77e2eSThierry Reding }; 1273a7a77e2eSThierry Reding 12749733a251SThierry Reding rtc: rtc@c2a0000 { 12759733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 12769733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 12779733a251SThierry Reding interrupt-parent = <&pmc>; 12789733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 12799733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 12809733a251SThierry Reding clock-names = "rtc"; 12819733a251SThierry Reding status = "disabled"; 12829733a251SThierry Reding }; 12839733a251SThierry Reding 1284fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1285fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1286fc4bb754SThierry Reding reg-names = "security", "gpio"; 1287fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1288fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1289fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1290fc4bb754SThierry Reding gpio-controller; 1291fc4bb754SThierry Reding #gpio-cells = <2>; 1292fc4bb754SThierry Reding interrupt-controller; 1293fc4bb754SThierry Reding #interrupt-cells = <2>; 1294fc4bb754SThierry Reding }; 1295fc4bb754SThierry Reding 1296913f8ad4SThierry Reding pwm4: pwm@c340000 { 1297913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1298913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1299913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1300913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1301913f8ad4SThierry Reding reset-names = "pwm"; 1302913f8ad4SThierry Reding status = "disabled"; 1303913f8ad4SThierry Reding #pwm-cells = <2>; 1304913f8ad4SThierry Reding }; 1305913f8ad4SThierry Reding 130632e66e46SThierry Reding pmc: pmc@c360000 { 130773bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 130873bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 130973bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 131073bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 131173bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 131273bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 131324005fd1SAapo Vienamo 131432e66e46SThierry Reding #interrupt-cells = <2>; 131532e66e46SThierry Reding interrupt-controller; 131632e66e46SThierry Reding 131724005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 131824005fd1SAapo Vienamo pins = "sdmmc1-hv"; 131924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 132024005fd1SAapo Vienamo }; 132124005fd1SAapo Vienamo 1322*79ed18d9SThierry Reding sdmmc1_3v3: sdmmc1-3v3 { 1323*79ed18d9SThierry Reding pins = "sdmmc1-hv"; 132424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 132524005fd1SAapo Vienamo }; 132624005fd1SAapo Vienamo 132724005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 132824005fd1SAapo Vienamo pins = "sdmmc2-hv"; 132924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 133024005fd1SAapo Vienamo }; 133124005fd1SAapo Vienamo 1332*79ed18d9SThierry Reding sdmmc2_3v3: sdmmc2-3v3 { 1333*79ed18d9SThierry Reding pins = "sdmmc2-hv"; 133424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 133524005fd1SAapo Vienamo }; 133624005fd1SAapo Vienamo 133724005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 133824005fd1SAapo Vienamo pins = "sdmmc3-hv"; 133924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 134024005fd1SAapo Vienamo }; 1341*79ed18d9SThierry Reding 1342*79ed18d9SThierry Reding sdmmc3_3v3: sdmmc3-3v3 { 1343*79ed18d9SThierry Reding pins = "sdmmc3-hv"; 1344*79ed18d9SThierry Reding power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1345*79ed18d9SThierry Reding }; 134673bf90d4SThierry Reding }; 134773bf90d4SThierry Reding 13487b7ef494SMikko Perttunen ccplex@e000000 { 13497b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 13502b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 13517b7ef494SMikko Perttunen 13527b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 13537b7ef494SMikko Perttunen }; 13547b7ef494SMikko Perttunen 1355f8973cf4SManikanta Maddireddy pcie@10003000 { 1356f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1357f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1358f8973cf4SManikanta Maddireddy device_type = "pci"; 1359644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1360644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1361644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1362f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1363f8973cf4SManikanta Maddireddy 1364f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1365f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1366f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1367f8973cf4SManikanta Maddireddy 1368f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1369f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1370f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1371f8973cf4SManikanta Maddireddy 1372f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1373f8973cf4SManikanta Maddireddy #address-cells = <3>; 1374f8973cf4SManikanta Maddireddy #size-cells = <2>; 1375f8973cf4SManikanta Maddireddy 1376644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1377644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1378644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1379644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1380644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1381644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1382f8973cf4SManikanta Maddireddy 138378b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 138478b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1385f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 138678b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1387f8973cf4SManikanta Maddireddy 138878b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 138978b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1390f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 139178b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1392f8973cf4SManikanta Maddireddy 1393954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1394954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1395954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1396954490b3SThierry Reding 1397f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1398f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1399f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1400f2a465e7SThierry Reding 1401f8973cf4SManikanta Maddireddy status = "disabled"; 1402f8973cf4SManikanta Maddireddy 1403f8973cf4SManikanta Maddireddy pci@1,0 { 1404f8973cf4SManikanta Maddireddy device_type = "pci"; 1405f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1406f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1407f8973cf4SManikanta Maddireddy status = "disabled"; 1408f8973cf4SManikanta Maddireddy 1409f8973cf4SManikanta Maddireddy #address-cells = <3>; 1410f8973cf4SManikanta Maddireddy #size-cells = <2>; 1411f8973cf4SManikanta Maddireddy ranges; 1412f8973cf4SManikanta Maddireddy 1413f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1414f8973cf4SManikanta Maddireddy }; 1415f8973cf4SManikanta Maddireddy 1416f8973cf4SManikanta Maddireddy pci@2,0 { 1417f8973cf4SManikanta Maddireddy device_type = "pci"; 1418f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1419f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1420f8973cf4SManikanta Maddireddy status = "disabled"; 1421f8973cf4SManikanta Maddireddy 1422f8973cf4SManikanta Maddireddy #address-cells = <3>; 1423f8973cf4SManikanta Maddireddy #size-cells = <2>; 1424f8973cf4SManikanta Maddireddy ranges; 1425f8973cf4SManikanta Maddireddy 1426f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1427f8973cf4SManikanta Maddireddy }; 1428f8973cf4SManikanta Maddireddy 1429f8973cf4SManikanta Maddireddy pci@3,0 { 1430f8973cf4SManikanta Maddireddy device_type = "pci"; 1431f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1432f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1433f8973cf4SManikanta Maddireddy status = "disabled"; 1434f8973cf4SManikanta Maddireddy 1435f8973cf4SManikanta Maddireddy #address-cells = <3>; 1436f8973cf4SManikanta Maddireddy #size-cells = <2>; 1437f8973cf4SManikanta Maddireddy ranges; 1438f8973cf4SManikanta Maddireddy 1439f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1440f8973cf4SManikanta Maddireddy }; 1441f8973cf4SManikanta Maddireddy }; 1442f8973cf4SManikanta Maddireddy 1443b30a8e61SThierry Reding smmu: iommu@12000000 { 1444bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1445b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1446b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1475b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1476b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1477b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1478b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1479b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1480b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1481b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1482b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1483b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1484b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1485b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1486b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1487b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1488b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1489b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1490b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1491b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1492b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1493b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1494b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1495b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1496b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1497b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1498b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1499b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1500b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1501b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1502b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1503b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1504b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1505b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1506b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1507b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1508b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1509b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1510b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1511b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1512b30a8e61SThierry Reding #global-interrupts = <1>; 1513b30a8e61SThierry Reding #iommu-cells = <1>; 1514b966d2dbSThierry Reding 1515b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1516b30a8e61SThierry Reding }; 1517b30a8e61SThierry Reding 15185524c61fSMikko Perttunen host1x@13e00000 { 1519ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 15205524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 15215524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 15225524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 15235524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 15245524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1525052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 15265524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 15275524c61fSMikko Perttunen clock-names = "host1x"; 15285524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 15295524c61fSMikko Perttunen reset-names = "host1x"; 15305524c61fSMikko Perttunen 15315524c61fSMikko Perttunen #address-cells = <1>; 15325524c61fSMikko Perttunen #size-cells = <1>; 15335524c61fSMikko Perttunen 15345524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1535954490b3SThierry Reding 1536954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1537954490b3SThierry Reding interconnect-names = "dma-mem"; 1538954490b3SThierry Reding 1539c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1540c2599da7SThierry Reding 1541e30cf101SMikko Perttunen /* Context isolation domains */ 1542b0c1a994SThierry Reding iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>, 1543b0c1a994SThierry Reding <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>, 1544b0c1a994SThierry Reding <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>, 1545b0c1a994SThierry Reding <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>, 1546b0c1a994SThierry Reding <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>, 1547b0c1a994SThierry Reding <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>, 1548b0c1a994SThierry Reding <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>, 1549b0c1a994SThierry Reding <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; 1550e30cf101SMikko Perttunen 1551c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1552c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1553c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1554c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1555c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1556c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1557c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1558c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1559c2599da7SThierry Reding reset-names = "dpaux"; 1560c2599da7SThierry Reding status = "disabled"; 1561c2599da7SThierry Reding 1562c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1563c2599da7SThierry Reding 1564c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1565c2599da7SThierry Reding groups = "dpaux-io"; 1566c2599da7SThierry Reding function = "aux"; 1567c2599da7SThierry Reding }; 1568c2599da7SThierry Reding 1569c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1570c2599da7SThierry Reding groups = "dpaux-io"; 1571c2599da7SThierry Reding function = "i2c"; 1572c2599da7SThierry Reding }; 1573c2599da7SThierry Reding 1574c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1575c2599da7SThierry Reding groups = "dpaux-io"; 1576c2599da7SThierry Reding function = "off"; 1577c2599da7SThierry Reding }; 1578c2599da7SThierry Reding 1579c2599da7SThierry Reding i2c-bus { 1580c2599da7SThierry Reding #address-cells = <1>; 1581c2599da7SThierry Reding #size-cells = <0>; 1582c2599da7SThierry Reding }; 1583c2599da7SThierry Reding }; 1584c2599da7SThierry Reding 1585c2599da7SThierry Reding display-hub@15200000 { 1586aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1587ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1588c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1589c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1590c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1591c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1592c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1593c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1594c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1595c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1596c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1597c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1598c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1599c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1600c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1601c2599da7SThierry Reding status = "disabled"; 1602c2599da7SThierry Reding 1603c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1604c2599da7SThierry Reding 1605c2599da7SThierry Reding #address-cells = <1>; 1606c2599da7SThierry Reding #size-cells = <1>; 1607c2599da7SThierry Reding 1608c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1609c2599da7SThierry Reding 1610c2599da7SThierry Reding display@15200000 { 1611c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1612c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1613c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1614c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1615c2599da7SThierry Reding clock-names = "dc"; 1616c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1617c2599da7SThierry Reding reset-names = "dc"; 1618c2599da7SThierry Reding 1619c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1620954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1621954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1622954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1623c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1624c2599da7SThierry Reding 1625c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1626c2599da7SThierry Reding nvidia,head = <0>; 1627c2599da7SThierry Reding }; 1628c2599da7SThierry Reding 1629c2599da7SThierry Reding display@15210000 { 1630c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1631c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1632c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1633c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1634c2599da7SThierry Reding clock-names = "dc"; 1635c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1636c2599da7SThierry Reding reset-names = "dc"; 1637c2599da7SThierry Reding 1638c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1639954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1640954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1641954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1642c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1643c2599da7SThierry Reding 1644c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1645c2599da7SThierry Reding nvidia,head = <1>; 1646c2599da7SThierry Reding }; 1647c2599da7SThierry Reding 1648c2599da7SThierry Reding display@15220000 { 1649c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1650c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1651c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1652c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1653c2599da7SThierry Reding clock-names = "dc"; 1654c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1655c2599da7SThierry Reding reset-names = "dc"; 1656c2599da7SThierry Reding 1657c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1658954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1659954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1660954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1661c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1662c2599da7SThierry Reding 1663c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1664c2599da7SThierry Reding nvidia,head = <2>; 1665c2599da7SThierry Reding }; 1666c2599da7SThierry Reding }; 1667c2599da7SThierry Reding 1668c2599da7SThierry Reding dsia: dsi@15300000 { 1669c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1670c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1671c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1672c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1673c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1674c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1675c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1676c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1677c2599da7SThierry Reding reset-names = "dsi"; 1678c2599da7SThierry Reding status = "disabled"; 1679c2599da7SThierry Reding 1680c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1681c2599da7SThierry Reding }; 1682effc4b44SMikko Perttunen 1683effc4b44SMikko Perttunen vic@15340000 { 1684effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1685effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1686effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1687effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1688effc4b44SMikko Perttunen clock-names = "vic"; 1689effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1690effc4b44SMikko Perttunen reset-names = "vic"; 1691effc4b44SMikko Perttunen 1692effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1693954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1694954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1695954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 169629ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1697effc4b44SMikko Perttunen }; 1698c2599da7SThierry Reding 1699f7eb2785SJon Hunter nvjpg@15380000 { 1700f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1701f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1702f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1703f7eb2785SJon Hunter clock-names = "nvjpg"; 1704f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1705f7eb2785SJon Hunter reset-names = "nvjpg"; 1706f7eb2785SJon Hunter 1707f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1708f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1709f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1710f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1711f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1712f7eb2785SJon Hunter }; 1713f7eb2785SJon Hunter 1714c2599da7SThierry Reding dsib: dsi@15400000 { 1715c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1716c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1717c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1718c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1719c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1720c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1721c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1722c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1723c2599da7SThierry Reding reset-names = "dsi"; 1724c2599da7SThierry Reding status = "disabled"; 1725c2599da7SThierry Reding 1726c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1727c2599da7SThierry Reding }; 1728c2599da7SThierry Reding 172978a05873SMikko Perttunen nvdec@15480000 { 173078a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 173178a05873SMikko Perttunen reg = <0x15480000 0x40000>; 173278a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 173378a05873SMikko Perttunen clock-names = "nvdec"; 173478a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 173578a05873SMikko Perttunen reset-names = "nvdec"; 173678a05873SMikko Perttunen 173778a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 173878a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 173978a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 174078a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 174178a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 174278a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 174378a05873SMikko Perttunen }; 174478a05873SMikko Perttunen 1745f7eb2785SJon Hunter nvenc@154c0000 { 1746f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1747f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1748f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1749f7eb2785SJon Hunter clock-names = "nvenc"; 1750f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1751f7eb2785SJon Hunter reset-names = "nvenc"; 1752f7eb2785SJon Hunter 1753f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1754f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1755f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1756f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1757f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1758f7eb2785SJon Hunter }; 1759f7eb2785SJon Hunter 1760c2599da7SThierry Reding sor0: sor@15540000 { 1761c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1762c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1763c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1764c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1765c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1766c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1767c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1768c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1769c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1770c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1771c2599da7SThierry Reding "pad"; 1772c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1773c2599da7SThierry Reding reset-names = "sor"; 1774c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1775c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1776c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1777c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1778c2599da7SThierry Reding status = "disabled"; 1779c2599da7SThierry Reding 1780c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1781c2599da7SThierry Reding nvidia,interface = <0>; 1782c2599da7SThierry Reding }; 1783c2599da7SThierry Reding 1784c2599da7SThierry Reding sor1: sor@15580000 { 1785d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1786c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1787c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1788c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1789c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1790c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1791c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1792c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1793c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1794c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1795c2599da7SThierry Reding "pad"; 1796c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1797c2599da7SThierry Reding reset-names = "sor"; 1798c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1799c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1800c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1801c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1802c2599da7SThierry Reding status = "disabled"; 1803c2599da7SThierry Reding 1804c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1805c2599da7SThierry Reding nvidia,interface = <1>; 1806c2599da7SThierry Reding }; 1807c2599da7SThierry Reding 1808c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1809c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1810c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1811c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1812c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1813c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1814c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1815c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1816c2599da7SThierry Reding reset-names = "dpaux"; 1817c2599da7SThierry Reding status = "disabled"; 1818c2599da7SThierry Reding 1819c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1820c2599da7SThierry Reding 1821c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1822c2599da7SThierry Reding groups = "dpaux-io"; 1823c2599da7SThierry Reding function = "aux"; 1824c2599da7SThierry Reding }; 1825c2599da7SThierry Reding 1826c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1827c2599da7SThierry Reding groups = "dpaux-io"; 1828c2599da7SThierry Reding function = "i2c"; 1829c2599da7SThierry Reding }; 1830c2599da7SThierry Reding 1831c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1832c2599da7SThierry Reding groups = "dpaux-io"; 1833c2599da7SThierry Reding function = "off"; 1834c2599da7SThierry Reding }; 1835c2599da7SThierry Reding 1836c2599da7SThierry Reding i2c-bus { 1837c2599da7SThierry Reding #address-cells = <1>; 1838c2599da7SThierry Reding #size-cells = <0>; 1839c2599da7SThierry Reding }; 1840c2599da7SThierry Reding }; 1841c2599da7SThierry Reding 1842c2599da7SThierry Reding padctl@15880000 { 1843c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1844c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1845c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1846c2599da7SThierry Reding reset-names = "dsi"; 1847c2599da7SThierry Reding status = "disabled"; 1848c2599da7SThierry Reding }; 1849c2599da7SThierry Reding 1850c2599da7SThierry Reding dsic: dsi@15900000 { 1851c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1852c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1853c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1854c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1855c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1856c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1857c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1858c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1859c2599da7SThierry Reding reset-names = "dsi"; 1860c2599da7SThierry Reding status = "disabled"; 1861c2599da7SThierry Reding 1862c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1863c2599da7SThierry Reding }; 1864c2599da7SThierry Reding 1865c2599da7SThierry Reding dsid: dsi@15940000 { 1866c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1867c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1868c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1869c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1870c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1871c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1872c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1873c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1874c2599da7SThierry Reding reset-names = "dsi"; 1875c2599da7SThierry Reding status = "disabled"; 1876c2599da7SThierry Reding 1877c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1878c2599da7SThierry Reding }; 18795524c61fSMikko Perttunen }; 18805524c61fSMikko Perttunen 1881dfd7a384SAlexandre Courbot gpu@17000000 { 1882dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1883dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1884dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 188559a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 188659a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1887dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1888dfd7a384SAlexandre Courbot 1889dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1890dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1891dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1892dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1893dfd7a384SAlexandre Courbot reset-names = "gpu"; 1894dfd7a384SAlexandre Courbot status = "disabled"; 1895dfd7a384SAlexandre Courbot 1896dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1897954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1898954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1899954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1900954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1901954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1902dfd7a384SAlexandre Courbot }; 1903dfd7a384SAlexandre Courbot 1904e867fe41SThierry Reding sram@30000000 { 190539cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 190639cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1907aa78032cSThierry Reding #address-cells = <1>; 1908aa78032cSThierry Reding #size-cells = <1>; 1909aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 191061192a9dSMikko Perttunen no-memory-wc; 191139cb62cbSJoseph Lo 1912e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1913aa78032cSThierry Reding reg = <0x4e000 0x1000>; 191439cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 191539cb62cbSJoseph Lo pool; 191639cb62cbSJoseph Lo }; 191739cb62cbSJoseph Lo 1918e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1919aa78032cSThierry Reding reg = <0x4f000 0x1000>; 192039cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 192139cb62cbSJoseph Lo pool; 192239cb62cbSJoseph Lo }; 192339cb62cbSJoseph Lo }; 192439cb62cbSJoseph Lo 1925541d7c44SThierry Reding bpmp: bpmp { 1926541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1927954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1928954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1929954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1930954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1931954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1932541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1933541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1934541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 19357fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1936541d7c44SThierry Reding #clock-cells = <1>; 1937541d7c44SThierry Reding #reset-cells = <1>; 1938541d7c44SThierry Reding #power-domain-cells = <1>; 1939541d7c44SThierry Reding 1940541d7c44SThierry Reding bpmp_i2c: i2c { 1941541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1942541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1943541d7c44SThierry Reding #address-cells = <1>; 1944541d7c44SThierry Reding #size-cells = <0>; 1945541d7c44SThierry Reding status = "disabled"; 1946541d7c44SThierry Reding }; 1947541d7c44SThierry Reding 1948541d7c44SThierry Reding bpmp_thermal: thermal { 1949541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1950541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1951541d7c44SThierry Reding }; 1952541d7c44SThierry Reding }; 1953541d7c44SThierry Reding 1954cd6fe32eSThierry Reding cpus { 1955cd6fe32eSThierry Reding #address-cells = <1>; 1956cd6fe32eSThierry Reding #size-cells = <0>; 1957cd6fe32eSThierry Reding 19583b4c1378SMarc Zyngier denver_0: cpu@0 { 195931af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1960cd6fe32eSThierry Reding device_type = "cpu"; 19615298166dSJoseph Lo i-cache-size = <0x20000>; 19625298166dSJoseph Lo i-cache-line-size = <64>; 19635298166dSJoseph Lo i-cache-sets = <512>; 19645298166dSJoseph Lo d-cache-size = <0x10000>; 19655298166dSJoseph Lo d-cache-line-size = <64>; 19665298166dSJoseph Lo d-cache-sets = <256>; 19675298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1968cd6fe32eSThierry Reding reg = <0x000>; 1969cd6fe32eSThierry Reding }; 1970cd6fe32eSThierry Reding 19713b4c1378SMarc Zyngier denver_1: cpu@1 { 197231af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1973cd6fe32eSThierry Reding device_type = "cpu"; 19745298166dSJoseph Lo i-cache-size = <0x20000>; 19755298166dSJoseph Lo i-cache-line-size = <64>; 19765298166dSJoseph Lo i-cache-sets = <512>; 19775298166dSJoseph Lo d-cache-size = <0x10000>; 19785298166dSJoseph Lo d-cache-line-size = <64>; 19795298166dSJoseph Lo d-cache-sets = <256>; 19805298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1981cd6fe32eSThierry Reding reg = <0x001>; 1982cd6fe32eSThierry Reding }; 1983cd6fe32eSThierry Reding 19843b4c1378SMarc Zyngier ca57_0: cpu@2 { 198531af04cdSRob Herring compatible = "arm,cortex-a57"; 1986cd6fe32eSThierry Reding device_type = "cpu"; 19875298166dSJoseph Lo i-cache-size = <0xC000>; 19885298166dSJoseph Lo i-cache-line-size = <64>; 19895298166dSJoseph Lo i-cache-sets = <256>; 19905298166dSJoseph Lo d-cache-size = <0x8000>; 19915298166dSJoseph Lo d-cache-line-size = <64>; 19925298166dSJoseph Lo d-cache-sets = <256>; 19935298166dSJoseph Lo next-level-cache = <&L2_A57>; 1994cd6fe32eSThierry Reding reg = <0x100>; 1995cd6fe32eSThierry Reding }; 1996cd6fe32eSThierry Reding 19973b4c1378SMarc Zyngier ca57_1: cpu@3 { 199831af04cdSRob Herring compatible = "arm,cortex-a57"; 1999cd6fe32eSThierry Reding device_type = "cpu"; 20005298166dSJoseph Lo i-cache-size = <0xC000>; 20015298166dSJoseph Lo i-cache-line-size = <64>; 20025298166dSJoseph Lo i-cache-sets = <256>; 20035298166dSJoseph Lo d-cache-size = <0x8000>; 20045298166dSJoseph Lo d-cache-line-size = <64>; 20055298166dSJoseph Lo d-cache-sets = <256>; 20065298166dSJoseph Lo next-level-cache = <&L2_A57>; 2007cd6fe32eSThierry Reding reg = <0x101>; 2008cd6fe32eSThierry Reding }; 2009cd6fe32eSThierry Reding 20103b4c1378SMarc Zyngier ca57_2: cpu@4 { 201131af04cdSRob Herring compatible = "arm,cortex-a57"; 2012cd6fe32eSThierry Reding device_type = "cpu"; 20135298166dSJoseph Lo i-cache-size = <0xC000>; 20145298166dSJoseph Lo i-cache-line-size = <64>; 20155298166dSJoseph Lo i-cache-sets = <256>; 20165298166dSJoseph Lo d-cache-size = <0x8000>; 20175298166dSJoseph Lo d-cache-line-size = <64>; 20185298166dSJoseph Lo d-cache-sets = <256>; 20195298166dSJoseph Lo next-level-cache = <&L2_A57>; 2020cd6fe32eSThierry Reding reg = <0x102>; 2021cd6fe32eSThierry Reding }; 2022cd6fe32eSThierry Reding 20233b4c1378SMarc Zyngier ca57_3: cpu@5 { 202431af04cdSRob Herring compatible = "arm,cortex-a57"; 2025cd6fe32eSThierry Reding device_type = "cpu"; 20265298166dSJoseph Lo i-cache-size = <0xC000>; 20275298166dSJoseph Lo i-cache-line-size = <64>; 20285298166dSJoseph Lo i-cache-sets = <256>; 20295298166dSJoseph Lo d-cache-size = <0x8000>; 20305298166dSJoseph Lo d-cache-line-size = <64>; 20315298166dSJoseph Lo d-cache-sets = <256>; 20325298166dSJoseph Lo next-level-cache = <&L2_A57>; 2033cd6fe32eSThierry Reding reg = <0x103>; 2034cd6fe32eSThierry Reding }; 20355298166dSJoseph Lo 20365298166dSJoseph Lo L2_DENVER: l2-cache0 { 20375298166dSJoseph Lo compatible = "cache"; 20385298166dSJoseph Lo cache-unified; 20395298166dSJoseph Lo cache-level = <2>; 20405298166dSJoseph Lo cache-size = <0x200000>; 20415298166dSJoseph Lo cache-line-size = <64>; 20425298166dSJoseph Lo cache-sets = <2048>; 20435298166dSJoseph Lo }; 20445298166dSJoseph Lo 20455298166dSJoseph Lo L2_A57: l2-cache1 { 20465298166dSJoseph Lo compatible = "cache"; 20475298166dSJoseph Lo cache-unified; 20485298166dSJoseph Lo cache-level = <2>; 20495298166dSJoseph Lo cache-size = <0x200000>; 20505298166dSJoseph Lo cache-line-size = <64>; 20515298166dSJoseph Lo cache-sets = <2048>; 20525298166dSJoseph Lo }; 2053cd6fe32eSThierry Reding }; 2054cd6fe32eSThierry Reding 2055*79ed18d9SThierry Reding pmu-a57 { 2056f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 20573b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 20583b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20593b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20603b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20613b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20623b4c1378SMarc Zyngier }; 20633b4c1378SMarc Zyngier 2064*79ed18d9SThierry Reding pmu-denver { 2065*79ed18d9SThierry Reding compatible = "nvidia,denver-pmu"; 2066*79ed18d9SThierry Reding interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2067*79ed18d9SThierry Reding <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2068*79ed18d9SThierry Reding interrupt-affinity = <&denver_0 &denver_1>; 2069*79ed18d9SThierry Reding }; 2070*79ed18d9SThierry Reding 2071e4710376SSameer Pujar sound { 2072e4710376SSameer Pujar status = "disabled"; 2073e4710376SSameer Pujar 2074e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2075e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2076e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2077e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2078e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2079e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2080e4710376SSameer Pujar assigned-clock-parents = <0>, 2081e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2082e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2083e4710376SSameer Pujar /* 2084e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2085e4710376SSameer Pujar * for this to work and oscillate between base rates required 2086e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2087e4710376SSameer Pujar */ 2088e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2089e4710376SSameer Pujar 2090e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2091e4710376SSameer Pujar }; 2092e4710376SSameer Pujar 209315274c23SMikko Perttunen thermal-zones { 2094fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2095fe57ff53SThierry Reding cpu-thermal { 209615274c23SMikko Perttunen polling-delay = <0>; 209715274c23SMikko Perttunen polling-delay-passive = <1000>; 209815274c23SMikko Perttunen 2099fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 210015274c23SMikko Perttunen 210115274c23SMikko Perttunen trips { 210215274c23SMikko Perttunen critical { 210315274c23SMikko Perttunen temperature = <101000>; 210415274c23SMikko Perttunen hysteresis = <0>; 210515274c23SMikko Perttunen type = "critical"; 210615274c23SMikko Perttunen }; 210715274c23SMikko Perttunen }; 210815274c23SMikko Perttunen 210915274c23SMikko Perttunen cooling-maps { 211015274c23SMikko Perttunen }; 211115274c23SMikko Perttunen }; 211215274c23SMikko Perttunen 2113fe57ff53SThierry Reding /* Denver cluster */ 2114fe57ff53SThierry Reding aux-thermal { 211515274c23SMikko Perttunen polling-delay = <0>; 211615274c23SMikko Perttunen polling-delay-passive = <1000>; 211715274c23SMikko Perttunen 2118fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 211915274c23SMikko Perttunen 212015274c23SMikko Perttunen trips { 212115274c23SMikko Perttunen critical { 212215274c23SMikko Perttunen temperature = <101000>; 212315274c23SMikko Perttunen hysteresis = <0>; 212415274c23SMikko Perttunen type = "critical"; 212515274c23SMikko Perttunen }; 212615274c23SMikko Perttunen }; 212715274c23SMikko Perttunen 212815274c23SMikko Perttunen cooling-maps { 212915274c23SMikko Perttunen }; 213015274c23SMikko Perttunen }; 213115274c23SMikko Perttunen 2132fe57ff53SThierry Reding gpu-thermal { 213315274c23SMikko Perttunen polling-delay = <0>; 213415274c23SMikko Perttunen polling-delay-passive = <1000>; 213515274c23SMikko Perttunen 2136fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 213715274c23SMikko Perttunen 213815274c23SMikko Perttunen trips { 213915274c23SMikko Perttunen critical { 214015274c23SMikko Perttunen temperature = <101000>; 214115274c23SMikko Perttunen hysteresis = <0>; 214215274c23SMikko Perttunen type = "critical"; 214315274c23SMikko Perttunen }; 214415274c23SMikko Perttunen }; 214515274c23SMikko Perttunen 214615274c23SMikko Perttunen cooling-maps { 214715274c23SMikko Perttunen }; 214815274c23SMikko Perttunen }; 214915274c23SMikko Perttunen 2150fe57ff53SThierry Reding pll-thermal { 215115274c23SMikko Perttunen polling-delay = <0>; 215215274c23SMikko Perttunen polling-delay-passive = <1000>; 215315274c23SMikko Perttunen 2154fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 215515274c23SMikko Perttunen 215615274c23SMikko Perttunen trips { 215715274c23SMikko Perttunen critical { 215815274c23SMikko Perttunen temperature = <101000>; 215915274c23SMikko Perttunen hysteresis = <0>; 216015274c23SMikko Perttunen type = "critical"; 216115274c23SMikko Perttunen }; 216215274c23SMikko Perttunen }; 216315274c23SMikko Perttunen 216415274c23SMikko Perttunen cooling-maps { 216515274c23SMikko Perttunen }; 216615274c23SMikko Perttunen }; 216715274c23SMikko Perttunen 2168fe57ff53SThierry Reding ao-thermal { 216915274c23SMikko Perttunen polling-delay = <0>; 217015274c23SMikko Perttunen polling-delay-passive = <1000>; 217115274c23SMikko Perttunen 2172fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 217315274c23SMikko Perttunen 217415274c23SMikko Perttunen trips { 217515274c23SMikko Perttunen critical { 217615274c23SMikko Perttunen temperature = <101000>; 217715274c23SMikko Perttunen hysteresis = <0>; 217815274c23SMikko Perttunen type = "critical"; 217915274c23SMikko Perttunen }; 218015274c23SMikko Perttunen }; 218115274c23SMikko Perttunen 218215274c23SMikko Perttunen cooling-maps { 218315274c23SMikko Perttunen }; 218415274c23SMikko Perttunen }; 218539cb62cbSJoseph Lo }; 218639cb62cbSJoseph Lo 218739cb62cbSJoseph Lo timer { 218839cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 218939cb62cbSJoseph Lo interrupts = <GIC_PPI 13 219039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 219139cb62cbSJoseph Lo <GIC_PPI 14 219239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 219339cb62cbSJoseph Lo <GIC_PPI 11 219439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 219539cb62cbSJoseph Lo <GIC_PPI 10 219639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219739cb62cbSJoseph Lo interrupt-parent = <&gic>; 2198b30be673SThierry Reding always-on; 219939cb62cbSJoseph Lo }; 220039cb62cbSJoseph Lo}; 2201