1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 764b154b94SThierry Reding aconnect@2900000 { 775d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 785d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 795d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 805d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 815d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 825d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 835d2249ddSSameer Pujar #address-cells = <1>; 845d2249ddSSameer Pujar #size-cells = <1>; 855d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 865d2249ddSSameer Pujar status = "disabled"; 875d2249ddSSameer Pujar 88177208f7SSameer Pujar adma: dma-controller@2930000 { 895d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 146177208f7SSameer Pujar reg = <0x02900800 0x800>; 147177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 148177208f7SSameer Pujar clock-names = "ahub"; 149177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151177208f7SSameer Pujar #address-cells = <1>; 152177208f7SSameer Pujar #size-cells = <1>; 153177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 154177208f7SSameer Pujar status = "disabled"; 155177208f7SSameer Pujar 156177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 157177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 158177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 159177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 160177208f7SSameer Pujar <&adma 2>, <&adma 2>, 161177208f7SSameer Pujar <&adma 3>, <&adma 3>, 162177208f7SSameer Pujar <&adma 4>, <&adma 4>, 163177208f7SSameer Pujar <&adma 5>, <&adma 5>, 164177208f7SSameer Pujar <&adma 6>, <&adma 6>, 165177208f7SSameer Pujar <&adma 7>, <&adma 7>, 166177208f7SSameer Pujar <&adma 8>, <&adma 8>, 167177208f7SSameer Pujar <&adma 9>, <&adma 9>, 168177208f7SSameer Pujar <&adma 10>, <&adma 10>, 169177208f7SSameer Pujar <&adma 11>, <&adma 11>, 170177208f7SSameer Pujar <&adma 12>, <&adma 12>, 171177208f7SSameer Pujar <&adma 13>, <&adma 13>, 172177208f7SSameer Pujar <&adma 14>, <&adma 14>, 173177208f7SSameer Pujar <&adma 15>, <&adma 15>, 174177208f7SSameer Pujar <&adma 16>, <&adma 16>, 175177208f7SSameer Pujar <&adma 17>, <&adma 17>, 176177208f7SSameer Pujar <&adma 18>, <&adma 18>, 177177208f7SSameer Pujar <&adma 19>, <&adma 19>, 178177208f7SSameer Pujar <&adma 20>, <&adma 20>; 179177208f7SSameer Pujar dma-names = "rx1", "tx1", 180177208f7SSameer Pujar "rx2", "tx2", 181177208f7SSameer Pujar "rx3", "tx3", 182177208f7SSameer Pujar "rx4", "tx4", 183177208f7SSameer Pujar "rx5", "tx5", 184177208f7SSameer Pujar "rx6", "tx6", 185177208f7SSameer Pujar "rx7", "tx7", 186177208f7SSameer Pujar "rx8", "tx8", 187177208f7SSameer Pujar "rx9", "tx9", 188177208f7SSameer Pujar "rx10", "tx10", 189177208f7SSameer Pujar "rx11", "tx11", 190177208f7SSameer Pujar "rx12", "tx12", 191177208f7SSameer Pujar "rx13", "tx13", 192177208f7SSameer Pujar "rx14", "tx14", 193177208f7SSameer Pujar "rx15", "tx15", 194177208f7SSameer Pujar "rx16", "tx16", 195177208f7SSameer Pujar "rx17", "tx17", 196177208f7SSameer Pujar "rx18", "tx18", 197177208f7SSameer Pujar "rx19", "tx19", 198177208f7SSameer Pujar "rx20", "tx20"; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar }; 201177208f7SSameer Pujar 202177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 203177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 204177208f7SSameer Pujar "nvidia,tegra210-i2s"; 205177208f7SSameer Pujar reg = <0x2901000 0x100>; 206177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 207177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 209177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211177208f7SSameer Pujar assigned-clock-rates = <1536000>; 212177208f7SSameer Pujar sound-name-prefix = "I2S1"; 213177208f7SSameer Pujar status = "disabled"; 214177208f7SSameer Pujar }; 215177208f7SSameer Pujar 216177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 217177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 218177208f7SSameer Pujar "nvidia,tegra210-i2s"; 219177208f7SSameer Pujar reg = <0x2901100 0x100>; 220177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 221177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 223177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225177208f7SSameer Pujar assigned-clock-rates = <1536000>; 226177208f7SSameer Pujar sound-name-prefix = "I2S2"; 227177208f7SSameer Pujar status = "disabled"; 228177208f7SSameer Pujar }; 229177208f7SSameer Pujar 230177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 231177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 232177208f7SSameer Pujar "nvidia,tegra210-i2s"; 233177208f7SSameer Pujar reg = <0x2901200 0x100>; 234177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 235177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239177208f7SSameer Pujar assigned-clock-rates = <1536000>; 240177208f7SSameer Pujar sound-name-prefix = "I2S3"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901300 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S4"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901400 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S5"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901500 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S6"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 287177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 288177208f7SSameer Pujar reg = <0x2904000 0x100>; 289177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290177208f7SSameer Pujar clock-names = "dmic"; 291177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293177208f7SSameer Pujar assigned-clock-rates = <3072000>; 294177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 295177208f7SSameer Pujar status = "disabled"; 296177208f7SSameer Pujar }; 297177208f7SSameer Pujar 298177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 299177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 300177208f7SSameer Pujar reg = <0x2904100 0x100>; 301177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302177208f7SSameer Pujar clock-names = "dmic"; 303177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305177208f7SSameer Pujar assigned-clock-rates = <3072000>; 306177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 307177208f7SSameer Pujar status = "disabled"; 308177208f7SSameer Pujar }; 309177208f7SSameer Pujar 310177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 311177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 312177208f7SSameer Pujar reg = <0x2904200 0x100>; 313177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314177208f7SSameer Pujar clock-names = "dmic"; 315177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317177208f7SSameer Pujar assigned-clock-rates = <3072000>; 318177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 319177208f7SSameer Pujar status = "disabled"; 320177208f7SSameer Pujar }; 321177208f7SSameer Pujar 322177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 323177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 324177208f7SSameer Pujar reg = <0x2904300 0x100>; 325177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326177208f7SSameer Pujar clock-names = "dmic"; 327177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329177208f7SSameer Pujar assigned-clock-rates = <3072000>; 330177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 331177208f7SSameer Pujar status = "disabled"; 332177208f7SSameer Pujar }; 333177208f7SSameer Pujar 334177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 335177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 336177208f7SSameer Pujar reg = <0x2905000 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338177208f7SSameer Pujar clock-names = "dspk"; 339177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341177208f7SSameer Pujar assigned-clock-rates = <12288000>; 342177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 343177208f7SSameer Pujar status = "disabled"; 344177208f7SSameer Pujar }; 345177208f7SSameer Pujar 346177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 347177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 348177208f7SSameer Pujar reg = <0x2905100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350177208f7SSameer Pujar clock-names = "dspk"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <12288000>; 354177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar }; 3585d2249ddSSameer Pujar }; 3595d2249ddSSameer Pujar 360954490b3SThierry Reding mc: memory-controller@2c00000 { 361d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 362d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 363b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 364d25a3bf1SThierry Reding status = "disabled"; 3653f6eaef9SThierry Reding 366954490b3SThierry Reding #interconnect-cells = <1>; 3673f6eaef9SThierry Reding #address-cells = <2>; 3683f6eaef9SThierry Reding #size-cells = <2>; 3693f6eaef9SThierry Reding 3703f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 3713f6eaef9SThierry Reding 3723f6eaef9SThierry Reding /* 3733f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 3743f6eaef9SThierry Reding * controller can address. 3753f6eaef9SThierry Reding */ 3763f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 3773f6eaef9SThierry Reding 3783f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 3793f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 3803f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 3813f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 3823f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 3833f6eaef9SThierry Reding clock-names = "emc"; 3843f6eaef9SThierry Reding 385954490b3SThierry Reding #interconnect-cells = <0>; 386954490b3SThierry Reding 3873f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 3883f6eaef9SThierry Reding }; 389d25a3bf1SThierry Reding }; 390d25a3bf1SThierry Reding 39139cb62cbSJoseph Lo uarta: serial@3100000 { 39239cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 39339cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 39439cb62cbSJoseph Lo reg-shift = <2>; 39539cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 396c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 397a7a77e2eSThierry Reding clock-names = "serial"; 3987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 399a7a77e2eSThierry Reding reset-names = "serial"; 400a7a77e2eSThierry Reding status = "disabled"; 401a7a77e2eSThierry Reding }; 402a7a77e2eSThierry Reding 403a7a77e2eSThierry Reding uartb: serial@3110000 { 404a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 406a7a77e2eSThierry Reding reg-shift = <2>; 407a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 408c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 409a7a77e2eSThierry Reding clock-names = "serial"; 4107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 411a7a77e2eSThierry Reding reset-names = "serial"; 412a7a77e2eSThierry Reding status = "disabled"; 413a7a77e2eSThierry Reding }; 414a7a77e2eSThierry Reding 415a7a77e2eSThierry Reding uartd: serial@3130000 { 416a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 418a7a77e2eSThierry Reding reg-shift = <2>; 419a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 420c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 421a7a77e2eSThierry Reding clock-names = "serial"; 4227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 423a7a77e2eSThierry Reding reset-names = "serial"; 424a7a77e2eSThierry Reding status = "disabled"; 425a7a77e2eSThierry Reding }; 426a7a77e2eSThierry Reding 427a7a77e2eSThierry Reding uarte: serial@3140000 { 428a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 429a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 430a7a77e2eSThierry Reding reg-shift = <2>; 431a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 432c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 433a7a77e2eSThierry Reding clock-names = "serial"; 4347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 435a7a77e2eSThierry Reding reset-names = "serial"; 436a7a77e2eSThierry Reding status = "disabled"; 437a7a77e2eSThierry Reding }; 438a7a77e2eSThierry Reding 439a7a77e2eSThierry Reding uartf: serial@3150000 { 440a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 441a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 442a7a77e2eSThierry Reding reg-shift = <2>; 443a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 444c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 445a7a77e2eSThierry Reding clock-names = "serial"; 4467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 447a7a77e2eSThierry Reding reset-names = "serial"; 44839cb62cbSJoseph Lo status = "disabled"; 44939cb62cbSJoseph Lo }; 45039cb62cbSJoseph Lo 45140cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 452250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 45340cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 45440cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 45540cc83b3SThierry Reding #address-cells = <1>; 45640cc83b3SThierry Reding #size-cells = <0>; 457c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 45840cc83b3SThierry Reding clock-names = "div-clk"; 4597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 46040cc83b3SThierry Reding reset-names = "i2c"; 46140cc83b3SThierry Reding status = "disabled"; 46240cc83b3SThierry Reding }; 46340cc83b3SThierry Reding 46440cc83b3SThierry Reding cam_i2c: i2c@3180000 { 465250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 46640cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 46740cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 46840cc83b3SThierry Reding #address-cells = <1>; 46940cc83b3SThierry Reding #size-cells = <0>; 470c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 47140cc83b3SThierry Reding clock-names = "div-clk"; 4727bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 47340cc83b3SThierry Reding reset-names = "i2c"; 47440cc83b3SThierry Reding status = "disabled"; 47540cc83b3SThierry Reding }; 47640cc83b3SThierry Reding 47740cc83b3SThierry Reding /* shares pads with dpaux1 */ 47840cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 479250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 48040cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 48140cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 48240cc83b3SThierry Reding #address-cells = <1>; 48340cc83b3SThierry Reding #size-cells = <0>; 484c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 48540cc83b3SThierry Reding clock-names = "div-clk"; 4867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 48740cc83b3SThierry Reding reset-names = "i2c"; 488846137c6SThierry Reding pinctrl-names = "default", "idle"; 489846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 490846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 49140cc83b3SThierry Reding status = "disabled"; 49240cc83b3SThierry Reding }; 49340cc83b3SThierry Reding 49440cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 49540cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 496250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 49740cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 49840cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 49940cc83b3SThierry Reding #address-cells = <1>; 50040cc83b3SThierry Reding #size-cells = <0>; 501c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 50240cc83b3SThierry Reding clock-names = "div-clk"; 5037bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 50440cc83b3SThierry Reding reset-names = "i2c"; 50540cc83b3SThierry Reding status = "disabled"; 50640cc83b3SThierry Reding }; 50740cc83b3SThierry Reding 50840cc83b3SThierry Reding /* shares pads with dpaux0 */ 50940cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 510250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 51140cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 51240cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 51340cc83b3SThierry Reding #address-cells = <1>; 51440cc83b3SThierry Reding #size-cells = <0>; 515c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 51640cc83b3SThierry Reding clock-names = "div-clk"; 5177bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 51840cc83b3SThierry Reding reset-names = "i2c"; 519846137c6SThierry Reding pinctrl-names = "default", "idle"; 520846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 521846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 52240cc83b3SThierry Reding status = "disabled"; 52340cc83b3SThierry Reding }; 52440cc83b3SThierry Reding 52540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 526250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 52740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 52840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 52940cc83b3SThierry Reding #address-cells = <1>; 53040cc83b3SThierry Reding #size-cells = <0>; 531c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 53240cc83b3SThierry Reding clock-names = "div-clk"; 5337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 53440cc83b3SThierry Reding reset-names = "i2c"; 53540cc83b3SThierry Reding status = "disabled"; 53640cc83b3SThierry Reding }; 53740cc83b3SThierry Reding 53840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 539250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 54040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 54140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 54240cc83b3SThierry Reding #address-cells = <1>; 54340cc83b3SThierry Reding #size-cells = <0>; 544c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 54540cc83b3SThierry Reding clock-names = "div-clk"; 5467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 54740cc83b3SThierry Reding reset-names = "i2c"; 54840cc83b3SThierry Reding status = "disabled"; 54940cc83b3SThierry Reding }; 55040cc83b3SThierry Reding 551913f8ad4SThierry Reding pwm1: pwm@3280000 { 552913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 553913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 554913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 555913f8ad4SThierry Reding clock-names = "pwm"; 556913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 557913f8ad4SThierry Reding reset-names = "pwm"; 558913f8ad4SThierry Reding status = "disabled"; 559913f8ad4SThierry Reding #pwm-cells = <2>; 560913f8ad4SThierry Reding }; 561913f8ad4SThierry Reding 562913f8ad4SThierry Reding pwm2: pwm@3290000 { 563913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 564913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 565913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 566913f8ad4SThierry Reding clock-names = "pwm"; 567913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 568913f8ad4SThierry Reding reset-names = "pwm"; 569913f8ad4SThierry Reding status = "disabled"; 570913f8ad4SThierry Reding #pwm-cells = <2>; 571913f8ad4SThierry Reding }; 572913f8ad4SThierry Reding 573913f8ad4SThierry Reding pwm3: pwm@32a0000 { 574913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 575913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 576913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 577913f8ad4SThierry Reding clock-names = "pwm"; 578913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 579913f8ad4SThierry Reding reset-names = "pwm"; 580913f8ad4SThierry Reding status = "disabled"; 581913f8ad4SThierry Reding #pwm-cells = <2>; 582913f8ad4SThierry Reding }; 583913f8ad4SThierry Reding 584913f8ad4SThierry Reding pwm5: pwm@32c0000 { 585913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 586913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 587913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 588913f8ad4SThierry Reding clock-names = "pwm"; 589913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 590913f8ad4SThierry Reding reset-names = "pwm"; 591913f8ad4SThierry Reding status = "disabled"; 592913f8ad4SThierry Reding #pwm-cells = <2>; 593913f8ad4SThierry Reding }; 594913f8ad4SThierry Reding 595913f8ad4SThierry Reding pwm6: pwm@32d0000 { 596913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 597913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 598913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 599913f8ad4SThierry Reding clock-names = "pwm"; 600913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 601913f8ad4SThierry Reding reset-names = "pwm"; 602913f8ad4SThierry Reding status = "disabled"; 603913f8ad4SThierry Reding #pwm-cells = <2>; 604913f8ad4SThierry Reding }; 605913f8ad4SThierry Reding 606913f8ad4SThierry Reding pwm7: pwm@32e0000 { 607913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 608913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 609913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 610913f8ad4SThierry Reding clock-names = "pwm"; 611913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 612913f8ad4SThierry Reding reset-names = "pwm"; 613913f8ad4SThierry Reding status = "disabled"; 614913f8ad4SThierry Reding #pwm-cells = <2>; 615913f8ad4SThierry Reding }; 616913f8ad4SThierry Reding 617913f8ad4SThierry Reding pwm8: pwm@32f0000 { 618913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 619913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 620913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 621913f8ad4SThierry Reding clock-names = "pwm"; 622913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 623913f8ad4SThierry Reding reset-names = "pwm"; 624913f8ad4SThierry Reding status = "disabled"; 625913f8ad4SThierry Reding #pwm-cells = <2>; 626913f8ad4SThierry Reding }; 627913f8ad4SThierry Reding 62867bb17f6SThierry Reding sdmmc1: mmc@3400000 { 62999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 63099425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 63199425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 632baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 633baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 634baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 6357bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 63699425dfdSThierry Reding reset-names = "sdhci"; 637954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 638954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 639954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 6408589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 64124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 64224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 64324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 64441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 64541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 64641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 64741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 64841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 64941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 6506f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 6516f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 65298a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 65398a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 65498a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 65599425dfdSThierry Reding status = "disabled"; 65699425dfdSThierry Reding }; 65799425dfdSThierry Reding 65867bb17f6SThierry Reding sdmmc2: mmc@3420000 { 65999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 66099425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 66199425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 662baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 663baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 664baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 6657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 66699425dfdSThierry Reding reset-names = "sdhci"; 667954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 668954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 669954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 6708589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 67124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 67224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 67324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 67441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 67541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 67641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 67741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 6786f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 6796f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 68099425dfdSThierry Reding status = "disabled"; 68199425dfdSThierry Reding }; 68299425dfdSThierry Reding 68367bb17f6SThierry Reding sdmmc3: mmc@3440000 { 68499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 68599425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 68699425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 687baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 688baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 689baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 6907bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 69199425dfdSThierry Reding reset-names = "sdhci"; 692954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 693954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 694954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 6958589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 69624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 69724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 69824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 69941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 70041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 70141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 70241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 70341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 70441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 7056f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 7066f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 70799425dfdSThierry Reding status = "disabled"; 70899425dfdSThierry Reding }; 70999425dfdSThierry Reding 71067bb17f6SThierry Reding sdmmc4: mmc@3460000 { 71199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 71299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 71399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 714baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 715baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 716baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 71798a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 71898a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 71998a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 7207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 72199425dfdSThierry Reding reset-names = "sdhci"; 722954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 723954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 724954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 7258589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 72641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 72741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 72841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 72941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 7304e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 7314e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 732e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 733e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 73422248e91SAapo Vienamo nvidia,dqs-trim = <63>; 735207f60baSAapo Vienamo mmc-hs400-1_8v; 736c4307836SSowjanya Komatineni supports-cqe; 73799425dfdSThierry Reding status = "disabled"; 73899425dfdSThierry Reding }; 73999425dfdSThierry Reding 740b066a310SThierry Reding hda@3510000 { 741b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 742b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 743b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 744b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 745b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 746b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 747b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 748b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 749b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 750b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 751b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 752b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 753954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 754954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 755954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 756dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 757b066a310SThierry Reding status = "disabled"; 758b066a310SThierry Reding }; 759b066a310SThierry Reding 7608bfde518SThierry Reding padctl: padctl@3520000 { 7618bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 7628bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 7638bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 7648bfde518SThierry Reding reg-names = "padctl", "ao"; 7656450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 7668bfde518SThierry Reding 7678bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 7688bfde518SThierry Reding reset-names = "padctl"; 7698bfde518SThierry Reding 7708bfde518SThierry Reding status = "disabled"; 7718bfde518SThierry Reding 7728bfde518SThierry Reding pads { 7738bfde518SThierry Reding usb2 { 7748bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 7758bfde518SThierry Reding clock-names = "trk"; 7768bfde518SThierry Reding status = "disabled"; 7778bfde518SThierry Reding 7788bfde518SThierry Reding lanes { 7798bfde518SThierry Reding usb2-0 { 7808bfde518SThierry Reding status = "disabled"; 7818bfde518SThierry Reding #phy-cells = <0>; 7828bfde518SThierry Reding }; 7838bfde518SThierry Reding 7848bfde518SThierry Reding usb2-1 { 7858bfde518SThierry Reding status = "disabled"; 7868bfde518SThierry Reding #phy-cells = <0>; 7878bfde518SThierry Reding }; 7888bfde518SThierry Reding 7898bfde518SThierry Reding usb2-2 { 7908bfde518SThierry Reding status = "disabled"; 7918bfde518SThierry Reding #phy-cells = <0>; 7928bfde518SThierry Reding }; 7938bfde518SThierry Reding }; 7948bfde518SThierry Reding }; 7958bfde518SThierry Reding 7968bfde518SThierry Reding hsic { 7978bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 7988bfde518SThierry Reding clock-names = "trk"; 7998bfde518SThierry Reding status = "disabled"; 8008bfde518SThierry Reding 8018bfde518SThierry Reding lanes { 8028bfde518SThierry Reding hsic-0 { 8038bfde518SThierry Reding status = "disabled"; 8048bfde518SThierry Reding #phy-cells = <0>; 8058bfde518SThierry Reding }; 8068bfde518SThierry Reding }; 8078bfde518SThierry Reding }; 8088bfde518SThierry Reding 8098bfde518SThierry Reding usb3 { 8108bfde518SThierry Reding status = "disabled"; 8118bfde518SThierry Reding 8128bfde518SThierry Reding lanes { 8138bfde518SThierry Reding usb3-0 { 8148bfde518SThierry Reding status = "disabled"; 8158bfde518SThierry Reding #phy-cells = <0>; 8168bfde518SThierry Reding }; 8178bfde518SThierry Reding 8188bfde518SThierry Reding usb3-1 { 8198bfde518SThierry Reding status = "disabled"; 8208bfde518SThierry Reding #phy-cells = <0>; 8218bfde518SThierry Reding }; 8228bfde518SThierry Reding 8238bfde518SThierry Reding usb3-2 { 8248bfde518SThierry Reding status = "disabled"; 8258bfde518SThierry Reding #phy-cells = <0>; 8268bfde518SThierry Reding }; 8278bfde518SThierry Reding }; 8288bfde518SThierry Reding }; 8298bfde518SThierry Reding }; 8308bfde518SThierry Reding 8318bfde518SThierry Reding ports { 8328bfde518SThierry Reding usb2-0 { 8338bfde518SThierry Reding status = "disabled"; 8348bfde518SThierry Reding }; 8358bfde518SThierry Reding 8368bfde518SThierry Reding usb2-1 { 8378bfde518SThierry Reding status = "disabled"; 8388bfde518SThierry Reding }; 8398bfde518SThierry Reding 8408bfde518SThierry Reding usb2-2 { 8418bfde518SThierry Reding status = "disabled"; 8428bfde518SThierry Reding }; 8438bfde518SThierry Reding 8448bfde518SThierry Reding hsic-0 { 8458bfde518SThierry Reding status = "disabled"; 8468bfde518SThierry Reding }; 8478bfde518SThierry Reding 8488bfde518SThierry Reding usb3-0 { 8498bfde518SThierry Reding status = "disabled"; 8508bfde518SThierry Reding }; 8518bfde518SThierry Reding 8528bfde518SThierry Reding usb3-1 { 8538bfde518SThierry Reding status = "disabled"; 8548bfde518SThierry Reding }; 8558bfde518SThierry Reding 8568bfde518SThierry Reding usb3-2 { 8578bfde518SThierry Reding status = "disabled"; 8588bfde518SThierry Reding }; 8598bfde518SThierry Reding }; 8608bfde518SThierry Reding }; 8618bfde518SThierry Reding 8628bfde518SThierry Reding usb@3530000 { 8638bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 8648bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 8658bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 8668bfde518SThierry Reding reg-names = "hcd", "fpci"; 8678bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 868a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 8698bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 8708bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 8718bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 8728bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 8738bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 8748bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 8758bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 8768bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 8778bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 8788bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 8798bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 8808bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 8818bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 8828bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 8838bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 884954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 885954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 886954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 88706c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 8888bfde518SThierry Reding #address-cells = <1>; 8898bfde518SThierry Reding #size-cells = <0>; 89006c6b06fSThierry Reding status = "disabled"; 89106c6b06fSThierry Reding 89206c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 8938bfde518SThierry Reding }; 8948bfde518SThierry Reding 895584f800cSNagarjuna Kristam usb@3550000 { 896584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 897584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 898584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 899584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 900584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 901584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 902584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 903584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 904584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 905584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 906d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 907d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 908d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 909584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 910584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 911584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 912584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 913584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 914584f800cSNagarjuna Kristam status = "disabled"; 915584f800cSNagarjuna Kristam }; 916584f800cSNagarjuna Kristam 91785593b75SThierry Reding fuse@3820000 { 91885593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 91985593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 92085593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 92185593b75SThierry Reding clock-names = "fuse"; 92285593b75SThierry Reding }; 92385593b75SThierry Reding 92439cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 92539cb62cbSJoseph Lo compatible = "arm,gic-400"; 92639cb62cbSJoseph Lo #interrupt-cells = <3>; 92739cb62cbSJoseph Lo interrupt-controller; 92839cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 929776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 930776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 931776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 93239cb62cbSJoseph Lo interrupts = <GIC_PPI 9 93339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 93439cb62cbSJoseph Lo interrupt-parent = <&gic>; 93539cb62cbSJoseph Lo }; 93639cb62cbSJoseph Lo 93797cf683cSThierry Reding cec@3960000 { 93897cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 93997cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 94097cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 94197cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 94297cf683cSThierry Reding clock-names = "cec"; 94397cf683cSThierry Reding status = "disabled"; 94497cf683cSThierry Reding }; 94597cf683cSThierry Reding 94639cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 94739cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 94839cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 94939cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 95039cb62cbSJoseph Lo interrupt-names = "doorbell"; 95139cb62cbSJoseph Lo #mbox-cells = <2>; 95239cb62cbSJoseph Lo status = "disabled"; 95339cb62cbSJoseph Lo }; 95439cb62cbSJoseph Lo 95540cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 956250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 95740cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 95840cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 95940cc83b3SThierry Reding #address-cells = <1>; 96040cc83b3SThierry Reding #size-cells = <0>; 961c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 96240cc83b3SThierry Reding clock-names = "div-clk"; 9637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 96440cc83b3SThierry Reding reset-names = "i2c"; 96540cc83b3SThierry Reding status = "disabled"; 96640cc83b3SThierry Reding }; 96740cc83b3SThierry Reding 96840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 969250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 97040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 97140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 97240cc83b3SThierry Reding #address-cells = <1>; 97340cc83b3SThierry Reding #size-cells = <0>; 974c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 97540cc83b3SThierry Reding clock-names = "div-clk"; 9767bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 97740cc83b3SThierry Reding reset-names = "i2c"; 97840cc83b3SThierry Reding status = "disabled"; 97940cc83b3SThierry Reding }; 98040cc83b3SThierry Reding 981a7a77e2eSThierry Reding uartc: serial@c280000 { 982a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 983a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 984a7a77e2eSThierry Reding reg-shift = <2>; 985a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 986c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 987a7a77e2eSThierry Reding clock-names = "serial"; 9887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 989a7a77e2eSThierry Reding reset-names = "serial"; 990a7a77e2eSThierry Reding status = "disabled"; 991a7a77e2eSThierry Reding }; 992a7a77e2eSThierry Reding 993a7a77e2eSThierry Reding uartg: serial@c290000 { 994a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 995a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 996a7a77e2eSThierry Reding reg-shift = <2>; 997a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 998c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 999a7a77e2eSThierry Reding clock-names = "serial"; 10007bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1001a7a77e2eSThierry Reding reset-names = "serial"; 1002a7a77e2eSThierry Reding status = "disabled"; 1003a7a77e2eSThierry Reding }; 1004a7a77e2eSThierry Reding 10059733a251SThierry Reding rtc: rtc@c2a0000 { 10069733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 10079733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 10089733a251SThierry Reding interrupt-parent = <&pmc>; 10099733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 10109733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 10119733a251SThierry Reding clock-names = "rtc"; 10129733a251SThierry Reding status = "disabled"; 10139733a251SThierry Reding }; 10149733a251SThierry Reding 1015fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1016fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1017fc4bb754SThierry Reding reg-names = "security", "gpio"; 1018fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1019fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1020fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1021fc4bb754SThierry Reding gpio-controller; 1022fc4bb754SThierry Reding #gpio-cells = <2>; 1023fc4bb754SThierry Reding interrupt-controller; 1024fc4bb754SThierry Reding #interrupt-cells = <2>; 1025fc4bb754SThierry Reding }; 1026fc4bb754SThierry Reding 1027913f8ad4SThierry Reding pwm4: pwm@c340000 { 1028913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1029913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1030913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1031913f8ad4SThierry Reding clock-names = "pwm"; 1032913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1033913f8ad4SThierry Reding reset-names = "pwm"; 1034913f8ad4SThierry Reding status = "disabled"; 1035913f8ad4SThierry Reding #pwm-cells = <2>; 1036913f8ad4SThierry Reding }; 1037913f8ad4SThierry Reding 103832e66e46SThierry Reding pmc: pmc@c360000 { 103973bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 104073bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 104173bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 104273bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 104373bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 104473bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 104524005fd1SAapo Vienamo 104632e66e46SThierry Reding #interrupt-cells = <2>; 104732e66e46SThierry Reding interrupt-controller; 104832e66e46SThierry Reding 104924005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 105024005fd1SAapo Vienamo pins = "sdmmc1-hv"; 105124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 105224005fd1SAapo Vienamo }; 105324005fd1SAapo Vienamo 105424005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 105524005fd1SAapo Vienamo pins = "sdmmc1-hv"; 105624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 105724005fd1SAapo Vienamo }; 105824005fd1SAapo Vienamo 105924005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 106024005fd1SAapo Vienamo pins = "sdmmc2-hv"; 106124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 106224005fd1SAapo Vienamo }; 106324005fd1SAapo Vienamo 106424005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 106524005fd1SAapo Vienamo pins = "sdmmc2-hv"; 106624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 106724005fd1SAapo Vienamo }; 106824005fd1SAapo Vienamo 106924005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 107024005fd1SAapo Vienamo pins = "sdmmc3-hv"; 107124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 107224005fd1SAapo Vienamo }; 107324005fd1SAapo Vienamo 107424005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 107524005fd1SAapo Vienamo pins = "sdmmc3-hv"; 107624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 107724005fd1SAapo Vienamo }; 107873bf90d4SThierry Reding }; 107973bf90d4SThierry Reding 10807b7ef494SMikko Perttunen ccplex@e000000 { 10817b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 10827b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 10837b7ef494SMikko Perttunen 10847b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 10857b7ef494SMikko Perttunen }; 10867b7ef494SMikko Perttunen 1087f8973cf4SManikanta Maddireddy pcie@10003000 { 1088f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1089f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1090f8973cf4SManikanta Maddireddy device_type = "pci"; 1091644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1092644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1093644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1094f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1095f8973cf4SManikanta Maddireddy 1096f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1097f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1098f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1099f8973cf4SManikanta Maddireddy 1100f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1101f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1102f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1103f8973cf4SManikanta Maddireddy 1104f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1105f8973cf4SManikanta Maddireddy #address-cells = <3>; 1106f8973cf4SManikanta Maddireddy #size-cells = <2>; 1107f8973cf4SManikanta Maddireddy 1108644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1109644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1110644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1111644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1112644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1113644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1114f8973cf4SManikanta Maddireddy 111578b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 111678b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1117f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 111878b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1119f8973cf4SManikanta Maddireddy 112078b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 112178b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1122f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 112378b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1124f8973cf4SManikanta Maddireddy 1125954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1126954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1127954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1128954490b3SThierry Reding 1129f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1130f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1131f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1132f2a465e7SThierry Reding 1133f8973cf4SManikanta Maddireddy status = "disabled"; 1134f8973cf4SManikanta Maddireddy 1135f8973cf4SManikanta Maddireddy pci@1,0 { 1136f8973cf4SManikanta Maddireddy device_type = "pci"; 1137f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1138f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1139f8973cf4SManikanta Maddireddy status = "disabled"; 1140f8973cf4SManikanta Maddireddy 1141f8973cf4SManikanta Maddireddy #address-cells = <3>; 1142f8973cf4SManikanta Maddireddy #size-cells = <2>; 1143f8973cf4SManikanta Maddireddy ranges; 1144f8973cf4SManikanta Maddireddy 1145f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1146f8973cf4SManikanta Maddireddy }; 1147f8973cf4SManikanta Maddireddy 1148f8973cf4SManikanta Maddireddy pci@2,0 { 1149f8973cf4SManikanta Maddireddy device_type = "pci"; 1150f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1151f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1152f8973cf4SManikanta Maddireddy status = "disabled"; 1153f8973cf4SManikanta Maddireddy 1154f8973cf4SManikanta Maddireddy #address-cells = <3>; 1155f8973cf4SManikanta Maddireddy #size-cells = <2>; 1156f8973cf4SManikanta Maddireddy ranges; 1157f8973cf4SManikanta Maddireddy 1158f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1159f8973cf4SManikanta Maddireddy }; 1160f8973cf4SManikanta Maddireddy 1161f8973cf4SManikanta Maddireddy pci@3,0 { 1162f8973cf4SManikanta Maddireddy device_type = "pci"; 1163f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1164f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1165f8973cf4SManikanta Maddireddy status = "disabled"; 1166f8973cf4SManikanta Maddireddy 1167f8973cf4SManikanta Maddireddy #address-cells = <3>; 1168f8973cf4SManikanta Maddireddy #size-cells = <2>; 1169f8973cf4SManikanta Maddireddy ranges; 1170f8973cf4SManikanta Maddireddy 1171f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1172f8973cf4SManikanta Maddireddy }; 1173f8973cf4SManikanta Maddireddy }; 1174f8973cf4SManikanta Maddireddy 1175b30a8e61SThierry Reding smmu: iommu@12000000 { 1176bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1177b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1178b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1179b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1180b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1181b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1182b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1183b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1184b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1185b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1186b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1187b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1188b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1189b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1190b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1191b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1192b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1193b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1194b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1195b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1196b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1197b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1198b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1199b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1200b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1201b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1202b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1203b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1204b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1205b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1206b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1207b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1208b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1209b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1210b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1211b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1212b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1213b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1214b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1215b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1216b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1217b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1218b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1219b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1220b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1221b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1222b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1223b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1224b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1225b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1226b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1227b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1228b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1229b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1230b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1231b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1232b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1233b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1234b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1235b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1236b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1237b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1238b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1239b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1240b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1241b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1242b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1243b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1244b30a8e61SThierry Reding #global-interrupts = <1>; 1245b30a8e61SThierry Reding #iommu-cells = <1>; 1246b966d2dbSThierry Reding 1247b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1248b30a8e61SThierry Reding }; 1249b30a8e61SThierry Reding 12505524c61fSMikko Perttunen host1x@13e00000 { 1251ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 12525524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 12535524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 12545524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 12555524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 12565524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1257052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 12585524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 12595524c61fSMikko Perttunen clock-names = "host1x"; 12605524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 12615524c61fSMikko Perttunen reset-names = "host1x"; 12625524c61fSMikko Perttunen 12635524c61fSMikko Perttunen #address-cells = <1>; 12645524c61fSMikko Perttunen #size-cells = <1>; 12655524c61fSMikko Perttunen 12665524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1267954490b3SThierry Reding 1268954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1269954490b3SThierry Reding interconnect-names = "dma-mem"; 1270954490b3SThierry Reding 1271c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1272c2599da7SThierry Reding 1273c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1274c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1275c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1276c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1277c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1278c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1279c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1280c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1281c2599da7SThierry Reding reset-names = "dpaux"; 1282c2599da7SThierry Reding status = "disabled"; 1283c2599da7SThierry Reding 1284c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1285c2599da7SThierry Reding 1286c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1287c2599da7SThierry Reding groups = "dpaux-io"; 1288c2599da7SThierry Reding function = "aux"; 1289c2599da7SThierry Reding }; 1290c2599da7SThierry Reding 1291c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1292c2599da7SThierry Reding groups = "dpaux-io"; 1293c2599da7SThierry Reding function = "i2c"; 1294c2599da7SThierry Reding }; 1295c2599da7SThierry Reding 1296c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1297c2599da7SThierry Reding groups = "dpaux-io"; 1298c2599da7SThierry Reding function = "off"; 1299c2599da7SThierry Reding }; 1300c2599da7SThierry Reding 1301c2599da7SThierry Reding i2c-bus { 1302c2599da7SThierry Reding #address-cells = <1>; 1303c2599da7SThierry Reding #size-cells = <0>; 1304c2599da7SThierry Reding }; 1305c2599da7SThierry Reding }; 1306c2599da7SThierry Reding 1307c2599da7SThierry Reding display-hub@15200000 { 1308aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1309ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1310c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1311c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1312c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1313c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1314c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1315c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1316c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1317c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1318c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1319c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1320c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1321c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1322c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1323c2599da7SThierry Reding status = "disabled"; 1324c2599da7SThierry Reding 1325c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1326c2599da7SThierry Reding 1327c2599da7SThierry Reding #address-cells = <1>; 1328c2599da7SThierry Reding #size-cells = <1>; 1329c2599da7SThierry Reding 1330c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1331c2599da7SThierry Reding 1332c2599da7SThierry Reding display@15200000 { 1333c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1334c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1335c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1336c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1337c2599da7SThierry Reding clock-names = "dc"; 1338c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1339c2599da7SThierry Reding reset-names = "dc"; 1340c2599da7SThierry Reding 1341c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1342954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1343954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1344954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1345c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1346c2599da7SThierry Reding 1347c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1348c2599da7SThierry Reding nvidia,head = <0>; 1349c2599da7SThierry Reding }; 1350c2599da7SThierry Reding 1351c2599da7SThierry Reding display@15210000 { 1352c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1353c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1354c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1355c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1356c2599da7SThierry Reding clock-names = "dc"; 1357c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1358c2599da7SThierry Reding reset-names = "dc"; 1359c2599da7SThierry Reding 1360c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1361954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1362954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1363954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1364c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1365c2599da7SThierry Reding 1366c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1367c2599da7SThierry Reding nvidia,head = <1>; 1368c2599da7SThierry Reding }; 1369c2599da7SThierry Reding 1370c2599da7SThierry Reding display@15220000 { 1371c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1372c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1373c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1374c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1375c2599da7SThierry Reding clock-names = "dc"; 1376c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1377c2599da7SThierry Reding reset-names = "dc"; 1378c2599da7SThierry Reding 1379c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1380954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1381954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1382954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1383c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1384c2599da7SThierry Reding 1385c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1386c2599da7SThierry Reding nvidia,head = <2>; 1387c2599da7SThierry Reding }; 1388c2599da7SThierry Reding }; 1389c2599da7SThierry Reding 1390c2599da7SThierry Reding dsia: dsi@15300000 { 1391c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1392c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1393c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1394c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1395c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1396c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1397c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1398c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1399c2599da7SThierry Reding reset-names = "dsi"; 1400c2599da7SThierry Reding status = "disabled"; 1401c2599da7SThierry Reding 1402c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1403c2599da7SThierry Reding }; 1404effc4b44SMikko Perttunen 1405effc4b44SMikko Perttunen vic@15340000 { 1406effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1407effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1408effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1409effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1410effc4b44SMikko Perttunen clock-names = "vic"; 1411effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1412effc4b44SMikko Perttunen reset-names = "vic"; 1413effc4b44SMikko Perttunen 1414effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1415954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1416954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1417954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 141829ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1419effc4b44SMikko Perttunen }; 1420c2599da7SThierry Reding 1421c2599da7SThierry Reding dsib: dsi@15400000 { 1422c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1423c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1424c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1425c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1426c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1427c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1428c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1429c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1430c2599da7SThierry Reding reset-names = "dsi"; 1431c2599da7SThierry Reding status = "disabled"; 1432c2599da7SThierry Reding 1433c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1434c2599da7SThierry Reding }; 1435c2599da7SThierry Reding 1436*78a05873SMikko Perttunen nvdec@15480000 { 1437*78a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 1438*78a05873SMikko Perttunen reg = <0x15480000 0x40000>; 1439*78a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 1440*78a05873SMikko Perttunen clock-names = "nvdec"; 1441*78a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 1442*78a05873SMikko Perttunen reset-names = "nvdec"; 1443*78a05873SMikko Perttunen 1444*78a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 1445*78a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 1446*78a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 1447*78a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 1448*78a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 1449*78a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 1450*78a05873SMikko Perttunen }; 1451*78a05873SMikko Perttunen 1452c2599da7SThierry Reding sor0: sor@15540000 { 1453c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1454c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1455c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1456c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1457c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1458c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1459c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1460c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1461c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1462c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1463c2599da7SThierry Reding "pad"; 1464c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1465c2599da7SThierry Reding reset-names = "sor"; 1466c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1467c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1468c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1469c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1470c2599da7SThierry Reding status = "disabled"; 1471c2599da7SThierry Reding 1472c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1473c2599da7SThierry Reding nvidia,interface = <0>; 1474c2599da7SThierry Reding }; 1475c2599da7SThierry Reding 1476c2599da7SThierry Reding sor1: sor@15580000 { 1477d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1478c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1479c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1480c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1481c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1482c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1483c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1484c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1485c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1486c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1487c2599da7SThierry Reding "pad"; 1488c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1489c2599da7SThierry Reding reset-names = "sor"; 1490c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1491c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1492c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1493c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1494c2599da7SThierry Reding status = "disabled"; 1495c2599da7SThierry Reding 1496c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1497c2599da7SThierry Reding nvidia,interface = <1>; 1498c2599da7SThierry Reding }; 1499c2599da7SThierry Reding 1500c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1501c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1502c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1503c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1504c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1505c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1506c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1507c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1508c2599da7SThierry Reding reset-names = "dpaux"; 1509c2599da7SThierry Reding status = "disabled"; 1510c2599da7SThierry Reding 1511c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1512c2599da7SThierry Reding 1513c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1514c2599da7SThierry Reding groups = "dpaux-io"; 1515c2599da7SThierry Reding function = "aux"; 1516c2599da7SThierry Reding }; 1517c2599da7SThierry Reding 1518c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1519c2599da7SThierry Reding groups = "dpaux-io"; 1520c2599da7SThierry Reding function = "i2c"; 1521c2599da7SThierry Reding }; 1522c2599da7SThierry Reding 1523c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1524c2599da7SThierry Reding groups = "dpaux-io"; 1525c2599da7SThierry Reding function = "off"; 1526c2599da7SThierry Reding }; 1527c2599da7SThierry Reding 1528c2599da7SThierry Reding i2c-bus { 1529c2599da7SThierry Reding #address-cells = <1>; 1530c2599da7SThierry Reding #size-cells = <0>; 1531c2599da7SThierry Reding }; 1532c2599da7SThierry Reding }; 1533c2599da7SThierry Reding 1534c2599da7SThierry Reding padctl@15880000 { 1535c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1536c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1537c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1538c2599da7SThierry Reding reset-names = "dsi"; 1539c2599da7SThierry Reding status = "disabled"; 1540c2599da7SThierry Reding }; 1541c2599da7SThierry Reding 1542c2599da7SThierry Reding dsic: dsi@15900000 { 1543c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1544c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1545c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1546c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1547c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1548c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1549c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1550c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1551c2599da7SThierry Reding reset-names = "dsi"; 1552c2599da7SThierry Reding status = "disabled"; 1553c2599da7SThierry Reding 1554c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1555c2599da7SThierry Reding }; 1556c2599da7SThierry Reding 1557c2599da7SThierry Reding dsid: dsi@15940000 { 1558c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1559c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1560c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1561c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1562c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1563c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1564c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1565c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1566c2599da7SThierry Reding reset-names = "dsi"; 1567c2599da7SThierry Reding status = "disabled"; 1568c2599da7SThierry Reding 1569c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1570c2599da7SThierry Reding }; 15715524c61fSMikko Perttunen }; 15725524c61fSMikko Perttunen 1573dfd7a384SAlexandre Courbot gpu@17000000 { 1574dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1575dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1576dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 157759a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 157859a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1579dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1580dfd7a384SAlexandre Courbot 1581dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1582dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1583dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1584dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1585dfd7a384SAlexandre Courbot reset-names = "gpu"; 1586dfd7a384SAlexandre Courbot status = "disabled"; 1587dfd7a384SAlexandre Courbot 1588dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1589954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1590954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1591954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1592954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1593954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1594dfd7a384SAlexandre Courbot }; 1595dfd7a384SAlexandre Courbot 1596e867fe41SThierry Reding sram@30000000 { 159739cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 159839cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1599aa78032cSThierry Reding #address-cells = <1>; 1600aa78032cSThierry Reding #size-cells = <1>; 1601aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 160239cb62cbSJoseph Lo 1603e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1604aa78032cSThierry Reding reg = <0x4e000 0x1000>; 160539cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 160639cb62cbSJoseph Lo pool; 160739cb62cbSJoseph Lo }; 160839cb62cbSJoseph Lo 1609e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1610aa78032cSThierry Reding reg = <0x4f000 0x1000>; 161139cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 161239cb62cbSJoseph Lo pool; 161339cb62cbSJoseph Lo }; 161439cb62cbSJoseph Lo }; 161539cb62cbSJoseph Lo 1616e061fbdfSSowjanya Komatineni sata@3507000 { 1617e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1618e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1619e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1620e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1621e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1622e061fbdfSSowjanya Komatineni 1623e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1624e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1625e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1626e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1627e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1628e061fbdfSSowjanya Komatineni 1629e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1630e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1631e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1632e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1633e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1634e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1635e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1636e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1637e061fbdfSSowjanya Komatineni <204000000>; 1638e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1639e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1640e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1641e061fbdfSSowjanya Komatineni status = "disabled"; 1642e061fbdfSSowjanya Komatineni }; 1643e061fbdfSSowjanya Komatineni 1644541d7c44SThierry Reding bpmp: bpmp { 1645541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1646954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1647954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1648954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1649954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1650954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1651541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1652541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1653541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1654541d7c44SThierry Reding shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1655541d7c44SThierry Reding #clock-cells = <1>; 1656541d7c44SThierry Reding #reset-cells = <1>; 1657541d7c44SThierry Reding #power-domain-cells = <1>; 1658541d7c44SThierry Reding 1659541d7c44SThierry Reding bpmp_i2c: i2c { 1660541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1661541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1662541d7c44SThierry Reding #address-cells = <1>; 1663541d7c44SThierry Reding #size-cells = <0>; 1664541d7c44SThierry Reding status = "disabled"; 1665541d7c44SThierry Reding }; 1666541d7c44SThierry Reding 1667541d7c44SThierry Reding bpmp_thermal: thermal { 1668541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1669541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1670541d7c44SThierry Reding }; 1671541d7c44SThierry Reding }; 1672541d7c44SThierry Reding 1673cd6fe32eSThierry Reding cpus { 1674cd6fe32eSThierry Reding #address-cells = <1>; 1675cd6fe32eSThierry Reding #size-cells = <0>; 1676cd6fe32eSThierry Reding 16773b4c1378SMarc Zyngier denver_0: cpu@0 { 167831af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1679cd6fe32eSThierry Reding device_type = "cpu"; 16805298166dSJoseph Lo i-cache-size = <0x20000>; 16815298166dSJoseph Lo i-cache-line-size = <64>; 16825298166dSJoseph Lo i-cache-sets = <512>; 16835298166dSJoseph Lo d-cache-size = <0x10000>; 16845298166dSJoseph Lo d-cache-line-size = <64>; 16855298166dSJoseph Lo d-cache-sets = <256>; 16865298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1687cd6fe32eSThierry Reding reg = <0x000>; 1688cd6fe32eSThierry Reding }; 1689cd6fe32eSThierry Reding 16903b4c1378SMarc Zyngier denver_1: cpu@1 { 169131af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1692cd6fe32eSThierry Reding device_type = "cpu"; 16935298166dSJoseph Lo i-cache-size = <0x20000>; 16945298166dSJoseph Lo i-cache-line-size = <64>; 16955298166dSJoseph Lo i-cache-sets = <512>; 16965298166dSJoseph Lo d-cache-size = <0x10000>; 16975298166dSJoseph Lo d-cache-line-size = <64>; 16985298166dSJoseph Lo d-cache-sets = <256>; 16995298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1700cd6fe32eSThierry Reding reg = <0x001>; 1701cd6fe32eSThierry Reding }; 1702cd6fe32eSThierry Reding 17033b4c1378SMarc Zyngier ca57_0: cpu@2 { 170431af04cdSRob Herring compatible = "arm,cortex-a57"; 1705cd6fe32eSThierry Reding device_type = "cpu"; 17065298166dSJoseph Lo i-cache-size = <0xC000>; 17075298166dSJoseph Lo i-cache-line-size = <64>; 17085298166dSJoseph Lo i-cache-sets = <256>; 17095298166dSJoseph Lo d-cache-size = <0x8000>; 17105298166dSJoseph Lo d-cache-line-size = <64>; 17115298166dSJoseph Lo d-cache-sets = <256>; 17125298166dSJoseph Lo next-level-cache = <&L2_A57>; 1713cd6fe32eSThierry Reding reg = <0x100>; 1714cd6fe32eSThierry Reding }; 1715cd6fe32eSThierry Reding 17163b4c1378SMarc Zyngier ca57_1: cpu@3 { 171731af04cdSRob Herring compatible = "arm,cortex-a57"; 1718cd6fe32eSThierry Reding device_type = "cpu"; 17195298166dSJoseph Lo i-cache-size = <0xC000>; 17205298166dSJoseph Lo i-cache-line-size = <64>; 17215298166dSJoseph Lo i-cache-sets = <256>; 17225298166dSJoseph Lo d-cache-size = <0x8000>; 17235298166dSJoseph Lo d-cache-line-size = <64>; 17245298166dSJoseph Lo d-cache-sets = <256>; 17255298166dSJoseph Lo next-level-cache = <&L2_A57>; 1726cd6fe32eSThierry Reding reg = <0x101>; 1727cd6fe32eSThierry Reding }; 1728cd6fe32eSThierry Reding 17293b4c1378SMarc Zyngier ca57_2: cpu@4 { 173031af04cdSRob Herring compatible = "arm,cortex-a57"; 1731cd6fe32eSThierry Reding device_type = "cpu"; 17325298166dSJoseph Lo i-cache-size = <0xC000>; 17335298166dSJoseph Lo i-cache-line-size = <64>; 17345298166dSJoseph Lo i-cache-sets = <256>; 17355298166dSJoseph Lo d-cache-size = <0x8000>; 17365298166dSJoseph Lo d-cache-line-size = <64>; 17375298166dSJoseph Lo d-cache-sets = <256>; 17385298166dSJoseph Lo next-level-cache = <&L2_A57>; 1739cd6fe32eSThierry Reding reg = <0x102>; 1740cd6fe32eSThierry Reding }; 1741cd6fe32eSThierry Reding 17423b4c1378SMarc Zyngier ca57_3: cpu@5 { 174331af04cdSRob Herring compatible = "arm,cortex-a57"; 1744cd6fe32eSThierry Reding device_type = "cpu"; 17455298166dSJoseph Lo i-cache-size = <0xC000>; 17465298166dSJoseph Lo i-cache-line-size = <64>; 17475298166dSJoseph Lo i-cache-sets = <256>; 17485298166dSJoseph Lo d-cache-size = <0x8000>; 17495298166dSJoseph Lo d-cache-line-size = <64>; 17505298166dSJoseph Lo d-cache-sets = <256>; 17515298166dSJoseph Lo next-level-cache = <&L2_A57>; 1752cd6fe32eSThierry Reding reg = <0x103>; 1753cd6fe32eSThierry Reding }; 17545298166dSJoseph Lo 17555298166dSJoseph Lo L2_DENVER: l2-cache0 { 17565298166dSJoseph Lo compatible = "cache"; 17575298166dSJoseph Lo cache-unified; 17585298166dSJoseph Lo cache-level = <2>; 17595298166dSJoseph Lo cache-size = <0x200000>; 17605298166dSJoseph Lo cache-line-size = <64>; 17615298166dSJoseph Lo cache-sets = <2048>; 17625298166dSJoseph Lo }; 17635298166dSJoseph Lo 17645298166dSJoseph Lo L2_A57: l2-cache1 { 17655298166dSJoseph Lo compatible = "cache"; 17665298166dSJoseph Lo cache-unified; 17675298166dSJoseph Lo cache-level = <2>; 17685298166dSJoseph Lo cache-size = <0x200000>; 17695298166dSJoseph Lo cache-line-size = <64>; 17705298166dSJoseph Lo cache-sets = <2048>; 17715298166dSJoseph Lo }; 1772cd6fe32eSThierry Reding }; 1773cd6fe32eSThierry Reding 17743b4c1378SMarc Zyngier pmu_denver { 17753b4c1378SMarc Zyngier compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; 17763b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 17773b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 17783b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 17793b4c1378SMarc Zyngier }; 17803b4c1378SMarc Zyngier 17813b4c1378SMarc Zyngier pmu_a57 { 17823b4c1378SMarc Zyngier compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; 17833b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 17843b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 17853b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 17863b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 17873b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 17883b4c1378SMarc Zyngier }; 17893b4c1378SMarc Zyngier 1790e4710376SSameer Pujar sound { 1791e4710376SSameer Pujar status = "disabled"; 1792e4710376SSameer Pujar 1793e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 1794e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1795e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 1796e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 1797e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 1798e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 1799e4710376SSameer Pujar assigned-clock-parents = <0>, 1800e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 1801e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 1802e4710376SSameer Pujar /* 1803e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 1804e4710376SSameer Pujar * for this to work and oscillate between base rates required 1805e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 1806e4710376SSameer Pujar */ 1807e4710376SSameer Pujar assigned-clock-rates = <258000000>; 1808e4710376SSameer Pujar 1809e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 1810e4710376SSameer Pujar }; 1811e4710376SSameer Pujar 181215274c23SMikko Perttunen thermal-zones { 181315274c23SMikko Perttunen a57 { 181415274c23SMikko Perttunen polling-delay = <0>; 181515274c23SMikko Perttunen polling-delay-passive = <1000>; 181615274c23SMikko Perttunen 181715274c23SMikko Perttunen thermal-sensors = 181815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 181915274c23SMikko Perttunen 182015274c23SMikko Perttunen trips { 182115274c23SMikko Perttunen critical { 182215274c23SMikko Perttunen temperature = <101000>; 182315274c23SMikko Perttunen hysteresis = <0>; 182415274c23SMikko Perttunen type = "critical"; 182515274c23SMikko Perttunen }; 182615274c23SMikko Perttunen }; 182715274c23SMikko Perttunen 182815274c23SMikko Perttunen cooling-maps { 182915274c23SMikko Perttunen }; 183015274c23SMikko Perttunen }; 183115274c23SMikko Perttunen 183215274c23SMikko Perttunen denver { 183315274c23SMikko Perttunen polling-delay = <0>; 183415274c23SMikko Perttunen polling-delay-passive = <1000>; 183515274c23SMikko Perttunen 183615274c23SMikko Perttunen thermal-sensors = 183715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 183815274c23SMikko Perttunen 183915274c23SMikko Perttunen trips { 184015274c23SMikko Perttunen critical { 184115274c23SMikko Perttunen temperature = <101000>; 184215274c23SMikko Perttunen hysteresis = <0>; 184315274c23SMikko Perttunen type = "critical"; 184415274c23SMikko Perttunen }; 184515274c23SMikko Perttunen }; 184615274c23SMikko Perttunen 184715274c23SMikko Perttunen cooling-maps { 184815274c23SMikko Perttunen }; 184915274c23SMikko Perttunen }; 185015274c23SMikko Perttunen 185115274c23SMikko Perttunen gpu { 185215274c23SMikko Perttunen polling-delay = <0>; 185315274c23SMikko Perttunen polling-delay-passive = <1000>; 185415274c23SMikko Perttunen 185515274c23SMikko Perttunen thermal-sensors = 185615274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 185715274c23SMikko Perttunen 185815274c23SMikko Perttunen trips { 185915274c23SMikko Perttunen critical { 186015274c23SMikko Perttunen temperature = <101000>; 186115274c23SMikko Perttunen hysteresis = <0>; 186215274c23SMikko Perttunen type = "critical"; 186315274c23SMikko Perttunen }; 186415274c23SMikko Perttunen }; 186515274c23SMikko Perttunen 186615274c23SMikko Perttunen cooling-maps { 186715274c23SMikko Perttunen }; 186815274c23SMikko Perttunen }; 186915274c23SMikko Perttunen 187015274c23SMikko Perttunen pll { 187115274c23SMikko Perttunen polling-delay = <0>; 187215274c23SMikko Perttunen polling-delay-passive = <1000>; 187315274c23SMikko Perttunen 187415274c23SMikko Perttunen thermal-sensors = 187515274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 187615274c23SMikko Perttunen 187715274c23SMikko Perttunen trips { 187815274c23SMikko Perttunen critical { 187915274c23SMikko Perttunen temperature = <101000>; 188015274c23SMikko Perttunen hysteresis = <0>; 188115274c23SMikko Perttunen type = "critical"; 188215274c23SMikko Perttunen }; 188315274c23SMikko Perttunen }; 188415274c23SMikko Perttunen 188515274c23SMikko Perttunen cooling-maps { 188615274c23SMikko Perttunen }; 188715274c23SMikko Perttunen }; 188815274c23SMikko Perttunen 188915274c23SMikko Perttunen always_on { 189015274c23SMikko Perttunen polling-delay = <0>; 189115274c23SMikko Perttunen polling-delay-passive = <1000>; 189215274c23SMikko Perttunen 189315274c23SMikko Perttunen thermal-sensors = 189415274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 189515274c23SMikko Perttunen 189615274c23SMikko Perttunen trips { 189715274c23SMikko Perttunen critical { 189815274c23SMikko Perttunen temperature = <101000>; 189915274c23SMikko Perttunen hysteresis = <0>; 190015274c23SMikko Perttunen type = "critical"; 190115274c23SMikko Perttunen }; 190215274c23SMikko Perttunen }; 190315274c23SMikko Perttunen 190415274c23SMikko Perttunen cooling-maps { 190515274c23SMikko Perttunen }; 190615274c23SMikko Perttunen }; 190739cb62cbSJoseph Lo }; 190839cb62cbSJoseph Lo 190939cb62cbSJoseph Lo timer { 191039cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 191139cb62cbSJoseph Lo interrupts = <GIC_PPI 13 191239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 191339cb62cbSJoseph Lo <GIC_PPI 14 191439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 191539cb62cbSJoseph Lo <GIC_PPI 11 191639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 191739cb62cbSJoseph Lo <GIC_PPI 10 191839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 191939cb62cbSJoseph Lo interrupt-parent = <&gic>; 1920b30be673SThierry Reding always-on; 192139cb62cbSJoseph Lo }; 192239cb62cbSJoseph Lo}; 1923