1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112835553b3SAkhil R #dma-cells = <1>; 113835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114835553b3SAkhil R dma-coherent; 115835553b3SAkhil R status = "okay"; 116835553b3SAkhil R }; 117835553b3SAkhil R 1184b154b94SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1815d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1825d2249ddSSameer Pujar clock-names = "clk"; 1835d2249ddSSameer Pujar status = "disabled"; 1845d2249ddSSameer Pujar }; 185177208f7SSameer Pujar 186177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 187177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 188177208f7SSameer Pujar reg = <0x02900800 0x800>; 189177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 190177208f7SSameer Pujar clock-names = "ahub"; 191177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193177208f7SSameer Pujar #address-cells = <1>; 194177208f7SSameer Pujar #size-cells = <1>; 195177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 196177208f7SSameer Pujar status = "disabled"; 197177208f7SSameer Pujar 198177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 199177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 200177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 201177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 202177208f7SSameer Pujar <&adma 2>, <&adma 2>, 203177208f7SSameer Pujar <&adma 3>, <&adma 3>, 204177208f7SSameer Pujar <&adma 4>, <&adma 4>, 205177208f7SSameer Pujar <&adma 5>, <&adma 5>, 206177208f7SSameer Pujar <&adma 6>, <&adma 6>, 207177208f7SSameer Pujar <&adma 7>, <&adma 7>, 208177208f7SSameer Pujar <&adma 8>, <&adma 8>, 209177208f7SSameer Pujar <&adma 9>, <&adma 9>, 210177208f7SSameer Pujar <&adma 10>, <&adma 10>, 211177208f7SSameer Pujar <&adma 11>, <&adma 11>, 212177208f7SSameer Pujar <&adma 12>, <&adma 12>, 213177208f7SSameer Pujar <&adma 13>, <&adma 13>, 214177208f7SSameer Pujar <&adma 14>, <&adma 14>, 215177208f7SSameer Pujar <&adma 15>, <&adma 15>, 216177208f7SSameer Pujar <&adma 16>, <&adma 16>, 217177208f7SSameer Pujar <&adma 17>, <&adma 17>, 218177208f7SSameer Pujar <&adma 18>, <&adma 18>, 219177208f7SSameer Pujar <&adma 19>, <&adma 19>, 220177208f7SSameer Pujar <&adma 20>, <&adma 20>; 221177208f7SSameer Pujar dma-names = "rx1", "tx1", 222177208f7SSameer Pujar "rx2", "tx2", 223177208f7SSameer Pujar "rx3", "tx3", 224177208f7SSameer Pujar "rx4", "tx4", 225177208f7SSameer Pujar "rx5", "tx5", 226177208f7SSameer Pujar "rx6", "tx6", 227177208f7SSameer Pujar "rx7", "tx7", 228177208f7SSameer Pujar "rx8", "tx8", 229177208f7SSameer Pujar "rx9", "tx9", 230177208f7SSameer Pujar "rx10", "tx10", 231177208f7SSameer Pujar "rx11", "tx11", 232177208f7SSameer Pujar "rx12", "tx12", 233177208f7SSameer Pujar "rx13", "tx13", 234177208f7SSameer Pujar "rx14", "tx14", 235177208f7SSameer Pujar "rx15", "tx15", 236177208f7SSameer Pujar "rx16", "tx16", 237177208f7SSameer Pujar "rx17", "tx17", 238177208f7SSameer Pujar "rx18", "tx18", 239177208f7SSameer Pujar "rx19", "tx19", 240177208f7SSameer Pujar "rx20", "tx20"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901000 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S1"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901100 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S2"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901200 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S3"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 287177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 288177208f7SSameer Pujar "nvidia,tegra210-i2s"; 289177208f7SSameer Pujar reg = <0x2901300 0x100>; 290177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 291177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 293177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295177208f7SSameer Pujar assigned-clock-rates = <1536000>; 296177208f7SSameer Pujar sound-name-prefix = "I2S4"; 297177208f7SSameer Pujar status = "disabled"; 298177208f7SSameer Pujar }; 299177208f7SSameer Pujar 300177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 301177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 302177208f7SSameer Pujar "nvidia,tegra210-i2s"; 303177208f7SSameer Pujar reg = <0x2901400 0x100>; 304177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 305177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <1536000>; 310177208f7SSameer Pujar sound-name-prefix = "I2S5"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 315177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 316177208f7SSameer Pujar "nvidia,tegra210-i2s"; 317177208f7SSameer Pujar reg = <0x2901500 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 319177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 321177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323177208f7SSameer Pujar assigned-clock-rates = <1536000>; 324177208f7SSameer Pujar sound-name-prefix = "I2S6"; 325177208f7SSameer Pujar status = "disabled"; 326177208f7SSameer Pujar }; 327177208f7SSameer Pujar 328177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 329177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904000 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 341177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 342177208f7SSameer Pujar reg = <0x2904100 0x100>; 343177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344177208f7SSameer Pujar clock-names = "dmic"; 345177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347177208f7SSameer Pujar assigned-clock-rates = <3072000>; 348177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 349177208f7SSameer Pujar status = "disabled"; 350177208f7SSameer Pujar }; 351177208f7SSameer Pujar 352177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 353177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 354177208f7SSameer Pujar reg = <0x2904200 0x100>; 355177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356177208f7SSameer Pujar clock-names = "dmic"; 357177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359177208f7SSameer Pujar assigned-clock-rates = <3072000>; 360177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 361177208f7SSameer Pujar status = "disabled"; 362177208f7SSameer Pujar }; 363177208f7SSameer Pujar 364177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 365177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 366177208f7SSameer Pujar reg = <0x2904300 0x100>; 367177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368177208f7SSameer Pujar clock-names = "dmic"; 369177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371177208f7SSameer Pujar assigned-clock-rates = <3072000>; 372177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 373177208f7SSameer Pujar status = "disabled"; 374177208f7SSameer Pujar }; 375177208f7SSameer Pujar 376177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 377177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 378177208f7SSameer Pujar reg = <0x2905000 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380177208f7SSameer Pujar clock-names = "dspk"; 381177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383177208f7SSameer Pujar assigned-clock-rates = <12288000>; 384177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 385177208f7SSameer Pujar status = "disabled"; 386177208f7SSameer Pujar }; 387177208f7SSameer Pujar 388177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 389177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 390177208f7SSameer Pujar reg = <0x2905100 0x100>; 391177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392177208f7SSameer Pujar clock-names = "dspk"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <12288000>; 396177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399848f3290SSameer Pujar 400848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 401848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 402848f3290SSameer Pujar "nvidia,tegra210-sfc"; 403848f3290SSameer Pujar reg = <0x2902000 0x200>; 404848f3290SSameer Pujar sound-name-prefix = "SFC1"; 405848f3290SSameer Pujar status = "disabled"; 406848f3290SSameer Pujar }; 407848f3290SSameer Pujar 408848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 409848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 410848f3290SSameer Pujar "nvidia,tegra210-sfc"; 411848f3290SSameer Pujar reg = <0x2902200 0x200>; 412848f3290SSameer Pujar sound-name-prefix = "SFC2"; 413848f3290SSameer Pujar status = "disabled"; 414848f3290SSameer Pujar }; 415848f3290SSameer Pujar 416848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 417848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 418848f3290SSameer Pujar "nvidia,tegra210-sfc"; 419848f3290SSameer Pujar reg = <0x2902400 0x200>; 420848f3290SSameer Pujar sound-name-prefix = "SFC3"; 421848f3290SSameer Pujar status = "disabled"; 422848f3290SSameer Pujar }; 423848f3290SSameer Pujar 424848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 425848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 426848f3290SSameer Pujar "nvidia,tegra210-sfc"; 427848f3290SSameer Pujar reg = <0x2902600 0x200>; 428848f3290SSameer Pujar sound-name-prefix = "SFC4"; 429848f3290SSameer Pujar status = "disabled"; 430848f3290SSameer Pujar }; 431848f3290SSameer Pujar 432848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 433848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 434848f3290SSameer Pujar "nvidia,tegra210-mvc"; 435848f3290SSameer Pujar reg = <0x290a000 0x200>; 436848f3290SSameer Pujar sound-name-prefix = "MVC1"; 437848f3290SSameer Pujar status = "disabled"; 438848f3290SSameer Pujar }; 439848f3290SSameer Pujar 440848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 441848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 442848f3290SSameer Pujar "nvidia,tegra210-mvc"; 443848f3290SSameer Pujar reg = <0x290a200 0x200>; 444848f3290SSameer Pujar sound-name-prefix = "MVC2"; 445848f3290SSameer Pujar status = "disabled"; 446848f3290SSameer Pujar }; 447848f3290SSameer Pujar 448848f3290SSameer Pujar tegra_amx1: amx@2903000 { 449848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 450848f3290SSameer Pujar "nvidia,tegra210-amx"; 451848f3290SSameer Pujar reg = <0x2903000 0x100>; 452848f3290SSameer Pujar sound-name-prefix = "AMX1"; 453848f3290SSameer Pujar status = "disabled"; 454848f3290SSameer Pujar }; 455848f3290SSameer Pujar 456848f3290SSameer Pujar tegra_amx2: amx@2903100 { 457848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 458848f3290SSameer Pujar "nvidia,tegra210-amx"; 459848f3290SSameer Pujar reg = <0x2903100 0x100>; 460848f3290SSameer Pujar sound-name-prefix = "AMX2"; 461848f3290SSameer Pujar status = "disabled"; 462848f3290SSameer Pujar }; 463848f3290SSameer Pujar 464848f3290SSameer Pujar tegra_amx3: amx@2903200 { 465848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 466848f3290SSameer Pujar "nvidia,tegra210-amx"; 467848f3290SSameer Pujar reg = <0x2903200 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX3"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx4: amx@2903300 { 473848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 474848f3290SSameer Pujar "nvidia,tegra210-amx"; 475848f3290SSameer Pujar reg = <0x2903300 0x100>; 476848f3290SSameer Pujar sound-name-prefix = "AMX4"; 477848f3290SSameer Pujar status = "disabled"; 478848f3290SSameer Pujar }; 479848f3290SSameer Pujar 480848f3290SSameer Pujar tegra_adx1: adx@2903800 { 481848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 482848f3290SSameer Pujar "nvidia,tegra210-adx"; 483848f3290SSameer Pujar reg = <0x2903800 0x100>; 484848f3290SSameer Pujar sound-name-prefix = "ADX1"; 485848f3290SSameer Pujar status = "disabled"; 486848f3290SSameer Pujar }; 487848f3290SSameer Pujar 488848f3290SSameer Pujar tegra_adx2: adx@2903900 { 489848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 490848f3290SSameer Pujar "nvidia,tegra210-adx"; 491848f3290SSameer Pujar reg = <0x2903900 0x100>; 492848f3290SSameer Pujar sound-name-prefix = "ADX2"; 493848f3290SSameer Pujar status = "disabled"; 494848f3290SSameer Pujar }; 495848f3290SSameer Pujar 496848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 497848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 498848f3290SSameer Pujar "nvidia,tegra210-adx"; 499848f3290SSameer Pujar reg = <0x2903a00 0x100>; 500848f3290SSameer Pujar sound-name-prefix = "ADX3"; 501848f3290SSameer Pujar status = "disabled"; 502848f3290SSameer Pujar }; 503848f3290SSameer Pujar 504848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 505848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 506848f3290SSameer Pujar "nvidia,tegra210-adx"; 507848f3290SSameer Pujar reg = <0x2903b00 0x100>; 508848f3290SSameer Pujar sound-name-prefix = "ADX4"; 509848f3290SSameer Pujar status = "disabled"; 510848f3290SSameer Pujar }; 511848f3290SSameer Pujar 512848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 513848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 514848f3290SSameer Pujar "nvidia,tegra210-amixer"; 515848f3290SSameer Pujar reg = <0x290bb00 0x800>; 516848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 517848f3290SSameer Pujar status = "disabled"; 518848f3290SSameer Pujar }; 519*47a08153SSameer Pujar 520*47a08153SSameer Pujar tegra_asrc: asrc@2910000 { 521*47a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 522*47a08153SSameer Pujar reg = <0x2910000 0x2000>; 523*47a08153SSameer Pujar sound-name-prefix = "ASRC1"; 524*47a08153SSameer Pujar status = "disabled"; 525*47a08153SSameer Pujar }; 526177208f7SSameer Pujar }; 5275d2249ddSSameer Pujar }; 5285d2249ddSSameer Pujar 529954490b3SThierry Reding mc: memory-controller@2c00000 { 530d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 531d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 532b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 533d25a3bf1SThierry Reding status = "disabled"; 5343f6eaef9SThierry Reding 535954490b3SThierry Reding #interconnect-cells = <1>; 5363f6eaef9SThierry Reding #address-cells = <2>; 5373f6eaef9SThierry Reding #size-cells = <2>; 5383f6eaef9SThierry Reding 5393f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5403f6eaef9SThierry Reding 5413f6eaef9SThierry Reding /* 5423f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5433f6eaef9SThierry Reding * controller can address. 5443f6eaef9SThierry Reding */ 5453f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5463f6eaef9SThierry Reding 5473f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5483f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5493f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5503f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5513f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5523f6eaef9SThierry Reding clock-names = "emc"; 5533f6eaef9SThierry Reding 554954490b3SThierry Reding #interconnect-cells = <0>; 555954490b3SThierry Reding 5563f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5573f6eaef9SThierry Reding }; 558d25a3bf1SThierry Reding }; 559d25a3bf1SThierry Reding 560bd1fefcbSThierry Reding timer@3010000 { 561bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 562bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 563bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 564bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 565bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 566bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 567bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 568bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 569bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 570bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 571bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 572bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 573bd1fefcbSThierry Reding status = "disabled"; 574bd1fefcbSThierry Reding }; 575bd1fefcbSThierry Reding 57639cb62cbSJoseph Lo uarta: serial@3100000 { 57739cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 57839cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 57939cb62cbSJoseph Lo reg-shift = <2>; 58039cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 581c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 582a7a77e2eSThierry Reding clock-names = "serial"; 5837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 584a7a77e2eSThierry Reding reset-names = "serial"; 585a7a77e2eSThierry Reding status = "disabled"; 586a7a77e2eSThierry Reding }; 587a7a77e2eSThierry Reding 588a7a77e2eSThierry Reding uartb: serial@3110000 { 589a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 590a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 591a7a77e2eSThierry Reding reg-shift = <2>; 592a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 593c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 594a7a77e2eSThierry Reding clock-names = "serial"; 5957bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 596a7a77e2eSThierry Reding reset-names = "serial"; 597a7a77e2eSThierry Reding status = "disabled"; 598a7a77e2eSThierry Reding }; 599a7a77e2eSThierry Reding 600a7a77e2eSThierry Reding uartd: serial@3130000 { 601a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 602a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 603a7a77e2eSThierry Reding reg-shift = <2>; 604a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 605c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 606a7a77e2eSThierry Reding clock-names = "serial"; 6077bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 608a7a77e2eSThierry Reding reset-names = "serial"; 609a7a77e2eSThierry Reding status = "disabled"; 610a7a77e2eSThierry Reding }; 611a7a77e2eSThierry Reding 612a7a77e2eSThierry Reding uarte: serial@3140000 { 613a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 614a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 615a7a77e2eSThierry Reding reg-shift = <2>; 616a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 617c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 618a7a77e2eSThierry Reding clock-names = "serial"; 6197bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 620a7a77e2eSThierry Reding reset-names = "serial"; 621a7a77e2eSThierry Reding status = "disabled"; 622a7a77e2eSThierry Reding }; 623a7a77e2eSThierry Reding 624a7a77e2eSThierry Reding uartf: serial@3150000 { 625a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 626a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 627a7a77e2eSThierry Reding reg-shift = <2>; 628a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 629c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 630a7a77e2eSThierry Reding clock-names = "serial"; 6317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 632a7a77e2eSThierry Reding reset-names = "serial"; 63339cb62cbSJoseph Lo status = "disabled"; 63439cb62cbSJoseph Lo }; 63539cb62cbSJoseph Lo 63640cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 637548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 63840cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 63940cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 64040cc83b3SThierry Reding #address-cells = <1>; 64140cc83b3SThierry Reding #size-cells = <0>; 642c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 64340cc83b3SThierry Reding clock-names = "div-clk"; 6447bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 64540cc83b3SThierry Reding reset-names = "i2c"; 64640cc83b3SThierry Reding status = "disabled"; 64740cc83b3SThierry Reding }; 64840cc83b3SThierry Reding 64940cc83b3SThierry Reding cam_i2c: i2c@3180000 { 650548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 65140cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 65240cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 65340cc83b3SThierry Reding #address-cells = <1>; 65440cc83b3SThierry Reding #size-cells = <0>; 655c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 65640cc83b3SThierry Reding clock-names = "div-clk"; 6577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 65840cc83b3SThierry Reding reset-names = "i2c"; 65940cc83b3SThierry Reding status = "disabled"; 66040cc83b3SThierry Reding }; 66140cc83b3SThierry Reding 66240cc83b3SThierry Reding /* shares pads with dpaux1 */ 66340cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 664548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 66540cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 66640cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 66740cc83b3SThierry Reding #address-cells = <1>; 66840cc83b3SThierry Reding #size-cells = <0>; 669c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 67040cc83b3SThierry Reding clock-names = "div-clk"; 6717bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 67240cc83b3SThierry Reding reset-names = "i2c"; 673846137c6SThierry Reding pinctrl-names = "default", "idle"; 674846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 675846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 67640cc83b3SThierry Reding status = "disabled"; 67740cc83b3SThierry Reding }; 67840cc83b3SThierry Reding 67940cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 68040cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 681548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68240cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 68340cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 68440cc83b3SThierry Reding #address-cells = <1>; 68540cc83b3SThierry Reding #size-cells = <0>; 686c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 68740cc83b3SThierry Reding clock-names = "div-clk"; 6887bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 68940cc83b3SThierry Reding reset-names = "i2c"; 69040cc83b3SThierry Reding status = "disabled"; 69140cc83b3SThierry Reding }; 69240cc83b3SThierry Reding 69340cc83b3SThierry Reding /* shares pads with dpaux0 */ 69440cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 695548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 69640cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 69740cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 69840cc83b3SThierry Reding #address-cells = <1>; 69940cc83b3SThierry Reding #size-cells = <0>; 700c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 70140cc83b3SThierry Reding clock-names = "div-clk"; 7027bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 70340cc83b3SThierry Reding reset-names = "i2c"; 704846137c6SThierry Reding pinctrl-names = "default", "idle"; 705846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 706846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 70740cc83b3SThierry Reding status = "disabled"; 70840cc83b3SThierry Reding }; 70940cc83b3SThierry Reding 71040cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 711548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 71240cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 71340cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 71440cc83b3SThierry Reding #address-cells = <1>; 71540cc83b3SThierry Reding #size-cells = <0>; 716c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 71740cc83b3SThierry Reding clock-names = "div-clk"; 7187bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 71940cc83b3SThierry Reding reset-names = "i2c"; 72040cc83b3SThierry Reding status = "disabled"; 72140cc83b3SThierry Reding }; 72240cc83b3SThierry Reding 72340cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 724548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 72540cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 72640cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 72740cc83b3SThierry Reding #address-cells = <1>; 72840cc83b3SThierry Reding #size-cells = <0>; 729c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 73040cc83b3SThierry Reding clock-names = "div-clk"; 7317bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 73240cc83b3SThierry Reding reset-names = "i2c"; 73340cc83b3SThierry Reding status = "disabled"; 73440cc83b3SThierry Reding }; 73540cc83b3SThierry Reding 736913f8ad4SThierry Reding pwm1: pwm@3280000 { 737913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 738913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 739913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 740913f8ad4SThierry Reding clock-names = "pwm"; 741913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 742913f8ad4SThierry Reding reset-names = "pwm"; 743913f8ad4SThierry Reding status = "disabled"; 744913f8ad4SThierry Reding #pwm-cells = <2>; 745913f8ad4SThierry Reding }; 746913f8ad4SThierry Reding 747913f8ad4SThierry Reding pwm2: pwm@3290000 { 748913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 749913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 750913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 751913f8ad4SThierry Reding clock-names = "pwm"; 752913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 753913f8ad4SThierry Reding reset-names = "pwm"; 754913f8ad4SThierry Reding status = "disabled"; 755913f8ad4SThierry Reding #pwm-cells = <2>; 756913f8ad4SThierry Reding }; 757913f8ad4SThierry Reding 758913f8ad4SThierry Reding pwm3: pwm@32a0000 { 759913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 760913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 761913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 762913f8ad4SThierry Reding clock-names = "pwm"; 763913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 764913f8ad4SThierry Reding reset-names = "pwm"; 765913f8ad4SThierry Reding status = "disabled"; 766913f8ad4SThierry Reding #pwm-cells = <2>; 767913f8ad4SThierry Reding }; 768913f8ad4SThierry Reding 769913f8ad4SThierry Reding pwm5: pwm@32c0000 { 770913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 771913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 772913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 773913f8ad4SThierry Reding clock-names = "pwm"; 774913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 775913f8ad4SThierry Reding reset-names = "pwm"; 776913f8ad4SThierry Reding status = "disabled"; 777913f8ad4SThierry Reding #pwm-cells = <2>; 778913f8ad4SThierry Reding }; 779913f8ad4SThierry Reding 780913f8ad4SThierry Reding pwm6: pwm@32d0000 { 781913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 782913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 783913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 784913f8ad4SThierry Reding clock-names = "pwm"; 785913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 786913f8ad4SThierry Reding reset-names = "pwm"; 787913f8ad4SThierry Reding status = "disabled"; 788913f8ad4SThierry Reding #pwm-cells = <2>; 789913f8ad4SThierry Reding }; 790913f8ad4SThierry Reding 791913f8ad4SThierry Reding pwm7: pwm@32e0000 { 792913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 793913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 794913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 795913f8ad4SThierry Reding clock-names = "pwm"; 796913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 797913f8ad4SThierry Reding reset-names = "pwm"; 798913f8ad4SThierry Reding status = "disabled"; 799913f8ad4SThierry Reding #pwm-cells = <2>; 800913f8ad4SThierry Reding }; 801913f8ad4SThierry Reding 802913f8ad4SThierry Reding pwm8: pwm@32f0000 { 803913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 804913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 805913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 806913f8ad4SThierry Reding clock-names = "pwm"; 807913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 808913f8ad4SThierry Reding reset-names = "pwm"; 809913f8ad4SThierry Reding status = "disabled"; 810913f8ad4SThierry Reding #pwm-cells = <2>; 811913f8ad4SThierry Reding }; 812913f8ad4SThierry Reding 81367bb17f6SThierry Reding sdmmc1: mmc@3400000 { 81499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 81599425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 81699425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 817baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 818baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 819baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 82199425dfdSThierry Reding reset-names = "sdhci"; 822954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 823954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 824954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8258589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 82624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 82724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 82824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 82941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 83041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 83141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 83241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 83341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 83441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8356f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8366f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 83798a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 83898a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 83998a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 84099425dfdSThierry Reding status = "disabled"; 84199425dfdSThierry Reding }; 84299425dfdSThierry Reding 84367bb17f6SThierry Reding sdmmc2: mmc@3420000 { 84499425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 84599425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 84699425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 847baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 848baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 849baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8507bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 85199425dfdSThierry Reding reset-names = "sdhci"; 852954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 853954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 854954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8558589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 85624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 85724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 85824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 85941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 86041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 86141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 86241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8636f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8646f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 86599425dfdSThierry Reding status = "disabled"; 86699425dfdSThierry Reding }; 86799425dfdSThierry Reding 86867bb17f6SThierry Reding sdmmc3: mmc@3440000 { 86999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 87099425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 87199425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 872baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 873baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 874baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8757bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 87699425dfdSThierry Reding reset-names = "sdhci"; 877954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 878954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 879954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8808589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 88124005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 88224005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 88324005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 88441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 88541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 88641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 88741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 88841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 88941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8906f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8916f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 89299425dfdSThierry Reding status = "disabled"; 89399425dfdSThierry Reding }; 89499425dfdSThierry Reding 89567bb17f6SThierry Reding sdmmc4: mmc@3460000 { 89699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 89799425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 89899425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 899baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 900baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 901baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 90298a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 90398a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 90498a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9057bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 90699425dfdSThierry Reding reset-names = "sdhci"; 907954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 908954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 909954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9108589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 91141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 91241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 91341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 91441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9154e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 917e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 918e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 91922248e91SAapo Vienamo nvidia,dqs-trim = <63>; 920207f60baSAapo Vienamo mmc-hs400-1_8v; 921c4307836SSowjanya Komatineni supports-cqe; 92299425dfdSThierry Reding status = "disabled"; 92399425dfdSThierry Reding }; 92499425dfdSThierry Reding 925b066a310SThierry Reding hda@3510000 { 926b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 927b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 928b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 929b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 930b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 931b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 932b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 933b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 934b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 935b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 936b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 937b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 938954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 939954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 940954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 941dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 942b066a310SThierry Reding status = "disabled"; 943b066a310SThierry Reding }; 944b066a310SThierry Reding 9458bfde518SThierry Reding padctl: padctl@3520000 { 9468bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 9478bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 9488bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 9498bfde518SThierry Reding reg-names = "padctl", "ao"; 9506450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 9518bfde518SThierry Reding 9528bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 9538bfde518SThierry Reding reset-names = "padctl"; 9548bfde518SThierry Reding 9558bfde518SThierry Reding status = "disabled"; 9568bfde518SThierry Reding 9578bfde518SThierry Reding pads { 9588bfde518SThierry Reding usb2 { 9598bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 9608bfde518SThierry Reding clock-names = "trk"; 9618bfde518SThierry Reding status = "disabled"; 9628bfde518SThierry Reding 9638bfde518SThierry Reding lanes { 9648bfde518SThierry Reding usb2-0 { 9658bfde518SThierry Reding status = "disabled"; 9668bfde518SThierry Reding #phy-cells = <0>; 9678bfde518SThierry Reding }; 9688bfde518SThierry Reding 9698bfde518SThierry Reding usb2-1 { 9708bfde518SThierry Reding status = "disabled"; 9718bfde518SThierry Reding #phy-cells = <0>; 9728bfde518SThierry Reding }; 9738bfde518SThierry Reding 9748bfde518SThierry Reding usb2-2 { 9758bfde518SThierry Reding status = "disabled"; 9768bfde518SThierry Reding #phy-cells = <0>; 9778bfde518SThierry Reding }; 9788bfde518SThierry Reding }; 9798bfde518SThierry Reding }; 9808bfde518SThierry Reding 9818bfde518SThierry Reding hsic { 9828bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 9838bfde518SThierry Reding clock-names = "trk"; 9848bfde518SThierry Reding status = "disabled"; 9858bfde518SThierry Reding 9868bfde518SThierry Reding lanes { 9878bfde518SThierry Reding hsic-0 { 9888bfde518SThierry Reding status = "disabled"; 9898bfde518SThierry Reding #phy-cells = <0>; 9908bfde518SThierry Reding }; 9918bfde518SThierry Reding }; 9928bfde518SThierry Reding }; 9938bfde518SThierry Reding 9948bfde518SThierry Reding usb3 { 9958bfde518SThierry Reding status = "disabled"; 9968bfde518SThierry Reding 9978bfde518SThierry Reding lanes { 9988bfde518SThierry Reding usb3-0 { 9998bfde518SThierry Reding status = "disabled"; 10008bfde518SThierry Reding #phy-cells = <0>; 10018bfde518SThierry Reding }; 10028bfde518SThierry Reding 10038bfde518SThierry Reding usb3-1 { 10048bfde518SThierry Reding status = "disabled"; 10058bfde518SThierry Reding #phy-cells = <0>; 10068bfde518SThierry Reding }; 10078bfde518SThierry Reding 10088bfde518SThierry Reding usb3-2 { 10098bfde518SThierry Reding status = "disabled"; 10108bfde518SThierry Reding #phy-cells = <0>; 10118bfde518SThierry Reding }; 10128bfde518SThierry Reding }; 10138bfde518SThierry Reding }; 10148bfde518SThierry Reding }; 10158bfde518SThierry Reding 10168bfde518SThierry Reding ports { 10178bfde518SThierry Reding usb2-0 { 10188bfde518SThierry Reding status = "disabled"; 10198bfde518SThierry Reding }; 10208bfde518SThierry Reding 10218bfde518SThierry Reding usb2-1 { 10228bfde518SThierry Reding status = "disabled"; 10238bfde518SThierry Reding }; 10248bfde518SThierry Reding 10258bfde518SThierry Reding usb2-2 { 10268bfde518SThierry Reding status = "disabled"; 10278bfde518SThierry Reding }; 10288bfde518SThierry Reding 10298bfde518SThierry Reding hsic-0 { 10308bfde518SThierry Reding status = "disabled"; 10318bfde518SThierry Reding }; 10328bfde518SThierry Reding 10338bfde518SThierry Reding usb3-0 { 10348bfde518SThierry Reding status = "disabled"; 10358bfde518SThierry Reding }; 10368bfde518SThierry Reding 10378bfde518SThierry Reding usb3-1 { 10388bfde518SThierry Reding status = "disabled"; 10398bfde518SThierry Reding }; 10408bfde518SThierry Reding 10418bfde518SThierry Reding usb3-2 { 10428bfde518SThierry Reding status = "disabled"; 10438bfde518SThierry Reding }; 10448bfde518SThierry Reding }; 10458bfde518SThierry Reding }; 10468bfde518SThierry Reding 10478bfde518SThierry Reding usb@3530000 { 10488bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 10498bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 10508bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 10518bfde518SThierry Reding reg-names = "hcd", "fpci"; 10528bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1053a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 10548bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 10558bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 10568bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 10578bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 10588bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10598bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 10608bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 10618bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10628bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 10638bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 10648bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 10658bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 10668bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 10678bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 10688bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1069954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1070954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1071954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 107206c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 10738bfde518SThierry Reding #address-cells = <1>; 10748bfde518SThierry Reding #size-cells = <0>; 107506c6b06fSThierry Reding status = "disabled"; 107606c6b06fSThierry Reding 107706c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 10788bfde518SThierry Reding }; 10798bfde518SThierry Reding 1080584f800cSNagarjuna Kristam usb@3550000 { 1081584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1082584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1083584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1084584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1085584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1086584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1087584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1088584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1089584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1090584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1091d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1092d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1093d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1094584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1095584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1096584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1097584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1098584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1099584f800cSNagarjuna Kristam status = "disabled"; 1100584f800cSNagarjuna Kristam }; 1101584f800cSNagarjuna Kristam 110285593b75SThierry Reding fuse@3820000 { 110385593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 110485593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 110585593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 110685593b75SThierry Reding clock-names = "fuse"; 110785593b75SThierry Reding }; 110885593b75SThierry Reding 110939cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 111039cb62cbSJoseph Lo compatible = "arm,gic-400"; 111139cb62cbSJoseph Lo #interrupt-cells = <3>; 111239cb62cbSJoseph Lo interrupt-controller; 111339cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1114776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1115776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1116776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 111739cb62cbSJoseph Lo interrupts = <GIC_PPI 9 111839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 111939cb62cbSJoseph Lo interrupt-parent = <&gic>; 112039cb62cbSJoseph Lo }; 112139cb62cbSJoseph Lo 112297cf683cSThierry Reding cec@3960000 { 112397cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 112497cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 112597cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 112697cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 112797cf683cSThierry Reding clock-names = "cec"; 112897cf683cSThierry Reding status = "disabled"; 112997cf683cSThierry Reding }; 113097cf683cSThierry Reding 113139cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 113239cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 113339cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 113439cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 113539cb62cbSJoseph Lo interrupt-names = "doorbell"; 113639cb62cbSJoseph Lo #mbox-cells = <2>; 113739cb62cbSJoseph Lo status = "disabled"; 113839cb62cbSJoseph Lo }; 113939cb62cbSJoseph Lo 114040cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1141548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 114240cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 114340cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 114440cc83b3SThierry Reding #address-cells = <1>; 114540cc83b3SThierry Reding #size-cells = <0>; 1146c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 114740cc83b3SThierry Reding clock-names = "div-clk"; 11487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 114940cc83b3SThierry Reding reset-names = "i2c"; 115040cc83b3SThierry Reding status = "disabled"; 115140cc83b3SThierry Reding }; 115240cc83b3SThierry Reding 115340cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1154548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 115540cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 115640cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 115740cc83b3SThierry Reding #address-cells = <1>; 115840cc83b3SThierry Reding #size-cells = <0>; 1159c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 116040cc83b3SThierry Reding clock-names = "div-clk"; 11617bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 116240cc83b3SThierry Reding reset-names = "i2c"; 116340cc83b3SThierry Reding status = "disabled"; 116440cc83b3SThierry Reding }; 116540cc83b3SThierry Reding 1166a7a77e2eSThierry Reding uartc: serial@c280000 { 1167a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1168a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1169a7a77e2eSThierry Reding reg-shift = <2>; 1170a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1171c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1172a7a77e2eSThierry Reding clock-names = "serial"; 11737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1174a7a77e2eSThierry Reding reset-names = "serial"; 1175a7a77e2eSThierry Reding status = "disabled"; 1176a7a77e2eSThierry Reding }; 1177a7a77e2eSThierry Reding 1178a7a77e2eSThierry Reding uartg: serial@c290000 { 1179a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1180a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1181a7a77e2eSThierry Reding reg-shift = <2>; 1182a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1183c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1184a7a77e2eSThierry Reding clock-names = "serial"; 11857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1186a7a77e2eSThierry Reding reset-names = "serial"; 1187a7a77e2eSThierry Reding status = "disabled"; 1188a7a77e2eSThierry Reding }; 1189a7a77e2eSThierry Reding 11909733a251SThierry Reding rtc: rtc@c2a0000 { 11919733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 11929733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 11939733a251SThierry Reding interrupt-parent = <&pmc>; 11949733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 11959733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 11969733a251SThierry Reding clock-names = "rtc"; 11979733a251SThierry Reding status = "disabled"; 11989733a251SThierry Reding }; 11999733a251SThierry Reding 1200fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1201fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1202fc4bb754SThierry Reding reg-names = "security", "gpio"; 1203fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1204fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1205fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1206fc4bb754SThierry Reding gpio-controller; 1207fc4bb754SThierry Reding #gpio-cells = <2>; 1208fc4bb754SThierry Reding interrupt-controller; 1209fc4bb754SThierry Reding #interrupt-cells = <2>; 1210fc4bb754SThierry Reding }; 1211fc4bb754SThierry Reding 1212913f8ad4SThierry Reding pwm4: pwm@c340000 { 1213913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1214913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1215913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1216913f8ad4SThierry Reding clock-names = "pwm"; 1217913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1218913f8ad4SThierry Reding reset-names = "pwm"; 1219913f8ad4SThierry Reding status = "disabled"; 1220913f8ad4SThierry Reding #pwm-cells = <2>; 1221913f8ad4SThierry Reding }; 1222913f8ad4SThierry Reding 122332e66e46SThierry Reding pmc: pmc@c360000 { 122473bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 122573bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 122673bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 122773bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 122873bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 122973bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 123024005fd1SAapo Vienamo 123132e66e46SThierry Reding #interrupt-cells = <2>; 123232e66e46SThierry Reding interrupt-controller; 123332e66e46SThierry Reding 123424005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 123524005fd1SAapo Vienamo pins = "sdmmc1-hv"; 123624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 123724005fd1SAapo Vienamo }; 123824005fd1SAapo Vienamo 123924005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 124024005fd1SAapo Vienamo pins = "sdmmc1-hv"; 124124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 124224005fd1SAapo Vienamo }; 124324005fd1SAapo Vienamo 124424005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 124524005fd1SAapo Vienamo pins = "sdmmc2-hv"; 124624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 124724005fd1SAapo Vienamo }; 124824005fd1SAapo Vienamo 124924005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 125024005fd1SAapo Vienamo pins = "sdmmc2-hv"; 125124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 125224005fd1SAapo Vienamo }; 125324005fd1SAapo Vienamo 125424005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 125524005fd1SAapo Vienamo pins = "sdmmc3-hv"; 125624005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 125724005fd1SAapo Vienamo }; 125824005fd1SAapo Vienamo 125924005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 126024005fd1SAapo Vienamo pins = "sdmmc3-hv"; 126124005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 126224005fd1SAapo Vienamo }; 126373bf90d4SThierry Reding }; 126473bf90d4SThierry Reding 12657b7ef494SMikko Perttunen ccplex@e000000 { 12667b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 12672b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 12687b7ef494SMikko Perttunen 12697b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 12707b7ef494SMikko Perttunen }; 12717b7ef494SMikko Perttunen 1272f8973cf4SManikanta Maddireddy pcie@10003000 { 1273f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1274f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1275f8973cf4SManikanta Maddireddy device_type = "pci"; 1276644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1277644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1278644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1279f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1280f8973cf4SManikanta Maddireddy 1281f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1282f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1283f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1284f8973cf4SManikanta Maddireddy 1285f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1286f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1287f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1288f8973cf4SManikanta Maddireddy 1289f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1290f8973cf4SManikanta Maddireddy #address-cells = <3>; 1291f8973cf4SManikanta Maddireddy #size-cells = <2>; 1292f8973cf4SManikanta Maddireddy 1293644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1294644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1295644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1296644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1297644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1298644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1299f8973cf4SManikanta Maddireddy 130078b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 130178b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1302f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 130378b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1304f8973cf4SManikanta Maddireddy 130578b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 130678b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1307f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 130878b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1309f8973cf4SManikanta Maddireddy 1310954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1311954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1312954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1313954490b3SThierry Reding 1314f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1315f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1316f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1317f2a465e7SThierry Reding 1318f8973cf4SManikanta Maddireddy status = "disabled"; 1319f8973cf4SManikanta Maddireddy 1320f8973cf4SManikanta Maddireddy pci@1,0 { 1321f8973cf4SManikanta Maddireddy device_type = "pci"; 1322f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1323f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1324f8973cf4SManikanta Maddireddy status = "disabled"; 1325f8973cf4SManikanta Maddireddy 1326f8973cf4SManikanta Maddireddy #address-cells = <3>; 1327f8973cf4SManikanta Maddireddy #size-cells = <2>; 1328f8973cf4SManikanta Maddireddy ranges; 1329f8973cf4SManikanta Maddireddy 1330f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1331f8973cf4SManikanta Maddireddy }; 1332f8973cf4SManikanta Maddireddy 1333f8973cf4SManikanta Maddireddy pci@2,0 { 1334f8973cf4SManikanta Maddireddy device_type = "pci"; 1335f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1336f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1337f8973cf4SManikanta Maddireddy status = "disabled"; 1338f8973cf4SManikanta Maddireddy 1339f8973cf4SManikanta Maddireddy #address-cells = <3>; 1340f8973cf4SManikanta Maddireddy #size-cells = <2>; 1341f8973cf4SManikanta Maddireddy ranges; 1342f8973cf4SManikanta Maddireddy 1343f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1344f8973cf4SManikanta Maddireddy }; 1345f8973cf4SManikanta Maddireddy 1346f8973cf4SManikanta Maddireddy pci@3,0 { 1347f8973cf4SManikanta Maddireddy device_type = "pci"; 1348f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1349f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1350f8973cf4SManikanta Maddireddy status = "disabled"; 1351f8973cf4SManikanta Maddireddy 1352f8973cf4SManikanta Maddireddy #address-cells = <3>; 1353f8973cf4SManikanta Maddireddy #size-cells = <2>; 1354f8973cf4SManikanta Maddireddy ranges; 1355f8973cf4SManikanta Maddireddy 1356f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1357f8973cf4SManikanta Maddireddy }; 1358f8973cf4SManikanta Maddireddy }; 1359f8973cf4SManikanta Maddireddy 1360b30a8e61SThierry Reding smmu: iommu@12000000 { 1361bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1362b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1363b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1364b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1365b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1367b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1428b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1429b30a8e61SThierry Reding #global-interrupts = <1>; 1430b30a8e61SThierry Reding #iommu-cells = <1>; 1431b966d2dbSThierry Reding 1432b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1433b30a8e61SThierry Reding }; 1434b30a8e61SThierry Reding 14355524c61fSMikko Perttunen host1x@13e00000 { 1436ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 14375524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 14385524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 14395524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 14405524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 14415524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1442052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 14435524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 14445524c61fSMikko Perttunen clock-names = "host1x"; 14455524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 14465524c61fSMikko Perttunen reset-names = "host1x"; 14475524c61fSMikko Perttunen 14485524c61fSMikko Perttunen #address-cells = <1>; 14495524c61fSMikko Perttunen #size-cells = <1>; 14505524c61fSMikko Perttunen 14515524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1452954490b3SThierry Reding 1453954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1454954490b3SThierry Reding interconnect-names = "dma-mem"; 1455954490b3SThierry Reding 1456c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1457c2599da7SThierry Reding 1458c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1459c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1460c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1461c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1462c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1463c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1464c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1465c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1466c2599da7SThierry Reding reset-names = "dpaux"; 1467c2599da7SThierry Reding status = "disabled"; 1468c2599da7SThierry Reding 1469c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1470c2599da7SThierry Reding 1471c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1472c2599da7SThierry Reding groups = "dpaux-io"; 1473c2599da7SThierry Reding function = "aux"; 1474c2599da7SThierry Reding }; 1475c2599da7SThierry Reding 1476c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1477c2599da7SThierry Reding groups = "dpaux-io"; 1478c2599da7SThierry Reding function = "i2c"; 1479c2599da7SThierry Reding }; 1480c2599da7SThierry Reding 1481c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1482c2599da7SThierry Reding groups = "dpaux-io"; 1483c2599da7SThierry Reding function = "off"; 1484c2599da7SThierry Reding }; 1485c2599da7SThierry Reding 1486c2599da7SThierry Reding i2c-bus { 1487c2599da7SThierry Reding #address-cells = <1>; 1488c2599da7SThierry Reding #size-cells = <0>; 1489c2599da7SThierry Reding }; 1490c2599da7SThierry Reding }; 1491c2599da7SThierry Reding 1492c2599da7SThierry Reding display-hub@15200000 { 1493aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1494ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1495c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1496c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1497c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1498c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1499c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1500c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1501c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1502c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1503c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1504c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1505c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1506c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1507c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1508c2599da7SThierry Reding status = "disabled"; 1509c2599da7SThierry Reding 1510c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1511c2599da7SThierry Reding 1512c2599da7SThierry Reding #address-cells = <1>; 1513c2599da7SThierry Reding #size-cells = <1>; 1514c2599da7SThierry Reding 1515c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1516c2599da7SThierry Reding 1517c2599da7SThierry Reding display@15200000 { 1518c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1519c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1520c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1521c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1522c2599da7SThierry Reding clock-names = "dc"; 1523c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1524c2599da7SThierry Reding reset-names = "dc"; 1525c2599da7SThierry Reding 1526c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1527954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1528954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1529954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1530c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1531c2599da7SThierry Reding 1532c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1533c2599da7SThierry Reding nvidia,head = <0>; 1534c2599da7SThierry Reding }; 1535c2599da7SThierry Reding 1536c2599da7SThierry Reding display@15210000 { 1537c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1538c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1539c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1540c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1541c2599da7SThierry Reding clock-names = "dc"; 1542c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1543c2599da7SThierry Reding reset-names = "dc"; 1544c2599da7SThierry Reding 1545c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1546954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1547954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1548954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1549c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1550c2599da7SThierry Reding 1551c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1552c2599da7SThierry Reding nvidia,head = <1>; 1553c2599da7SThierry Reding }; 1554c2599da7SThierry Reding 1555c2599da7SThierry Reding display@15220000 { 1556c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1557c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1558c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1559c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1560c2599da7SThierry Reding clock-names = "dc"; 1561c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1562c2599da7SThierry Reding reset-names = "dc"; 1563c2599da7SThierry Reding 1564c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1565954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1566954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1567954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1568c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1569c2599da7SThierry Reding 1570c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1571c2599da7SThierry Reding nvidia,head = <2>; 1572c2599da7SThierry Reding }; 1573c2599da7SThierry Reding }; 1574c2599da7SThierry Reding 1575c2599da7SThierry Reding dsia: dsi@15300000 { 1576c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1577c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1578c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1579c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1580c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1581c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1582c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1583c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1584c2599da7SThierry Reding reset-names = "dsi"; 1585c2599da7SThierry Reding status = "disabled"; 1586c2599da7SThierry Reding 1587c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1588c2599da7SThierry Reding }; 1589effc4b44SMikko Perttunen 1590effc4b44SMikko Perttunen vic@15340000 { 1591effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1592effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1593effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1594effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1595effc4b44SMikko Perttunen clock-names = "vic"; 1596effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1597effc4b44SMikko Perttunen reset-names = "vic"; 1598effc4b44SMikko Perttunen 1599effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1600954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1601954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1602954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 160329ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1604effc4b44SMikko Perttunen }; 1605c2599da7SThierry Reding 1606f7eb2785SJon Hunter nvjpg@15380000 { 1607f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1608f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1609f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1610f7eb2785SJon Hunter clock-names = "nvjpg"; 1611f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1612f7eb2785SJon Hunter reset-names = "nvjpg"; 1613f7eb2785SJon Hunter 1614f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1615f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1616f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1617f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1618f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1619f7eb2785SJon Hunter }; 1620f7eb2785SJon Hunter 1621c2599da7SThierry Reding dsib: dsi@15400000 { 1622c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1623c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1624c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1625c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1626c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1627c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1628c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1629c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1630c2599da7SThierry Reding reset-names = "dsi"; 1631c2599da7SThierry Reding status = "disabled"; 1632c2599da7SThierry Reding 1633c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1634c2599da7SThierry Reding }; 1635c2599da7SThierry Reding 163678a05873SMikko Perttunen nvdec@15480000 { 163778a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 163878a05873SMikko Perttunen reg = <0x15480000 0x40000>; 163978a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 164078a05873SMikko Perttunen clock-names = "nvdec"; 164178a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 164278a05873SMikko Perttunen reset-names = "nvdec"; 164378a05873SMikko Perttunen 164478a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 164578a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 164678a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 164778a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 164878a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 164978a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 165078a05873SMikko Perttunen }; 165178a05873SMikko Perttunen 1652f7eb2785SJon Hunter nvenc@154c0000 { 1653f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1654f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1655f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1656f7eb2785SJon Hunter clock-names = "nvenc"; 1657f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1658f7eb2785SJon Hunter reset-names = "nvenc"; 1659f7eb2785SJon Hunter 1660f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1661f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1662f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1663f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1664f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1665f7eb2785SJon Hunter }; 1666f7eb2785SJon Hunter 1667c2599da7SThierry Reding sor0: sor@15540000 { 1668c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1669c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1670c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1671c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1672c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1673c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1674c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1675c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1676c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1677c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1678c2599da7SThierry Reding "pad"; 1679c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1680c2599da7SThierry Reding reset-names = "sor"; 1681c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1682c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1683c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1684c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1685c2599da7SThierry Reding status = "disabled"; 1686c2599da7SThierry Reding 1687c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1688c2599da7SThierry Reding nvidia,interface = <0>; 1689c2599da7SThierry Reding }; 1690c2599da7SThierry Reding 1691c2599da7SThierry Reding sor1: sor@15580000 { 1692d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1693c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1694c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1695c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1696c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1697c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1698c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1699c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1700c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1701c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1702c2599da7SThierry Reding "pad"; 1703c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1704c2599da7SThierry Reding reset-names = "sor"; 1705c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1706c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1707c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1708c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1709c2599da7SThierry Reding status = "disabled"; 1710c2599da7SThierry Reding 1711c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1712c2599da7SThierry Reding nvidia,interface = <1>; 1713c2599da7SThierry Reding }; 1714c2599da7SThierry Reding 1715c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1716c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1717c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1718c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1719c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1720c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1721c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1722c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1723c2599da7SThierry Reding reset-names = "dpaux"; 1724c2599da7SThierry Reding status = "disabled"; 1725c2599da7SThierry Reding 1726c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1727c2599da7SThierry Reding 1728c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1729c2599da7SThierry Reding groups = "dpaux-io"; 1730c2599da7SThierry Reding function = "aux"; 1731c2599da7SThierry Reding }; 1732c2599da7SThierry Reding 1733c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1734c2599da7SThierry Reding groups = "dpaux-io"; 1735c2599da7SThierry Reding function = "i2c"; 1736c2599da7SThierry Reding }; 1737c2599da7SThierry Reding 1738c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1739c2599da7SThierry Reding groups = "dpaux-io"; 1740c2599da7SThierry Reding function = "off"; 1741c2599da7SThierry Reding }; 1742c2599da7SThierry Reding 1743c2599da7SThierry Reding i2c-bus { 1744c2599da7SThierry Reding #address-cells = <1>; 1745c2599da7SThierry Reding #size-cells = <0>; 1746c2599da7SThierry Reding }; 1747c2599da7SThierry Reding }; 1748c2599da7SThierry Reding 1749c2599da7SThierry Reding padctl@15880000 { 1750c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1751c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1752c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1753c2599da7SThierry Reding reset-names = "dsi"; 1754c2599da7SThierry Reding status = "disabled"; 1755c2599da7SThierry Reding }; 1756c2599da7SThierry Reding 1757c2599da7SThierry Reding dsic: dsi@15900000 { 1758c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1759c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1760c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1761c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1762c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1763c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1764c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1765c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1766c2599da7SThierry Reding reset-names = "dsi"; 1767c2599da7SThierry Reding status = "disabled"; 1768c2599da7SThierry Reding 1769c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1770c2599da7SThierry Reding }; 1771c2599da7SThierry Reding 1772c2599da7SThierry Reding dsid: dsi@15940000 { 1773c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1774c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1775c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1776c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1777c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1778c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1779c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1780c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1781c2599da7SThierry Reding reset-names = "dsi"; 1782c2599da7SThierry Reding status = "disabled"; 1783c2599da7SThierry Reding 1784c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1785c2599da7SThierry Reding }; 17865524c61fSMikko Perttunen }; 17875524c61fSMikko Perttunen 1788dfd7a384SAlexandre Courbot gpu@17000000 { 1789dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1790dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1791dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 179259a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 179359a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1794dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1795dfd7a384SAlexandre Courbot 1796dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1797dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1798dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1799dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1800dfd7a384SAlexandre Courbot reset-names = "gpu"; 1801dfd7a384SAlexandre Courbot status = "disabled"; 1802dfd7a384SAlexandre Courbot 1803dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1804954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1805954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1806954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1807954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1808954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1809dfd7a384SAlexandre Courbot }; 1810dfd7a384SAlexandre Courbot 1811e867fe41SThierry Reding sram@30000000 { 181239cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 181339cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1814aa78032cSThierry Reding #address-cells = <1>; 1815aa78032cSThierry Reding #size-cells = <1>; 1816aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 181739cb62cbSJoseph Lo 1818e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1819aa78032cSThierry Reding reg = <0x4e000 0x1000>; 182039cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 182139cb62cbSJoseph Lo pool; 182239cb62cbSJoseph Lo }; 182339cb62cbSJoseph Lo 1824e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1825aa78032cSThierry Reding reg = <0x4f000 0x1000>; 182639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 182739cb62cbSJoseph Lo pool; 182839cb62cbSJoseph Lo }; 182939cb62cbSJoseph Lo }; 183039cb62cbSJoseph Lo 1831e061fbdfSSowjanya Komatineni sata@3507000 { 1832e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1833e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1834e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1835e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1836e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1837e061fbdfSSowjanya Komatineni 1838e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1839e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1840e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1841e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1842e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1843e061fbdfSSowjanya Komatineni 1844e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1845e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1846e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1847e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1848e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1849e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1850e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1851e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1852e061fbdfSSowjanya Komatineni <204000000>; 1853e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1854e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1855e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1856e061fbdfSSowjanya Komatineni status = "disabled"; 1857e061fbdfSSowjanya Komatineni }; 1858e061fbdfSSowjanya Komatineni 1859541d7c44SThierry Reding bpmp: bpmp { 1860541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1861954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1862954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1863954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1864954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1865954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1866541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1867541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1868541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 18697fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1870541d7c44SThierry Reding #clock-cells = <1>; 1871541d7c44SThierry Reding #reset-cells = <1>; 1872541d7c44SThierry Reding #power-domain-cells = <1>; 1873541d7c44SThierry Reding 1874541d7c44SThierry Reding bpmp_i2c: i2c { 1875541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1876541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1877541d7c44SThierry Reding #address-cells = <1>; 1878541d7c44SThierry Reding #size-cells = <0>; 1879541d7c44SThierry Reding status = "disabled"; 1880541d7c44SThierry Reding }; 1881541d7c44SThierry Reding 1882541d7c44SThierry Reding bpmp_thermal: thermal { 1883541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1884541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1885541d7c44SThierry Reding }; 1886541d7c44SThierry Reding }; 1887541d7c44SThierry Reding 1888cd6fe32eSThierry Reding cpus { 1889cd6fe32eSThierry Reding #address-cells = <1>; 1890cd6fe32eSThierry Reding #size-cells = <0>; 1891cd6fe32eSThierry Reding 18923b4c1378SMarc Zyngier denver_0: cpu@0 { 189331af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1894cd6fe32eSThierry Reding device_type = "cpu"; 18955298166dSJoseph Lo i-cache-size = <0x20000>; 18965298166dSJoseph Lo i-cache-line-size = <64>; 18975298166dSJoseph Lo i-cache-sets = <512>; 18985298166dSJoseph Lo d-cache-size = <0x10000>; 18995298166dSJoseph Lo d-cache-line-size = <64>; 19005298166dSJoseph Lo d-cache-sets = <256>; 19015298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1902cd6fe32eSThierry Reding reg = <0x000>; 1903cd6fe32eSThierry Reding }; 1904cd6fe32eSThierry Reding 19053b4c1378SMarc Zyngier denver_1: cpu@1 { 190631af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1907cd6fe32eSThierry Reding device_type = "cpu"; 19085298166dSJoseph Lo i-cache-size = <0x20000>; 19095298166dSJoseph Lo i-cache-line-size = <64>; 19105298166dSJoseph Lo i-cache-sets = <512>; 19115298166dSJoseph Lo d-cache-size = <0x10000>; 19125298166dSJoseph Lo d-cache-line-size = <64>; 19135298166dSJoseph Lo d-cache-sets = <256>; 19145298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1915cd6fe32eSThierry Reding reg = <0x001>; 1916cd6fe32eSThierry Reding }; 1917cd6fe32eSThierry Reding 19183b4c1378SMarc Zyngier ca57_0: cpu@2 { 191931af04cdSRob Herring compatible = "arm,cortex-a57"; 1920cd6fe32eSThierry Reding device_type = "cpu"; 19215298166dSJoseph Lo i-cache-size = <0xC000>; 19225298166dSJoseph Lo i-cache-line-size = <64>; 19235298166dSJoseph Lo i-cache-sets = <256>; 19245298166dSJoseph Lo d-cache-size = <0x8000>; 19255298166dSJoseph Lo d-cache-line-size = <64>; 19265298166dSJoseph Lo d-cache-sets = <256>; 19275298166dSJoseph Lo next-level-cache = <&L2_A57>; 1928cd6fe32eSThierry Reding reg = <0x100>; 1929cd6fe32eSThierry Reding }; 1930cd6fe32eSThierry Reding 19313b4c1378SMarc Zyngier ca57_1: cpu@3 { 193231af04cdSRob Herring compatible = "arm,cortex-a57"; 1933cd6fe32eSThierry Reding device_type = "cpu"; 19345298166dSJoseph Lo i-cache-size = <0xC000>; 19355298166dSJoseph Lo i-cache-line-size = <64>; 19365298166dSJoseph Lo i-cache-sets = <256>; 19375298166dSJoseph Lo d-cache-size = <0x8000>; 19385298166dSJoseph Lo d-cache-line-size = <64>; 19395298166dSJoseph Lo d-cache-sets = <256>; 19405298166dSJoseph Lo next-level-cache = <&L2_A57>; 1941cd6fe32eSThierry Reding reg = <0x101>; 1942cd6fe32eSThierry Reding }; 1943cd6fe32eSThierry Reding 19443b4c1378SMarc Zyngier ca57_2: cpu@4 { 194531af04cdSRob Herring compatible = "arm,cortex-a57"; 1946cd6fe32eSThierry Reding device_type = "cpu"; 19475298166dSJoseph Lo i-cache-size = <0xC000>; 19485298166dSJoseph Lo i-cache-line-size = <64>; 19495298166dSJoseph Lo i-cache-sets = <256>; 19505298166dSJoseph Lo d-cache-size = <0x8000>; 19515298166dSJoseph Lo d-cache-line-size = <64>; 19525298166dSJoseph Lo d-cache-sets = <256>; 19535298166dSJoseph Lo next-level-cache = <&L2_A57>; 1954cd6fe32eSThierry Reding reg = <0x102>; 1955cd6fe32eSThierry Reding }; 1956cd6fe32eSThierry Reding 19573b4c1378SMarc Zyngier ca57_3: cpu@5 { 195831af04cdSRob Herring compatible = "arm,cortex-a57"; 1959cd6fe32eSThierry Reding device_type = "cpu"; 19605298166dSJoseph Lo i-cache-size = <0xC000>; 19615298166dSJoseph Lo i-cache-line-size = <64>; 19625298166dSJoseph Lo i-cache-sets = <256>; 19635298166dSJoseph Lo d-cache-size = <0x8000>; 19645298166dSJoseph Lo d-cache-line-size = <64>; 19655298166dSJoseph Lo d-cache-sets = <256>; 19665298166dSJoseph Lo next-level-cache = <&L2_A57>; 1967cd6fe32eSThierry Reding reg = <0x103>; 1968cd6fe32eSThierry Reding }; 19695298166dSJoseph Lo 19705298166dSJoseph Lo L2_DENVER: l2-cache0 { 19715298166dSJoseph Lo compatible = "cache"; 19725298166dSJoseph Lo cache-unified; 19735298166dSJoseph Lo cache-level = <2>; 19745298166dSJoseph Lo cache-size = <0x200000>; 19755298166dSJoseph Lo cache-line-size = <64>; 19765298166dSJoseph Lo cache-sets = <2048>; 19775298166dSJoseph Lo }; 19785298166dSJoseph Lo 19795298166dSJoseph Lo L2_A57: l2-cache1 { 19805298166dSJoseph Lo compatible = "cache"; 19815298166dSJoseph Lo cache-unified; 19825298166dSJoseph Lo cache-level = <2>; 19835298166dSJoseph Lo cache-size = <0x200000>; 19845298166dSJoseph Lo cache-line-size = <64>; 19855298166dSJoseph Lo cache-sets = <2048>; 19865298166dSJoseph Lo }; 1987cd6fe32eSThierry Reding }; 1988cd6fe32eSThierry Reding 19893b4c1378SMarc Zyngier pmu_denver { 1990f0a48120SThierry Reding compatible = "nvidia,denver-pmu"; 19913b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 19923b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 19933b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 19943b4c1378SMarc Zyngier }; 19953b4c1378SMarc Zyngier 19963b4c1378SMarc Zyngier pmu_a57 { 1997f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 19983b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 19993b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20003b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20013b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20023b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20033b4c1378SMarc Zyngier }; 20043b4c1378SMarc Zyngier 2005e4710376SSameer Pujar sound { 2006e4710376SSameer Pujar status = "disabled"; 2007e4710376SSameer Pujar 2008e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2009e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2010e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2011e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2012e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2013e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2014e4710376SSameer Pujar assigned-clock-parents = <0>, 2015e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2016e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2017e4710376SSameer Pujar /* 2018e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2019e4710376SSameer Pujar * for this to work and oscillate between base rates required 2020e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2021e4710376SSameer Pujar */ 2022e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2023e4710376SSameer Pujar 2024e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2025e4710376SSameer Pujar }; 2026e4710376SSameer Pujar 202715274c23SMikko Perttunen thermal-zones { 2028fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2029fe57ff53SThierry Reding cpu-thermal { 203015274c23SMikko Perttunen polling-delay = <0>; 203115274c23SMikko Perttunen polling-delay-passive = <1000>; 203215274c23SMikko Perttunen 2033fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 203415274c23SMikko Perttunen 203515274c23SMikko Perttunen trips { 203615274c23SMikko Perttunen critical { 203715274c23SMikko Perttunen temperature = <101000>; 203815274c23SMikko Perttunen hysteresis = <0>; 203915274c23SMikko Perttunen type = "critical"; 204015274c23SMikko Perttunen }; 204115274c23SMikko Perttunen }; 204215274c23SMikko Perttunen 204315274c23SMikko Perttunen cooling-maps { 204415274c23SMikko Perttunen }; 204515274c23SMikko Perttunen }; 204615274c23SMikko Perttunen 2047fe57ff53SThierry Reding /* Denver cluster */ 2048fe57ff53SThierry Reding aux-thermal { 204915274c23SMikko Perttunen polling-delay = <0>; 205015274c23SMikko Perttunen polling-delay-passive = <1000>; 205115274c23SMikko Perttunen 2052fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 205315274c23SMikko Perttunen 205415274c23SMikko Perttunen trips { 205515274c23SMikko Perttunen critical { 205615274c23SMikko Perttunen temperature = <101000>; 205715274c23SMikko Perttunen hysteresis = <0>; 205815274c23SMikko Perttunen type = "critical"; 205915274c23SMikko Perttunen }; 206015274c23SMikko Perttunen }; 206115274c23SMikko Perttunen 206215274c23SMikko Perttunen cooling-maps { 206315274c23SMikko Perttunen }; 206415274c23SMikko Perttunen }; 206515274c23SMikko Perttunen 2066fe57ff53SThierry Reding gpu-thermal { 206715274c23SMikko Perttunen polling-delay = <0>; 206815274c23SMikko Perttunen polling-delay-passive = <1000>; 206915274c23SMikko Perttunen 2070fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 207115274c23SMikko Perttunen 207215274c23SMikko Perttunen trips { 207315274c23SMikko Perttunen critical { 207415274c23SMikko Perttunen temperature = <101000>; 207515274c23SMikko Perttunen hysteresis = <0>; 207615274c23SMikko Perttunen type = "critical"; 207715274c23SMikko Perttunen }; 207815274c23SMikko Perttunen }; 207915274c23SMikko Perttunen 208015274c23SMikko Perttunen cooling-maps { 208115274c23SMikko Perttunen }; 208215274c23SMikko Perttunen }; 208315274c23SMikko Perttunen 2084fe57ff53SThierry Reding pll-thermal { 208515274c23SMikko Perttunen polling-delay = <0>; 208615274c23SMikko Perttunen polling-delay-passive = <1000>; 208715274c23SMikko Perttunen 2088fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 208915274c23SMikko Perttunen 209015274c23SMikko Perttunen trips { 209115274c23SMikko Perttunen critical { 209215274c23SMikko Perttunen temperature = <101000>; 209315274c23SMikko Perttunen hysteresis = <0>; 209415274c23SMikko Perttunen type = "critical"; 209515274c23SMikko Perttunen }; 209615274c23SMikko Perttunen }; 209715274c23SMikko Perttunen 209815274c23SMikko Perttunen cooling-maps { 209915274c23SMikko Perttunen }; 210015274c23SMikko Perttunen }; 210115274c23SMikko Perttunen 2102fe57ff53SThierry Reding ao-thermal { 210315274c23SMikko Perttunen polling-delay = <0>; 210415274c23SMikko Perttunen polling-delay-passive = <1000>; 210515274c23SMikko Perttunen 2106fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 210715274c23SMikko Perttunen 210815274c23SMikko Perttunen trips { 210915274c23SMikko Perttunen critical { 211015274c23SMikko Perttunen temperature = <101000>; 211115274c23SMikko Perttunen hysteresis = <0>; 211215274c23SMikko Perttunen type = "critical"; 211315274c23SMikko Perttunen }; 211415274c23SMikko Perttunen }; 211515274c23SMikko Perttunen 211615274c23SMikko Perttunen cooling-maps { 211715274c23SMikko Perttunen }; 211815274c23SMikko Perttunen }; 211939cb62cbSJoseph Lo }; 212039cb62cbSJoseph Lo 212139cb62cbSJoseph Lo timer { 212239cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 212339cb62cbSJoseph Lo interrupts = <GIC_PPI 13 212439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 212539cb62cbSJoseph Lo <GIC_PPI 14 212639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 212739cb62cbSJoseph Lo <GIC_PPI 11 212839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 212939cb62cbSJoseph Lo <GIC_PPI 10 213039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 213139cb62cbSJoseph Lo interrupt-parent = <&gic>; 2132b30be673SThierry Reding always-on; 213339cb62cbSJoseph Lo }; 213439cb62cbSJoseph Lo}; 2135