1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 630caafbdeSThierry Reding status = "disabled"; 640caafbdeSThierry Reding 650caafbdeSThierry Reding snps,write-requests = <1>; 660caafbdeSThierry Reding snps,read-requests = <3>; 670caafbdeSThierry Reding snps,burst-map = <0x7>; 680caafbdeSThierry Reding snps,txpbl = <32>; 690caafbdeSThierry Reding snps,rxpbl = <8>; 700caafbdeSThierry Reding }; 710caafbdeSThierry Reding 72d25a3bf1SThierry Reding memory-controller@2c00000 { 73d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 74d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 75d25a3bf1SThierry Reding status = "disabled"; 76d25a3bf1SThierry Reding }; 77d25a3bf1SThierry Reding 7839cb62cbSJoseph Lo uarta: serial@3100000 { 7939cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8039cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8139cb62cbSJoseph Lo reg-shift = <2>; 8239cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 84a7a77e2eSThierry Reding clock-names = "serial"; 857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 86a7a77e2eSThierry Reding reset-names = "serial"; 87a7a77e2eSThierry Reding status = "disabled"; 88a7a77e2eSThierry Reding }; 89a7a77e2eSThierry Reding 90a7a77e2eSThierry Reding uartb: serial@3110000 { 91a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 93a7a77e2eSThierry Reding reg-shift = <2>; 94a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 96a7a77e2eSThierry Reding clock-names = "serial"; 977bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 98a7a77e2eSThierry Reding reset-names = "serial"; 99a7a77e2eSThierry Reding status = "disabled"; 100a7a77e2eSThierry Reding }; 101a7a77e2eSThierry Reding 102a7a77e2eSThierry Reding uartd: serial@3130000 { 103a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 105a7a77e2eSThierry Reding reg-shift = <2>; 106a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 108a7a77e2eSThierry Reding clock-names = "serial"; 1097bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 110a7a77e2eSThierry Reding reset-names = "serial"; 111a7a77e2eSThierry Reding status = "disabled"; 112a7a77e2eSThierry Reding }; 113a7a77e2eSThierry Reding 114a7a77e2eSThierry Reding uarte: serial@3140000 { 115a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 117a7a77e2eSThierry Reding reg-shift = <2>; 118a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 120a7a77e2eSThierry Reding clock-names = "serial"; 1217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 122a7a77e2eSThierry Reding reset-names = "serial"; 123a7a77e2eSThierry Reding status = "disabled"; 124a7a77e2eSThierry Reding }; 125a7a77e2eSThierry Reding 126a7a77e2eSThierry Reding uartf: serial@3150000 { 127a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 129a7a77e2eSThierry Reding reg-shift = <2>; 130a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 132a7a77e2eSThierry Reding clock-names = "serial"; 1337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 134a7a77e2eSThierry Reding reset-names = "serial"; 13539cb62cbSJoseph Lo status = "disabled"; 13639cb62cbSJoseph Lo }; 13739cb62cbSJoseph Lo 13840cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14040cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14140cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14240cc83b3SThierry Reding #address-cells = <1>; 14340cc83b3SThierry Reding #size-cells = <0>; 144c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14540cc83b3SThierry Reding clock-names = "div-clk"; 1467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14740cc83b3SThierry Reding reset-names = "i2c"; 14840cc83b3SThierry Reding status = "disabled"; 14940cc83b3SThierry Reding }; 15040cc83b3SThierry Reding 15140cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15340cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15440cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15540cc83b3SThierry Reding #address-cells = <1>; 15640cc83b3SThierry Reding #size-cells = <0>; 157c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15840cc83b3SThierry Reding clock-names = "div-clk"; 1597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16040cc83b3SThierry Reding reset-names = "i2c"; 16140cc83b3SThierry Reding status = "disabled"; 16240cc83b3SThierry Reding }; 16340cc83b3SThierry Reding 16440cc83b3SThierry Reding /* shares pads with dpaux1 */ 16540cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16740cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16840cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16940cc83b3SThierry Reding #address-cells = <1>; 17040cc83b3SThierry Reding #size-cells = <0>; 171c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17240cc83b3SThierry Reding clock-names = "div-clk"; 1737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17440cc83b3SThierry Reding reset-names = "i2c"; 17540cc83b3SThierry Reding status = "disabled"; 17640cc83b3SThierry Reding }; 17740cc83b3SThierry Reding 17840cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17940cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 18040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18140cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18240cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18340cc83b3SThierry Reding #address-cells = <1>; 18440cc83b3SThierry Reding #size-cells = <0>; 185c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18640cc83b3SThierry Reding clock-names = "div-clk"; 1877bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18840cc83b3SThierry Reding reset-names = "i2c"; 18940cc83b3SThierry Reding status = "disabled"; 19040cc83b3SThierry Reding }; 19140cc83b3SThierry Reding 19240cc83b3SThierry Reding /* shares pads with dpaux0 */ 19340cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19540cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19640cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19740cc83b3SThierry Reding #address-cells = <1>; 19840cc83b3SThierry Reding #size-cells = <0>; 199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20040cc83b3SThierry Reding clock-names = "div-clk"; 2017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20240cc83b3SThierry Reding reset-names = "i2c"; 20340cc83b3SThierry Reding status = "disabled"; 20440cc83b3SThierry Reding }; 20540cc83b3SThierry Reding 20640cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20840cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20940cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21040cc83b3SThierry Reding #address-cells = <1>; 21140cc83b3SThierry Reding #size-cells = <0>; 212c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21340cc83b3SThierry Reding clock-names = "div-clk"; 2147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21540cc83b3SThierry Reding reset-names = "i2c"; 21640cc83b3SThierry Reding status = "disabled"; 21740cc83b3SThierry Reding }; 21840cc83b3SThierry Reding 21940cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 22040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22140cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22240cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22340cc83b3SThierry Reding #address-cells = <1>; 22440cc83b3SThierry Reding #size-cells = <0>; 225c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22640cc83b3SThierry Reding clock-names = "div-clk"; 2277bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22840cc83b3SThierry Reding reset-names = "i2c"; 22940cc83b3SThierry Reding status = "disabled"; 23040cc83b3SThierry Reding }; 23140cc83b3SThierry Reding 23299425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23499425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23599425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23799425dfdSThierry Reding clock-names = "sdhci"; 2387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23999425dfdSThierry Reding reset-names = "sdhci"; 24024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 24224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 24341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 24441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 24541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 24641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 24741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 24841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 24999425dfdSThierry Reding status = "disabled"; 25099425dfdSThierry Reding }; 25199425dfdSThierry Reding 25299425dfdSThierry Reding sdmmc2: sdhci@3420000 { 25399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25499425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 25599425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 256c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 25799425dfdSThierry Reding clock-names = "sdhci"; 2587bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 25999425dfdSThierry Reding reset-names = "sdhci"; 26024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 26124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 26224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 26341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 26441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 26541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 26641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 26799425dfdSThierry Reding status = "disabled"; 26899425dfdSThierry Reding }; 26999425dfdSThierry Reding 27099425dfdSThierry Reding sdmmc3: sdhci@3440000 { 27199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 27299425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 27399425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 274c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 27599425dfdSThierry Reding clock-names = "sdhci"; 2767bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 27799425dfdSThierry Reding reset-names = "sdhci"; 27824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 27924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 28024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 28141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 28241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 28341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 28441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 28541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 28641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 28799425dfdSThierry Reding status = "disabled"; 28899425dfdSThierry Reding }; 28999425dfdSThierry Reding 29099425dfdSThierry Reding sdmmc4: sdhci@3460000 { 29199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 29299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 29399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 294c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 29599425dfdSThierry Reding clock-names = "sdhci"; 2967bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 29799425dfdSThierry Reding reset-names = "sdhci"; 29841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 29941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 30041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 30141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 30299425dfdSThierry Reding status = "disabled"; 30399425dfdSThierry Reding }; 30499425dfdSThierry Reding 30585593b75SThierry Reding fuse@3820000 { 30685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 30785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 30885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 30985593b75SThierry Reding clock-names = "fuse"; 31085593b75SThierry Reding }; 31185593b75SThierry Reding 31239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 31339cb62cbSJoseph Lo compatible = "arm,gic-400"; 31439cb62cbSJoseph Lo #interrupt-cells = <3>; 31539cb62cbSJoseph Lo interrupt-controller; 31639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 31739cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 31839cb62cbSJoseph Lo interrupts = <GIC_PPI 9 31939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 32039cb62cbSJoseph Lo interrupt-parent = <&gic>; 32139cb62cbSJoseph Lo }; 32239cb62cbSJoseph Lo 32339cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 32439cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 32539cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 32639cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 32739cb62cbSJoseph Lo interrupt-names = "doorbell"; 32839cb62cbSJoseph Lo #mbox-cells = <2>; 32939cb62cbSJoseph Lo status = "disabled"; 33039cb62cbSJoseph Lo }; 33139cb62cbSJoseph Lo 33240cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 33340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 33440cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 33540cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 33640cc83b3SThierry Reding #address-cells = <1>; 33740cc83b3SThierry Reding #size-cells = <0>; 338c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 33940cc83b3SThierry Reding clock-names = "div-clk"; 3407bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 34140cc83b3SThierry Reding reset-names = "i2c"; 34240cc83b3SThierry Reding status = "disabled"; 34340cc83b3SThierry Reding }; 34440cc83b3SThierry Reding 34540cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 34640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 34740cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 34840cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 34940cc83b3SThierry Reding #address-cells = <1>; 35040cc83b3SThierry Reding #size-cells = <0>; 351c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 35240cc83b3SThierry Reding clock-names = "div-clk"; 3537bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 35440cc83b3SThierry Reding reset-names = "i2c"; 35540cc83b3SThierry Reding status = "disabled"; 35640cc83b3SThierry Reding }; 35740cc83b3SThierry Reding 358a7a77e2eSThierry Reding uartc: serial@c280000 { 359a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 360a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 361a7a77e2eSThierry Reding reg-shift = <2>; 362a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 363c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 364a7a77e2eSThierry Reding clock-names = "serial"; 3657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 366a7a77e2eSThierry Reding reset-names = "serial"; 367a7a77e2eSThierry Reding status = "disabled"; 368a7a77e2eSThierry Reding }; 369a7a77e2eSThierry Reding 370a7a77e2eSThierry Reding uartg: serial@c290000 { 371a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 372a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 373a7a77e2eSThierry Reding reg-shift = <2>; 374a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 375c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 376a7a77e2eSThierry Reding clock-names = "serial"; 3777bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 378a7a77e2eSThierry Reding reset-names = "serial"; 379a7a77e2eSThierry Reding status = "disabled"; 380a7a77e2eSThierry Reding }; 381a7a77e2eSThierry Reding 382fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 383fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 384fc4bb754SThierry Reding reg-names = "security", "gpio"; 385fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 386fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 387fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 388fc4bb754SThierry Reding gpio-controller; 389fc4bb754SThierry Reding #gpio-cells = <2>; 390fc4bb754SThierry Reding interrupt-controller; 391fc4bb754SThierry Reding #interrupt-cells = <2>; 392fc4bb754SThierry Reding }; 393fc4bb754SThierry Reding 39473bf90d4SThierry Reding pmc@c360000 { 39573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 39673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 39773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 39873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 39973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 40073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 40124005fd1SAapo Vienamo 40224005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 40324005fd1SAapo Vienamo pins = "sdmmc1-hv"; 40424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 40524005fd1SAapo Vienamo }; 40624005fd1SAapo Vienamo 40724005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 40824005fd1SAapo Vienamo pins = "sdmmc1-hv"; 40924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 41024005fd1SAapo Vienamo }; 41124005fd1SAapo Vienamo 41224005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 41324005fd1SAapo Vienamo pins = "sdmmc2-hv"; 41424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 41524005fd1SAapo Vienamo }; 41624005fd1SAapo Vienamo 41724005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 41824005fd1SAapo Vienamo pins = "sdmmc2-hv"; 41924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 42024005fd1SAapo Vienamo }; 42124005fd1SAapo Vienamo 42224005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 42324005fd1SAapo Vienamo pins = "sdmmc3-hv"; 42424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 42524005fd1SAapo Vienamo }; 42624005fd1SAapo Vienamo 42724005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 42824005fd1SAapo Vienamo pins = "sdmmc3-hv"; 42924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 43024005fd1SAapo Vienamo }; 43173bf90d4SThierry Reding }; 43273bf90d4SThierry Reding 4337b7ef494SMikko Perttunen ccplex@e000000 { 4347b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 4357b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 4367b7ef494SMikko Perttunen 4377b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 4387b7ef494SMikko Perttunen }; 4397b7ef494SMikko Perttunen 440f8973cf4SManikanta Maddireddy pcie@10003000 { 441f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 442f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 443f8973cf4SManikanta Maddireddy device_type = "pci"; 444f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 445f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 446f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 447f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 448f8973cf4SManikanta Maddireddy 449f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 450f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 451f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 452f8973cf4SManikanta Maddireddy 453f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 454f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 455f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 456f8973cf4SManikanta Maddireddy 457f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 458f8973cf4SManikanta Maddireddy #address-cells = <3>; 459f8973cf4SManikanta Maddireddy #size-cells = <2>; 460f8973cf4SManikanta Maddireddy 461f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 462f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 463f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 464f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 465f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 466f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 467f8973cf4SManikanta Maddireddy 468f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 469f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 470f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 471f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 472f8973cf4SManikanta Maddireddy 473f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 474f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 475f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 476f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 477f8973cf4SManikanta Maddireddy 478f8973cf4SManikanta Maddireddy status = "disabled"; 479f8973cf4SManikanta Maddireddy 480f8973cf4SManikanta Maddireddy pci@1,0 { 481f8973cf4SManikanta Maddireddy device_type = "pci"; 482f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 483f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 484f8973cf4SManikanta Maddireddy status = "disabled"; 485f8973cf4SManikanta Maddireddy 486f8973cf4SManikanta Maddireddy #address-cells = <3>; 487f8973cf4SManikanta Maddireddy #size-cells = <2>; 488f8973cf4SManikanta Maddireddy ranges; 489f8973cf4SManikanta Maddireddy 490f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 491f8973cf4SManikanta Maddireddy }; 492f8973cf4SManikanta Maddireddy 493f8973cf4SManikanta Maddireddy pci@2,0 { 494f8973cf4SManikanta Maddireddy device_type = "pci"; 495f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 496f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 497f8973cf4SManikanta Maddireddy status = "disabled"; 498f8973cf4SManikanta Maddireddy 499f8973cf4SManikanta Maddireddy #address-cells = <3>; 500f8973cf4SManikanta Maddireddy #size-cells = <2>; 501f8973cf4SManikanta Maddireddy ranges; 502f8973cf4SManikanta Maddireddy 503f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 504f8973cf4SManikanta Maddireddy }; 505f8973cf4SManikanta Maddireddy 506f8973cf4SManikanta Maddireddy pci@3,0 { 507f8973cf4SManikanta Maddireddy device_type = "pci"; 508f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 509f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 510f8973cf4SManikanta Maddireddy status = "disabled"; 511f8973cf4SManikanta Maddireddy 512f8973cf4SManikanta Maddireddy #address-cells = <3>; 513f8973cf4SManikanta Maddireddy #size-cells = <2>; 514f8973cf4SManikanta Maddireddy ranges; 515f8973cf4SManikanta Maddireddy 516f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 517f8973cf4SManikanta Maddireddy }; 518f8973cf4SManikanta Maddireddy }; 519f8973cf4SManikanta Maddireddy 520b30a8e61SThierry Reding smmu: iommu@12000000 { 521b30a8e61SThierry Reding compatible = "arm,mmu-500"; 522b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 523b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 528b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 529b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 530b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 531b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 532b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 533b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 534b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 535b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 536b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 537b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 588b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 589b30a8e61SThierry Reding #global-interrupts = <1>; 590b30a8e61SThierry Reding #iommu-cells = <1>; 591b30a8e61SThierry Reding }; 592b30a8e61SThierry Reding 5935524c61fSMikko Perttunen host1x@13e00000 { 5945524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 5955524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 5965524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 5975524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 5985524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 5995524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 6005524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 6015524c61fSMikko Perttunen clock-names = "host1x"; 6025524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 6035524c61fSMikko Perttunen reset-names = "host1x"; 6045524c61fSMikko Perttunen 6055524c61fSMikko Perttunen #address-cells = <1>; 6065524c61fSMikko Perttunen #size-cells = <1>; 6075524c61fSMikko Perttunen 6085524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 609c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 610c2599da7SThierry Reding 611c2599da7SThierry Reding dpaux1: dpaux@15040000 { 612c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 613c2599da7SThierry Reding reg = <0x15040000 0x10000>; 614c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 615c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 616c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 617c2599da7SThierry Reding clock-names = "dpaux", "parent"; 618c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 619c2599da7SThierry Reding reset-names = "dpaux"; 620c2599da7SThierry Reding status = "disabled"; 621c2599da7SThierry Reding 622c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 623c2599da7SThierry Reding 624c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 625c2599da7SThierry Reding groups = "dpaux-io"; 626c2599da7SThierry Reding function = "aux"; 627c2599da7SThierry Reding }; 628c2599da7SThierry Reding 629c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 630c2599da7SThierry Reding groups = "dpaux-io"; 631c2599da7SThierry Reding function = "i2c"; 632c2599da7SThierry Reding }; 633c2599da7SThierry Reding 634c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 635c2599da7SThierry Reding groups = "dpaux-io"; 636c2599da7SThierry Reding function = "off"; 637c2599da7SThierry Reding }; 638c2599da7SThierry Reding 639c2599da7SThierry Reding i2c-bus { 640c2599da7SThierry Reding #address-cells = <1>; 641c2599da7SThierry Reding #size-cells = <0>; 642c2599da7SThierry Reding }; 643c2599da7SThierry Reding }; 644c2599da7SThierry Reding 645c2599da7SThierry Reding display-hub@15200000 { 646c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 647c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 648c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 649c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 650c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 651c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 652c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 653c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 654c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 655c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 656c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 657c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 658c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 659c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 660c2599da7SThierry Reding status = "disabled"; 661c2599da7SThierry Reding 662c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 663c2599da7SThierry Reding 664c2599da7SThierry Reding #address-cells = <1>; 665c2599da7SThierry Reding #size-cells = <1>; 666c2599da7SThierry Reding 667c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 668c2599da7SThierry Reding 669c2599da7SThierry Reding display@15200000 { 670c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 671c2599da7SThierry Reding reg = <0x15200000 0x10000>; 672c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 673c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 674c2599da7SThierry Reding clock-names = "dc"; 675c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 676c2599da7SThierry Reding reset-names = "dc"; 677c2599da7SThierry Reding 678c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 679c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 680c2599da7SThierry Reding 681c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 682c2599da7SThierry Reding nvidia,head = <0>; 683c2599da7SThierry Reding }; 684c2599da7SThierry Reding 685c2599da7SThierry Reding display@15210000 { 686c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 687c2599da7SThierry Reding reg = <0x15210000 0x10000>; 688c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 689c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 690c2599da7SThierry Reding clock-names = "dc"; 691c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 692c2599da7SThierry Reding reset-names = "dc"; 693c2599da7SThierry Reding 694c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 695c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 696c2599da7SThierry Reding 697c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 698c2599da7SThierry Reding nvidia,head = <1>; 699c2599da7SThierry Reding }; 700c2599da7SThierry Reding 701c2599da7SThierry Reding display@15220000 { 702c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 703c2599da7SThierry Reding reg = <0x15220000 0x10000>; 704c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 705c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 706c2599da7SThierry Reding clock-names = "dc"; 707c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 708c2599da7SThierry Reding reset-names = "dc"; 709c2599da7SThierry Reding 710c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 711c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 712c2599da7SThierry Reding 713c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 714c2599da7SThierry Reding nvidia,head = <2>; 715c2599da7SThierry Reding }; 716c2599da7SThierry Reding }; 717c2599da7SThierry Reding 718c2599da7SThierry Reding dsia: dsi@15300000 { 719c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 720c2599da7SThierry Reding reg = <0x15300000 0x10000>; 721c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 722c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 723c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 724c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 725c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 726c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 727c2599da7SThierry Reding reset-names = "dsi"; 728c2599da7SThierry Reding status = "disabled"; 729c2599da7SThierry Reding 730c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 731c2599da7SThierry Reding }; 732effc4b44SMikko Perttunen 733effc4b44SMikko Perttunen vic@15340000 { 734effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 735effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 736effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 737effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 738effc4b44SMikko Perttunen clock-names = "vic"; 739effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 740effc4b44SMikko Perttunen reset-names = "vic"; 741effc4b44SMikko Perttunen 742effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 743effc4b44SMikko Perttunen }; 744c2599da7SThierry Reding 745c2599da7SThierry Reding dsib: dsi@15400000 { 746c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 747c2599da7SThierry Reding reg = <0x15400000 0x10000>; 748c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 749c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 750c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 751c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 752c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 753c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 754c2599da7SThierry Reding reset-names = "dsi"; 755c2599da7SThierry Reding status = "disabled"; 756c2599da7SThierry Reding 757c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 758c2599da7SThierry Reding }; 759c2599da7SThierry Reding 760c2599da7SThierry Reding sor0: sor@15540000 { 761c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 762c2599da7SThierry Reding reg = <0x15540000 0x10000>; 763c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 764c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 765c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 766c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 767c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 768c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 769c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 770c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 771c2599da7SThierry Reding "pad"; 772c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 773c2599da7SThierry Reding reset-names = "sor"; 774c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 775c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 776c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 777c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 778c2599da7SThierry Reding status = "disabled"; 779c2599da7SThierry Reding 780c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 781c2599da7SThierry Reding nvidia,interface = <0>; 782c2599da7SThierry Reding }; 783c2599da7SThierry Reding 784c2599da7SThierry Reding sor1: sor@15580000 { 785c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 786c2599da7SThierry Reding reg = <0x15580000 0x10000>; 787c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 788c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 789c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 790c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 791c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 792c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 793c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 794c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 795c2599da7SThierry Reding "pad"; 796c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 797c2599da7SThierry Reding reset-names = "sor"; 798c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 799c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 800c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 801c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 802c2599da7SThierry Reding status = "disabled"; 803c2599da7SThierry Reding 804c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 805c2599da7SThierry Reding nvidia,interface = <1>; 806c2599da7SThierry Reding }; 807c2599da7SThierry Reding 808c2599da7SThierry Reding dpaux: dpaux@155c0000 { 809c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 810c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 811c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 812c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 813c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 814c2599da7SThierry Reding clock-names = "dpaux", "parent"; 815c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 816c2599da7SThierry Reding reset-names = "dpaux"; 817c2599da7SThierry Reding status = "disabled"; 818c2599da7SThierry Reding 819c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 820c2599da7SThierry Reding 821c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 822c2599da7SThierry Reding groups = "dpaux-io"; 823c2599da7SThierry Reding function = "aux"; 824c2599da7SThierry Reding }; 825c2599da7SThierry Reding 826c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 827c2599da7SThierry Reding groups = "dpaux-io"; 828c2599da7SThierry Reding function = "i2c"; 829c2599da7SThierry Reding }; 830c2599da7SThierry Reding 831c2599da7SThierry Reding state_dpaux_off: pinmux-off { 832c2599da7SThierry Reding groups = "dpaux-io"; 833c2599da7SThierry Reding function = "off"; 834c2599da7SThierry Reding }; 835c2599da7SThierry Reding 836c2599da7SThierry Reding i2c-bus { 837c2599da7SThierry Reding #address-cells = <1>; 838c2599da7SThierry Reding #size-cells = <0>; 839c2599da7SThierry Reding }; 840c2599da7SThierry Reding }; 841c2599da7SThierry Reding 842c2599da7SThierry Reding padctl@15880000 { 843c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 844c2599da7SThierry Reding reg = <0x15880000 0x10000>; 845c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 846c2599da7SThierry Reding reset-names = "dsi"; 847c2599da7SThierry Reding status = "disabled"; 848c2599da7SThierry Reding }; 849c2599da7SThierry Reding 850c2599da7SThierry Reding dsic: dsi@15900000 { 851c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 852c2599da7SThierry Reding reg = <0x15900000 0x10000>; 853c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 854c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 855c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 856c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 857c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 858c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 859c2599da7SThierry Reding reset-names = "dsi"; 860c2599da7SThierry Reding status = "disabled"; 861c2599da7SThierry Reding 862c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 863c2599da7SThierry Reding }; 864c2599da7SThierry Reding 865c2599da7SThierry Reding dsid: dsi@15940000 { 866c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 867c2599da7SThierry Reding reg = <0x15940000 0x10000>; 868c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 869c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 870c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 871c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 872c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 873c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 874c2599da7SThierry Reding reset-names = "dsi"; 875c2599da7SThierry Reding status = "disabled"; 876c2599da7SThierry Reding 877c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 878c2599da7SThierry Reding }; 8795524c61fSMikko Perttunen }; 8805524c61fSMikko Perttunen 881dfd7a384SAlexandre Courbot gpu@17000000 { 882dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 883dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 884dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 885dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 886dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 887dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 888dfd7a384SAlexandre Courbot 889dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 890dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 891dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 892dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 893dfd7a384SAlexandre Courbot reset-names = "gpu"; 894dfd7a384SAlexandre Courbot status = "disabled"; 895dfd7a384SAlexandre Courbot 896dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 897dfd7a384SAlexandre Courbot }; 898dfd7a384SAlexandre Courbot 89939cb62cbSJoseph Lo sysram@30000000 { 90039cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 90139cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 90239cb62cbSJoseph Lo #address-cells = <2>; 90339cb62cbSJoseph Lo #size-cells = <2>; 90439cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 90539cb62cbSJoseph Lo 90639cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 90739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 90839cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 90939cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 91039cb62cbSJoseph Lo pool; 91139cb62cbSJoseph Lo }; 91239cb62cbSJoseph Lo 91339cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 91439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 91539cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 91639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 91739cb62cbSJoseph Lo pool; 91839cb62cbSJoseph Lo }; 91939cb62cbSJoseph Lo }; 92039cb62cbSJoseph Lo 921cd6fe32eSThierry Reding cpus { 922cd6fe32eSThierry Reding #address-cells = <1>; 923cd6fe32eSThierry Reding #size-cells = <0>; 924cd6fe32eSThierry Reding 925cd6fe32eSThierry Reding cpu@0 { 926cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 927cd6fe32eSThierry Reding device_type = "cpu"; 928cd6fe32eSThierry Reding reg = <0x000>; 929cd6fe32eSThierry Reding }; 930cd6fe32eSThierry Reding 931cd6fe32eSThierry Reding cpu@1 { 932cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 933cd6fe32eSThierry Reding device_type = "cpu"; 934cd6fe32eSThierry Reding reg = <0x001>; 935cd6fe32eSThierry Reding }; 936cd6fe32eSThierry Reding 937cd6fe32eSThierry Reding cpu@2 { 938cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 939cd6fe32eSThierry Reding device_type = "cpu"; 940cd6fe32eSThierry Reding reg = <0x100>; 941cd6fe32eSThierry Reding }; 942cd6fe32eSThierry Reding 943cd6fe32eSThierry Reding cpu@3 { 944cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 945cd6fe32eSThierry Reding device_type = "cpu"; 946cd6fe32eSThierry Reding reg = <0x101>; 947cd6fe32eSThierry Reding }; 948cd6fe32eSThierry Reding 949cd6fe32eSThierry Reding cpu@4 { 950cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 951cd6fe32eSThierry Reding device_type = "cpu"; 952cd6fe32eSThierry Reding reg = <0x102>; 953cd6fe32eSThierry Reding }; 954cd6fe32eSThierry Reding 955cd6fe32eSThierry Reding cpu@5 { 956cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 957cd6fe32eSThierry Reding device_type = "cpu"; 958cd6fe32eSThierry Reding reg = <0x103>; 959cd6fe32eSThierry Reding }; 960cd6fe32eSThierry Reding }; 961cd6fe32eSThierry Reding 96239cb62cbSJoseph Lo bpmp: bpmp { 96339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 9645edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 9655edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 96639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 96739cb62cbSJoseph Lo #clock-cells = <1>; 96839cb62cbSJoseph Lo #reset-cells = <1>; 969dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 97039cb62cbSJoseph Lo 97139cb62cbSJoseph Lo bpmp_i2c: i2c { 97239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 97339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 97439cb62cbSJoseph Lo #address-cells = <1>; 97539cb62cbSJoseph Lo #size-cells = <0>; 97639cb62cbSJoseph Lo status = "disabled"; 97739cb62cbSJoseph Lo }; 97815274c23SMikko Perttunen 97915274c23SMikko Perttunen bpmp_thermal: thermal { 98015274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 98115274c23SMikko Perttunen #thermal-sensor-cells = <1>; 98215274c23SMikko Perttunen }; 98315274c23SMikko Perttunen }; 98415274c23SMikko Perttunen 98515274c23SMikko Perttunen thermal-zones { 98615274c23SMikko Perttunen a57 { 98715274c23SMikko Perttunen polling-delay = <0>; 98815274c23SMikko Perttunen polling-delay-passive = <1000>; 98915274c23SMikko Perttunen 99015274c23SMikko Perttunen thermal-sensors = 99115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 99215274c23SMikko Perttunen 99315274c23SMikko Perttunen trips { 99415274c23SMikko Perttunen critical { 99515274c23SMikko Perttunen temperature = <101000>; 99615274c23SMikko Perttunen hysteresis = <0>; 99715274c23SMikko Perttunen type = "critical"; 99815274c23SMikko Perttunen }; 99915274c23SMikko Perttunen }; 100015274c23SMikko Perttunen 100115274c23SMikko Perttunen cooling-maps { 100215274c23SMikko Perttunen }; 100315274c23SMikko Perttunen }; 100415274c23SMikko Perttunen 100515274c23SMikko Perttunen denver { 100615274c23SMikko Perttunen polling-delay = <0>; 100715274c23SMikko Perttunen polling-delay-passive = <1000>; 100815274c23SMikko Perttunen 100915274c23SMikko Perttunen thermal-sensors = 101015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 101115274c23SMikko Perttunen 101215274c23SMikko Perttunen trips { 101315274c23SMikko Perttunen critical { 101415274c23SMikko Perttunen temperature = <101000>; 101515274c23SMikko Perttunen hysteresis = <0>; 101615274c23SMikko Perttunen type = "critical"; 101715274c23SMikko Perttunen }; 101815274c23SMikko Perttunen }; 101915274c23SMikko Perttunen 102015274c23SMikko Perttunen cooling-maps { 102115274c23SMikko Perttunen }; 102215274c23SMikko Perttunen }; 102315274c23SMikko Perttunen 102415274c23SMikko Perttunen gpu { 102515274c23SMikko Perttunen polling-delay = <0>; 102615274c23SMikko Perttunen polling-delay-passive = <1000>; 102715274c23SMikko Perttunen 102815274c23SMikko Perttunen thermal-sensors = 102915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 103015274c23SMikko Perttunen 103115274c23SMikko Perttunen trips { 103215274c23SMikko Perttunen critical { 103315274c23SMikko Perttunen temperature = <101000>; 103415274c23SMikko Perttunen hysteresis = <0>; 103515274c23SMikko Perttunen type = "critical"; 103615274c23SMikko Perttunen }; 103715274c23SMikko Perttunen }; 103815274c23SMikko Perttunen 103915274c23SMikko Perttunen cooling-maps { 104015274c23SMikko Perttunen }; 104115274c23SMikko Perttunen }; 104215274c23SMikko Perttunen 104315274c23SMikko Perttunen pll { 104415274c23SMikko Perttunen polling-delay = <0>; 104515274c23SMikko Perttunen polling-delay-passive = <1000>; 104615274c23SMikko Perttunen 104715274c23SMikko Perttunen thermal-sensors = 104815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 104915274c23SMikko Perttunen 105015274c23SMikko Perttunen trips { 105115274c23SMikko Perttunen critical { 105215274c23SMikko Perttunen temperature = <101000>; 105315274c23SMikko Perttunen hysteresis = <0>; 105415274c23SMikko Perttunen type = "critical"; 105515274c23SMikko Perttunen }; 105615274c23SMikko Perttunen }; 105715274c23SMikko Perttunen 105815274c23SMikko Perttunen cooling-maps { 105915274c23SMikko Perttunen }; 106015274c23SMikko Perttunen }; 106115274c23SMikko Perttunen 106215274c23SMikko Perttunen always_on { 106315274c23SMikko Perttunen polling-delay = <0>; 106415274c23SMikko Perttunen polling-delay-passive = <1000>; 106515274c23SMikko Perttunen 106615274c23SMikko Perttunen thermal-sensors = 106715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 106815274c23SMikko Perttunen 106915274c23SMikko Perttunen trips { 107015274c23SMikko Perttunen critical { 107115274c23SMikko Perttunen temperature = <101000>; 107215274c23SMikko Perttunen hysteresis = <0>; 107315274c23SMikko Perttunen type = "critical"; 107415274c23SMikko Perttunen }; 107515274c23SMikko Perttunen }; 107615274c23SMikko Perttunen 107715274c23SMikko Perttunen cooling-maps { 107815274c23SMikko Perttunen }; 107915274c23SMikko Perttunen }; 108039cb62cbSJoseph Lo }; 108139cb62cbSJoseph Lo 108239cb62cbSJoseph Lo timer { 108339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 108439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 108539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 108639cb62cbSJoseph Lo <GIC_PPI 14 108739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 108839cb62cbSJoseph Lo <GIC_PPI 11 108939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 109039cb62cbSJoseph Lo <GIC_PPI 10 109139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 109239cb62cbSJoseph Lo interrupt-parent = <&gic>; 109339cb62cbSJoseph Lo }; 109439cb62cbSJoseph Lo}; 1095