1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 640caafbdeSThierry Reding status = "disabled"; 650caafbdeSThierry Reding 660caafbdeSThierry Reding snps,write-requests = <1>; 670caafbdeSThierry Reding snps,read-requests = <3>; 680caafbdeSThierry Reding snps,burst-map = <0x7>; 690caafbdeSThierry Reding snps,txpbl = <32>; 700caafbdeSThierry Reding snps,rxpbl = <8>; 710caafbdeSThierry Reding }; 720caafbdeSThierry Reding 735d2249ddSSameer Pujar aconnect { 745d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 755d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 765d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 775d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 785d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 795d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 805d2249ddSSameer Pujar #address-cells = <1>; 815d2249ddSSameer Pujar #size-cells = <1>; 825d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 835d2249ddSSameer Pujar status = "disabled"; 845d2249ddSSameer Pujar 855d2249ddSSameer Pujar dma-controller@2930000 { 865d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 875d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 885d2249ddSSameer Pujar interrupt-parent = <&agic>; 895d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 905d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 915d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 925d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1215d2249ddSSameer Pujar #dma-cells = <1>; 1225d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1235d2249ddSSameer Pujar clock-names = "d_audio"; 1245d2249ddSSameer Pujar status = "disabled"; 1255d2249ddSSameer Pujar }; 1265d2249ddSSameer Pujar 1275d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1285d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1295d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1305d2249ddSSameer Pujar #interrupt-cells = <3>; 1315d2249ddSSameer Pujar interrupt-controller; 1325d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1335d2249ddSSameer Pujar <0x02a42000 0x2000>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1355d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1365d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1375d2249ddSSameer Pujar clock-names = "clk"; 1385d2249ddSSameer Pujar status = "disabled"; 1395d2249ddSSameer Pujar }; 1405d2249ddSSameer Pujar }; 1415d2249ddSSameer Pujar 142d25a3bf1SThierry Reding memory-controller@2c00000 { 143d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 144d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 145b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146d25a3bf1SThierry Reding status = "disabled"; 1473f6eaef9SThierry Reding 1483f6eaef9SThierry Reding #address-cells = <2>; 1493f6eaef9SThierry Reding #size-cells = <2>; 1503f6eaef9SThierry Reding 1513f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 1523f6eaef9SThierry Reding 1533f6eaef9SThierry Reding /* 1543f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 1553f6eaef9SThierry Reding * controller can address. 1563f6eaef9SThierry Reding */ 1573f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 1583f6eaef9SThierry Reding 1593f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 1603f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 1613f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 1623f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1633f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 1643f6eaef9SThierry Reding clock-names = "emc"; 1653f6eaef9SThierry Reding 1663f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 1673f6eaef9SThierry Reding }; 168d25a3bf1SThierry Reding }; 169d25a3bf1SThierry Reding 17039cb62cbSJoseph Lo uarta: serial@3100000 { 17139cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 17239cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 17339cb62cbSJoseph Lo reg-shift = <2>; 17439cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 175c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 176a7a77e2eSThierry Reding clock-names = "serial"; 1777bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 178a7a77e2eSThierry Reding reset-names = "serial"; 179a7a77e2eSThierry Reding status = "disabled"; 180a7a77e2eSThierry Reding }; 181a7a77e2eSThierry Reding 182a7a77e2eSThierry Reding uartb: serial@3110000 { 183a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 184a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 185a7a77e2eSThierry Reding reg-shift = <2>; 186a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 187c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 188a7a77e2eSThierry Reding clock-names = "serial"; 1897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 190a7a77e2eSThierry Reding reset-names = "serial"; 191a7a77e2eSThierry Reding status = "disabled"; 192a7a77e2eSThierry Reding }; 193a7a77e2eSThierry Reding 194a7a77e2eSThierry Reding uartd: serial@3130000 { 195a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 196a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 197a7a77e2eSThierry Reding reg-shift = <2>; 198a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 200a7a77e2eSThierry Reding clock-names = "serial"; 2017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 202a7a77e2eSThierry Reding reset-names = "serial"; 203a7a77e2eSThierry Reding status = "disabled"; 204a7a77e2eSThierry Reding }; 205a7a77e2eSThierry Reding 206a7a77e2eSThierry Reding uarte: serial@3140000 { 207a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 208a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 209a7a77e2eSThierry Reding reg-shift = <2>; 210a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 211c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 212a7a77e2eSThierry Reding clock-names = "serial"; 2137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 214a7a77e2eSThierry Reding reset-names = "serial"; 215a7a77e2eSThierry Reding status = "disabled"; 216a7a77e2eSThierry Reding }; 217a7a77e2eSThierry Reding 218a7a77e2eSThierry Reding uartf: serial@3150000 { 219a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 220a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 221a7a77e2eSThierry Reding reg-shift = <2>; 222a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 223c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 224a7a77e2eSThierry Reding clock-names = "serial"; 2257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 226a7a77e2eSThierry Reding reset-names = "serial"; 22739cb62cbSJoseph Lo status = "disabled"; 22839cb62cbSJoseph Lo }; 22939cb62cbSJoseph Lo 23040cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 231250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 23240cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 23340cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 23440cc83b3SThierry Reding #address-cells = <1>; 23540cc83b3SThierry Reding #size-cells = <0>; 236c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 23740cc83b3SThierry Reding clock-names = "div-clk"; 2387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 23940cc83b3SThierry Reding reset-names = "i2c"; 24040cc83b3SThierry Reding status = "disabled"; 24140cc83b3SThierry Reding }; 24240cc83b3SThierry Reding 24340cc83b3SThierry Reding cam_i2c: i2c@3180000 { 244250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 24540cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 24640cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 24740cc83b3SThierry Reding #address-cells = <1>; 24840cc83b3SThierry Reding #size-cells = <0>; 249c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 25040cc83b3SThierry Reding clock-names = "div-clk"; 2517bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 25240cc83b3SThierry Reding reset-names = "i2c"; 25340cc83b3SThierry Reding status = "disabled"; 25440cc83b3SThierry Reding }; 25540cc83b3SThierry Reding 25640cc83b3SThierry Reding /* shares pads with dpaux1 */ 25740cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 258250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 25940cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 26040cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 26140cc83b3SThierry Reding #address-cells = <1>; 26240cc83b3SThierry Reding #size-cells = <0>; 263c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 26440cc83b3SThierry Reding clock-names = "div-clk"; 2657bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 26640cc83b3SThierry Reding reset-names = "i2c"; 267846137c6SThierry Reding pinctrl-names = "default", "idle"; 268846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 269846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 27040cc83b3SThierry Reding status = "disabled"; 27140cc83b3SThierry Reding }; 27240cc83b3SThierry Reding 27340cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 27440cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 275250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 27640cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 27740cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 27840cc83b3SThierry Reding #address-cells = <1>; 27940cc83b3SThierry Reding #size-cells = <0>; 280c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 28140cc83b3SThierry Reding clock-names = "div-clk"; 2827bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 28340cc83b3SThierry Reding reset-names = "i2c"; 28440cc83b3SThierry Reding status = "disabled"; 28540cc83b3SThierry Reding }; 28640cc83b3SThierry Reding 28740cc83b3SThierry Reding /* shares pads with dpaux0 */ 28840cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 289250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 29040cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 29140cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 29240cc83b3SThierry Reding #address-cells = <1>; 29340cc83b3SThierry Reding #size-cells = <0>; 294c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 29540cc83b3SThierry Reding clock-names = "div-clk"; 2967bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 29740cc83b3SThierry Reding reset-names = "i2c"; 298846137c6SThierry Reding pinctrl-names = "default", "idle"; 299846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 300846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 30140cc83b3SThierry Reding status = "disabled"; 30240cc83b3SThierry Reding }; 30340cc83b3SThierry Reding 30440cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 305250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 30640cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 30740cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 30840cc83b3SThierry Reding #address-cells = <1>; 30940cc83b3SThierry Reding #size-cells = <0>; 310c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 31140cc83b3SThierry Reding clock-names = "div-clk"; 3127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 31340cc83b3SThierry Reding reset-names = "i2c"; 31440cc83b3SThierry Reding status = "disabled"; 31540cc83b3SThierry Reding }; 31640cc83b3SThierry Reding 31740cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 318250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 31940cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 32040cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 32140cc83b3SThierry Reding #address-cells = <1>; 32240cc83b3SThierry Reding #size-cells = <0>; 323c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 32440cc83b3SThierry Reding clock-names = "div-clk"; 3257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 32640cc83b3SThierry Reding reset-names = "i2c"; 32740cc83b3SThierry Reding status = "disabled"; 32840cc83b3SThierry Reding }; 32940cc83b3SThierry Reding 33099425dfdSThierry Reding sdmmc1: sdhci@3400000 { 33199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 33299425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 33399425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 334c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 33599425dfdSThierry Reding clock-names = "sdhci"; 3367bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 33799425dfdSThierry Reding reset-names = "sdhci"; 3388589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 33924005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 34024005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 34124005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 34241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 34341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 34441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 34541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 34641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 34741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 3486f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3496f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 35098a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 35198a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 35298a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 35399425dfdSThierry Reding status = "disabled"; 35499425dfdSThierry Reding }; 35599425dfdSThierry Reding 35699425dfdSThierry Reding sdmmc2: sdhci@3420000 { 35799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 35899425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 35999425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 360c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 36199425dfdSThierry Reding clock-names = "sdhci"; 3627bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 36399425dfdSThierry Reding reset-names = "sdhci"; 3648589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 36524005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 36624005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 36724005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 36841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 36941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 37041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 37141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3726f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3736f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 37499425dfdSThierry Reding status = "disabled"; 37599425dfdSThierry Reding }; 37699425dfdSThierry Reding 37799425dfdSThierry Reding sdmmc3: sdhci@3440000 { 37899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 37999425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 38099425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 381c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 38299425dfdSThierry Reding clock-names = "sdhci"; 3837bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 38499425dfdSThierry Reding reset-names = "sdhci"; 3858589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 38624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 38724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 38824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 38941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 39041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 39141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 39241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 39341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 39441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3956f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 3966f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 39799425dfdSThierry Reding status = "disabled"; 39899425dfdSThierry Reding }; 39999425dfdSThierry Reding 40099425dfdSThierry Reding sdmmc4: sdhci@3460000 { 40199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 40299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 40399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 404c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 40599425dfdSThierry Reding clock-names = "sdhci"; 40698a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 40798a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 40898a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 4097bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 41099425dfdSThierry Reding reset-names = "sdhci"; 4118589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 41241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 41341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 41441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 41541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 4164e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 4174e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 418e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 419e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 42022248e91SAapo Vienamo nvidia,dqs-trim = <63>; 421207f60baSAapo Vienamo mmc-hs400-1_8v; 422c4307836SSowjanya Komatineni supports-cqe; 42399425dfdSThierry Reding status = "disabled"; 42499425dfdSThierry Reding }; 42599425dfdSThierry Reding 426b066a310SThierry Reding hda@3510000 { 427b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 428b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 429b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 430b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 431b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 432b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 433b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 434b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 435b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 436b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 437b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 438b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 439dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 440b066a310SThierry Reding status = "disabled"; 441b066a310SThierry Reding }; 442b066a310SThierry Reding 4438bfde518SThierry Reding padctl: padctl@3520000 { 4448bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 4458bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 4468bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 4478bfde518SThierry Reding reg-names = "padctl", "ao"; 4488bfde518SThierry Reding 4498bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 4508bfde518SThierry Reding reset-names = "padctl"; 4518bfde518SThierry Reding 4528bfde518SThierry Reding status = "disabled"; 4538bfde518SThierry Reding 4548bfde518SThierry Reding pads { 4558bfde518SThierry Reding usb2 { 4568bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 4578bfde518SThierry Reding clock-names = "trk"; 4588bfde518SThierry Reding status = "disabled"; 4598bfde518SThierry Reding 4608bfde518SThierry Reding lanes { 4618bfde518SThierry Reding usb2-0 { 4628bfde518SThierry Reding status = "disabled"; 4638bfde518SThierry Reding #phy-cells = <0>; 4648bfde518SThierry Reding }; 4658bfde518SThierry Reding 4668bfde518SThierry Reding usb2-1 { 4678bfde518SThierry Reding status = "disabled"; 4688bfde518SThierry Reding #phy-cells = <0>; 4698bfde518SThierry Reding }; 4708bfde518SThierry Reding 4718bfde518SThierry Reding usb2-2 { 4728bfde518SThierry Reding status = "disabled"; 4738bfde518SThierry Reding #phy-cells = <0>; 4748bfde518SThierry Reding }; 4758bfde518SThierry Reding }; 4768bfde518SThierry Reding }; 4778bfde518SThierry Reding 4788bfde518SThierry Reding hsic { 4798bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 4808bfde518SThierry Reding clock-names = "trk"; 4818bfde518SThierry Reding status = "disabled"; 4828bfde518SThierry Reding 4838bfde518SThierry Reding lanes { 4848bfde518SThierry Reding hsic-0 { 4858bfde518SThierry Reding status = "disabled"; 4868bfde518SThierry Reding #phy-cells = <0>; 4878bfde518SThierry Reding }; 4888bfde518SThierry Reding }; 4898bfde518SThierry Reding }; 4908bfde518SThierry Reding 4918bfde518SThierry Reding usb3 { 4928bfde518SThierry Reding status = "disabled"; 4938bfde518SThierry Reding 4948bfde518SThierry Reding lanes { 4958bfde518SThierry Reding usb3-0 { 4968bfde518SThierry Reding status = "disabled"; 4978bfde518SThierry Reding #phy-cells = <0>; 4988bfde518SThierry Reding }; 4998bfde518SThierry Reding 5008bfde518SThierry Reding usb3-1 { 5018bfde518SThierry Reding status = "disabled"; 5028bfde518SThierry Reding #phy-cells = <0>; 5038bfde518SThierry Reding }; 5048bfde518SThierry Reding 5058bfde518SThierry Reding usb3-2 { 5068bfde518SThierry Reding status = "disabled"; 5078bfde518SThierry Reding #phy-cells = <0>; 5088bfde518SThierry Reding }; 5098bfde518SThierry Reding }; 5108bfde518SThierry Reding }; 5118bfde518SThierry Reding }; 5128bfde518SThierry Reding 5138bfde518SThierry Reding ports { 5148bfde518SThierry Reding usb2-0 { 5158bfde518SThierry Reding status = "disabled"; 5168bfde518SThierry Reding }; 5178bfde518SThierry Reding 5188bfde518SThierry Reding usb2-1 { 5198bfde518SThierry Reding status = "disabled"; 5208bfde518SThierry Reding }; 5218bfde518SThierry Reding 5228bfde518SThierry Reding usb2-2 { 5238bfde518SThierry Reding status = "disabled"; 5248bfde518SThierry Reding }; 5258bfde518SThierry Reding 5268bfde518SThierry Reding hsic-0 { 5278bfde518SThierry Reding status = "disabled"; 5288bfde518SThierry Reding }; 5298bfde518SThierry Reding 5308bfde518SThierry Reding usb3-0 { 5318bfde518SThierry Reding status = "disabled"; 5328bfde518SThierry Reding }; 5338bfde518SThierry Reding 5348bfde518SThierry Reding usb3-1 { 5358bfde518SThierry Reding status = "disabled"; 5368bfde518SThierry Reding }; 5378bfde518SThierry Reding 5388bfde518SThierry Reding usb3-2 { 5398bfde518SThierry Reding status = "disabled"; 5408bfde518SThierry Reding }; 5418bfde518SThierry Reding }; 5428bfde518SThierry Reding }; 5438bfde518SThierry Reding 5448bfde518SThierry Reding usb@3530000 { 5458bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 5468bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 5478bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 5488bfde518SThierry Reding reg-names = "hcd", "fpci"; 5498bfde518SThierry Reding 55005705c72SNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 5518bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 5528bfde518SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 5538bfde518SThierry Reding <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 5548bfde518SThierry Reding 5558bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 5568bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 5578bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 5588bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 5598bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5608bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 5618bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 5628bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 5638bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 5648bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 5658bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 5668bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 5678bfde518SThierry Reding 5688bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 5698bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 5708bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 5718bfde518SThierry Reding nvidia,xusb-padctl = <&padctl>; 5728bfde518SThierry Reding 5738bfde518SThierry Reding status = "disabled"; 5748bfde518SThierry Reding 5758bfde518SThierry Reding #address-cells = <1>; 5768bfde518SThierry Reding #size-cells = <0>; 5778bfde518SThierry Reding }; 5788bfde518SThierry Reding 57985593b75SThierry Reding fuse@3820000 { 58085593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 58185593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 58285593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 58385593b75SThierry Reding clock-names = "fuse"; 58485593b75SThierry Reding }; 58585593b75SThierry Reding 58639cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 58739cb62cbSJoseph Lo compatible = "arm,gic-400"; 58839cb62cbSJoseph Lo #interrupt-cells = <3>; 58939cb62cbSJoseph Lo interrupt-controller; 59039cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 59139cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 59239cb62cbSJoseph Lo interrupts = <GIC_PPI 9 59339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 59439cb62cbSJoseph Lo interrupt-parent = <&gic>; 59539cb62cbSJoseph Lo }; 59639cb62cbSJoseph Lo 59797cf683cSThierry Reding cec@3960000 { 59897cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 59997cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 60097cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 60197cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 60297cf683cSThierry Reding clock-names = "cec"; 60397cf683cSThierry Reding status = "disabled"; 60497cf683cSThierry Reding }; 60597cf683cSThierry Reding 60639cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 60739cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 60839cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 60939cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 61039cb62cbSJoseph Lo interrupt-names = "doorbell"; 61139cb62cbSJoseph Lo #mbox-cells = <2>; 61239cb62cbSJoseph Lo status = "disabled"; 61339cb62cbSJoseph Lo }; 61439cb62cbSJoseph Lo 61540cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 616250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 61740cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 61840cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 61940cc83b3SThierry Reding #address-cells = <1>; 62040cc83b3SThierry Reding #size-cells = <0>; 621c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 62240cc83b3SThierry Reding clock-names = "div-clk"; 6237bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 62440cc83b3SThierry Reding reset-names = "i2c"; 62540cc83b3SThierry Reding status = "disabled"; 62640cc83b3SThierry Reding }; 62740cc83b3SThierry Reding 62840cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 629250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 63040cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 63140cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 63240cc83b3SThierry Reding #address-cells = <1>; 63340cc83b3SThierry Reding #size-cells = <0>; 634c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 63540cc83b3SThierry Reding clock-names = "div-clk"; 6367bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 63740cc83b3SThierry Reding reset-names = "i2c"; 63840cc83b3SThierry Reding status = "disabled"; 63940cc83b3SThierry Reding }; 64040cc83b3SThierry Reding 641a7a77e2eSThierry Reding uartc: serial@c280000 { 642a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 644a7a77e2eSThierry Reding reg-shift = <2>; 645a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 646c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 647a7a77e2eSThierry Reding clock-names = "serial"; 6487bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 649a7a77e2eSThierry Reding reset-names = "serial"; 650a7a77e2eSThierry Reding status = "disabled"; 651a7a77e2eSThierry Reding }; 652a7a77e2eSThierry Reding 653a7a77e2eSThierry Reding uartg: serial@c290000 { 654a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 656a7a77e2eSThierry Reding reg-shift = <2>; 657a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 658c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 659a7a77e2eSThierry Reding clock-names = "serial"; 6607bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 661a7a77e2eSThierry Reding reset-names = "serial"; 662a7a77e2eSThierry Reding status = "disabled"; 663a7a77e2eSThierry Reding }; 664a7a77e2eSThierry Reding 6659733a251SThierry Reding rtc: rtc@c2a0000 { 6669733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 6679733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 6689733a251SThierry Reding interrupt-parent = <&pmc>; 6699733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 6709733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 6719733a251SThierry Reding clock-names = "rtc"; 6729733a251SThierry Reding status = "disabled"; 6739733a251SThierry Reding }; 6749733a251SThierry Reding 675fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 676fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 677fc4bb754SThierry Reding reg-names = "security", "gpio"; 678fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 679fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 680fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 681fc4bb754SThierry Reding gpio-controller; 682fc4bb754SThierry Reding #gpio-cells = <2>; 683fc4bb754SThierry Reding interrupt-controller; 684fc4bb754SThierry Reding #interrupt-cells = <2>; 685fc4bb754SThierry Reding }; 686fc4bb754SThierry Reding 68732e66e46SThierry Reding pmc: pmc@c360000 { 68873bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 68973bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 69073bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 69173bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 69273bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 69373bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 69424005fd1SAapo Vienamo 69532e66e46SThierry Reding #interrupt-cells = <2>; 69632e66e46SThierry Reding interrupt-controller; 69732e66e46SThierry Reding 69824005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 69924005fd1SAapo Vienamo pins = "sdmmc1-hv"; 70024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 70124005fd1SAapo Vienamo }; 70224005fd1SAapo Vienamo 70324005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 70424005fd1SAapo Vienamo pins = "sdmmc1-hv"; 70524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 70624005fd1SAapo Vienamo }; 70724005fd1SAapo Vienamo 70824005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 70924005fd1SAapo Vienamo pins = "sdmmc2-hv"; 71024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 71124005fd1SAapo Vienamo }; 71224005fd1SAapo Vienamo 71324005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 71424005fd1SAapo Vienamo pins = "sdmmc2-hv"; 71524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 71624005fd1SAapo Vienamo }; 71724005fd1SAapo Vienamo 71824005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 71924005fd1SAapo Vienamo pins = "sdmmc3-hv"; 72024005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 72124005fd1SAapo Vienamo }; 72224005fd1SAapo Vienamo 72324005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 72424005fd1SAapo Vienamo pins = "sdmmc3-hv"; 72524005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 72624005fd1SAapo Vienamo }; 72773bf90d4SThierry Reding }; 72873bf90d4SThierry Reding 7297b7ef494SMikko Perttunen ccplex@e000000 { 7307b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 7317b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 7327b7ef494SMikko Perttunen 7337b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 7347b7ef494SMikko Perttunen }; 7357b7ef494SMikko Perttunen 736f8973cf4SManikanta Maddireddy pcie@10003000 { 737f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 738f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 739f8973cf4SManikanta Maddireddy device_type = "pci"; 740f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 741f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 742f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 743f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 744f8973cf4SManikanta Maddireddy 745f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 746f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 747f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 748f8973cf4SManikanta Maddireddy 749f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 750f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 751f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 752f8973cf4SManikanta Maddireddy 753f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 754f8973cf4SManikanta Maddireddy #address-cells = <3>; 755f8973cf4SManikanta Maddireddy #size-cells = <2>; 756f8973cf4SManikanta Maddireddy 757f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 758f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 759f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 760f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 761f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 762f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 763f8973cf4SManikanta Maddireddy 764f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 765f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 766f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 767f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 768f8973cf4SManikanta Maddireddy 769f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 770f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 771f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 772f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 773f8973cf4SManikanta Maddireddy 774f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 775f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 776f2a465e7SThierry Reding iommu-map-mask = <0x0>; 777f2a465e7SThierry Reding 778f8973cf4SManikanta Maddireddy status = "disabled"; 779f8973cf4SManikanta Maddireddy 780f8973cf4SManikanta Maddireddy pci@1,0 { 781f8973cf4SManikanta Maddireddy device_type = "pci"; 782f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 783f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 784f8973cf4SManikanta Maddireddy status = "disabled"; 785f8973cf4SManikanta Maddireddy 786f8973cf4SManikanta Maddireddy #address-cells = <3>; 787f8973cf4SManikanta Maddireddy #size-cells = <2>; 788f8973cf4SManikanta Maddireddy ranges; 789f8973cf4SManikanta Maddireddy 790f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 791f8973cf4SManikanta Maddireddy }; 792f8973cf4SManikanta Maddireddy 793f8973cf4SManikanta Maddireddy pci@2,0 { 794f8973cf4SManikanta Maddireddy device_type = "pci"; 795f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 796f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 797f8973cf4SManikanta Maddireddy status = "disabled"; 798f8973cf4SManikanta Maddireddy 799f8973cf4SManikanta Maddireddy #address-cells = <3>; 800f8973cf4SManikanta Maddireddy #size-cells = <2>; 801f8973cf4SManikanta Maddireddy ranges; 802f8973cf4SManikanta Maddireddy 803f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 804f8973cf4SManikanta Maddireddy }; 805f8973cf4SManikanta Maddireddy 806f8973cf4SManikanta Maddireddy pci@3,0 { 807f8973cf4SManikanta Maddireddy device_type = "pci"; 808f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 809f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 810f8973cf4SManikanta Maddireddy status = "disabled"; 811f8973cf4SManikanta Maddireddy 812f8973cf4SManikanta Maddireddy #address-cells = <3>; 813f8973cf4SManikanta Maddireddy #size-cells = <2>; 814f8973cf4SManikanta Maddireddy ranges; 815f8973cf4SManikanta Maddireddy 816f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 817f8973cf4SManikanta Maddireddy }; 818f8973cf4SManikanta Maddireddy }; 819f8973cf4SManikanta Maddireddy 820b30a8e61SThierry Reding smmu: iommu@12000000 { 821b30a8e61SThierry Reding compatible = "arm,mmu-500"; 822b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 823b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 888b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 889b30a8e61SThierry Reding #global-interrupts = <1>; 890b30a8e61SThierry Reding #iommu-cells = <1>; 891b30a8e61SThierry Reding }; 892b30a8e61SThierry Reding 8935524c61fSMikko Perttunen host1x@13e00000 { 8945524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 8955524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 8965524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 8975524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 8985524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 8995524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 9005524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 9015524c61fSMikko Perttunen clock-names = "host1x"; 9025524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 9035524c61fSMikko Perttunen reset-names = "host1x"; 9045524c61fSMikko Perttunen 9055524c61fSMikko Perttunen #address-cells = <1>; 9065524c61fSMikko Perttunen #size-cells = <1>; 9075524c61fSMikko Perttunen 9085524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 909c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 910c2599da7SThierry Reding 911c2599da7SThierry Reding dpaux1: dpaux@15040000 { 912c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 913c2599da7SThierry Reding reg = <0x15040000 0x10000>; 914c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 915c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 916c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 917c2599da7SThierry Reding clock-names = "dpaux", "parent"; 918c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 919c2599da7SThierry Reding reset-names = "dpaux"; 920c2599da7SThierry Reding status = "disabled"; 921c2599da7SThierry Reding 922c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 923c2599da7SThierry Reding 924c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 925c2599da7SThierry Reding groups = "dpaux-io"; 926c2599da7SThierry Reding function = "aux"; 927c2599da7SThierry Reding }; 928c2599da7SThierry Reding 929c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 930c2599da7SThierry Reding groups = "dpaux-io"; 931c2599da7SThierry Reding function = "i2c"; 932c2599da7SThierry Reding }; 933c2599da7SThierry Reding 934c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 935c2599da7SThierry Reding groups = "dpaux-io"; 936c2599da7SThierry Reding function = "off"; 937c2599da7SThierry Reding }; 938c2599da7SThierry Reding 939c2599da7SThierry Reding i2c-bus { 940c2599da7SThierry Reding #address-cells = <1>; 941c2599da7SThierry Reding #size-cells = <0>; 942c2599da7SThierry Reding }; 943c2599da7SThierry Reding }; 944c2599da7SThierry Reding 945c2599da7SThierry Reding display-hub@15200000 { 946c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 947ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 948c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 949c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 950c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 951c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 952c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 953c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 954c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 955c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 956c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 957c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 958c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 959c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 960c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 961c2599da7SThierry Reding status = "disabled"; 962c2599da7SThierry Reding 963c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 964c2599da7SThierry Reding 965c2599da7SThierry Reding #address-cells = <1>; 966c2599da7SThierry Reding #size-cells = <1>; 967c2599da7SThierry Reding 968c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 969c2599da7SThierry Reding 970c2599da7SThierry Reding display@15200000 { 971c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 972c2599da7SThierry Reding reg = <0x15200000 0x10000>; 973c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 974c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 975c2599da7SThierry Reding clock-names = "dc"; 976c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 977c2599da7SThierry Reding reset-names = "dc"; 978c2599da7SThierry Reding 979c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 980c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 981c2599da7SThierry Reding 982c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 983c2599da7SThierry Reding nvidia,head = <0>; 984c2599da7SThierry Reding }; 985c2599da7SThierry Reding 986c2599da7SThierry Reding display@15210000 { 987c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 988c2599da7SThierry Reding reg = <0x15210000 0x10000>; 989c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 990c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 991c2599da7SThierry Reding clock-names = "dc"; 992c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 993c2599da7SThierry Reding reset-names = "dc"; 994c2599da7SThierry Reding 995c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 996c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 997c2599da7SThierry Reding 998c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 999c2599da7SThierry Reding nvidia,head = <1>; 1000c2599da7SThierry Reding }; 1001c2599da7SThierry Reding 1002c2599da7SThierry Reding display@15220000 { 1003c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1004c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1005c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1006c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1007c2599da7SThierry Reding clock-names = "dc"; 1008c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1009c2599da7SThierry Reding reset-names = "dc"; 1010c2599da7SThierry Reding 1011c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1012c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1013c2599da7SThierry Reding 1014c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1015c2599da7SThierry Reding nvidia,head = <2>; 1016c2599da7SThierry Reding }; 1017c2599da7SThierry Reding }; 1018c2599da7SThierry Reding 1019c2599da7SThierry Reding dsia: dsi@15300000 { 1020c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1021c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1022c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1023c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1024c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1025c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1026c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1027c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1028c2599da7SThierry Reding reset-names = "dsi"; 1029c2599da7SThierry Reding status = "disabled"; 1030c2599da7SThierry Reding 1031c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1032c2599da7SThierry Reding }; 1033effc4b44SMikko Perttunen 1034effc4b44SMikko Perttunen vic@15340000 { 1035effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1036effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1037effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1038effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1039effc4b44SMikko Perttunen clock-names = "vic"; 1040effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1041effc4b44SMikko Perttunen reset-names = "vic"; 1042effc4b44SMikko Perttunen 1043effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 104429ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1045effc4b44SMikko Perttunen }; 1046c2599da7SThierry Reding 1047c2599da7SThierry Reding dsib: dsi@15400000 { 1048c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1049c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1050c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1051c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1052c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1053c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1054c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1055c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1056c2599da7SThierry Reding reset-names = "dsi"; 1057c2599da7SThierry Reding status = "disabled"; 1058c2599da7SThierry Reding 1059c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1060c2599da7SThierry Reding }; 1061c2599da7SThierry Reding 1062c2599da7SThierry Reding sor0: sor@15540000 { 1063c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1064c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1065c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1066c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1067c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1068c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1069c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1070c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1071c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1072c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1073c2599da7SThierry Reding "pad"; 1074c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1075c2599da7SThierry Reding reset-names = "sor"; 1076c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1077c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1078c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1079c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1080c2599da7SThierry Reding status = "disabled"; 1081c2599da7SThierry Reding 1082c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1083c2599da7SThierry Reding nvidia,interface = <0>; 1084c2599da7SThierry Reding }; 1085c2599da7SThierry Reding 1086c2599da7SThierry Reding sor1: sor@15580000 { 1087d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1088c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1089c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1090c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1091c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1092c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1093c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1094c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1095c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1096c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1097c2599da7SThierry Reding "pad"; 1098c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1099c2599da7SThierry Reding reset-names = "sor"; 1100c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1101c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1102c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1103c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1104c2599da7SThierry Reding status = "disabled"; 1105c2599da7SThierry Reding 1106c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1107c2599da7SThierry Reding nvidia,interface = <1>; 1108c2599da7SThierry Reding }; 1109c2599da7SThierry Reding 1110c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1111c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1112c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1113c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1114c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1115c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1116c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1117c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1118c2599da7SThierry Reding reset-names = "dpaux"; 1119c2599da7SThierry Reding status = "disabled"; 1120c2599da7SThierry Reding 1121c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1122c2599da7SThierry Reding 1123c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1124c2599da7SThierry Reding groups = "dpaux-io"; 1125c2599da7SThierry Reding function = "aux"; 1126c2599da7SThierry Reding }; 1127c2599da7SThierry Reding 1128c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1129c2599da7SThierry Reding groups = "dpaux-io"; 1130c2599da7SThierry Reding function = "i2c"; 1131c2599da7SThierry Reding }; 1132c2599da7SThierry Reding 1133c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1134c2599da7SThierry Reding groups = "dpaux-io"; 1135c2599da7SThierry Reding function = "off"; 1136c2599da7SThierry Reding }; 1137c2599da7SThierry Reding 1138c2599da7SThierry Reding i2c-bus { 1139c2599da7SThierry Reding #address-cells = <1>; 1140c2599da7SThierry Reding #size-cells = <0>; 1141c2599da7SThierry Reding }; 1142c2599da7SThierry Reding }; 1143c2599da7SThierry Reding 1144c2599da7SThierry Reding padctl@15880000 { 1145c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1146c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1147c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1148c2599da7SThierry Reding reset-names = "dsi"; 1149c2599da7SThierry Reding status = "disabled"; 1150c2599da7SThierry Reding }; 1151c2599da7SThierry Reding 1152c2599da7SThierry Reding dsic: dsi@15900000 { 1153c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1154c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1155c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1156c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1157c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1158c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1159c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1160c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1161c2599da7SThierry Reding reset-names = "dsi"; 1162c2599da7SThierry Reding status = "disabled"; 1163c2599da7SThierry Reding 1164c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1165c2599da7SThierry Reding }; 1166c2599da7SThierry Reding 1167c2599da7SThierry Reding dsid: dsi@15940000 { 1168c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1169c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1170c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1171c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1172c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1173c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1174c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1175c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1176c2599da7SThierry Reding reset-names = "dsi"; 1177c2599da7SThierry Reding status = "disabled"; 1178c2599da7SThierry Reding 1179c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1180c2599da7SThierry Reding }; 11815524c61fSMikko Perttunen }; 11825524c61fSMikko Perttunen 1183dfd7a384SAlexandre Courbot gpu@17000000 { 1184dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1185dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1186dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 1187dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1188dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1189dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1190dfd7a384SAlexandre Courbot 1191dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1192dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1193dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1194dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1195dfd7a384SAlexandre Courbot reset-names = "gpu"; 1196dfd7a384SAlexandre Courbot status = "disabled"; 1197dfd7a384SAlexandre Courbot 1198dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1199dfd7a384SAlexandre Courbot }; 1200dfd7a384SAlexandre Courbot 120139cb62cbSJoseph Lo sysram@30000000 { 120239cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 120339cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 120439cb62cbSJoseph Lo #address-cells = <2>; 120539cb62cbSJoseph Lo #size-cells = <2>; 120639cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 120739cb62cbSJoseph Lo 120839cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 120939cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 121039cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 121139cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 121239cb62cbSJoseph Lo pool; 121339cb62cbSJoseph Lo }; 121439cb62cbSJoseph Lo 121539cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 121639cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 121739cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 121839cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 121939cb62cbSJoseph Lo pool; 122039cb62cbSJoseph Lo }; 122139cb62cbSJoseph Lo }; 122239cb62cbSJoseph Lo 1223541d7c44SThierry Reding bpmp: bpmp { 1224541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1225541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1226541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1227541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1228541d7c44SThierry Reding shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1229541d7c44SThierry Reding #clock-cells = <1>; 1230541d7c44SThierry Reding #reset-cells = <1>; 1231541d7c44SThierry Reding #power-domain-cells = <1>; 1232541d7c44SThierry Reding 1233541d7c44SThierry Reding bpmp_i2c: i2c { 1234541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1235541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1236541d7c44SThierry Reding #address-cells = <1>; 1237541d7c44SThierry Reding #size-cells = <0>; 1238541d7c44SThierry Reding status = "disabled"; 1239541d7c44SThierry Reding }; 1240541d7c44SThierry Reding 1241541d7c44SThierry Reding bpmp_thermal: thermal { 1242541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1243541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1244541d7c44SThierry Reding }; 1245541d7c44SThierry Reding }; 1246541d7c44SThierry Reding 1247cd6fe32eSThierry Reding cpus { 1248cd6fe32eSThierry Reding #address-cells = <1>; 1249cd6fe32eSThierry Reding #size-cells = <0>; 1250cd6fe32eSThierry Reding 1251cd6fe32eSThierry Reding cpu@0 { 125231af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1253cd6fe32eSThierry Reding device_type = "cpu"; 12545298166dSJoseph Lo i-cache-size = <0x20000>; 12555298166dSJoseph Lo i-cache-line-size = <64>; 12565298166dSJoseph Lo i-cache-sets = <512>; 12575298166dSJoseph Lo d-cache-size = <0x10000>; 12585298166dSJoseph Lo d-cache-line-size = <64>; 12595298166dSJoseph Lo d-cache-sets = <256>; 12605298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1261cd6fe32eSThierry Reding reg = <0x000>; 1262cd6fe32eSThierry Reding }; 1263cd6fe32eSThierry Reding 1264cd6fe32eSThierry Reding cpu@1 { 126531af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1266cd6fe32eSThierry Reding device_type = "cpu"; 12675298166dSJoseph Lo i-cache-size = <0x20000>; 12685298166dSJoseph Lo i-cache-line-size = <64>; 12695298166dSJoseph Lo i-cache-sets = <512>; 12705298166dSJoseph Lo d-cache-size = <0x10000>; 12715298166dSJoseph Lo d-cache-line-size = <64>; 12725298166dSJoseph Lo d-cache-sets = <256>; 12735298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1274cd6fe32eSThierry Reding reg = <0x001>; 1275cd6fe32eSThierry Reding }; 1276cd6fe32eSThierry Reding 1277cd6fe32eSThierry Reding cpu@2 { 127831af04cdSRob Herring compatible = "arm,cortex-a57"; 1279cd6fe32eSThierry Reding device_type = "cpu"; 12805298166dSJoseph Lo i-cache-size = <0xC000>; 12815298166dSJoseph Lo i-cache-line-size = <64>; 12825298166dSJoseph Lo i-cache-sets = <256>; 12835298166dSJoseph Lo d-cache-size = <0x8000>; 12845298166dSJoseph Lo d-cache-line-size = <64>; 12855298166dSJoseph Lo d-cache-sets = <256>; 12865298166dSJoseph Lo next-level-cache = <&L2_A57>; 1287cd6fe32eSThierry Reding reg = <0x100>; 1288cd6fe32eSThierry Reding }; 1289cd6fe32eSThierry Reding 1290cd6fe32eSThierry Reding cpu@3 { 129131af04cdSRob Herring compatible = "arm,cortex-a57"; 1292cd6fe32eSThierry Reding device_type = "cpu"; 12935298166dSJoseph Lo i-cache-size = <0xC000>; 12945298166dSJoseph Lo i-cache-line-size = <64>; 12955298166dSJoseph Lo i-cache-sets = <256>; 12965298166dSJoseph Lo d-cache-size = <0x8000>; 12975298166dSJoseph Lo d-cache-line-size = <64>; 12985298166dSJoseph Lo d-cache-sets = <256>; 12995298166dSJoseph Lo next-level-cache = <&L2_A57>; 1300cd6fe32eSThierry Reding reg = <0x101>; 1301cd6fe32eSThierry Reding }; 1302cd6fe32eSThierry Reding 1303cd6fe32eSThierry Reding cpu@4 { 130431af04cdSRob Herring compatible = "arm,cortex-a57"; 1305cd6fe32eSThierry Reding device_type = "cpu"; 13065298166dSJoseph Lo i-cache-size = <0xC000>; 13075298166dSJoseph Lo i-cache-line-size = <64>; 13085298166dSJoseph Lo i-cache-sets = <256>; 13095298166dSJoseph Lo d-cache-size = <0x8000>; 13105298166dSJoseph Lo d-cache-line-size = <64>; 13115298166dSJoseph Lo d-cache-sets = <256>; 13125298166dSJoseph Lo next-level-cache = <&L2_A57>; 1313cd6fe32eSThierry Reding reg = <0x102>; 1314cd6fe32eSThierry Reding }; 1315cd6fe32eSThierry Reding 1316cd6fe32eSThierry Reding cpu@5 { 131731af04cdSRob Herring compatible = "arm,cortex-a57"; 1318cd6fe32eSThierry Reding device_type = "cpu"; 13195298166dSJoseph Lo i-cache-size = <0xC000>; 13205298166dSJoseph Lo i-cache-line-size = <64>; 13215298166dSJoseph Lo i-cache-sets = <256>; 13225298166dSJoseph Lo d-cache-size = <0x8000>; 13235298166dSJoseph Lo d-cache-line-size = <64>; 13245298166dSJoseph Lo d-cache-sets = <256>; 13255298166dSJoseph Lo next-level-cache = <&L2_A57>; 1326cd6fe32eSThierry Reding reg = <0x103>; 1327cd6fe32eSThierry Reding }; 13285298166dSJoseph Lo 13295298166dSJoseph Lo L2_DENVER: l2-cache0 { 13305298166dSJoseph Lo compatible = "cache"; 13315298166dSJoseph Lo cache-unified; 13325298166dSJoseph Lo cache-level = <2>; 13335298166dSJoseph Lo cache-size = <0x200000>; 13345298166dSJoseph Lo cache-line-size = <64>; 13355298166dSJoseph Lo cache-sets = <2048>; 13365298166dSJoseph Lo }; 13375298166dSJoseph Lo 13385298166dSJoseph Lo L2_A57: l2-cache1 { 13395298166dSJoseph Lo compatible = "cache"; 13405298166dSJoseph Lo cache-unified; 13415298166dSJoseph Lo cache-level = <2>; 13425298166dSJoseph Lo cache-size = <0x200000>; 13435298166dSJoseph Lo cache-line-size = <64>; 13445298166dSJoseph Lo cache-sets = <2048>; 13455298166dSJoseph Lo }; 1346cd6fe32eSThierry Reding }; 1347cd6fe32eSThierry Reding 134815274c23SMikko Perttunen thermal-zones { 134915274c23SMikko Perttunen a57 { 135015274c23SMikko Perttunen polling-delay = <0>; 135115274c23SMikko Perttunen polling-delay-passive = <1000>; 135215274c23SMikko Perttunen 135315274c23SMikko Perttunen thermal-sensors = 135415274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 135515274c23SMikko Perttunen 135615274c23SMikko Perttunen trips { 135715274c23SMikko Perttunen critical { 135815274c23SMikko Perttunen temperature = <101000>; 135915274c23SMikko Perttunen hysteresis = <0>; 136015274c23SMikko Perttunen type = "critical"; 136115274c23SMikko Perttunen }; 136215274c23SMikko Perttunen }; 136315274c23SMikko Perttunen 136415274c23SMikko Perttunen cooling-maps { 136515274c23SMikko Perttunen }; 136615274c23SMikko Perttunen }; 136715274c23SMikko Perttunen 136815274c23SMikko Perttunen denver { 136915274c23SMikko Perttunen polling-delay = <0>; 137015274c23SMikko Perttunen polling-delay-passive = <1000>; 137115274c23SMikko Perttunen 137215274c23SMikko Perttunen thermal-sensors = 137315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 137415274c23SMikko Perttunen 137515274c23SMikko Perttunen trips { 137615274c23SMikko Perttunen critical { 137715274c23SMikko Perttunen temperature = <101000>; 137815274c23SMikko Perttunen hysteresis = <0>; 137915274c23SMikko Perttunen type = "critical"; 138015274c23SMikko Perttunen }; 138115274c23SMikko Perttunen }; 138215274c23SMikko Perttunen 138315274c23SMikko Perttunen cooling-maps { 138415274c23SMikko Perttunen }; 138515274c23SMikko Perttunen }; 138615274c23SMikko Perttunen 138715274c23SMikko Perttunen gpu { 138815274c23SMikko Perttunen polling-delay = <0>; 138915274c23SMikko Perttunen polling-delay-passive = <1000>; 139015274c23SMikko Perttunen 139115274c23SMikko Perttunen thermal-sensors = 139215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 139315274c23SMikko Perttunen 139415274c23SMikko Perttunen trips { 139515274c23SMikko Perttunen critical { 139615274c23SMikko Perttunen temperature = <101000>; 139715274c23SMikko Perttunen hysteresis = <0>; 139815274c23SMikko Perttunen type = "critical"; 139915274c23SMikko Perttunen }; 140015274c23SMikko Perttunen }; 140115274c23SMikko Perttunen 140215274c23SMikko Perttunen cooling-maps { 140315274c23SMikko Perttunen }; 140415274c23SMikko Perttunen }; 140515274c23SMikko Perttunen 140615274c23SMikko Perttunen pll { 140715274c23SMikko Perttunen polling-delay = <0>; 140815274c23SMikko Perttunen polling-delay-passive = <1000>; 140915274c23SMikko Perttunen 141015274c23SMikko Perttunen thermal-sensors = 141115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 141215274c23SMikko Perttunen 141315274c23SMikko Perttunen trips { 141415274c23SMikko Perttunen critical { 141515274c23SMikko Perttunen temperature = <101000>; 141615274c23SMikko Perttunen hysteresis = <0>; 141715274c23SMikko Perttunen type = "critical"; 141815274c23SMikko Perttunen }; 141915274c23SMikko Perttunen }; 142015274c23SMikko Perttunen 142115274c23SMikko Perttunen cooling-maps { 142215274c23SMikko Perttunen }; 142315274c23SMikko Perttunen }; 142415274c23SMikko Perttunen 142515274c23SMikko Perttunen always_on { 142615274c23SMikko Perttunen polling-delay = <0>; 142715274c23SMikko Perttunen polling-delay-passive = <1000>; 142815274c23SMikko Perttunen 142915274c23SMikko Perttunen thermal-sensors = 143015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 143115274c23SMikko Perttunen 143215274c23SMikko Perttunen trips { 143315274c23SMikko Perttunen critical { 143415274c23SMikko Perttunen temperature = <101000>; 143515274c23SMikko Perttunen hysteresis = <0>; 143615274c23SMikko Perttunen type = "critical"; 143715274c23SMikko Perttunen }; 143815274c23SMikko Perttunen }; 143915274c23SMikko Perttunen 144015274c23SMikko Perttunen cooling-maps { 144115274c23SMikko Perttunen }; 144215274c23SMikko Perttunen }; 144339cb62cbSJoseph Lo }; 144439cb62cbSJoseph Lo 144539cb62cbSJoseph Lo timer { 144639cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 144739cb62cbSJoseph Lo interrupts = <GIC_PPI 13 144839cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 144939cb62cbSJoseph Lo <GIC_PPI 14 145039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 145139cb62cbSJoseph Lo <GIC_PPI 11 145239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 145339cb62cbSJoseph Lo <GIC_PPI 10 145439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 145539cb62cbSJoseph Lo interrupt-parent = <&gic>; 1456b30be673SThierry Reding always-on; 145739cb62cbSJoseph Lo }; 145839cb62cbSJoseph Lo}; 1459