1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 630caafbdeSThierry Reding status = "disabled"; 640caafbdeSThierry Reding 650caafbdeSThierry Reding snps,write-requests = <1>; 660caafbdeSThierry Reding snps,read-requests = <3>; 670caafbdeSThierry Reding snps,burst-map = <0x7>; 680caafbdeSThierry Reding snps,txpbl = <32>; 690caafbdeSThierry Reding snps,rxpbl = <8>; 700caafbdeSThierry Reding }; 710caafbdeSThierry Reding 72d25a3bf1SThierry Reding memory-controller@2c00000 { 73d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 74d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 75d25a3bf1SThierry Reding status = "disabled"; 76d25a3bf1SThierry Reding }; 77d25a3bf1SThierry Reding 7839cb62cbSJoseph Lo uarta: serial@3100000 { 7939cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 8039cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 8139cb62cbSJoseph Lo reg-shift = <2>; 8239cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 84a7a77e2eSThierry Reding clock-names = "serial"; 857bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 86a7a77e2eSThierry Reding reset-names = "serial"; 87a7a77e2eSThierry Reding status = "disabled"; 88a7a77e2eSThierry Reding }; 89a7a77e2eSThierry Reding 90a7a77e2eSThierry Reding uartb: serial@3110000 { 91a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 93a7a77e2eSThierry Reding reg-shift = <2>; 94a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 96a7a77e2eSThierry Reding clock-names = "serial"; 977bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 98a7a77e2eSThierry Reding reset-names = "serial"; 99a7a77e2eSThierry Reding status = "disabled"; 100a7a77e2eSThierry Reding }; 101a7a77e2eSThierry Reding 102a7a77e2eSThierry Reding uartd: serial@3130000 { 103a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 105a7a77e2eSThierry Reding reg-shift = <2>; 106a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 108a7a77e2eSThierry Reding clock-names = "serial"; 1097bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 110a7a77e2eSThierry Reding reset-names = "serial"; 111a7a77e2eSThierry Reding status = "disabled"; 112a7a77e2eSThierry Reding }; 113a7a77e2eSThierry Reding 114a7a77e2eSThierry Reding uarte: serial@3140000 { 115a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 117a7a77e2eSThierry Reding reg-shift = <2>; 118a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 120a7a77e2eSThierry Reding clock-names = "serial"; 1217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 122a7a77e2eSThierry Reding reset-names = "serial"; 123a7a77e2eSThierry Reding status = "disabled"; 124a7a77e2eSThierry Reding }; 125a7a77e2eSThierry Reding 126a7a77e2eSThierry Reding uartf: serial@3150000 { 127a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 129a7a77e2eSThierry Reding reg-shift = <2>; 130a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 132a7a77e2eSThierry Reding clock-names = "serial"; 1337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 134a7a77e2eSThierry Reding reset-names = "serial"; 13539cb62cbSJoseph Lo status = "disabled"; 13639cb62cbSJoseph Lo }; 13739cb62cbSJoseph Lo 13840cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 13940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 14040cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 14140cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 14240cc83b3SThierry Reding #address-cells = <1>; 14340cc83b3SThierry Reding #size-cells = <0>; 144c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 14540cc83b3SThierry Reding clock-names = "div-clk"; 1467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 14740cc83b3SThierry Reding reset-names = "i2c"; 14840cc83b3SThierry Reding status = "disabled"; 14940cc83b3SThierry Reding }; 15040cc83b3SThierry Reding 15140cc83b3SThierry Reding cam_i2c: i2c@3180000 { 15240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15340cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 15440cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 15540cc83b3SThierry Reding #address-cells = <1>; 15640cc83b3SThierry Reding #size-cells = <0>; 157c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 15840cc83b3SThierry Reding clock-names = "div-clk"; 1597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 16040cc83b3SThierry Reding reset-names = "i2c"; 16140cc83b3SThierry Reding status = "disabled"; 16240cc83b3SThierry Reding }; 16340cc83b3SThierry Reding 16440cc83b3SThierry Reding /* shares pads with dpaux1 */ 16540cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 16640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16740cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 16840cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 16940cc83b3SThierry Reding #address-cells = <1>; 17040cc83b3SThierry Reding #size-cells = <0>; 171c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 17240cc83b3SThierry Reding clock-names = "div-clk"; 1737bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 17440cc83b3SThierry Reding reset-names = "i2c"; 17540cc83b3SThierry Reding status = "disabled"; 17640cc83b3SThierry Reding }; 17740cc83b3SThierry Reding 17840cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 17940cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 18040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 18140cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 18240cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 18340cc83b3SThierry Reding #address-cells = <1>; 18440cc83b3SThierry Reding #size-cells = <0>; 185c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 18640cc83b3SThierry Reding clock-names = "div-clk"; 1877bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 18840cc83b3SThierry Reding reset-names = "i2c"; 18940cc83b3SThierry Reding status = "disabled"; 19040cc83b3SThierry Reding }; 19140cc83b3SThierry Reding 19240cc83b3SThierry Reding /* shares pads with dpaux0 */ 19340cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 19440cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19540cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 19640cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 19740cc83b3SThierry Reding #address-cells = <1>; 19840cc83b3SThierry Reding #size-cells = <0>; 199c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 20040cc83b3SThierry Reding clock-names = "div-clk"; 2017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 20240cc83b3SThierry Reding reset-names = "i2c"; 20340cc83b3SThierry Reding status = "disabled"; 20440cc83b3SThierry Reding }; 20540cc83b3SThierry Reding 20640cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 20740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20840cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 20940cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 21040cc83b3SThierry Reding #address-cells = <1>; 21140cc83b3SThierry Reding #size-cells = <0>; 212c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 21340cc83b3SThierry Reding clock-names = "div-clk"; 2147bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 21540cc83b3SThierry Reding reset-names = "i2c"; 21640cc83b3SThierry Reding status = "disabled"; 21740cc83b3SThierry Reding }; 21840cc83b3SThierry Reding 21940cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 22040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 22140cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 22240cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 22340cc83b3SThierry Reding #address-cells = <1>; 22440cc83b3SThierry Reding #size-cells = <0>; 225c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 22640cc83b3SThierry Reding clock-names = "div-clk"; 2277bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 22840cc83b3SThierry Reding reset-names = "i2c"; 22940cc83b3SThierry Reding status = "disabled"; 23040cc83b3SThierry Reding }; 23140cc83b3SThierry Reding 23299425dfdSThierry Reding sdmmc1: sdhci@3400000 { 23399425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23499425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 23599425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 23799425dfdSThierry Reding clock-names = "sdhci"; 2387bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 23999425dfdSThierry Reding reset-names = "sdhci"; 24024005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 24124005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 24224005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 24399425dfdSThierry Reding status = "disabled"; 24499425dfdSThierry Reding }; 24599425dfdSThierry Reding 24699425dfdSThierry Reding sdmmc2: sdhci@3420000 { 24799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 24899425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 24999425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 250c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 25199425dfdSThierry Reding clock-names = "sdhci"; 2527bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 25399425dfdSThierry Reding reset-names = "sdhci"; 25424005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 25524005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 25624005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 25799425dfdSThierry Reding status = "disabled"; 25899425dfdSThierry Reding }; 25999425dfdSThierry Reding 26099425dfdSThierry Reding sdmmc3: sdhci@3440000 { 26199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 26299425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 26399425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 264c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 26599425dfdSThierry Reding clock-names = "sdhci"; 2667bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 26799425dfdSThierry Reding reset-names = "sdhci"; 26824005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 26924005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 27024005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 27199425dfdSThierry Reding status = "disabled"; 27299425dfdSThierry Reding }; 27399425dfdSThierry Reding 27499425dfdSThierry Reding sdmmc4: sdhci@3460000 { 27599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 27699425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 27799425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 278c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 27999425dfdSThierry Reding clock-names = "sdhci"; 2807bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 28199425dfdSThierry Reding reset-names = "sdhci"; 28299425dfdSThierry Reding status = "disabled"; 28399425dfdSThierry Reding }; 28499425dfdSThierry Reding 28585593b75SThierry Reding fuse@3820000 { 28685593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 28785593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 28885593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 28985593b75SThierry Reding clock-names = "fuse"; 29085593b75SThierry Reding }; 29185593b75SThierry Reding 29239cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 29339cb62cbSJoseph Lo compatible = "arm,gic-400"; 29439cb62cbSJoseph Lo #interrupt-cells = <3>; 29539cb62cbSJoseph Lo interrupt-controller; 29639cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 29739cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 29839cb62cbSJoseph Lo interrupts = <GIC_PPI 9 29939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 30039cb62cbSJoseph Lo interrupt-parent = <&gic>; 30139cb62cbSJoseph Lo }; 30239cb62cbSJoseph Lo 30339cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 30439cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 30539cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 30639cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 30739cb62cbSJoseph Lo interrupt-names = "doorbell"; 30839cb62cbSJoseph Lo #mbox-cells = <2>; 30939cb62cbSJoseph Lo status = "disabled"; 31039cb62cbSJoseph Lo }; 31139cb62cbSJoseph Lo 31240cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 31340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 31440cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 31540cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 31640cc83b3SThierry Reding #address-cells = <1>; 31740cc83b3SThierry Reding #size-cells = <0>; 318c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 31940cc83b3SThierry Reding clock-names = "div-clk"; 3207bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 32140cc83b3SThierry Reding reset-names = "i2c"; 32240cc83b3SThierry Reding status = "disabled"; 32340cc83b3SThierry Reding }; 32440cc83b3SThierry Reding 32540cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 32640cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 32740cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 32840cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 32940cc83b3SThierry Reding #address-cells = <1>; 33040cc83b3SThierry Reding #size-cells = <0>; 331c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 33240cc83b3SThierry Reding clock-names = "div-clk"; 3337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 33440cc83b3SThierry Reding reset-names = "i2c"; 33540cc83b3SThierry Reding status = "disabled"; 33640cc83b3SThierry Reding }; 33740cc83b3SThierry Reding 338a7a77e2eSThierry Reding uartc: serial@c280000 { 339a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 340a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 341a7a77e2eSThierry Reding reg-shift = <2>; 342a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 343c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 344a7a77e2eSThierry Reding clock-names = "serial"; 3457bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 346a7a77e2eSThierry Reding reset-names = "serial"; 347a7a77e2eSThierry Reding status = "disabled"; 348a7a77e2eSThierry Reding }; 349a7a77e2eSThierry Reding 350a7a77e2eSThierry Reding uartg: serial@c290000 { 351a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 352a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 353a7a77e2eSThierry Reding reg-shift = <2>; 354a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 355c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 356a7a77e2eSThierry Reding clock-names = "serial"; 3577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 358a7a77e2eSThierry Reding reset-names = "serial"; 359a7a77e2eSThierry Reding status = "disabled"; 360a7a77e2eSThierry Reding }; 361a7a77e2eSThierry Reding 362fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 363fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 364fc4bb754SThierry Reding reg-names = "security", "gpio"; 365fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 366fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 367fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 368fc4bb754SThierry Reding gpio-controller; 369fc4bb754SThierry Reding #gpio-cells = <2>; 370fc4bb754SThierry Reding interrupt-controller; 371fc4bb754SThierry Reding #interrupt-cells = <2>; 372fc4bb754SThierry Reding }; 373fc4bb754SThierry Reding 37473bf90d4SThierry Reding pmc@c360000 { 37573bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 37673bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 37773bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 37873bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 37973bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 38073bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 38124005fd1SAapo Vienamo 38224005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 38324005fd1SAapo Vienamo pins = "sdmmc1-hv"; 38424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 38524005fd1SAapo Vienamo }; 38624005fd1SAapo Vienamo 38724005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 38824005fd1SAapo Vienamo pins = "sdmmc1-hv"; 38924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 39024005fd1SAapo Vienamo }; 39124005fd1SAapo Vienamo 39224005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 39324005fd1SAapo Vienamo pins = "sdmmc2-hv"; 39424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 39524005fd1SAapo Vienamo }; 39624005fd1SAapo Vienamo 39724005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 39824005fd1SAapo Vienamo pins = "sdmmc2-hv"; 39924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 40024005fd1SAapo Vienamo }; 40124005fd1SAapo Vienamo 40224005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 40324005fd1SAapo Vienamo pins = "sdmmc3-hv"; 40424005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 40524005fd1SAapo Vienamo }; 40624005fd1SAapo Vienamo 40724005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 40824005fd1SAapo Vienamo pins = "sdmmc3-hv"; 40924005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 41024005fd1SAapo Vienamo }; 41173bf90d4SThierry Reding }; 41273bf90d4SThierry Reding 4137b7ef494SMikko Perttunen ccplex@e000000 { 4147b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 4157b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 4167b7ef494SMikko Perttunen 4177b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 4187b7ef494SMikko Perttunen }; 4197b7ef494SMikko Perttunen 420f8973cf4SManikanta Maddireddy pcie@10003000 { 421f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 422f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 423f8973cf4SManikanta Maddireddy device_type = "pci"; 424f8973cf4SManikanta Maddireddy reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 425f8973cf4SManikanta Maddireddy 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 426f8973cf4SManikanta Maddireddy 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 427f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 428f8973cf4SManikanta Maddireddy 429f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 430f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 431f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 432f8973cf4SManikanta Maddireddy 433f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 434f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 435f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 436f8973cf4SManikanta Maddireddy 437f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 438f8973cf4SManikanta Maddireddy #address-cells = <3>; 439f8973cf4SManikanta Maddireddy #size-cells = <2>; 440f8973cf4SManikanta Maddireddy 441f8973cf4SManikanta Maddireddy ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 442f8973cf4SManikanta Maddireddy 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 443f8973cf4SManikanta Maddireddy 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 444f8973cf4SManikanta Maddireddy 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 445f8973cf4SManikanta Maddireddy 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 446f8973cf4SManikanta Maddireddy 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 447f8973cf4SManikanta Maddireddy 448f8973cf4SManikanta Maddireddy clocks = <&bpmp TEGRA186_CLK_AFI>, 449f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PCIE>, 450f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 451f8973cf4SManikanta Maddireddy clock-names = "afi", "pex", "pll_e"; 452f8973cf4SManikanta Maddireddy 453f8973cf4SManikanta Maddireddy resets = <&bpmp TEGRA186_RESET_AFI>, 454f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIE>, 455f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 456f8973cf4SManikanta Maddireddy reset-names = "afi", "pex", "pcie_x"; 457f8973cf4SManikanta Maddireddy 458f8973cf4SManikanta Maddireddy status = "disabled"; 459f8973cf4SManikanta Maddireddy 460f8973cf4SManikanta Maddireddy pci@1,0 { 461f8973cf4SManikanta Maddireddy device_type = "pci"; 462f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 463f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 464f8973cf4SManikanta Maddireddy status = "disabled"; 465f8973cf4SManikanta Maddireddy 466f8973cf4SManikanta Maddireddy #address-cells = <3>; 467f8973cf4SManikanta Maddireddy #size-cells = <2>; 468f8973cf4SManikanta Maddireddy ranges; 469f8973cf4SManikanta Maddireddy 470f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 471f8973cf4SManikanta Maddireddy }; 472f8973cf4SManikanta Maddireddy 473f8973cf4SManikanta Maddireddy pci@2,0 { 474f8973cf4SManikanta Maddireddy device_type = "pci"; 475f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 476f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 477f8973cf4SManikanta Maddireddy status = "disabled"; 478f8973cf4SManikanta Maddireddy 479f8973cf4SManikanta Maddireddy #address-cells = <3>; 480f8973cf4SManikanta Maddireddy #size-cells = <2>; 481f8973cf4SManikanta Maddireddy ranges; 482f8973cf4SManikanta Maddireddy 483f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 484f8973cf4SManikanta Maddireddy }; 485f8973cf4SManikanta Maddireddy 486f8973cf4SManikanta Maddireddy pci@3,0 { 487f8973cf4SManikanta Maddireddy device_type = "pci"; 488f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 489f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 490f8973cf4SManikanta Maddireddy status = "disabled"; 491f8973cf4SManikanta Maddireddy 492f8973cf4SManikanta Maddireddy #address-cells = <3>; 493f8973cf4SManikanta Maddireddy #size-cells = <2>; 494f8973cf4SManikanta Maddireddy ranges; 495f8973cf4SManikanta Maddireddy 496f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 497f8973cf4SManikanta Maddireddy }; 498f8973cf4SManikanta Maddireddy }; 499f8973cf4SManikanta Maddireddy 500b30a8e61SThierry Reding smmu: iommu@12000000 { 501b30a8e61SThierry Reding compatible = "arm,mmu-500"; 502b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 503b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 504b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 505b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 506b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 507b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 508b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 509b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 510b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 511b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 512b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 513b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 514b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 515b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 516b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 517b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 518b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 519b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 520b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 521b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 522b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 523b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 528b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 529b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 530b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 531b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 532b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 533b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 534b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 535b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 536b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 537b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 568b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 569b30a8e61SThierry Reding #global-interrupts = <1>; 570b30a8e61SThierry Reding #iommu-cells = <1>; 571b30a8e61SThierry Reding }; 572b30a8e61SThierry Reding 5735524c61fSMikko Perttunen host1x@13e00000 { 5745524c61fSMikko Perttunen compatible = "nvidia,tegra186-host1x", "simple-bus"; 5755524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 5765524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 5775524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 5785524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 5795524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 5805524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 5815524c61fSMikko Perttunen clock-names = "host1x"; 5825524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 5835524c61fSMikko Perttunen reset-names = "host1x"; 5845524c61fSMikko Perttunen 5855524c61fSMikko Perttunen #address-cells = <1>; 5865524c61fSMikko Perttunen #size-cells = <1>; 5875524c61fSMikko Perttunen 5885524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 589c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 590c2599da7SThierry Reding 591c2599da7SThierry Reding dpaux1: dpaux@15040000 { 592c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 593c2599da7SThierry Reding reg = <0x15040000 0x10000>; 594c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 595c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 596c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 597c2599da7SThierry Reding clock-names = "dpaux", "parent"; 598c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 599c2599da7SThierry Reding reset-names = "dpaux"; 600c2599da7SThierry Reding status = "disabled"; 601c2599da7SThierry Reding 602c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 603c2599da7SThierry Reding 604c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 605c2599da7SThierry Reding groups = "dpaux-io"; 606c2599da7SThierry Reding function = "aux"; 607c2599da7SThierry Reding }; 608c2599da7SThierry Reding 609c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 610c2599da7SThierry Reding groups = "dpaux-io"; 611c2599da7SThierry Reding function = "i2c"; 612c2599da7SThierry Reding }; 613c2599da7SThierry Reding 614c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 615c2599da7SThierry Reding groups = "dpaux-io"; 616c2599da7SThierry Reding function = "off"; 617c2599da7SThierry Reding }; 618c2599da7SThierry Reding 619c2599da7SThierry Reding i2c-bus { 620c2599da7SThierry Reding #address-cells = <1>; 621c2599da7SThierry Reding #size-cells = <0>; 622c2599da7SThierry Reding }; 623c2599da7SThierry Reding }; 624c2599da7SThierry Reding 625c2599da7SThierry Reding display-hub@15200000 { 626c2599da7SThierry Reding compatible = "nvidia,tegra186-display", "simple-bus"; 627c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 628c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 629c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 630c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 631c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 632c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 633c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 634c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 635c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 636c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 637c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 638c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 639c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 640c2599da7SThierry Reding status = "disabled"; 641c2599da7SThierry Reding 642c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 643c2599da7SThierry Reding 644c2599da7SThierry Reding #address-cells = <1>; 645c2599da7SThierry Reding #size-cells = <1>; 646c2599da7SThierry Reding 647c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 648c2599da7SThierry Reding 649c2599da7SThierry Reding display@15200000 { 650c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 651c2599da7SThierry Reding reg = <0x15200000 0x10000>; 652c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 653c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 654c2599da7SThierry Reding clock-names = "dc"; 655c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 656c2599da7SThierry Reding reset-names = "dc"; 657c2599da7SThierry Reding 658c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 659c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 660c2599da7SThierry Reding 661c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 662c2599da7SThierry Reding nvidia,head = <0>; 663c2599da7SThierry Reding }; 664c2599da7SThierry Reding 665c2599da7SThierry Reding display@15210000 { 666c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 667c2599da7SThierry Reding reg = <0x15210000 0x10000>; 668c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 669c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 670c2599da7SThierry Reding clock-names = "dc"; 671c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 672c2599da7SThierry Reding reset-names = "dc"; 673c2599da7SThierry Reding 674c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 675c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 676c2599da7SThierry Reding 677c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 678c2599da7SThierry Reding nvidia,head = <1>; 679c2599da7SThierry Reding }; 680c2599da7SThierry Reding 681c2599da7SThierry Reding display@15220000 { 682c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 683c2599da7SThierry Reding reg = <0x15220000 0x10000>; 684c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 685c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 686c2599da7SThierry Reding clock-names = "dc"; 687c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 688c2599da7SThierry Reding reset-names = "dc"; 689c2599da7SThierry Reding 690c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 691c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 692c2599da7SThierry Reding 693c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 694c2599da7SThierry Reding nvidia,head = <2>; 695c2599da7SThierry Reding }; 696c2599da7SThierry Reding }; 697c2599da7SThierry Reding 698c2599da7SThierry Reding dsia: dsi@15300000 { 699c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 700c2599da7SThierry Reding reg = <0x15300000 0x10000>; 701c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 702c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 703c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 704c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 705c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 706c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 707c2599da7SThierry Reding reset-names = "dsi"; 708c2599da7SThierry Reding status = "disabled"; 709c2599da7SThierry Reding 710c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 711c2599da7SThierry Reding }; 712effc4b44SMikko Perttunen 713effc4b44SMikko Perttunen vic@15340000 { 714effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 715effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 716effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 717effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 718effc4b44SMikko Perttunen clock-names = "vic"; 719effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 720effc4b44SMikko Perttunen reset-names = "vic"; 721effc4b44SMikko Perttunen 722effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 723effc4b44SMikko Perttunen }; 724c2599da7SThierry Reding 725c2599da7SThierry Reding dsib: dsi@15400000 { 726c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 727c2599da7SThierry Reding reg = <0x15400000 0x10000>; 728c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 729c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 730c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 731c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 732c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 733c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 734c2599da7SThierry Reding reset-names = "dsi"; 735c2599da7SThierry Reding status = "disabled"; 736c2599da7SThierry Reding 737c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 738c2599da7SThierry Reding }; 739c2599da7SThierry Reding 740c2599da7SThierry Reding sor0: sor@15540000 { 741c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 742c2599da7SThierry Reding reg = <0x15540000 0x10000>; 743c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 744c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 745c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 746c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 747c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 748c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 749c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 750c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 751c2599da7SThierry Reding "pad"; 752c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 753c2599da7SThierry Reding reset-names = "sor"; 754c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 755c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 756c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 757c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 758c2599da7SThierry Reding status = "disabled"; 759c2599da7SThierry Reding 760c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 761c2599da7SThierry Reding nvidia,interface = <0>; 762c2599da7SThierry Reding }; 763c2599da7SThierry Reding 764c2599da7SThierry Reding sor1: sor@15580000 { 765c2599da7SThierry Reding compatible = "nvidia,tegra186-sor1"; 766c2599da7SThierry Reding reg = <0x15580000 0x10000>; 767c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 768c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 769c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 770c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 771c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 772c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 773c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 774c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 775c2599da7SThierry Reding "pad"; 776c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 777c2599da7SThierry Reding reset-names = "sor"; 778c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 779c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 780c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 781c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 782c2599da7SThierry Reding status = "disabled"; 783c2599da7SThierry Reding 784c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 785c2599da7SThierry Reding nvidia,interface = <1>; 786c2599da7SThierry Reding }; 787c2599da7SThierry Reding 788c2599da7SThierry Reding dpaux: dpaux@155c0000 { 789c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 790c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 791c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 792c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 793c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 794c2599da7SThierry Reding clock-names = "dpaux", "parent"; 795c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 796c2599da7SThierry Reding reset-names = "dpaux"; 797c2599da7SThierry Reding status = "disabled"; 798c2599da7SThierry Reding 799c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 800c2599da7SThierry Reding 801c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 802c2599da7SThierry Reding groups = "dpaux-io"; 803c2599da7SThierry Reding function = "aux"; 804c2599da7SThierry Reding }; 805c2599da7SThierry Reding 806c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 807c2599da7SThierry Reding groups = "dpaux-io"; 808c2599da7SThierry Reding function = "i2c"; 809c2599da7SThierry Reding }; 810c2599da7SThierry Reding 811c2599da7SThierry Reding state_dpaux_off: pinmux-off { 812c2599da7SThierry Reding groups = "dpaux-io"; 813c2599da7SThierry Reding function = "off"; 814c2599da7SThierry Reding }; 815c2599da7SThierry Reding 816c2599da7SThierry Reding i2c-bus { 817c2599da7SThierry Reding #address-cells = <1>; 818c2599da7SThierry Reding #size-cells = <0>; 819c2599da7SThierry Reding }; 820c2599da7SThierry Reding }; 821c2599da7SThierry Reding 822c2599da7SThierry Reding padctl@15880000 { 823c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 824c2599da7SThierry Reding reg = <0x15880000 0x10000>; 825c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 826c2599da7SThierry Reding reset-names = "dsi"; 827c2599da7SThierry Reding status = "disabled"; 828c2599da7SThierry Reding }; 829c2599da7SThierry Reding 830c2599da7SThierry Reding dsic: dsi@15900000 { 831c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 832c2599da7SThierry Reding reg = <0x15900000 0x10000>; 833c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 834c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 835c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 836c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 837c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 838c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 839c2599da7SThierry Reding reset-names = "dsi"; 840c2599da7SThierry Reding status = "disabled"; 841c2599da7SThierry Reding 842c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 843c2599da7SThierry Reding }; 844c2599da7SThierry Reding 845c2599da7SThierry Reding dsid: dsi@15940000 { 846c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 847c2599da7SThierry Reding reg = <0x15940000 0x10000>; 848c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 849c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 850c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 851c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 852c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 853c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 854c2599da7SThierry Reding reset-names = "dsi"; 855c2599da7SThierry Reding status = "disabled"; 856c2599da7SThierry Reding 857c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 858c2599da7SThierry Reding }; 8595524c61fSMikko Perttunen }; 8605524c61fSMikko Perttunen 861dfd7a384SAlexandre Courbot gpu@17000000 { 862dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 863dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 864dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 865dfd7a384SAlexandre Courbot interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 866dfd7a384SAlexandre Courbot GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 867dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 868dfd7a384SAlexandre Courbot 869dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 870dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 871dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 872dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 873dfd7a384SAlexandre Courbot reset-names = "gpu"; 874dfd7a384SAlexandre Courbot status = "disabled"; 875dfd7a384SAlexandre Courbot 876dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 877dfd7a384SAlexandre Courbot }; 878dfd7a384SAlexandre Courbot 87939cb62cbSJoseph Lo sysram@30000000 { 88039cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 88139cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 88239cb62cbSJoseph Lo #address-cells = <2>; 88339cb62cbSJoseph Lo #size-cells = <2>; 88439cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 88539cb62cbSJoseph Lo 88639cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 88739cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 88839cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 88939cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 89039cb62cbSJoseph Lo pool; 89139cb62cbSJoseph Lo }; 89239cb62cbSJoseph Lo 89339cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 89439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 89539cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 89639cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 89739cb62cbSJoseph Lo pool; 89839cb62cbSJoseph Lo }; 89939cb62cbSJoseph Lo }; 90039cb62cbSJoseph Lo 901cd6fe32eSThierry Reding cpus { 902cd6fe32eSThierry Reding #address-cells = <1>; 903cd6fe32eSThierry Reding #size-cells = <0>; 904cd6fe32eSThierry Reding 905cd6fe32eSThierry Reding cpu@0 { 906cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 907cd6fe32eSThierry Reding device_type = "cpu"; 908cd6fe32eSThierry Reding reg = <0x000>; 909cd6fe32eSThierry Reding }; 910cd6fe32eSThierry Reding 911cd6fe32eSThierry Reding cpu@1 { 912cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 913cd6fe32eSThierry Reding device_type = "cpu"; 914cd6fe32eSThierry Reding reg = <0x001>; 915cd6fe32eSThierry Reding }; 916cd6fe32eSThierry Reding 917cd6fe32eSThierry Reding cpu@2 { 918cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 919cd6fe32eSThierry Reding device_type = "cpu"; 920cd6fe32eSThierry Reding reg = <0x100>; 921cd6fe32eSThierry Reding }; 922cd6fe32eSThierry Reding 923cd6fe32eSThierry Reding cpu@3 { 924cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 925cd6fe32eSThierry Reding device_type = "cpu"; 926cd6fe32eSThierry Reding reg = <0x101>; 927cd6fe32eSThierry Reding }; 928cd6fe32eSThierry Reding 929cd6fe32eSThierry Reding cpu@4 { 930cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 931cd6fe32eSThierry Reding device_type = "cpu"; 932cd6fe32eSThierry Reding reg = <0x102>; 933cd6fe32eSThierry Reding }; 934cd6fe32eSThierry Reding 935cd6fe32eSThierry Reding cpu@5 { 936cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 937cd6fe32eSThierry Reding device_type = "cpu"; 938cd6fe32eSThierry Reding reg = <0x103>; 939cd6fe32eSThierry Reding }; 940cd6fe32eSThierry Reding }; 941cd6fe32eSThierry Reding 94239cb62cbSJoseph Lo bpmp: bpmp { 94339cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 9445edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 9455edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 94639cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 94739cb62cbSJoseph Lo #clock-cells = <1>; 94839cb62cbSJoseph Lo #reset-cells = <1>; 949dcbc5e44SMikko Perttunen #power-domain-cells = <1>; 95039cb62cbSJoseph Lo 95139cb62cbSJoseph Lo bpmp_i2c: i2c { 95239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 95339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 95439cb62cbSJoseph Lo #address-cells = <1>; 95539cb62cbSJoseph Lo #size-cells = <0>; 95639cb62cbSJoseph Lo status = "disabled"; 95739cb62cbSJoseph Lo }; 95815274c23SMikko Perttunen 95915274c23SMikko Perttunen bpmp_thermal: thermal { 96015274c23SMikko Perttunen compatible = "nvidia,tegra186-bpmp-thermal"; 96115274c23SMikko Perttunen #thermal-sensor-cells = <1>; 96215274c23SMikko Perttunen }; 96315274c23SMikko Perttunen }; 96415274c23SMikko Perttunen 96515274c23SMikko Perttunen thermal-zones { 96615274c23SMikko Perttunen a57 { 96715274c23SMikko Perttunen polling-delay = <0>; 96815274c23SMikko Perttunen polling-delay-passive = <1000>; 96915274c23SMikko Perttunen 97015274c23SMikko Perttunen thermal-sensors = 97115274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 97215274c23SMikko Perttunen 97315274c23SMikko Perttunen trips { 97415274c23SMikko Perttunen critical { 97515274c23SMikko Perttunen temperature = <101000>; 97615274c23SMikko Perttunen hysteresis = <0>; 97715274c23SMikko Perttunen type = "critical"; 97815274c23SMikko Perttunen }; 97915274c23SMikko Perttunen }; 98015274c23SMikko Perttunen 98115274c23SMikko Perttunen cooling-maps { 98215274c23SMikko Perttunen }; 98315274c23SMikko Perttunen }; 98415274c23SMikko Perttunen 98515274c23SMikko Perttunen denver { 98615274c23SMikko Perttunen polling-delay = <0>; 98715274c23SMikko Perttunen polling-delay-passive = <1000>; 98815274c23SMikko Perttunen 98915274c23SMikko Perttunen thermal-sensors = 99015274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 99115274c23SMikko Perttunen 99215274c23SMikko Perttunen trips { 99315274c23SMikko Perttunen critical { 99415274c23SMikko Perttunen temperature = <101000>; 99515274c23SMikko Perttunen hysteresis = <0>; 99615274c23SMikko Perttunen type = "critical"; 99715274c23SMikko Perttunen }; 99815274c23SMikko Perttunen }; 99915274c23SMikko Perttunen 100015274c23SMikko Perttunen cooling-maps { 100115274c23SMikko Perttunen }; 100215274c23SMikko Perttunen }; 100315274c23SMikko Perttunen 100415274c23SMikko Perttunen gpu { 100515274c23SMikko Perttunen polling-delay = <0>; 100615274c23SMikko Perttunen polling-delay-passive = <1000>; 100715274c23SMikko Perttunen 100815274c23SMikko Perttunen thermal-sensors = 100915274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 101015274c23SMikko Perttunen 101115274c23SMikko Perttunen trips { 101215274c23SMikko Perttunen critical { 101315274c23SMikko Perttunen temperature = <101000>; 101415274c23SMikko Perttunen hysteresis = <0>; 101515274c23SMikko Perttunen type = "critical"; 101615274c23SMikko Perttunen }; 101715274c23SMikko Perttunen }; 101815274c23SMikko Perttunen 101915274c23SMikko Perttunen cooling-maps { 102015274c23SMikko Perttunen }; 102115274c23SMikko Perttunen }; 102215274c23SMikko Perttunen 102315274c23SMikko Perttunen pll { 102415274c23SMikko Perttunen polling-delay = <0>; 102515274c23SMikko Perttunen polling-delay-passive = <1000>; 102615274c23SMikko Perttunen 102715274c23SMikko Perttunen thermal-sensors = 102815274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 102915274c23SMikko Perttunen 103015274c23SMikko Perttunen trips { 103115274c23SMikko Perttunen critical { 103215274c23SMikko Perttunen temperature = <101000>; 103315274c23SMikko Perttunen hysteresis = <0>; 103415274c23SMikko Perttunen type = "critical"; 103515274c23SMikko Perttunen }; 103615274c23SMikko Perttunen }; 103715274c23SMikko Perttunen 103815274c23SMikko Perttunen cooling-maps { 103915274c23SMikko Perttunen }; 104015274c23SMikko Perttunen }; 104115274c23SMikko Perttunen 104215274c23SMikko Perttunen always_on { 104315274c23SMikko Perttunen polling-delay = <0>; 104415274c23SMikko Perttunen polling-delay-passive = <1000>; 104515274c23SMikko Perttunen 104615274c23SMikko Perttunen thermal-sensors = 104715274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 104815274c23SMikko Perttunen 104915274c23SMikko Perttunen trips { 105015274c23SMikko Perttunen critical { 105115274c23SMikko Perttunen temperature = <101000>; 105215274c23SMikko Perttunen hysteresis = <0>; 105315274c23SMikko Perttunen type = "critical"; 105415274c23SMikko Perttunen }; 105515274c23SMikko Perttunen }; 105615274c23SMikko Perttunen 105715274c23SMikko Perttunen cooling-maps { 105815274c23SMikko Perttunen }; 105915274c23SMikko Perttunen }; 106039cb62cbSJoseph Lo }; 106139cb62cbSJoseph Lo 106239cb62cbSJoseph Lo timer { 106339cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 106439cb62cbSJoseph Lo interrupts = <GIC_PPI 13 106539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 106639cb62cbSJoseph Lo <GIC_PPI 14 106739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 106839cb62cbSJoseph Lo <GIC_PPI 11 106939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107039cb62cbSJoseph Lo <GIC_PPI 10 107139cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 107239cb62cbSJoseph Lo interrupt-parent = <&gic>; 107339cb62cbSJoseph Lo }; 107439cb62cbSJoseph Lo}; 1075