1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 765d2249ddSSameer Pujar aconnect { 775d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 785d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 795d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 805d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 815d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 825d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 835d2249ddSSameer Pujar #address-cells = <1>; 845d2249ddSSameer Pujar #size-cells = <1>; 855d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 865d2249ddSSameer Pujar status = "disabled"; 875d2249ddSSameer Pujar 88177208f7SSameer Pujar adma: dma-controller@2930000 { 895d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 905d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 915d2249ddSSameer Pujar interrupt-parent = <&agic>; 925d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 935d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 945d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 955d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 965d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 975d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 985d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 995d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1005d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1015d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1025d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1035d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1045d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1055d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1065d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1075d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1085d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1095d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1105d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1115d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1125d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1135d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1145d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1155d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1165d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1175d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1185d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1195d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1205d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1215d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1225d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1235d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1245d2249ddSSameer Pujar #dma-cells = <1>; 1255d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1265d2249ddSSameer Pujar clock-names = "d_audio"; 1275d2249ddSSameer Pujar status = "disabled"; 1285d2249ddSSameer Pujar }; 1295d2249ddSSameer Pujar 1305d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1325d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1335d2249ddSSameer Pujar #interrupt-cells = <3>; 1345d2249ddSSameer Pujar interrupt-controller; 1355d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1365d2249ddSSameer Pujar <0x02a42000 0x2000>; 1375d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1385d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1395d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1405d2249ddSSameer Pujar clock-names = "clk"; 1415d2249ddSSameer Pujar status = "disabled"; 1425d2249ddSSameer Pujar }; 143177208f7SSameer Pujar 144177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 145177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 146177208f7SSameer Pujar reg = <0x02900800 0x800>; 147177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 148177208f7SSameer Pujar clock-names = "ahub"; 149177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151177208f7SSameer Pujar #address-cells = <1>; 152177208f7SSameer Pujar #size-cells = <1>; 153177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 154177208f7SSameer Pujar status = "disabled"; 155177208f7SSameer Pujar 156177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 157177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 158177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 159177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 160177208f7SSameer Pujar <&adma 2>, <&adma 2>, 161177208f7SSameer Pujar <&adma 3>, <&adma 3>, 162177208f7SSameer Pujar <&adma 4>, <&adma 4>, 163177208f7SSameer Pujar <&adma 5>, <&adma 5>, 164177208f7SSameer Pujar <&adma 6>, <&adma 6>, 165177208f7SSameer Pujar <&adma 7>, <&adma 7>, 166177208f7SSameer Pujar <&adma 8>, <&adma 8>, 167177208f7SSameer Pujar <&adma 9>, <&adma 9>, 168177208f7SSameer Pujar <&adma 10>, <&adma 10>, 169177208f7SSameer Pujar <&adma 11>, <&adma 11>, 170177208f7SSameer Pujar <&adma 12>, <&adma 12>, 171177208f7SSameer Pujar <&adma 13>, <&adma 13>, 172177208f7SSameer Pujar <&adma 14>, <&adma 14>, 173177208f7SSameer Pujar <&adma 15>, <&adma 15>, 174177208f7SSameer Pujar <&adma 16>, <&adma 16>, 175177208f7SSameer Pujar <&adma 17>, <&adma 17>, 176177208f7SSameer Pujar <&adma 18>, <&adma 18>, 177177208f7SSameer Pujar <&adma 19>, <&adma 19>, 178177208f7SSameer Pujar <&adma 20>, <&adma 20>; 179177208f7SSameer Pujar dma-names = "rx1", "tx1", 180177208f7SSameer Pujar "rx2", "tx2", 181177208f7SSameer Pujar "rx3", "tx3", 182177208f7SSameer Pujar "rx4", "tx4", 183177208f7SSameer Pujar "rx5", "tx5", 184177208f7SSameer Pujar "rx6", "tx6", 185177208f7SSameer Pujar "rx7", "tx7", 186177208f7SSameer Pujar "rx8", "tx8", 187177208f7SSameer Pujar "rx9", "tx9", 188177208f7SSameer Pujar "rx10", "tx10", 189177208f7SSameer Pujar "rx11", "tx11", 190177208f7SSameer Pujar "rx12", "tx12", 191177208f7SSameer Pujar "rx13", "tx13", 192177208f7SSameer Pujar "rx14", "tx14", 193177208f7SSameer Pujar "rx15", "tx15", 194177208f7SSameer Pujar "rx16", "tx16", 195177208f7SSameer Pujar "rx17", "tx17", 196177208f7SSameer Pujar "rx18", "tx18", 197177208f7SSameer Pujar "rx19", "tx19", 198177208f7SSameer Pujar "rx20", "tx20"; 199177208f7SSameer Pujar status = "disabled"; 200177208f7SSameer Pujar }; 201177208f7SSameer Pujar 202177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 203177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 204177208f7SSameer Pujar "nvidia,tegra210-i2s"; 205177208f7SSameer Pujar reg = <0x2901000 0x100>; 206177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 207177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 209177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211177208f7SSameer Pujar assigned-clock-rates = <1536000>; 212177208f7SSameer Pujar sound-name-prefix = "I2S1"; 213177208f7SSameer Pujar status = "disabled"; 214177208f7SSameer Pujar }; 215177208f7SSameer Pujar 216177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 217177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 218177208f7SSameer Pujar "nvidia,tegra210-i2s"; 219177208f7SSameer Pujar reg = <0x2901100 0x100>; 220177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 221177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 223177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225177208f7SSameer Pujar assigned-clock-rates = <1536000>; 226177208f7SSameer Pujar sound-name-prefix = "I2S2"; 227177208f7SSameer Pujar status = "disabled"; 228177208f7SSameer Pujar }; 229177208f7SSameer Pujar 230177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 231177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 232177208f7SSameer Pujar "nvidia,tegra210-i2s"; 233177208f7SSameer Pujar reg = <0x2901200 0x100>; 234177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 235177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 237177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239177208f7SSameer Pujar assigned-clock-rates = <1536000>; 240177208f7SSameer Pujar sound-name-prefix = "I2S3"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901300 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S4"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901400 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S5"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901500 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S6"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 287177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 288177208f7SSameer Pujar reg = <0x2904000 0x100>; 289177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290177208f7SSameer Pujar clock-names = "dmic"; 291177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293177208f7SSameer Pujar assigned-clock-rates = <3072000>; 294177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 295177208f7SSameer Pujar status = "disabled"; 296177208f7SSameer Pujar }; 297177208f7SSameer Pujar 298177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 299177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 300177208f7SSameer Pujar reg = <0x2904100 0x100>; 301177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302177208f7SSameer Pujar clock-names = "dmic"; 303177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305177208f7SSameer Pujar assigned-clock-rates = <3072000>; 306177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 307177208f7SSameer Pujar status = "disabled"; 308177208f7SSameer Pujar }; 309177208f7SSameer Pujar 310177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 311177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 312177208f7SSameer Pujar reg = <0x2904200 0x100>; 313177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314177208f7SSameer Pujar clock-names = "dmic"; 315177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317177208f7SSameer Pujar assigned-clock-rates = <3072000>; 318177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 319177208f7SSameer Pujar status = "disabled"; 320177208f7SSameer Pujar }; 321177208f7SSameer Pujar 322177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 323177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 324177208f7SSameer Pujar reg = <0x2904300 0x100>; 325177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326177208f7SSameer Pujar clock-names = "dmic"; 327177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329177208f7SSameer Pujar assigned-clock-rates = <3072000>; 330177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 331177208f7SSameer Pujar status = "disabled"; 332177208f7SSameer Pujar }; 333177208f7SSameer Pujar 334177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 335177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 336177208f7SSameer Pujar reg = <0x2905000 0x100>; 337177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338177208f7SSameer Pujar clock-names = "dspk"; 339177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341177208f7SSameer Pujar assigned-clock-rates = <12288000>; 342177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 343177208f7SSameer Pujar status = "disabled"; 344177208f7SSameer Pujar }; 345177208f7SSameer Pujar 346177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 347177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 348177208f7SSameer Pujar reg = <0x2905100 0x100>; 349177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350177208f7SSameer Pujar clock-names = "dspk"; 351177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353177208f7SSameer Pujar assigned-clock-rates = <12288000>; 354177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 355177208f7SSameer Pujar status = "disabled"; 356177208f7SSameer Pujar }; 357177208f7SSameer Pujar }; 3585d2249ddSSameer Pujar }; 3595d2249ddSSameer Pujar 360954490b3SThierry Reding mc: memory-controller@2c00000 { 361d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 362d25a3bf1SThierry Reding reg = <0x0 0x02c00000 0x0 0xb0000>; 363b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 364d25a3bf1SThierry Reding status = "disabled"; 3653f6eaef9SThierry Reding 366954490b3SThierry Reding #interconnect-cells = <1>; 3673f6eaef9SThierry Reding #address-cells = <2>; 3683f6eaef9SThierry Reding #size-cells = <2>; 3693f6eaef9SThierry Reding 3703f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 3713f6eaef9SThierry Reding 3723f6eaef9SThierry Reding /* 3733f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 3743f6eaef9SThierry Reding * controller can address. 3753f6eaef9SThierry Reding */ 3763f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 3773f6eaef9SThierry Reding 3783f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 3793f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 3803f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 3813f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 3823f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 3833f6eaef9SThierry Reding clock-names = "emc"; 3843f6eaef9SThierry Reding 385954490b3SThierry Reding #interconnect-cells = <0>; 386954490b3SThierry Reding 3873f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 3883f6eaef9SThierry Reding }; 389d25a3bf1SThierry Reding }; 390d25a3bf1SThierry Reding 39139cb62cbSJoseph Lo uarta: serial@3100000 { 39239cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 39339cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 39439cb62cbSJoseph Lo reg-shift = <2>; 39539cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 396c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 397a7a77e2eSThierry Reding clock-names = "serial"; 3987bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 399a7a77e2eSThierry Reding reset-names = "serial"; 400a7a77e2eSThierry Reding status = "disabled"; 401a7a77e2eSThierry Reding }; 402a7a77e2eSThierry Reding 403a7a77e2eSThierry Reding uartb: serial@3110000 { 404a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 406a7a77e2eSThierry Reding reg-shift = <2>; 407a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 408c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 409a7a77e2eSThierry Reding clock-names = "serial"; 4107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 411a7a77e2eSThierry Reding reset-names = "serial"; 412a7a77e2eSThierry Reding status = "disabled"; 413a7a77e2eSThierry Reding }; 414a7a77e2eSThierry Reding 415a7a77e2eSThierry Reding uartd: serial@3130000 { 416a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 418a7a77e2eSThierry Reding reg-shift = <2>; 419a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 420c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 421a7a77e2eSThierry Reding clock-names = "serial"; 4227bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 423a7a77e2eSThierry Reding reset-names = "serial"; 424a7a77e2eSThierry Reding status = "disabled"; 425a7a77e2eSThierry Reding }; 426a7a77e2eSThierry Reding 427a7a77e2eSThierry Reding uarte: serial@3140000 { 428a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 429a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 430a7a77e2eSThierry Reding reg-shift = <2>; 431a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 432c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 433a7a77e2eSThierry Reding clock-names = "serial"; 4347bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 435a7a77e2eSThierry Reding reset-names = "serial"; 436a7a77e2eSThierry Reding status = "disabled"; 437a7a77e2eSThierry Reding }; 438a7a77e2eSThierry Reding 439a7a77e2eSThierry Reding uartf: serial@3150000 { 440a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 441a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 442a7a77e2eSThierry Reding reg-shift = <2>; 443a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 444c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 445a7a77e2eSThierry Reding clock-names = "serial"; 4467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 447a7a77e2eSThierry Reding reset-names = "serial"; 44839cb62cbSJoseph Lo status = "disabled"; 44939cb62cbSJoseph Lo }; 45039cb62cbSJoseph Lo 45140cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 452250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 45340cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 45440cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 45540cc83b3SThierry Reding #address-cells = <1>; 45640cc83b3SThierry Reding #size-cells = <0>; 457c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 45840cc83b3SThierry Reding clock-names = "div-clk"; 4597bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 46040cc83b3SThierry Reding reset-names = "i2c"; 46140cc83b3SThierry Reding status = "disabled"; 46240cc83b3SThierry Reding }; 46340cc83b3SThierry Reding 46440cc83b3SThierry Reding cam_i2c: i2c@3180000 { 465250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 46640cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 46740cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 46840cc83b3SThierry Reding #address-cells = <1>; 46940cc83b3SThierry Reding #size-cells = <0>; 470c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 47140cc83b3SThierry Reding clock-names = "div-clk"; 4727bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 47340cc83b3SThierry Reding reset-names = "i2c"; 47440cc83b3SThierry Reding status = "disabled"; 47540cc83b3SThierry Reding }; 47640cc83b3SThierry Reding 47740cc83b3SThierry Reding /* shares pads with dpaux1 */ 47840cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 479250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 48040cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 48140cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 48240cc83b3SThierry Reding #address-cells = <1>; 48340cc83b3SThierry Reding #size-cells = <0>; 484c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 48540cc83b3SThierry Reding clock-names = "div-clk"; 4867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 48740cc83b3SThierry Reding reset-names = "i2c"; 488846137c6SThierry Reding pinctrl-names = "default", "idle"; 489846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 490846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 49140cc83b3SThierry Reding status = "disabled"; 49240cc83b3SThierry Reding }; 49340cc83b3SThierry Reding 49440cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 49540cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 496250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 49740cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 49840cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 49940cc83b3SThierry Reding #address-cells = <1>; 50040cc83b3SThierry Reding #size-cells = <0>; 501c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 50240cc83b3SThierry Reding clock-names = "div-clk"; 5037bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 50440cc83b3SThierry Reding reset-names = "i2c"; 50540cc83b3SThierry Reding status = "disabled"; 50640cc83b3SThierry Reding }; 50740cc83b3SThierry Reding 50840cc83b3SThierry Reding /* shares pads with dpaux0 */ 50940cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 510250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 51140cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 51240cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 51340cc83b3SThierry Reding #address-cells = <1>; 51440cc83b3SThierry Reding #size-cells = <0>; 515c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 51640cc83b3SThierry Reding clock-names = "div-clk"; 5177bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 51840cc83b3SThierry Reding reset-names = "i2c"; 519846137c6SThierry Reding pinctrl-names = "default", "idle"; 520846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 521846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 52240cc83b3SThierry Reding status = "disabled"; 52340cc83b3SThierry Reding }; 52440cc83b3SThierry Reding 52540cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 526250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 52740cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 52840cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 52940cc83b3SThierry Reding #address-cells = <1>; 53040cc83b3SThierry Reding #size-cells = <0>; 531c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 53240cc83b3SThierry Reding clock-names = "div-clk"; 5337bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 53440cc83b3SThierry Reding reset-names = "i2c"; 53540cc83b3SThierry Reding status = "disabled"; 53640cc83b3SThierry Reding }; 53740cc83b3SThierry Reding 53840cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 539250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 54040cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 54140cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 54240cc83b3SThierry Reding #address-cells = <1>; 54340cc83b3SThierry Reding #size-cells = <0>; 544c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 54540cc83b3SThierry Reding clock-names = "div-clk"; 5467bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 54740cc83b3SThierry Reding reset-names = "i2c"; 54840cc83b3SThierry Reding status = "disabled"; 54940cc83b3SThierry Reding }; 55040cc83b3SThierry Reding 55167bb17f6SThierry Reding sdmmc1: mmc@3400000 { 55299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 55399425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 55499425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 555c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 55699425dfdSThierry Reding clock-names = "sdhci"; 5577bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 55899425dfdSThierry Reding reset-names = "sdhci"; 559954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 560954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 561954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 5628589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 56324005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 56424005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 56524005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 56641408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 56741408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 56841408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 56941408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 57041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 57141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 5726f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 5736f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 57498a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 57598a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 57698a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 57799425dfdSThierry Reding status = "disabled"; 57899425dfdSThierry Reding }; 57999425dfdSThierry Reding 58067bb17f6SThierry Reding sdmmc2: mmc@3420000 { 58199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 58299425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 58399425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 584c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 58599425dfdSThierry Reding clock-names = "sdhci"; 5867bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 58799425dfdSThierry Reding reset-names = "sdhci"; 588954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 589954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 590954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 5918589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 59224005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 59324005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 59424005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 59541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 59641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 59741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 59841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 5996f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 6006f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 60199425dfdSThierry Reding status = "disabled"; 60299425dfdSThierry Reding }; 60399425dfdSThierry Reding 60467bb17f6SThierry Reding sdmmc3: mmc@3440000 { 60599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 60699425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 60799425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 608c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 60999425dfdSThierry Reding clock-names = "sdhci"; 6107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 61199425dfdSThierry Reding reset-names = "sdhci"; 612954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 613954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 614954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 6158589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 61624005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 61724005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 61824005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 61941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 62041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 62141408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 62241408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 62341408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 62441408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 6256f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 6266f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 62799425dfdSThierry Reding status = "disabled"; 62899425dfdSThierry Reding }; 62999425dfdSThierry Reding 63067bb17f6SThierry Reding sdmmc4: mmc@3460000 { 63199425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 63299425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 63399425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 634c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 63599425dfdSThierry Reding clock-names = "sdhci"; 63698a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 63798a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 63898a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 6397bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 64099425dfdSThierry Reding reset-names = "sdhci"; 641954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 642954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 643954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 6448589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 64541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 64641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 64741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 64841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 6494e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 6504e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 651e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 652e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 65322248e91SAapo Vienamo nvidia,dqs-trim = <63>; 654207f60baSAapo Vienamo mmc-hs400-1_8v; 655c4307836SSowjanya Komatineni supports-cqe; 65699425dfdSThierry Reding status = "disabled"; 65799425dfdSThierry Reding }; 65899425dfdSThierry Reding 659b066a310SThierry Reding hda@3510000 { 660b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 661b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 662b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 663b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 664b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 665b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 666b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 667b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 668b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 669b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 670b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 671b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 672954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 673954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 674954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 675dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 676b066a310SThierry Reding status = "disabled"; 677b066a310SThierry Reding }; 678b066a310SThierry Reding 6798bfde518SThierry Reding padctl: padctl@3520000 { 6808bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 6818bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 6828bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 6838bfde518SThierry Reding reg-names = "padctl", "ao"; 6848bfde518SThierry Reding 6858bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 6868bfde518SThierry Reding reset-names = "padctl"; 6878bfde518SThierry Reding 6888bfde518SThierry Reding status = "disabled"; 6898bfde518SThierry Reding 6908bfde518SThierry Reding pads { 6918bfde518SThierry Reding usb2 { 6928bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 6938bfde518SThierry Reding clock-names = "trk"; 6948bfde518SThierry Reding status = "disabled"; 6958bfde518SThierry Reding 6968bfde518SThierry Reding lanes { 6978bfde518SThierry Reding usb2-0 { 6988bfde518SThierry Reding status = "disabled"; 6998bfde518SThierry Reding #phy-cells = <0>; 7008bfde518SThierry Reding }; 7018bfde518SThierry Reding 7028bfde518SThierry Reding usb2-1 { 7038bfde518SThierry Reding status = "disabled"; 7048bfde518SThierry Reding #phy-cells = <0>; 7058bfde518SThierry Reding }; 7068bfde518SThierry Reding 7078bfde518SThierry Reding usb2-2 { 7088bfde518SThierry Reding status = "disabled"; 7098bfde518SThierry Reding #phy-cells = <0>; 7108bfde518SThierry Reding }; 7118bfde518SThierry Reding }; 7128bfde518SThierry Reding }; 7138bfde518SThierry Reding 7148bfde518SThierry Reding hsic { 7158bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 7168bfde518SThierry Reding clock-names = "trk"; 7178bfde518SThierry Reding status = "disabled"; 7188bfde518SThierry Reding 7198bfde518SThierry Reding lanes { 7208bfde518SThierry Reding hsic-0 { 7218bfde518SThierry Reding status = "disabled"; 7228bfde518SThierry Reding #phy-cells = <0>; 7238bfde518SThierry Reding }; 7248bfde518SThierry Reding }; 7258bfde518SThierry Reding }; 7268bfde518SThierry Reding 7278bfde518SThierry Reding usb3 { 7288bfde518SThierry Reding status = "disabled"; 7298bfde518SThierry Reding 7308bfde518SThierry Reding lanes { 7318bfde518SThierry Reding usb3-0 { 7328bfde518SThierry Reding status = "disabled"; 7338bfde518SThierry Reding #phy-cells = <0>; 7348bfde518SThierry Reding }; 7358bfde518SThierry Reding 7368bfde518SThierry Reding usb3-1 { 7378bfde518SThierry Reding status = "disabled"; 7388bfde518SThierry Reding #phy-cells = <0>; 7398bfde518SThierry Reding }; 7408bfde518SThierry Reding 7418bfde518SThierry Reding usb3-2 { 7428bfde518SThierry Reding status = "disabled"; 7438bfde518SThierry Reding #phy-cells = <0>; 7448bfde518SThierry Reding }; 7458bfde518SThierry Reding }; 7468bfde518SThierry Reding }; 7478bfde518SThierry Reding }; 7488bfde518SThierry Reding 7498bfde518SThierry Reding ports { 7508bfde518SThierry Reding usb2-0 { 7518bfde518SThierry Reding status = "disabled"; 7528bfde518SThierry Reding }; 7538bfde518SThierry Reding 7548bfde518SThierry Reding usb2-1 { 7558bfde518SThierry Reding status = "disabled"; 7568bfde518SThierry Reding }; 7578bfde518SThierry Reding 7588bfde518SThierry Reding usb2-2 { 7598bfde518SThierry Reding status = "disabled"; 7608bfde518SThierry Reding }; 7618bfde518SThierry Reding 7628bfde518SThierry Reding hsic-0 { 7638bfde518SThierry Reding status = "disabled"; 7648bfde518SThierry Reding }; 7658bfde518SThierry Reding 7668bfde518SThierry Reding usb3-0 { 7678bfde518SThierry Reding status = "disabled"; 7688bfde518SThierry Reding }; 7698bfde518SThierry Reding 7708bfde518SThierry Reding usb3-1 { 7718bfde518SThierry Reding status = "disabled"; 7728bfde518SThierry Reding }; 7738bfde518SThierry Reding 7748bfde518SThierry Reding usb3-2 { 7758bfde518SThierry Reding status = "disabled"; 7768bfde518SThierry Reding }; 7778bfde518SThierry Reding }; 7788bfde518SThierry Reding }; 7798bfde518SThierry Reding 7808bfde518SThierry Reding usb@3530000 { 7818bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 7828bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 7838bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 7848bfde518SThierry Reding reg-names = "hcd", "fpci"; 7858bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 786a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 7878bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 7888bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 7898bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 7908bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 7918bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 7928bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 7938bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 7948bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 7958bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 7968bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 7978bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 7988bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 7998bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 8008bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 8018bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 802954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 803954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 804954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 80506c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 8068bfde518SThierry Reding #address-cells = <1>; 8078bfde518SThierry Reding #size-cells = <0>; 80806c6b06fSThierry Reding status = "disabled"; 80906c6b06fSThierry Reding 81006c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 8118bfde518SThierry Reding }; 8128bfde518SThierry Reding 813584f800cSNagarjuna Kristam usb@3550000 { 814584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 815584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 816584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 817584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 818584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 819584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 820584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 821584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 822584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 823584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 824584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 825584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 826584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 827584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 828584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 829584f800cSNagarjuna Kristam status = "disabled"; 830584f800cSNagarjuna Kristam }; 831584f800cSNagarjuna Kristam 83285593b75SThierry Reding fuse@3820000 { 83385593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 83485593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 83585593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 83685593b75SThierry Reding clock-names = "fuse"; 83785593b75SThierry Reding }; 83885593b75SThierry Reding 83939cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 84039cb62cbSJoseph Lo compatible = "arm,gic-400"; 84139cb62cbSJoseph Lo #interrupt-cells = <3>; 84239cb62cbSJoseph Lo interrupt-controller; 84339cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 84439cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 84539cb62cbSJoseph Lo interrupts = <GIC_PPI 9 84639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 84739cb62cbSJoseph Lo interrupt-parent = <&gic>; 84839cb62cbSJoseph Lo }; 84939cb62cbSJoseph Lo 85097cf683cSThierry Reding cec@3960000 { 85197cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 85297cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 85397cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 85497cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 85597cf683cSThierry Reding clock-names = "cec"; 85697cf683cSThierry Reding status = "disabled"; 85797cf683cSThierry Reding }; 85897cf683cSThierry Reding 85939cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 86039cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 86139cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 86239cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 86339cb62cbSJoseph Lo interrupt-names = "doorbell"; 86439cb62cbSJoseph Lo #mbox-cells = <2>; 86539cb62cbSJoseph Lo status = "disabled"; 86639cb62cbSJoseph Lo }; 86739cb62cbSJoseph Lo 86840cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 869250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 87040cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 87140cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 87240cc83b3SThierry Reding #address-cells = <1>; 87340cc83b3SThierry Reding #size-cells = <0>; 874c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 87540cc83b3SThierry Reding clock-names = "div-clk"; 8767bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 87740cc83b3SThierry Reding reset-names = "i2c"; 87840cc83b3SThierry Reding status = "disabled"; 87940cc83b3SThierry Reding }; 88040cc83b3SThierry Reding 88140cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 882250a36c0SSowjanya Komatineni compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 88340cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 88440cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 88540cc83b3SThierry Reding #address-cells = <1>; 88640cc83b3SThierry Reding #size-cells = <0>; 887c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 88840cc83b3SThierry Reding clock-names = "div-clk"; 8897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 89040cc83b3SThierry Reding reset-names = "i2c"; 89140cc83b3SThierry Reding status = "disabled"; 89240cc83b3SThierry Reding }; 89340cc83b3SThierry Reding 894a7a77e2eSThierry Reding uartc: serial@c280000 { 895a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 896a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 897a7a77e2eSThierry Reding reg-shift = <2>; 898a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 899c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 900a7a77e2eSThierry Reding clock-names = "serial"; 9017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 902a7a77e2eSThierry Reding reset-names = "serial"; 903a7a77e2eSThierry Reding status = "disabled"; 904a7a77e2eSThierry Reding }; 905a7a77e2eSThierry Reding 906a7a77e2eSThierry Reding uartg: serial@c290000 { 907a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 908a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 909a7a77e2eSThierry Reding reg-shift = <2>; 910a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 911c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 912a7a77e2eSThierry Reding clock-names = "serial"; 9137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 914a7a77e2eSThierry Reding reset-names = "serial"; 915a7a77e2eSThierry Reding status = "disabled"; 916a7a77e2eSThierry Reding }; 917a7a77e2eSThierry Reding 9189733a251SThierry Reding rtc: rtc@c2a0000 { 9199733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 9209733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 9219733a251SThierry Reding interrupt-parent = <&pmc>; 9229733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 9239733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 9249733a251SThierry Reding clock-names = "rtc"; 9259733a251SThierry Reding status = "disabled"; 9269733a251SThierry Reding }; 9279733a251SThierry Reding 928fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 929fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 930fc4bb754SThierry Reding reg-names = "security", "gpio"; 931fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 932fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 933fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 934fc4bb754SThierry Reding gpio-controller; 935fc4bb754SThierry Reding #gpio-cells = <2>; 936fc4bb754SThierry Reding interrupt-controller; 937fc4bb754SThierry Reding #interrupt-cells = <2>; 938fc4bb754SThierry Reding }; 939fc4bb754SThierry Reding 94032e66e46SThierry Reding pmc: pmc@c360000 { 94173bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 94273bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 94373bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 94473bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 94573bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 94673bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 94724005fd1SAapo Vienamo 94832e66e46SThierry Reding #interrupt-cells = <2>; 94932e66e46SThierry Reding interrupt-controller; 95032e66e46SThierry Reding 95124005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 95224005fd1SAapo Vienamo pins = "sdmmc1-hv"; 95324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 95424005fd1SAapo Vienamo }; 95524005fd1SAapo Vienamo 95624005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 95724005fd1SAapo Vienamo pins = "sdmmc1-hv"; 95824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 95924005fd1SAapo Vienamo }; 96024005fd1SAapo Vienamo 96124005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 96224005fd1SAapo Vienamo pins = "sdmmc2-hv"; 96324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 96424005fd1SAapo Vienamo }; 96524005fd1SAapo Vienamo 96624005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 96724005fd1SAapo Vienamo pins = "sdmmc2-hv"; 96824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 96924005fd1SAapo Vienamo }; 97024005fd1SAapo Vienamo 97124005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 97224005fd1SAapo Vienamo pins = "sdmmc3-hv"; 97324005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 97424005fd1SAapo Vienamo }; 97524005fd1SAapo Vienamo 97624005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 97724005fd1SAapo Vienamo pins = "sdmmc3-hv"; 97824005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 97924005fd1SAapo Vienamo }; 98073bf90d4SThierry Reding }; 98173bf90d4SThierry Reding 9827b7ef494SMikko Perttunen ccplex@e000000 { 9837b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 9847b7ef494SMikko Perttunen reg = <0x0 0x0e000000 0x0 0x3fffff>; 9857b7ef494SMikko Perttunen 9867b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 9877b7ef494SMikko Perttunen }; 9887b7ef494SMikko Perttunen 989f8973cf4SManikanta Maddireddy pcie@10003000 { 990f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 991f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 992f8973cf4SManikanta Maddireddy device_type = "pci"; 993644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 994644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 995644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 996f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 997f8973cf4SManikanta Maddireddy 998f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 999f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1000f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1001f8973cf4SManikanta Maddireddy 1002f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1003f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1004f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1005f8973cf4SManikanta Maddireddy 1006f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1007f8973cf4SManikanta Maddireddy #address-cells = <3>; 1008f8973cf4SManikanta Maddireddy #size-cells = <2>; 1009f8973cf4SManikanta Maddireddy 1010644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1011644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1012644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1013644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1014644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1015644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1016f8973cf4SManikanta Maddireddy 101778b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 101878b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1019f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 102078b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1021f8973cf4SManikanta Maddireddy 102278b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 102378b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1024f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 102578b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1026f8973cf4SManikanta Maddireddy 1027954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1028954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1029954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1030954490b3SThierry Reding 1031f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1032f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1033f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1034f2a465e7SThierry Reding 1035f8973cf4SManikanta Maddireddy status = "disabled"; 1036f8973cf4SManikanta Maddireddy 1037f8973cf4SManikanta Maddireddy pci@1,0 { 1038f8973cf4SManikanta Maddireddy device_type = "pci"; 1039f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1040f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1041f8973cf4SManikanta Maddireddy status = "disabled"; 1042f8973cf4SManikanta Maddireddy 1043f8973cf4SManikanta Maddireddy #address-cells = <3>; 1044f8973cf4SManikanta Maddireddy #size-cells = <2>; 1045f8973cf4SManikanta Maddireddy ranges; 1046f8973cf4SManikanta Maddireddy 1047f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1048f8973cf4SManikanta Maddireddy }; 1049f8973cf4SManikanta Maddireddy 1050f8973cf4SManikanta Maddireddy pci@2,0 { 1051f8973cf4SManikanta Maddireddy device_type = "pci"; 1052f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1053f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1054f8973cf4SManikanta Maddireddy status = "disabled"; 1055f8973cf4SManikanta Maddireddy 1056f8973cf4SManikanta Maddireddy #address-cells = <3>; 1057f8973cf4SManikanta Maddireddy #size-cells = <2>; 1058f8973cf4SManikanta Maddireddy ranges; 1059f8973cf4SManikanta Maddireddy 1060f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1061f8973cf4SManikanta Maddireddy }; 1062f8973cf4SManikanta Maddireddy 1063f8973cf4SManikanta Maddireddy pci@3,0 { 1064f8973cf4SManikanta Maddireddy device_type = "pci"; 1065f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1066f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1067f8973cf4SManikanta Maddireddy status = "disabled"; 1068f8973cf4SManikanta Maddireddy 1069f8973cf4SManikanta Maddireddy #address-cells = <3>; 1070f8973cf4SManikanta Maddireddy #size-cells = <2>; 1071f8973cf4SManikanta Maddireddy ranges; 1072f8973cf4SManikanta Maddireddy 1073f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1074f8973cf4SManikanta Maddireddy }; 1075f8973cf4SManikanta Maddireddy }; 1076f8973cf4SManikanta Maddireddy 1077b30a8e61SThierry Reding smmu: iommu@12000000 { 1078b30a8e61SThierry Reding compatible = "arm,mmu-500"; 1079b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1080b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1081b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1082b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1083b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1084b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1085b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1086b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1087b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1088b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1089b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1090b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1091b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1092b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1093b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1094b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1095b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1096b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1097b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1098b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1099b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1100b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1101b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1102b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1103b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1104b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1105b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1106b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1107b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1108b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1109b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1110b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1111b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1112b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1113b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1114b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1115b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1116b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1117b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1118b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1119b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1120b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1121b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1122b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1123b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1124b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1125b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1126b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1127b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1128b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1129b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1130b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1131b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1132b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1133b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1134b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1135b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1136b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1137b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1138b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1139b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1140b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1141b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1142b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1143b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1144b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1145b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1146b30a8e61SThierry Reding #global-interrupts = <1>; 1147b30a8e61SThierry Reding #iommu-cells = <1>; 1148b30a8e61SThierry Reding }; 1149b30a8e61SThierry Reding 11505524c61fSMikko Perttunen host1x@13e00000 { 1151ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 11525524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 11535524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 11545524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 11555524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 11565524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1157052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 11585524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 11595524c61fSMikko Perttunen clock-names = "host1x"; 11605524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 11615524c61fSMikko Perttunen reset-names = "host1x"; 11625524c61fSMikko Perttunen 11635524c61fSMikko Perttunen #address-cells = <1>; 11645524c61fSMikko Perttunen #size-cells = <1>; 11655524c61fSMikko Perttunen 11665524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1167954490b3SThierry Reding 1168954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1169954490b3SThierry Reding interconnect-names = "dma-mem"; 1170954490b3SThierry Reding 1171c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1172c2599da7SThierry Reding 1173c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1174c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1175c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1176c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1177c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1178c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1179c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1180c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1181c2599da7SThierry Reding reset-names = "dpaux"; 1182c2599da7SThierry Reding status = "disabled"; 1183c2599da7SThierry Reding 1184c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1185c2599da7SThierry Reding 1186c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1187c2599da7SThierry Reding groups = "dpaux-io"; 1188c2599da7SThierry Reding function = "aux"; 1189c2599da7SThierry Reding }; 1190c2599da7SThierry Reding 1191c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1192c2599da7SThierry Reding groups = "dpaux-io"; 1193c2599da7SThierry Reding function = "i2c"; 1194c2599da7SThierry Reding }; 1195c2599da7SThierry Reding 1196c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1197c2599da7SThierry Reding groups = "dpaux-io"; 1198c2599da7SThierry Reding function = "off"; 1199c2599da7SThierry Reding }; 1200c2599da7SThierry Reding 1201c2599da7SThierry Reding i2c-bus { 1202c2599da7SThierry Reding #address-cells = <1>; 1203c2599da7SThierry Reding #size-cells = <0>; 1204c2599da7SThierry Reding }; 1205c2599da7SThierry Reding }; 1206c2599da7SThierry Reding 1207c2599da7SThierry Reding display-hub@15200000 { 1208aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1209ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1210c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1211c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1212c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1213c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1214c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1215c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1216c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1217c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1218c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1219c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1220c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1221c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1222c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1223c2599da7SThierry Reding status = "disabled"; 1224c2599da7SThierry Reding 1225c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1226c2599da7SThierry Reding 1227c2599da7SThierry Reding #address-cells = <1>; 1228c2599da7SThierry Reding #size-cells = <1>; 1229c2599da7SThierry Reding 1230c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1231c2599da7SThierry Reding 1232c2599da7SThierry Reding display@15200000 { 1233c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1234c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1235c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1236c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1237c2599da7SThierry Reding clock-names = "dc"; 1238c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1239c2599da7SThierry Reding reset-names = "dc"; 1240c2599da7SThierry Reding 1241c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1242954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1243954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1244954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1245c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1246c2599da7SThierry Reding 1247c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1248c2599da7SThierry Reding nvidia,head = <0>; 1249c2599da7SThierry Reding }; 1250c2599da7SThierry Reding 1251c2599da7SThierry Reding display@15210000 { 1252c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1253c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1254c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1255c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1256c2599da7SThierry Reding clock-names = "dc"; 1257c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1258c2599da7SThierry Reding reset-names = "dc"; 1259c2599da7SThierry Reding 1260c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1261954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1262954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1263954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1264c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1265c2599da7SThierry Reding 1266c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1267c2599da7SThierry Reding nvidia,head = <1>; 1268c2599da7SThierry Reding }; 1269c2599da7SThierry Reding 1270c2599da7SThierry Reding display@15220000 { 1271c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1272c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1273c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1274c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1275c2599da7SThierry Reding clock-names = "dc"; 1276c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1277c2599da7SThierry Reding reset-names = "dc"; 1278c2599da7SThierry Reding 1279c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1280954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1281954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1282954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1283c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1284c2599da7SThierry Reding 1285c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1286c2599da7SThierry Reding nvidia,head = <2>; 1287c2599da7SThierry Reding }; 1288c2599da7SThierry Reding }; 1289c2599da7SThierry Reding 1290c2599da7SThierry Reding dsia: dsi@15300000 { 1291c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1292c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1293c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1294c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1295c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1296c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1297c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1298c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1299c2599da7SThierry Reding reset-names = "dsi"; 1300c2599da7SThierry Reding status = "disabled"; 1301c2599da7SThierry Reding 1302c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1303c2599da7SThierry Reding }; 1304effc4b44SMikko Perttunen 1305effc4b44SMikko Perttunen vic@15340000 { 1306effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1307effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1308effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1309effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1310effc4b44SMikko Perttunen clock-names = "vic"; 1311effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1312effc4b44SMikko Perttunen reset-names = "vic"; 1313effc4b44SMikko Perttunen 1314effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1315954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1316954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1317954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 131829ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1319effc4b44SMikko Perttunen }; 1320c2599da7SThierry Reding 1321c2599da7SThierry Reding dsib: dsi@15400000 { 1322c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1323c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1324c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1325c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1326c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1327c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1328c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1329c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1330c2599da7SThierry Reding reset-names = "dsi"; 1331c2599da7SThierry Reding status = "disabled"; 1332c2599da7SThierry Reding 1333c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1334c2599da7SThierry Reding }; 1335c2599da7SThierry Reding 1336c2599da7SThierry Reding sor0: sor@15540000 { 1337c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1338c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1339c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1340c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1341c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1342c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1343c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1344c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1345c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1346c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1347c2599da7SThierry Reding "pad"; 1348c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1349c2599da7SThierry Reding reset-names = "sor"; 1350c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1351c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1352c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1353c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1354c2599da7SThierry Reding status = "disabled"; 1355c2599da7SThierry Reding 1356c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1357c2599da7SThierry Reding nvidia,interface = <0>; 1358c2599da7SThierry Reding }; 1359c2599da7SThierry Reding 1360c2599da7SThierry Reding sor1: sor@15580000 { 1361d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1362c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1363c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1364c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1365c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1366c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1367c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1368c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1369c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1370c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1371c2599da7SThierry Reding "pad"; 1372c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1373c2599da7SThierry Reding reset-names = "sor"; 1374c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1375c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1376c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1377c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1378c2599da7SThierry Reding status = "disabled"; 1379c2599da7SThierry Reding 1380c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1381c2599da7SThierry Reding nvidia,interface = <1>; 1382c2599da7SThierry Reding }; 1383c2599da7SThierry Reding 1384c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1385c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1386c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1387c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1388c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1389c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1390c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1391c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1392c2599da7SThierry Reding reset-names = "dpaux"; 1393c2599da7SThierry Reding status = "disabled"; 1394c2599da7SThierry Reding 1395c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1396c2599da7SThierry Reding 1397c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1398c2599da7SThierry Reding groups = "dpaux-io"; 1399c2599da7SThierry Reding function = "aux"; 1400c2599da7SThierry Reding }; 1401c2599da7SThierry Reding 1402c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1403c2599da7SThierry Reding groups = "dpaux-io"; 1404c2599da7SThierry Reding function = "i2c"; 1405c2599da7SThierry Reding }; 1406c2599da7SThierry Reding 1407c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1408c2599da7SThierry Reding groups = "dpaux-io"; 1409c2599da7SThierry Reding function = "off"; 1410c2599da7SThierry Reding }; 1411c2599da7SThierry Reding 1412c2599da7SThierry Reding i2c-bus { 1413c2599da7SThierry Reding #address-cells = <1>; 1414c2599da7SThierry Reding #size-cells = <0>; 1415c2599da7SThierry Reding }; 1416c2599da7SThierry Reding }; 1417c2599da7SThierry Reding 1418c2599da7SThierry Reding padctl@15880000 { 1419c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1420c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1421c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1422c2599da7SThierry Reding reset-names = "dsi"; 1423c2599da7SThierry Reding status = "disabled"; 1424c2599da7SThierry Reding }; 1425c2599da7SThierry Reding 1426c2599da7SThierry Reding dsic: dsi@15900000 { 1427c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1428c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1429c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1430c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1431c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1432c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1433c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1434c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1435c2599da7SThierry Reding reset-names = "dsi"; 1436c2599da7SThierry Reding status = "disabled"; 1437c2599da7SThierry Reding 1438c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1439c2599da7SThierry Reding }; 1440c2599da7SThierry Reding 1441c2599da7SThierry Reding dsid: dsi@15940000 { 1442c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1443c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1444c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1445c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1446c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1447c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1448c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1449c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1450c2599da7SThierry Reding reset-names = "dsi"; 1451c2599da7SThierry Reding status = "disabled"; 1452c2599da7SThierry Reding 1453c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1454c2599da7SThierry Reding }; 14555524c61fSMikko Perttunen }; 14565524c61fSMikko Perttunen 1457dfd7a384SAlexandre Courbot gpu@17000000 { 1458dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1459dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1460dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 146159a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 146259a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1463dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1464dfd7a384SAlexandre Courbot 1465dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1466dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1467dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1468dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1469dfd7a384SAlexandre Courbot reset-names = "gpu"; 1470dfd7a384SAlexandre Courbot status = "disabled"; 1471dfd7a384SAlexandre Courbot 1472dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1473954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1474954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1475954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1476954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1477954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1478dfd7a384SAlexandre Courbot }; 1479dfd7a384SAlexandre Courbot 1480e867fe41SThierry Reding sram@30000000 { 148139cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 148239cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1483aa78032cSThierry Reding #address-cells = <1>; 1484aa78032cSThierry Reding #size-cells = <1>; 1485aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 148639cb62cbSJoseph Lo 1487e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1488aa78032cSThierry Reding reg = <0x4e000 0x1000>; 148939cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 149039cb62cbSJoseph Lo pool; 149139cb62cbSJoseph Lo }; 149239cb62cbSJoseph Lo 1493e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1494aa78032cSThierry Reding reg = <0x4f000 0x1000>; 149539cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 149639cb62cbSJoseph Lo pool; 149739cb62cbSJoseph Lo }; 149839cb62cbSJoseph Lo }; 149939cb62cbSJoseph Lo 1500541d7c44SThierry Reding bpmp: bpmp { 1501541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1502954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1503954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1504954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1505954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1506954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1507541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1508541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1509541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 1510541d7c44SThierry Reding shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1511541d7c44SThierry Reding #clock-cells = <1>; 1512541d7c44SThierry Reding #reset-cells = <1>; 1513541d7c44SThierry Reding #power-domain-cells = <1>; 1514541d7c44SThierry Reding 1515541d7c44SThierry Reding bpmp_i2c: i2c { 1516541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1517541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1518541d7c44SThierry Reding #address-cells = <1>; 1519541d7c44SThierry Reding #size-cells = <0>; 1520541d7c44SThierry Reding status = "disabled"; 1521541d7c44SThierry Reding }; 1522541d7c44SThierry Reding 1523541d7c44SThierry Reding bpmp_thermal: thermal { 1524541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1525541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1526541d7c44SThierry Reding }; 1527541d7c44SThierry Reding }; 1528541d7c44SThierry Reding 1529cd6fe32eSThierry Reding cpus { 1530cd6fe32eSThierry Reding #address-cells = <1>; 1531cd6fe32eSThierry Reding #size-cells = <0>; 1532cd6fe32eSThierry Reding 1533cd6fe32eSThierry Reding cpu@0 { 153431af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1535cd6fe32eSThierry Reding device_type = "cpu"; 15365298166dSJoseph Lo i-cache-size = <0x20000>; 15375298166dSJoseph Lo i-cache-line-size = <64>; 15385298166dSJoseph Lo i-cache-sets = <512>; 15395298166dSJoseph Lo d-cache-size = <0x10000>; 15405298166dSJoseph Lo d-cache-line-size = <64>; 15415298166dSJoseph Lo d-cache-sets = <256>; 15425298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1543cd6fe32eSThierry Reding reg = <0x000>; 1544cd6fe32eSThierry Reding }; 1545cd6fe32eSThierry Reding 1546cd6fe32eSThierry Reding cpu@1 { 154731af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1548cd6fe32eSThierry Reding device_type = "cpu"; 15495298166dSJoseph Lo i-cache-size = <0x20000>; 15505298166dSJoseph Lo i-cache-line-size = <64>; 15515298166dSJoseph Lo i-cache-sets = <512>; 15525298166dSJoseph Lo d-cache-size = <0x10000>; 15535298166dSJoseph Lo d-cache-line-size = <64>; 15545298166dSJoseph Lo d-cache-sets = <256>; 15555298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1556cd6fe32eSThierry Reding reg = <0x001>; 1557cd6fe32eSThierry Reding }; 1558cd6fe32eSThierry Reding 1559cd6fe32eSThierry Reding cpu@2 { 156031af04cdSRob Herring compatible = "arm,cortex-a57"; 1561cd6fe32eSThierry Reding device_type = "cpu"; 15625298166dSJoseph Lo i-cache-size = <0xC000>; 15635298166dSJoseph Lo i-cache-line-size = <64>; 15645298166dSJoseph Lo i-cache-sets = <256>; 15655298166dSJoseph Lo d-cache-size = <0x8000>; 15665298166dSJoseph Lo d-cache-line-size = <64>; 15675298166dSJoseph Lo d-cache-sets = <256>; 15685298166dSJoseph Lo next-level-cache = <&L2_A57>; 1569cd6fe32eSThierry Reding reg = <0x100>; 1570cd6fe32eSThierry Reding }; 1571cd6fe32eSThierry Reding 1572cd6fe32eSThierry Reding cpu@3 { 157331af04cdSRob Herring compatible = "arm,cortex-a57"; 1574cd6fe32eSThierry Reding device_type = "cpu"; 15755298166dSJoseph Lo i-cache-size = <0xC000>; 15765298166dSJoseph Lo i-cache-line-size = <64>; 15775298166dSJoseph Lo i-cache-sets = <256>; 15785298166dSJoseph Lo d-cache-size = <0x8000>; 15795298166dSJoseph Lo d-cache-line-size = <64>; 15805298166dSJoseph Lo d-cache-sets = <256>; 15815298166dSJoseph Lo next-level-cache = <&L2_A57>; 1582cd6fe32eSThierry Reding reg = <0x101>; 1583cd6fe32eSThierry Reding }; 1584cd6fe32eSThierry Reding 1585cd6fe32eSThierry Reding cpu@4 { 158631af04cdSRob Herring compatible = "arm,cortex-a57"; 1587cd6fe32eSThierry Reding device_type = "cpu"; 15885298166dSJoseph Lo i-cache-size = <0xC000>; 15895298166dSJoseph Lo i-cache-line-size = <64>; 15905298166dSJoseph Lo i-cache-sets = <256>; 15915298166dSJoseph Lo d-cache-size = <0x8000>; 15925298166dSJoseph Lo d-cache-line-size = <64>; 15935298166dSJoseph Lo d-cache-sets = <256>; 15945298166dSJoseph Lo next-level-cache = <&L2_A57>; 1595cd6fe32eSThierry Reding reg = <0x102>; 1596cd6fe32eSThierry Reding }; 1597cd6fe32eSThierry Reding 1598cd6fe32eSThierry Reding cpu@5 { 159931af04cdSRob Herring compatible = "arm,cortex-a57"; 1600cd6fe32eSThierry Reding device_type = "cpu"; 16015298166dSJoseph Lo i-cache-size = <0xC000>; 16025298166dSJoseph Lo i-cache-line-size = <64>; 16035298166dSJoseph Lo i-cache-sets = <256>; 16045298166dSJoseph Lo d-cache-size = <0x8000>; 16055298166dSJoseph Lo d-cache-line-size = <64>; 16065298166dSJoseph Lo d-cache-sets = <256>; 16075298166dSJoseph Lo next-level-cache = <&L2_A57>; 1608cd6fe32eSThierry Reding reg = <0x103>; 1609cd6fe32eSThierry Reding }; 16105298166dSJoseph Lo 16115298166dSJoseph Lo L2_DENVER: l2-cache0 { 16125298166dSJoseph Lo compatible = "cache"; 16135298166dSJoseph Lo cache-unified; 16145298166dSJoseph Lo cache-level = <2>; 16155298166dSJoseph Lo cache-size = <0x200000>; 16165298166dSJoseph Lo cache-line-size = <64>; 16175298166dSJoseph Lo cache-sets = <2048>; 16185298166dSJoseph Lo }; 16195298166dSJoseph Lo 16205298166dSJoseph Lo L2_A57: l2-cache1 { 16215298166dSJoseph Lo compatible = "cache"; 16225298166dSJoseph Lo cache-unified; 16235298166dSJoseph Lo cache-level = <2>; 16245298166dSJoseph Lo cache-size = <0x200000>; 16255298166dSJoseph Lo cache-line-size = <64>; 16265298166dSJoseph Lo cache-sets = <2048>; 16275298166dSJoseph Lo }; 1628cd6fe32eSThierry Reding }; 1629cd6fe32eSThierry Reding 163015274c23SMikko Perttunen thermal-zones { 163115274c23SMikko Perttunen a57 { 163215274c23SMikko Perttunen polling-delay = <0>; 163315274c23SMikko Perttunen polling-delay-passive = <1000>; 163415274c23SMikko Perttunen 163515274c23SMikko Perttunen thermal-sensors = 163615274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 163715274c23SMikko Perttunen 163815274c23SMikko Perttunen trips { 163915274c23SMikko Perttunen critical { 164015274c23SMikko Perttunen temperature = <101000>; 164115274c23SMikko Perttunen hysteresis = <0>; 164215274c23SMikko Perttunen type = "critical"; 164315274c23SMikko Perttunen }; 164415274c23SMikko Perttunen }; 164515274c23SMikko Perttunen 164615274c23SMikko Perttunen cooling-maps { 164715274c23SMikko Perttunen }; 164815274c23SMikko Perttunen }; 164915274c23SMikko Perttunen 165015274c23SMikko Perttunen denver { 165115274c23SMikko Perttunen polling-delay = <0>; 165215274c23SMikko Perttunen polling-delay-passive = <1000>; 165315274c23SMikko Perttunen 165415274c23SMikko Perttunen thermal-sensors = 165515274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 165615274c23SMikko Perttunen 165715274c23SMikko Perttunen trips { 165815274c23SMikko Perttunen critical { 165915274c23SMikko Perttunen temperature = <101000>; 166015274c23SMikko Perttunen hysteresis = <0>; 166115274c23SMikko Perttunen type = "critical"; 166215274c23SMikko Perttunen }; 166315274c23SMikko Perttunen }; 166415274c23SMikko Perttunen 166515274c23SMikko Perttunen cooling-maps { 166615274c23SMikko Perttunen }; 166715274c23SMikko Perttunen }; 166815274c23SMikko Perttunen 166915274c23SMikko Perttunen gpu { 167015274c23SMikko Perttunen polling-delay = <0>; 167115274c23SMikko Perttunen polling-delay-passive = <1000>; 167215274c23SMikko Perttunen 167315274c23SMikko Perttunen thermal-sensors = 167415274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 167515274c23SMikko Perttunen 167615274c23SMikko Perttunen trips { 167715274c23SMikko Perttunen critical { 167815274c23SMikko Perttunen temperature = <101000>; 167915274c23SMikko Perttunen hysteresis = <0>; 168015274c23SMikko Perttunen type = "critical"; 168115274c23SMikko Perttunen }; 168215274c23SMikko Perttunen }; 168315274c23SMikko Perttunen 168415274c23SMikko Perttunen cooling-maps { 168515274c23SMikko Perttunen }; 168615274c23SMikko Perttunen }; 168715274c23SMikko Perttunen 168815274c23SMikko Perttunen pll { 168915274c23SMikko Perttunen polling-delay = <0>; 169015274c23SMikko Perttunen polling-delay-passive = <1000>; 169115274c23SMikko Perttunen 169215274c23SMikko Perttunen thermal-sensors = 169315274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 169415274c23SMikko Perttunen 169515274c23SMikko Perttunen trips { 169615274c23SMikko Perttunen critical { 169715274c23SMikko Perttunen temperature = <101000>; 169815274c23SMikko Perttunen hysteresis = <0>; 169915274c23SMikko Perttunen type = "critical"; 170015274c23SMikko Perttunen }; 170115274c23SMikko Perttunen }; 170215274c23SMikko Perttunen 170315274c23SMikko Perttunen cooling-maps { 170415274c23SMikko Perttunen }; 170515274c23SMikko Perttunen }; 170615274c23SMikko Perttunen 170715274c23SMikko Perttunen always_on { 170815274c23SMikko Perttunen polling-delay = <0>; 170915274c23SMikko Perttunen polling-delay-passive = <1000>; 171015274c23SMikko Perttunen 171115274c23SMikko Perttunen thermal-sensors = 171215274c23SMikko Perttunen <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 171315274c23SMikko Perttunen 171415274c23SMikko Perttunen trips { 171515274c23SMikko Perttunen critical { 171615274c23SMikko Perttunen temperature = <101000>; 171715274c23SMikko Perttunen hysteresis = <0>; 171815274c23SMikko Perttunen type = "critical"; 171915274c23SMikko Perttunen }; 172015274c23SMikko Perttunen }; 172115274c23SMikko Perttunen 172215274c23SMikko Perttunen cooling-maps { 172315274c23SMikko Perttunen }; 172415274c23SMikko Perttunen }; 172539cb62cbSJoseph Lo }; 172639cb62cbSJoseph Lo 172739cb62cbSJoseph Lo timer { 172839cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 172939cb62cbSJoseph Lo interrupts = <GIC_PPI 13 173039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 173139cb62cbSJoseph Lo <GIC_PPI 14 173239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 173339cb62cbSJoseph Lo <GIC_PPI 11 173439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 173539cb62cbSJoseph Lo <GIC_PPI 10 173639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 173739cb62cbSJoseph Lo interrupt-parent = <&gic>; 1738b30be673SThierry Reding always-on; 173939cb62cbSJoseph Lo }; 174039cb62cbSJoseph Lo}; 1741